Jyri Sarha | e00447f | 2014-03-11 12:57:32 +0200 | [diff] [blame] | 1 | /* |
| 2 | * ALSA SoC TLV320AIC31XX codec driver |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments, Inc. |
| 5 | * |
| 6 | * This package is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
| 11 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
| 12 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
| 13 | * |
| 14 | */ |
| 15 | #ifndef _TLV320AIC31XX_H |
| 16 | #define _TLV320AIC31XX_H |
| 17 | |
| 18 | #define AIC31XX_RATES SNDRV_PCM_RATE_8000_192000 |
| 19 | |
| 20 | #define AIC31XX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \ |
Peter Ujfalusi | 9cfb769 | 2014-09-04 10:59:41 +0300 | [diff] [blame] | 21 | | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE \ |
| 22 | | SNDRV_PCM_FMTBIT_S32_LE) |
Jyri Sarha | e00447f | 2014-03-11 12:57:32 +0200 | [diff] [blame] | 23 | |
| 24 | |
| 25 | #define AIC31XX_STEREO_CLASS_D_BIT 0x1 |
| 26 | #define AIC31XX_MINIDSP_BIT 0x2 |
| 27 | |
| 28 | enum aic31xx_type { |
| 29 | AIC3100 = 0, |
| 30 | AIC3110 = AIC31XX_STEREO_CLASS_D_BIT, |
| 31 | AIC3120 = AIC31XX_MINIDSP_BIT, |
| 32 | AIC3111 = (AIC31XX_STEREO_CLASS_D_BIT | AIC31XX_MINIDSP_BIT), |
| 33 | }; |
| 34 | |
| 35 | struct aic31xx_pdata { |
| 36 | enum aic31xx_type codec_type; |
| 37 | unsigned int gpio_reset; |
| 38 | int micbias_vg; |
| 39 | }; |
| 40 | |
| 41 | /* Page Control Register */ |
| 42 | #define AIC31XX_PAGECTL 0x00 |
| 43 | |
| 44 | /* Page 0 Registers */ |
| 45 | /* Software reset register */ |
| 46 | #define AIC31XX_RESET 0x01 |
| 47 | /* OT FLAG register */ |
| 48 | #define AIC31XX_OT_FLAG 0x03 |
| 49 | /* Clock clock Gen muxing, Multiplexers*/ |
| 50 | #define AIC31XX_CLKMUX 0x04 |
| 51 | /* PLL P and R-VAL register */ |
| 52 | #define AIC31XX_PLLPR 0x05 |
| 53 | /* PLL J-VAL register */ |
| 54 | #define AIC31XX_PLLJ 0x06 |
| 55 | /* PLL D-VAL MSB register */ |
| 56 | #define AIC31XX_PLLDMSB 0x07 |
| 57 | /* PLL D-VAL LSB register */ |
| 58 | #define AIC31XX_PLLDLSB 0x08 |
| 59 | /* DAC NDAC_VAL register*/ |
| 60 | #define AIC31XX_NDAC 0x0B |
| 61 | /* DAC MDAC_VAL register */ |
| 62 | #define AIC31XX_MDAC 0x0C |
| 63 | /* DAC OSR setting register 1, MSB value */ |
| 64 | #define AIC31XX_DOSRMSB 0x0D |
| 65 | /* DAC OSR setting register 2, LSB value */ |
| 66 | #define AIC31XX_DOSRLSB 0x0E |
| 67 | #define AIC31XX_MINI_DSP_INPOL 0x10 |
| 68 | /* Clock setting register 8, PLL */ |
| 69 | #define AIC31XX_NADC 0x12 |
| 70 | /* Clock setting register 9, PLL */ |
| 71 | #define AIC31XX_MADC 0x13 |
| 72 | /* ADC Oversampling (AOSR) Register */ |
| 73 | #define AIC31XX_AOSR 0x14 |
| 74 | /* Clock setting register 9, Multiplexers */ |
| 75 | #define AIC31XX_CLKOUTMUX 0x19 |
| 76 | /* Clock setting register 10, CLOCKOUT M divider value */ |
| 77 | #define AIC31XX_CLKOUTMVAL 0x1A |
| 78 | /* Audio Interface Setting Register 1 */ |
| 79 | #define AIC31XX_IFACE1 0x1B |
| 80 | /* Audio Data Slot Offset Programming */ |
| 81 | #define AIC31XX_DATA_OFFSET 0x1C |
| 82 | /* Audio Interface Setting Register 2 */ |
| 83 | #define AIC31XX_IFACE2 0x1D |
| 84 | /* Clock setting register 11, BCLK N Divider */ |
| 85 | #define AIC31XX_BCLKN 0x1E |
| 86 | /* Audio Interface Setting Register 3, Secondary Audio Interface */ |
| 87 | #define AIC31XX_IFACESEC1 0x1F |
| 88 | /* Audio Interface Setting Register 4 */ |
| 89 | #define AIC31XX_IFACESEC2 0x20 |
| 90 | /* Audio Interface Setting Register 5 */ |
| 91 | #define AIC31XX_IFACESEC3 0x21 |
| 92 | /* I2C Bus Condition */ |
| 93 | #define AIC31XX_I2C 0x22 |
| 94 | /* ADC FLAG */ |
| 95 | #define AIC31XX_ADCFLAG 0x24 |
| 96 | /* DAC Flag Registers */ |
| 97 | #define AIC31XX_DACFLAG1 0x25 |
| 98 | #define AIC31XX_DACFLAG2 0x26 |
| 99 | /* Sticky Interrupt flag (overflow) */ |
| 100 | #define AIC31XX_OFFLAG 0x27 |
| 101 | /* Sticy DAC Interrupt flags */ |
| 102 | #define AIC31XX_INTRDACFLAG 0x2C |
| 103 | /* Sticy ADC Interrupt flags */ |
| 104 | #define AIC31XX_INTRADCFLAG 0x2D |
| 105 | /* DAC Interrupt flags 2 */ |
| 106 | #define AIC31XX_INTRDACFLAG2 0x2E |
| 107 | /* ADC Interrupt flags 2 */ |
| 108 | #define AIC31XX_INTRADCFLAG2 0x2F |
| 109 | /* INT1 interrupt control */ |
| 110 | #define AIC31XX_INT1CTRL 0x30 |
| 111 | /* INT2 interrupt control */ |
| 112 | #define AIC31XX_INT2CTRL 0x31 |
| 113 | /* GPIO1 control */ |
| 114 | #define AIC31XX_GPIO1 0x33 |
| 115 | |
| 116 | #define AIC31XX_DACPRB 0x3C |
| 117 | /* ADC Instruction Set Register */ |
| 118 | #define AIC31XX_ADCPRB 0x3D |
| 119 | /* DAC channel setup register */ |
| 120 | #define AIC31XX_DACSETUP 0x3F |
| 121 | /* DAC Mute and volume control register */ |
| 122 | #define AIC31XX_DACMUTE 0x40 |
| 123 | /* Left DAC channel digital volume control */ |
| 124 | #define AIC31XX_LDACVOL 0x41 |
| 125 | /* Right DAC channel digital volume control */ |
| 126 | #define AIC31XX_RDACVOL 0x42 |
| 127 | /* Headset detection */ |
| 128 | #define AIC31XX_HSDETECT 0x43 |
| 129 | /* ADC Digital Mic */ |
| 130 | #define AIC31XX_ADCSETUP 0x51 |
| 131 | /* ADC Digital Volume Control Fine Adjust */ |
| 132 | #define AIC31XX_ADCFGA 0x52 |
| 133 | /* ADC Digital Volume Control Coarse Adjust */ |
| 134 | #define AIC31XX_ADCVOL 0x53 |
| 135 | |
| 136 | |
| 137 | /* Page 1 Registers */ |
| 138 | /* Headphone drivers */ |
| 139 | #define AIC31XX_HPDRIVER 0x9F |
| 140 | /* Class-D Speakear Amplifier */ |
| 141 | #define AIC31XX_SPKAMP 0xA0 |
| 142 | /* HP Output Drivers POP Removal Settings */ |
| 143 | #define AIC31XX_HPPOP 0xA1 |
| 144 | /* Output Driver PGA Ramp-Down Period Control */ |
| 145 | #define AIC31XX_SPPGARAMP 0xA2 |
| 146 | /* DAC_L and DAC_R Output Mixer Routing */ |
| 147 | #define AIC31XX_DACMIXERROUTE 0xA3 |
| 148 | /* Left Analog Vol to HPL */ |
| 149 | #define AIC31XX_LANALOGHPL 0xA4 |
| 150 | /* Right Analog Vol to HPR */ |
| 151 | #define AIC31XX_RANALOGHPR 0xA5 |
| 152 | /* Left Analog Vol to SPL */ |
| 153 | #define AIC31XX_LANALOGSPL 0xA6 |
| 154 | /* Right Analog Vol to SPR */ |
| 155 | #define AIC31XX_RANALOGSPR 0xA7 |
| 156 | /* HPL Driver */ |
| 157 | #define AIC31XX_HPLGAIN 0xA8 |
| 158 | /* HPR Driver */ |
| 159 | #define AIC31XX_HPRGAIN 0xA9 |
| 160 | /* SPL Driver */ |
| 161 | #define AIC31XX_SPLGAIN 0xAA |
| 162 | /* SPR Driver */ |
| 163 | #define AIC31XX_SPRGAIN 0xAB |
| 164 | /* HP Driver Control */ |
| 165 | #define AIC31XX_HPCONTROL 0xAC |
| 166 | /* MIC Bias Control */ |
| 167 | #define AIC31XX_MICBIAS 0xAE |
| 168 | /* MIC PGA*/ |
| 169 | #define AIC31XX_MICPGA 0xAF |
| 170 | /* Delta-Sigma Mono ADC Channel Fine-Gain Input Selection for P-Terminal */ |
| 171 | #define AIC31XX_MICPGAPI 0xB0 |
| 172 | /* ADC Input Selection for M-Terminal */ |
| 173 | #define AIC31XX_MICPGAMI 0xB1 |
| 174 | /* Input CM Settings */ |
| 175 | #define AIC31XX_MICPGACM 0xB2 |
| 176 | |
| 177 | /* Bits, masks and shifts */ |
| 178 | |
| 179 | /* AIC31XX_CLKMUX */ |
| 180 | #define AIC31XX_PLL_CLKIN_MASK 0x0c |
| 181 | #define AIC31XX_PLL_CLKIN_SHIFT 2 |
| 182 | #define AIC31XX_PLL_CLKIN_MCLK 0 |
| 183 | #define AIC31XX_CODEC_CLKIN_MASK 0x03 |
| 184 | #define AIC31XX_CODEC_CLKIN_SHIFT 0 |
| 185 | #define AIC31XX_CODEC_CLKIN_PLL 3 |
| 186 | #define AIC31XX_CODEC_CLKIN_BCLK 1 |
| 187 | |
| 188 | /* AIC31XX_PLLPR, AIC31XX_NDAC, AIC31XX_MDAC, AIC31XX_NADC, AIC31XX_MADC, |
| 189 | AIC31XX_BCLKN */ |
| 190 | #define AIC31XX_PLL_MASK 0x7f |
| 191 | #define AIC31XX_PM_MASK 0x80 |
| 192 | |
| 193 | /* AIC31XX_IFACE1 */ |
| 194 | #define AIC31XX_WORD_LEN_16BITS 0x00 |
| 195 | #define AIC31XX_WORD_LEN_20BITS 0x01 |
| 196 | #define AIC31XX_WORD_LEN_24BITS 0x02 |
| 197 | #define AIC31XX_WORD_LEN_32BITS 0x03 |
| 198 | #define AIC31XX_IFACE1_DATALEN_MASK 0x30 |
| 199 | #define AIC31XX_IFACE1_DATALEN_SHIFT (4) |
| 200 | #define AIC31XX_IFACE1_DATATYPE_MASK 0xC0 |
| 201 | #define AIC31XX_IFACE1_DATATYPE_SHIFT (6) |
| 202 | #define AIC31XX_I2S_MODE 0x00 |
| 203 | #define AIC31XX_DSP_MODE 0x01 |
| 204 | #define AIC31XX_RIGHT_JUSTIFIED_MODE 0x02 |
| 205 | #define AIC31XX_LEFT_JUSTIFIED_MODE 0x03 |
| 206 | #define AIC31XX_IFACE1_MASTER_MASK 0x0C |
| 207 | #define AIC31XX_BCLK_MASTER 0x08 |
| 208 | #define AIC31XX_WCLK_MASTER 0x04 |
| 209 | |
| 210 | /* AIC31XX_DATA_OFFSET */ |
| 211 | #define AIC31XX_DATA_OFFSET_MASK 0xFF |
| 212 | |
| 213 | /* AIC31XX_IFACE2 */ |
| 214 | #define AIC31XX_BCLKINV_MASK 0x08 |
| 215 | #define AIC31XX_BDIVCLK_MASK 0x03 |
| 216 | #define AIC31XX_DAC2BCLK 0x00 |
| 217 | #define AIC31XX_DACMOD2BCLK 0x01 |
| 218 | #define AIC31XX_ADC2BCLK 0x02 |
| 219 | #define AIC31XX_ADCMOD2BCLK 0x03 |
| 220 | |
| 221 | /* AIC31XX_ADCFLAG */ |
| 222 | #define AIC31XX_ADCPWRSTATUS_MASK 0x40 |
| 223 | |
| 224 | /* AIC31XX_DACFLAG1 */ |
| 225 | #define AIC31XX_LDACPWRSTATUS_MASK 0x80 |
| 226 | #define AIC31XX_RDACPWRSTATUS_MASK 0x08 |
| 227 | #define AIC31XX_HPLDRVPWRSTATUS_MASK 0x20 |
| 228 | #define AIC31XX_HPRDRVPWRSTATUS_MASK 0x02 |
| 229 | #define AIC31XX_SPLDRVPWRSTATUS_MASK 0x10 |
| 230 | #define AIC31XX_SPRDRVPWRSTATUS_MASK 0x01 |
| 231 | |
| 232 | /* AIC31XX_INTRDACFLAG */ |
| 233 | #define AIC31XX_HPSCDETECT_MASK 0x80 |
| 234 | #define AIC31XX_BUTTONPRESS_MASK 0x20 |
| 235 | #define AIC31XX_HSPLUG_MASK 0x10 |
| 236 | #define AIC31XX_LDRCTHRES_MASK 0x08 |
| 237 | #define AIC31XX_RDRCTHRES_MASK 0x04 |
| 238 | #define AIC31XX_DACSINT_MASK 0x02 |
| 239 | #define AIC31XX_DACAINT_MASK 0x01 |
| 240 | |
| 241 | /* AIC31XX_INT1CTRL */ |
| 242 | #define AIC31XX_HSPLUGDET_MASK 0x80 |
| 243 | #define AIC31XX_BUTTONPRESSDET_MASK 0x40 |
| 244 | #define AIC31XX_DRCTHRES_MASK 0x20 |
| 245 | #define AIC31XX_AGCNOISE_MASK 0x10 |
| 246 | #define AIC31XX_OC_MASK 0x08 |
| 247 | #define AIC31XX_ENGINE_MASK 0x04 |
| 248 | |
| 249 | /* AIC31XX_DACSETUP */ |
| 250 | #define AIC31XX_SOFTSTEP_MASK 0x03 |
| 251 | |
| 252 | /* AIC31XX_DACMUTE */ |
| 253 | #define AIC31XX_DACMUTE_MASK 0x0C |
| 254 | |
| 255 | /* AIC31XX_MICBIAS */ |
| 256 | #define AIC31XX_MICBIAS_MASK 0x03 |
| 257 | #define AIC31XX_MICBIAS_SHIFT 0 |
| 258 | |
| 259 | #endif /* _TLV320AIC31XX_H */ |