blob: 13e94bf9d8ba5f95d1f89999712a98f26778f581 [file] [log] [blame]
Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Robin Getz96f10502009-09-24 14:11:24 +00002 * Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Robin Getz96f10502009-09-24 14:11:24 +00004 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
Bryan Wu1394f032007-05-06 14:50:22 -070010 *
Robin Getz96f10502009-09-24 14:11:24 +000011 * Licensed under the GPL-2
Bryan Wu1394f032007-05-06 14:50:22 -070012 */
13
14#include <linux/module.h>
15#include <linux/kernel_stat.h>
16#include <linux/seq_file.h>
17#include <linux/irq.h>
Philippe Gerum5b5da4c2011-03-17 02:12:48 -040018#include <linux/sched.h>
Ingo Molnarb17b0152017-02-08 18:51:35 +010019#include <linux/sched/debug.h>
Steven Miao4f6b6002012-05-16 17:56:51 +080020#include <linux/syscore_ops.h>
Bjorn Helgaas288e6ea2016-02-02 13:53:23 -060021#include <linux/gpio.h>
Steven Miao4f6b6002012-05-16 17:56:51 +080022#include <asm/delay.h>
Yi Li6a01f232009-01-07 23:14:39 +080023#ifdef CONFIG_IPIPE
24#include <linux/ipipe.h>
25#endif
Bryan Wu1394f032007-05-06 14:50:22 -070026#include <asm/traps.h>
27#include <asm/blackfin.h>
Bryan Wu1394f032007-05-06 14:50:22 -070028#include <asm/irq_handler.h>
Mike Frysinger761ec442009-10-15 17:12:05 +000029#include <asm/dpmc.h>
Sonic Zhang06051fd2012-07-04 19:22:55 +080030#include <asm/traps.h>
Bryan Wu1394f032007-05-06 14:50:22 -070031
Bryan Wu1394f032007-05-06 14:50:22 -070032/*
33 * NOTES:
34 * - we have separated the physical Hardware interrupt from the
35 * levels that the LINUX kernel sees (see the description in irq.h)
36 * -
37 */
38
Graf Yang6b3087c2009-01-07 23:14:39 +080039#ifndef CONFIG_SMP
Mike Frysingera99bbcc2007-10-22 00:19:31 +080040/* Initialize this to an actual value to force it into the .data
41 * section so that we know it is properly initialized at entry into
42 * the kernel but before bss is initialized to zero (which is where
43 * it would live otherwise). The 0x1f magic represents the IRQs we
44 * cannot actually mask out in hardware.
45 */
Mike Frysinger40059782008-11-18 17:48:22 +080046unsigned long bfin_irq_flags = 0x1f;
47EXPORT_SYMBOL(bfin_irq_flags);
Graf Yang6b3087c2009-01-07 23:14:39 +080048#endif
Bryan Wu1394f032007-05-06 14:50:22 -070049
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080050#ifdef CONFIG_PM
51unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
Michael Hennerich4a88d0c2008-08-05 17:38:41 +080052unsigned vr_wakeup;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080053#endif
54
Sonic Zhang11b27cb2012-06-28 19:16:48 +080055#ifndef SEC_GCTL
Mike Frysingere9e334c2011-03-30 00:43:52 -040056static struct ivgx {
Michael Hennerich464abc52008-02-25 13:50:20 +080057 /* irq number for request_irq, available in mach-bf5xx/irq.h */
Roy Huang24a07a12007-07-12 22:41:45 +080058 unsigned int irqno;
Bryan Wu1394f032007-05-06 14:50:22 -070059 /* corresponding bit in the SIC_ISR register */
Roy Huang24a07a12007-07-12 22:41:45 +080060 unsigned int isrflag;
Bryan Wu1394f032007-05-06 14:50:22 -070061} ivg_table[NR_PERI_INTS];
62
Mike Frysingere9e334c2011-03-30 00:43:52 -040063static struct ivg_slice {
Bryan Wu1394f032007-05-06 14:50:22 -070064 /* position of first irq in ivg_table for given ivg */
65 struct ivgx *ifirst;
66 struct ivgx *istop;
67} ivg7_13[IVG13 - IVG7 + 1];
68
Bryan Wu1394f032007-05-06 14:50:22 -070069
70/*
71 * Search SIC_IAR and fill tables with the irqvalues
72 * and their positions in the SIC_ISR register.
73 */
74static void __init search_IAR(void)
75{
76 unsigned ivg, irq_pos = 0;
77 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
Mike Frysinger80fcdb92010-04-22 21:15:00 +000078 int irqN;
Bryan Wu1394f032007-05-06 14:50:22 -070079
Michael Hennerich34e0fc82007-07-12 16:17:18 +080080 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
Bryan Wu1394f032007-05-06 14:50:22 -070081
Mike Frysinger80fcdb92010-04-22 21:15:00 +000082 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
83 int irqn;
Steven Miao4f6b6002012-05-16 17:56:51 +080084 u32 iar =
85 bfin_read32((unsigned long *)SIC_IAR0 +
Mike Frysinger80fcdb92010-04-22 21:15:00 +000086#if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
87 defined(CONFIG_BF538) || defined(CONFIG_BF539)
88 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
Michael Hennerich59003142007-10-21 16:54:27 +080089#else
Mike Frysinger80fcdb92010-04-22 21:15:00 +000090 (irqN >> 3)
Michael Hennerich59003142007-10-21 16:54:27 +080091#endif
Mike Frysinger80fcdb92010-04-22 21:15:00 +000092 );
Mike Frysinger80fcdb92010-04-22 21:15:00 +000093 for (irqn = irqN; irqn < irqN + 4; ++irqn) {
94 int iar_shift = (irqn & 7) * 4;
95 if (ivg == (0xf & (iar >> iar_shift))) {
96 ivg_table[irq_pos].irqno = IVG7 + irqn;
97 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
98 ivg7_13[ivg].istop++;
99 irq_pos++;
100 }
Bryan Wu1394f032007-05-06 14:50:22 -0700101 }
102 }
103 }
104}
Steven Miao4f6b6002012-05-16 17:56:51 +0800105#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700106
107/*
Michael Hennerich464abc52008-02-25 13:50:20 +0800108 * This is for core internal IRQs
Bryan Wu1394f032007-05-06 14:50:22 -0700109 */
Mike Frysingerf58c3272011-04-15 03:08:20 -0400110void bfin_ack_noop(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700111{
112 /* Dummy function. */
113}
114
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000115static void bfin_core_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700116{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000117 bfin_irq_flags &= ~(1 << d->irq);
David Howells3b139cd2010-10-07 14:08:52 +0100118 if (!hard_irqs_disabled())
119 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700120}
121
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000122static void bfin_core_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700123{
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000124 bfin_irq_flags |= 1 << d->irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700125 /*
126 * If interrupts are enabled, IMASK must contain the same value
Mike Frysinger40059782008-11-18 17:48:22 +0800127 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
Bryan Wu1394f032007-05-06 14:50:22 -0700128 * are currently disabled we need not do anything; one of the
129 * callers will take care of setting IMASK to the proper value
130 * when reenabling interrupts.
Mike Frysinger40059782008-11-18 17:48:22 +0800131 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
Bryan Wu1394f032007-05-06 14:50:22 -0700132 * what we need.
133 */
David Howells3b139cd2010-10-07 14:08:52 +0100134 if (!hard_irqs_disabled())
135 hard_local_irq_enable();
Bryan Wu1394f032007-05-06 14:50:22 -0700136 return;
137}
138
Sonic Zhang86794b42012-12-14 11:19:24 +0800139#ifndef SEC_GCTL
Mike Frysingerf58c3272011-04-15 03:08:20 -0400140void bfin_internal_mask_irq(unsigned int irq)
Bryan Wu1394f032007-05-06 14:50:22 -0700141{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400142 unsigned long flags = hard_local_irq_save();
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400143#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800144 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
145 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Bryan Wuc04d66b2007-07-12 17:26:31 +0800146 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800147 ~(1 << mask_bit));
148# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800149 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
Steven Miao4f6b6002012-05-16 17:56:51 +0800150 ~(1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400151# endif
152#else
153 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
Sonic Zhang86794b42012-12-14 11:19:24 +0800154 ~(1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800155#endif /* end of SIC_IMASK0 */
David Howells3b139cd2010-10-07 14:08:52 +0100156 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700157}
158
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000159static void bfin_internal_mask_irq_chip(struct irq_data *d)
160{
161 bfin_internal_mask_irq(d->irq);
162}
163
Sonic Zhang0325f252009-12-28 07:29:57 +0000164#ifdef CONFIG_SMP
Steven Miao4f6b6002012-05-16 17:56:51 +0800165void bfin_internal_unmask_irq_affinity(unsigned int irq,
Sonic Zhang0325f252009-12-28 07:29:57 +0000166 const struct cpumask *affinity)
167#else
Mike Frysingerf58c3272011-04-15 03:08:20 -0400168void bfin_internal_unmask_irq(unsigned int irq)
Sonic Zhang0325f252009-12-28 07:29:57 +0000169#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700170{
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400171 unsigned long flags = hard_local_irq_save();
Philippe Gerum9bd50df2009-03-04 16:52:38 +0800172
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400173#ifdef SIC_IMASK0
Sonic Zhang86794b42012-12-14 11:19:24 +0800174 unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
175 unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400176# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000177 if (cpumask_test_cpu(0, affinity))
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400178# endif
Sonic Zhang0325f252009-12-28 07:29:57 +0000179 bfin_write_SIC_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800180 bfin_read_SIC_IMASK(mask_bank) |
181 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400182# ifdef CONFIG_SMP
Sonic Zhang0325f252009-12-28 07:29:57 +0000183 if (cpumask_test_cpu(1, affinity))
184 bfin_write_SICB_IMASK(mask_bank,
Steven Miao4f6b6002012-05-16 17:56:51 +0800185 bfin_read_SICB_IMASK(mask_bank) |
186 (1 << mask_bit));
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400187# endif
188#else
189 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
Sonic Zhang86794b42012-12-14 11:19:24 +0800190 (1 << BFIN_SYSIRQ(irq)));
Steven Miao4f6b6002012-05-16 17:56:51 +0800191#endif
192 hard_local_irq_restore(flags);
193}
194
Sonic Zhang86794b42012-12-14 11:19:24 +0800195#ifdef CONFIG_SMP
196static void bfin_internal_unmask_irq_chip(struct irq_data *d)
197{
Jiang Liu247bd4f2015-07-13 20:34:56 +0000198 bfin_internal_unmask_irq_affinity(d->irq,
199 irq_data_get_affinity_mask(d));
Sonic Zhang86794b42012-12-14 11:19:24 +0800200}
201
202static int bfin_internal_set_affinity(struct irq_data *d,
203 const struct cpumask *mask, bool force)
204{
205 bfin_internal_mask_irq(d->irq);
206 bfin_internal_unmask_irq_affinity(d->irq, mask);
207
208 return 0;
209}
210#else
211static void bfin_internal_unmask_irq_chip(struct irq_data *d)
212{
213 bfin_internal_unmask_irq(d->irq);
214}
215#endif
216
217#if defined(CONFIG_PM)
218int bfin_internal_set_wake(unsigned int irq, unsigned int state)
219{
220 u32 bank, bit, wakeup = 0;
221 unsigned long flags;
222 bank = BFIN_SYSIRQ(irq) / 32;
223 bit = BFIN_SYSIRQ(irq) % 32;
224
225 switch (irq) {
226#ifdef IRQ_RTC
227 case IRQ_RTC:
228 wakeup |= WAKE;
229 break;
230#endif
231#ifdef IRQ_CAN0_RX
232 case IRQ_CAN0_RX:
233 wakeup |= CANWE;
234 break;
235#endif
236#ifdef IRQ_CAN1_RX
237 case IRQ_CAN1_RX:
238 wakeup |= CANWE;
239 break;
240#endif
241#ifdef IRQ_USB_INT0
242 case IRQ_USB_INT0:
243 wakeup |= USBWE;
244 break;
245#endif
246#ifdef CONFIG_BF54x
247 case IRQ_CNT:
248 wakeup |= ROTWE;
249 break;
250#endif
251 default:
252 break;
253 }
254
255 flags = hard_local_irq_save();
256
257 if (state) {
258 bfin_sic_iwr[bank] |= (1 << bit);
259 vr_wakeup |= wakeup;
260
261 } else {
262 bfin_sic_iwr[bank] &= ~(1 << bit);
263 vr_wakeup &= ~wakeup;
264 }
265
266 hard_local_irq_restore(flags);
267
268 return 0;
269}
270
271static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
272{
273 return bfin_internal_set_wake(d->irq, state);
274}
275#else
276inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
277{
278 return 0;
279}
280# define bfin_internal_set_wake_chip NULL
281#endif
282
283#else /* SEC_GCTL */
Steven Miao4f6b6002012-05-16 17:56:51 +0800284static void bfin_sec_preflow_handler(struct irq_data *d)
285{
286 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800287 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800288
289 bfin_write_SEC_SCI(0, SEC_CSID, sid);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400290
David Howells3b139cd2010-10-07 14:08:52 +0100291 hard_local_irq_restore(flags);
Bryan Wu1394f032007-05-06 14:50:22 -0700292}
293
Steven Miao4f6b6002012-05-16 17:56:51 +0800294static void bfin_sec_mask_ack_irq(struct irq_data *d)
295{
296 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800297 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800298
299 bfin_write_SEC_SCI(0, SEC_CSID, sid);
300
301 hard_local_irq_restore(flags);
302}
303
304static void bfin_sec_unmask_irq(struct irq_data *d)
305{
306 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800307 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800308
309 bfin_write32(SEC_END, sid);
310
311 hard_local_irq_restore(flags);
312}
313
314static void bfin_sec_enable_ssi(unsigned int sid)
315{
316 unsigned long flags = hard_local_irq_save();
317 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
318
319 reg_sctl |= SEC_SCTL_SRC_EN;
320 bfin_write_SEC_SCTL(sid, reg_sctl);
321
322 hard_local_irq_restore(flags);
323}
324
325static void bfin_sec_disable_ssi(unsigned int sid)
326{
327 unsigned long flags = hard_local_irq_save();
328 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
329
330 reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
331 bfin_write_SEC_SCTL(sid, reg_sctl);
332
333 hard_local_irq_restore(flags);
334}
335
336static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
337{
338 unsigned long flags = hard_local_irq_save();
339 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
340
341 reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
342 bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
343
344 hard_local_irq_restore(flags);
345}
346
347static void bfin_sec_enable_sci(unsigned int sid)
348{
349 unsigned long flags = hard_local_irq_save();
350 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
351
Sonic Zhang86794b42012-12-14 11:19:24 +0800352 if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
Steven Miao4f6b6002012-05-16 17:56:51 +0800353 reg_sctl |= SEC_SCTL_FAULT_EN;
354 else
355 reg_sctl |= SEC_SCTL_INT_EN;
356 bfin_write_SEC_SCTL(sid, reg_sctl);
357
358 hard_local_irq_restore(flags);
359}
360
361static void bfin_sec_disable_sci(unsigned int sid)
362{
363 unsigned long flags = hard_local_irq_save();
364 uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
365
366 reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
367 bfin_write_SEC_SCTL(sid, reg_sctl);
368
369 hard_local_irq_restore(flags);
370}
371
372static void bfin_sec_enable(struct irq_data *d)
373{
374 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800375 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800376
377 bfin_sec_enable_sci(sid);
378 bfin_sec_enable_ssi(sid);
379
380 hard_local_irq_restore(flags);
381}
382
383static void bfin_sec_disable(struct irq_data *d)
384{
385 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800386 unsigned int sid = BFIN_SYSIRQ(d->irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800387
388 bfin_sec_disable_sci(sid);
389 bfin_sec_disable_ssi(sid);
390
391 hard_local_irq_restore(flags);
392}
393
Sonic Zhange0a59312012-06-29 18:19:29 +0800394static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
395{
396 unsigned long flags = hard_local_irq_save();
397 uint32_t reg_sctl;
398 int i;
399
400 bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
401
402 for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
403 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
404 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
405 bfin_write_SEC_SCTL(i, reg_sctl);
406 }
407
408 hard_local_irq_restore(flags);
409}
410
Sonic Zhang86794b42012-12-14 11:19:24 +0800411void bfin_sec_raise_irq(unsigned int irq)
Steven Miao4f6b6002012-05-16 17:56:51 +0800412{
413 unsigned long flags = hard_local_irq_save();
Sonic Zhang86794b42012-12-14 11:19:24 +0800414 unsigned int sid = BFIN_SYSIRQ(irq);
Steven Miao4f6b6002012-05-16 17:56:51 +0800415
416 bfin_write32(SEC_RAISE, sid);
417
418 hard_local_irq_restore(flags);
419}
420
421static void init_software_driven_irq(void)
422{
423 bfin_sec_set_ssi_coreid(34, 0);
424 bfin_sec_set_ssi_coreid(35, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800425
426 bfin_sec_enable_sci(35);
427 bfin_sec_enable_ssi(35);
Steven Miao4f6b6002012-05-16 17:56:51 +0800428 bfin_sec_set_ssi_coreid(36, 0);
429 bfin_sec_set_ssi_coreid(37, 1);
Sonic Zhang86794b42012-12-14 11:19:24 +0800430 bfin_sec_enable_sci(37);
431 bfin_sec_enable_ssi(37);
Steven Miao4f6b6002012-05-16 17:56:51 +0800432}
433
Steven Miao4f6b6002012-05-16 17:56:51 +0800434void handle_sec_sfi_fault(uint32_t gstat)
435{
436
437}
438
439void handle_sec_sci_fault(uint32_t gstat)
440{
441 uint32_t core_id;
442 uint32_t cstat;
443
444 core_id = gstat & SEC_GSTAT_SCI;
445 cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
446 if (cstat & SEC_CSTAT_ERR) {
447 switch (cstat & SEC_CSTAT_ERRC) {
448 case SEC_CSTAT_ACKERR:
449 printk(KERN_DEBUG "sec ack err\n");
450 break;
451 default:
Masanari Iida9b134942014-08-06 22:31:28 +0900452 printk(KERN_DEBUG "sec sci unknown err\n");
Steven Miao4f6b6002012-05-16 17:56:51 +0800453 }
454 }
455
456}
457
458void handle_sec_ssi_fault(uint32_t gstat)
459{
460 uint32_t sid;
461 uint32_t sstat;
462
463 sid = gstat & SEC_GSTAT_SID;
464 sstat = bfin_read_SEC_SSTAT(sid);
465
466}
467
Sonic Zhang1b601232013-12-04 15:27:47 +0800468void handle_sec_fault(uint32_t sec_gstat)
Steven Miao4f6b6002012-05-16 17:56:51 +0800469{
Steven Miao4f6b6002012-05-16 17:56:51 +0800470 if (sec_gstat & SEC_GSTAT_ERR) {
471
472 switch (sec_gstat & SEC_GSTAT_ERRC) {
473 case 0:
474 handle_sec_sfi_fault(sec_gstat);
475 break;
476 case SEC_GSTAT_SCIERR:
477 handle_sec_sci_fault(sec_gstat);
478 break;
479 case SEC_GSTAT_SSIERR:
480 handle_sec_ssi_fault(sec_gstat);
481 break;
482 }
483
484
485 }
Steven Miao4f6b6002012-05-16 17:56:51 +0800486}
487
Sonic Zhang1b601232013-12-04 15:27:47 +0800488static struct irqaction bfin_fault_irq = {
489 .name = "Blackfin fault",
490};
491
492static irqreturn_t bfin_fault_routine(int irq, void *data)
Sonic Zhang06051fd2012-07-04 19:22:55 +0800493{
494 struct pt_regs *fp = get_irq_regs();
495
Sonic Zhang06051fd2012-07-04 19:22:55 +0800496 switch (irq) {
497 case IRQ_C0_DBL_FAULT:
498 double_fault_c(fp);
499 break;
500 case IRQ_C0_HW_ERR:
501 dump_bfin_process(fp);
502 dump_bfin_mem(fp);
503 show_regs(fp);
504 printk(KERN_NOTICE "Kernel Stack\n");
505 show_stack(current, NULL);
506 print_modules();
Sonic Zhang86794b42012-12-14 11:19:24 +0800507 panic("Core 0 hardware error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800508 break;
509 case IRQ_C0_NMI_L1_PARITY_ERR:
Sonic Zhang86794b42012-12-14 11:19:24 +0800510 panic("Core 0 NMI L1 parity error");
Sonic Zhang06051fd2012-07-04 19:22:55 +0800511 break;
Sonic Zhang1b601232013-12-04 15:27:47 +0800512 case IRQ_SEC_ERR:
513 pr_err("SEC error\n");
514 handle_sec_fault(bfin_read32(SEC_GSTAT));
515 break;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800516 default:
Sonic Zhang1b601232013-12-04 15:27:47 +0800517 panic("Unknown fault %d", irq);
Sonic Zhang06051fd2012-07-04 19:22:55 +0800518 }
519
Sonic Zhang1b601232013-12-04 15:27:47 +0800520 return IRQ_HANDLED;
Sonic Zhang06051fd2012-07-04 19:22:55 +0800521}
Sonic Zhang86794b42012-12-14 11:19:24 +0800522#endif /* SEC_GCTL */
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800523
Bryan Wu1394f032007-05-06 14:50:22 -0700524static struct irq_chip bfin_core_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800525 .name = "CORE",
Thomas Gleixner4f19ea42011-02-06 18:23:27 +0000526 .irq_mask = bfin_core_mask_irq,
527 .irq_unmask = bfin_core_unmask_irq,
Bryan Wu1394f032007-05-06 14:50:22 -0700528};
529
Sonic Zhang86794b42012-12-14 11:19:24 +0800530#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700531static struct irq_chip bfin_internal_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800532 .name = "INTN",
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000533 .irq_mask = bfin_internal_mask_irq_chip,
534 .irq_unmask = bfin_internal_unmask_irq_chip,
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000535 .irq_disable = bfin_internal_mask_irq_chip,
536 .irq_enable = bfin_internal_unmask_irq_chip,
Sonic Zhang0325f252009-12-28 07:29:57 +0000537#ifdef CONFIG_SMP
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000538 .irq_set_affinity = bfin_internal_set_affinity,
Sonic Zhang0325f252009-12-28 07:29:57 +0000539#endif
Thomas Gleixnerff43a672011-02-06 18:23:29 +0000540 .irq_set_wake = bfin_internal_set_wake_chip,
Bryan Wu1394f032007-05-06 14:50:22 -0700541};
Sonic Zhang86794b42012-12-14 11:19:24 +0800542#else
Steven Miao4f6b6002012-05-16 17:56:51 +0800543static struct irq_chip bfin_sec_irqchip = {
544 .name = "SEC",
545 .irq_mask_ack = bfin_sec_mask_ack_irq,
546 .irq_mask = bfin_sec_mask_ack_irq,
547 .irq_unmask = bfin_sec_unmask_irq,
548 .irq_eoi = bfin_sec_unmask_irq,
549 .irq_disable = bfin_sec_disable,
550 .irq_enable = bfin_sec_enable,
551};
552#endif
553
Mike Frysingerf58c3272011-04-15 03:08:20 -0400554void bfin_handle_irq(unsigned irq)
Yi Li6a01f232009-01-07 23:14:39 +0800555{
556#ifdef CONFIG_IPIPE
557 struct pt_regs regs; /* Contents not used. */
558 ipipe_trace_irq_entry(irq);
559 __ipipe_handle_irq(irq, &regs);
560 ipipe_trace_irq_exit(irq);
561#else /* !CONFIG_IPIPE */
Thomas Gleixnerb10bbbb2011-02-06 18:23:25 +0000562 generic_handle_irq(irq);
Yi Li6a01f232009-01-07 23:14:39 +0800563#endif /* !CONFIG_IPIPE */
564}
565
Michael Hennerichaec59c92010-02-19 15:09:10 +0000566#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
567static int mac_stat_int_mask;
568
569static void bfin_mac_status_ack_irq(unsigned int irq)
570{
571 switch (irq) {
572 case IRQ_MAC_MMCINT:
573 bfin_write_EMAC_MMC_TIRQS(
574 bfin_read_EMAC_MMC_TIRQE() &
575 bfin_read_EMAC_MMC_TIRQS());
576 bfin_write_EMAC_MMC_RIRQS(
577 bfin_read_EMAC_MMC_RIRQE() &
578 bfin_read_EMAC_MMC_RIRQS());
579 break;
580 case IRQ_MAC_RXFSINT:
581 bfin_write_EMAC_RX_STKY(
582 bfin_read_EMAC_RX_IRQE() &
583 bfin_read_EMAC_RX_STKY());
584 break;
585 case IRQ_MAC_TXFSINT:
586 bfin_write_EMAC_TX_STKY(
587 bfin_read_EMAC_TX_IRQE() &
588 bfin_read_EMAC_TX_STKY());
589 break;
590 case IRQ_MAC_WAKEDET:
591 bfin_write_EMAC_WKUP_CTL(
592 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
593 break;
594 default:
595 /* These bits are W1C */
596 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
597 break;
598 }
599}
600
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000601static void bfin_mac_status_mask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000602{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000603 unsigned int irq = d->irq;
604
Michael Hennerichaec59c92010-02-19 15:09:10 +0000605 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
Mike Frysingerf58c3272011-04-15 03:08:20 -0400606#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000607 switch (irq) {
608 case IRQ_MAC_PHYINT:
609 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
610 break;
611 default:
612 break;
613 }
614#else
615 if (!mac_stat_int_mask)
616 bfin_internal_mask_irq(IRQ_MAC_ERROR);
617#endif
618 bfin_mac_status_ack_irq(irq);
619}
620
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000621static void bfin_mac_status_unmask_irq(struct irq_data *d)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000622{
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000623 unsigned int irq = d->irq;
624
Mike Frysingerf58c3272011-04-15 03:08:20 -0400625#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000626 switch (irq) {
627 case IRQ_MAC_PHYINT:
628 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
629 break;
630 default:
631 break;
632 }
633#else
634 if (!mac_stat_int_mask)
635 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
636#endif
637 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
638}
639
640#ifdef CONFIG_PM
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000641int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000642{
Mike Frysingerf58c3272011-04-15 03:08:20 -0400643#ifdef BF537_FAMILY
Michael Hennerichaec59c92010-02-19 15:09:10 +0000644 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
645#else
646 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
647#endif
648}
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400649#else
650# define bfin_mac_status_set_wake NULL
Michael Hennerichaec59c92010-02-19 15:09:10 +0000651#endif
652
653static struct irq_chip bfin_mac_status_irqchip = {
654 .name = "MACST",
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000655 .irq_mask = bfin_mac_status_mask_irq,
656 .irq_unmask = bfin_mac_status_unmask_irq,
Thomas Gleixner172d2d12011-02-06 18:23:34 +0000657 .irq_set_wake = bfin_mac_status_set_wake,
Michael Hennerichaec59c92010-02-19 15:09:10 +0000658};
659
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200660void bfin_demux_mac_status_irq(struct irq_desc *inta_desc)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000661{
662 int i, irq = 0;
663 u32 status = bfin_read_EMAC_SYSTAT();
664
Michael Hennerichbedeea62010-08-20 11:59:27 +0000665 for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
Michael Hennerichaec59c92010-02-19 15:09:10 +0000666 if (status & (1L << i)) {
667 irq = IRQ_MAC_PHYINT + i;
668 break;
669 }
670
671 if (irq) {
672 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
673 bfin_handle_irq(irq);
674 } else {
675 bfin_mac_status_ack_irq(irq);
676 pr_debug("IRQ %d:"
Steven Miao4f6b6002012-05-16 17:56:51 +0800677 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
678 irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000679 }
680 } else
681 printk(KERN_ERR
Steven Miao4f6b6002012-05-16 17:56:51 +0800682 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
683 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
684 "(EMAC_SYSTAT=0x%X)\n",
685 __func__, __FILE__, __LINE__, status);
Michael Hennerichaec59c92010-02-19 15:09:10 +0000686}
687#endif
688
Thomas Gleixner28438442015-07-13 20:34:57 +0000689static inline void bfin_set_irq_handler(struct irq_data *d, irq_flow_handler_t handle)
Graf Yangbfd15112008-10-08 18:02:44 +0800690{
Yi Li6a01f232009-01-07 23:14:39 +0800691#ifdef CONFIG_IPIPE
Philippe Gerum5b5da4c2011-03-17 02:12:48 -0400692 handle = handle_level_irq;
Yi Li6a01f232009-01-07 23:14:39 +0800693#endif
Thomas Gleixner28438442015-07-13 20:34:57 +0000694 irq_set_handler_locked(d, handle);
Graf Yangbfd15112008-10-08 18:02:44 +0800695}
696
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800697#ifdef CONFIG_GPIO_ADI
Michael Hennerich6fce6a82007-12-24 16:56:12 +0800698
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800699static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
Michael Hennerich8d022372008-11-18 17:48:22 +0800700
Thomas Gleixnere9502852011-02-06 18:23:36 +0000701static void bfin_gpio_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700702{
Michael Hennerich8d022372008-11-18 17:48:22 +0800703 /* AFAIK ack_irq in case mask_ack is provided
704 * get's only called for edge sense irqs
705 */
Thomas Gleixnere9502852011-02-06 18:23:36 +0000706 set_gpio_data(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700707}
708
Thomas Gleixnere9502852011-02-06 18:23:36 +0000709static void bfin_gpio_mask_ack_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700710{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000711 unsigned int irq = d->irq;
Michael Hennerich8d022372008-11-18 17:48:22 +0800712 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700713
Thomas Gleixner1907d8b2011-03-24 17:21:01 +0100714 if (!irqd_is_level_type(d))
Bryan Wu1394f032007-05-06 14:50:22 -0700715 set_gpio_data(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700716
717 set_gpio_maska(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700718}
719
Thomas Gleixnere9502852011-02-06 18:23:36 +0000720static void bfin_gpio_mask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700721{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000722 set_gpio_maska(irq_to_gpio(d->irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700723}
724
Thomas Gleixnere9502852011-02-06 18:23:36 +0000725static void bfin_gpio_unmask_irq(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700726{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000727 set_gpio_maska(irq_to_gpio(d->irq), 1);
Bryan Wu1394f032007-05-06 14:50:22 -0700728}
729
Thomas Gleixnere9502852011-02-06 18:23:36 +0000730static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700731{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000732 u32 gpionr = irq_to_gpio(d->irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700733
Michael Hennerich8d022372008-11-18 17:48:22 +0800734 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800735 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700736
Thomas Gleixnere9502852011-02-06 18:23:36 +0000737 bfin_gpio_unmask_irq(d);
Bryan Wu1394f032007-05-06 14:50:22 -0700738
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800739 return 0;
Bryan Wu1394f032007-05-06 14:50:22 -0700740}
741
Thomas Gleixnere9502852011-02-06 18:23:36 +0000742static void bfin_gpio_irq_shutdown(struct irq_data *d)
Bryan Wu1394f032007-05-06 14:50:22 -0700743{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000744 u32 gpionr = irq_to_gpio(d->irq);
Graf Yang30af6d42008-11-18 17:48:21 +0800745
Thomas Gleixnere9502852011-02-06 18:23:36 +0000746 bfin_gpio_mask_irq(d);
Graf Yang30af6d42008-11-18 17:48:21 +0800747 __clear_bit(gpionr, gpio_enabled);
Graf Yang9570ff42009-01-07 23:14:38 +0800748 bfin_gpio_irq_free(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700749}
750
Thomas Gleixnere9502852011-02-06 18:23:36 +0000751static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
Bryan Wu1394f032007-05-06 14:50:22 -0700752{
Thomas Gleixnere9502852011-02-06 18:23:36 +0000753 unsigned int irq = d->irq;
Graf Yang8eb3e3b2008-11-18 17:48:22 +0800754 int ret;
755 char buf[16];
Michael Hennerich8d022372008-11-18 17:48:22 +0800756 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700757
758 if (type == IRQ_TYPE_PROBE) {
759 /* only probe unenabled GPIO interrupt lines */
Mike Frysingerc3695342009-06-13 10:32:29 -0400760 if (test_bit(gpionr, gpio_enabled))
Bryan Wu1394f032007-05-06 14:50:22 -0700761 return 0;
762 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
763 }
764
765 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800766 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
Michael Hennerich8d022372008-11-18 17:48:22 +0800767
Graf Yang9570ff42009-01-07 23:14:38 +0800768 snprintf(buf, 16, "gpio-irq%d", irq);
769 ret = bfin_gpio_irq_request(gpionr, buf);
770 if (ret)
771 return ret;
772
Michael Hennerich8d022372008-11-18 17:48:22 +0800773 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800774 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700775
Bryan Wu1394f032007-05-06 14:50:22 -0700776 } else {
Michael Hennerich8d022372008-11-18 17:48:22 +0800777 __clear_bit(gpionr, gpio_enabled);
Bryan Wu1394f032007-05-06 14:50:22 -0700778 return 0;
779 }
780
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800781 set_gpio_inen(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700782 set_gpio_dir(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700783
784 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
785 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
786 set_gpio_both(gpionr, 1);
787 else
788 set_gpio_both(gpionr, 0);
789
790 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
791 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
792 else
793 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
794
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800795 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
796 set_gpio_edge(gpionr, 1);
797 set_gpio_inen(gpionr, 1);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800798 set_gpio_data(gpionr, 0);
799
800 } else {
801 set_gpio_edge(gpionr, 0);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800802 set_gpio_inen(gpionr, 1);
803 }
804
Bryan Wu1394f032007-05-06 14:50:22 -0700805 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
Thomas Gleixner28438442015-07-13 20:34:57 +0000806 bfin_set_irq_handler(d, handle_edge_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700807 else
Thomas Gleixner28438442015-07-13 20:34:57 +0000808 bfin_set_irq_handler(d, handle_level_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700809
810 return 0;
811}
812
Mike Frysingere2a80922011-04-15 12:51:33 -0400813static void bfin_demux_gpio_block(unsigned int irq)
814{
815 unsigned int gpio, mask;
816
817 gpio = irq_to_gpio(irq);
818 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
819
820 while (mask) {
821 if (mask & 1)
822 bfin_handle_irq(irq);
823 irq++;
824 mask >>= 1;
825 }
826}
827
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200828void bfin_demux_gpio_irq(struct irq_desc *desc)
Bryan Wu1394f032007-05-06 14:50:22 -0700829{
Thomas Gleixner2b5017692015-07-31 21:50:30 +0200830 unsigned int inta_irq = irq_desc_get_irq(desc);
Mike Frysingere2a80922011-04-15 12:51:33 -0400831 unsigned int irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700832
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800833 switch (inta_irq) {
Mike Frysingere2a80922011-04-15 12:51:33 -0400834#if defined(BF537_FAMILY)
Mike Frysinger8c054102011-04-15 13:04:59 -0400835 case IRQ_PF_INTA_PG_INTA:
Mike Frysingere2a80922011-04-15 12:51:33 -0400836 bfin_demux_gpio_block(IRQ_PF0);
837 irq = IRQ_PG0;
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800838 break;
Mike Frysinger8c054102011-04-15 13:04:59 -0400839 case IRQ_PH_INTA_MAC_RX:
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800840 irq = IRQ_PH0;
841 break;
Mike Frysingere2a80922011-04-15 12:51:33 -0400842#elif defined(BF533_FAMILY)
843 case IRQ_PROG_INTA:
844 irq = IRQ_PF0;
845 break;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400846#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800847 case IRQ_PORTF_INTA:
848 irq = IRQ_PF0;
849 break;
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800850#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800851 case IRQ_PORTF_INTA:
852 irq = IRQ_PF0;
853 break;
854 case IRQ_PORTG_INTA:
855 irq = IRQ_PG0;
856 break;
857 case IRQ_PORTH_INTA:
858 irq = IRQ_PH0;
859 break;
860#elif defined(CONFIG_BF561)
861 case IRQ_PROG0_INTA:
862 irq = IRQ_PF0;
863 break;
864 case IRQ_PROG1_INTA:
865 irq = IRQ_PF16;
866 break;
867 case IRQ_PROG2_INTA:
868 irq = IRQ_PF32;
869 break;
870#endif
871 default:
872 BUG();
873 return;
Bryan Wu1394f032007-05-06 14:50:22 -0700874 }
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800875
Mike Frysingere2a80922011-04-15 12:51:33 -0400876 bfin_demux_gpio_block(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700877}
878
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800879#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800880
Mike Frysingerdd8cb372011-04-15 03:19:22 -0400881static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800882{
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800883 return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
884}
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800885
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800886#else
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800887
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800888# define bfin_gpio_set_wake NULL
889
Sonic Zhang86794b42012-12-14 11:19:24 +0800890#endif
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800891
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800892static struct irq_chip bfin_gpio_irqchip = {
893 .name = "GPIO",
894 .irq_ack = bfin_gpio_ack_irq,
895 .irq_mask = bfin_gpio_mask_irq,
896 .irq_mask_ack = bfin_gpio_mask_ack_irq,
897 .irq_unmask = bfin_gpio_unmask_irq,
898 .irq_disable = bfin_gpio_mask_irq,
899 .irq_enable = bfin_gpio_unmask_irq,
900 .irq_set_type = bfin_gpio_irq_type,
901 .irq_startup = bfin_gpio_irq_startup,
902 .irq_shutdown = bfin_gpio_irq_shutdown,
903 .irq_set_wake = bfin_gpio_set_wake,
904};
Steven Miaod49cdf8402012-06-14 18:04:01 +0800905
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800906#endif
Steven Miaod49cdf8402012-06-14 18:04:01 +0800907
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800908#ifdef CONFIG_PM
Steven Miaod49cdf8402012-06-14 18:04:01 +0800909
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800910#ifdef SEC_GCTL
Sonic Zhang54e4ff42013-05-30 18:37:28 +0800911static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
912
Steven Miaod49cdf8402012-06-14 18:04:01 +0800913static int sec_suspend(void)
914{
915 u32 bank;
916
917 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800918 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
Steven Miaod49cdf8402012-06-14 18:04:01 +0800919 return 0;
920}
921
922static void sec_resume(void)
923{
924 u32 bank;
925
926 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
927 udelay(100);
928 bfin_write_SEC_GCTL(SEC_GCTL_EN);
929 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
930
931 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
Sonic Zhang86794b42012-12-14 11:19:24 +0800932 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
Steven Miaod49cdf8402012-06-14 18:04:01 +0800933}
934
935static struct syscore_ops sec_pm_syscore_ops = {
936 .suspend = sec_suspend,
937 .resume = sec_resume,
938};
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800939#endif
940
Steven Miao4f6b6002012-05-16 17:56:51 +0800941#endif
Michael Hennerich8d022372008-11-18 17:48:22 +0800942
Paul Gortmaker13dff622013-06-18 16:56:21 -0400943void init_exception_vectors(void)
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800944{
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800945 /* cannot program in software:
946 * evt0 - emulation (jtag)
947 * evt1 - reset
948 */
949 bfin_write_EVT2(evt_nmi);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800950 bfin_write_EVT3(trap);
951 bfin_write_EVT5(evt_ivhw);
952 bfin_write_EVT6(evt_timer);
953 bfin_write_EVT7(evt_evt7);
954 bfin_write_EVT8(evt_evt8);
955 bfin_write_EVT9(evt_evt9);
956 bfin_write_EVT10(evt_evt10);
957 bfin_write_EVT11(evt_evt11);
958 bfin_write_EVT12(evt_evt12);
959 bfin_write_EVT13(evt_evt13);
Philippe Gerum9703a732009-06-22 18:23:48 +0200960 bfin_write_EVT14(evt_evt14);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800961 bfin_write_EVT15(evt_system_call);
962 CSYNC();
963}
964
Sonic Zhang11b27cb2012-06-28 19:16:48 +0800965#ifndef SEC_GCTL
Bryan Wu1394f032007-05-06 14:50:22 -0700966/*
967 * This function should be called during kernel startup to initialize
968 * the BFin IRQ handling routines.
969 */
Michael Hennerich8d022372008-11-18 17:48:22 +0800970
Bryan Wu1394f032007-05-06 14:50:22 -0700971int __init init_arch_irq(void)
972{
973 int irq;
974 unsigned long ilat = 0;
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400975
Bryan Wu1394f032007-05-06 14:50:22 -0700976 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400977#ifdef SIC_IMASK0
Roy Huang24a07a12007-07-12 22:41:45 +0800978 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
979 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -0400980# ifdef SIC_IMASK2
Michael Hennerich59003142007-10-21 16:54:27 +0800981 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
Mike Frysingera055b2b2007-11-15 21:12:32 +0800982# endif
Steven Miao4f6b6002012-05-16 17:56:51 +0800983# if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +0800984 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
985 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
986# endif
Roy Huang24a07a12007-07-12 22:41:45 +0800987#else
Bryan Wu1394f032007-05-06 14:50:22 -0700988 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
Roy Huang24a07a12007-07-12 22:41:45 +0800989#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700990
991 local_irq_disable();
992
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800993 for (irq = 0; irq <= SYS_IRQS; irq++) {
Bryan Wu1394f032007-05-06 14:50:22 -0700994 if (irq <= IRQ_CORETMR)
Thomas Gleixner43f2f112011-03-24 17:22:30 +0100995 irq_set_chip(irq, &bfin_core_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -0700996 else
Thomas Gleixner43f2f112011-03-24 17:22:30 +0100997 irq_set_chip(irq, &bfin_internal_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -0700998
Michael Hennerich464abc52008-02-25 13:50:20 +0800999 switch (irq) {
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001000#if !BFIN_GPIO_PINT
1001#if defined(BF537_FAMILY)
Mike Frysinger01f8e342011-06-26 13:56:23 -04001002 case IRQ_PH_INTA_MAC_RX:
1003 case IRQ_PF_INTA_PG_INTA:
1004#elif defined(BF533_FAMILY)
1005 case IRQ_PROG_INTA:
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001006#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001007 case IRQ_PORTF_INTA:
1008 case IRQ_PORTG_INTA:
1009 case IRQ_PORTH_INTA:
Michael Hennerich2c4f8292008-02-09 04:11:14 +08001010#elif defined(CONFIG_BF561)
Michael Hennerich464abc52008-02-25 13:50:20 +08001011 case IRQ_PROG0_INTA:
1012 case IRQ_PROG1_INTA:
1013 case IRQ_PROG2_INTA:
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001014#elif defined(BF538_FAMILY)
Michael Hennerichdc26aec2008-11-18 17:48:22 +08001015 case IRQ_PORTF_INTA:
Michael Hennerich59003142007-10-21 16:54:27 +08001016#endif
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001017 irq_set_chained_handler(irq, bfin_demux_gpio_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001018 break;
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001019#endif
Michael Hennerichaec59c92010-02-19 15:09:10 +00001020#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1021 case IRQ_MAC_ERROR:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001022 irq_set_chained_handler(irq,
1023 bfin_demux_mac_status_irq);
Michael Hennerichaec59c92010-02-19 15:09:10 +00001024 break;
1025#endif
Steven Miao4f6b6002012-05-16 17:56:51 +08001026#if defined(CONFIG_SMP) || defined(CONFIG_ICC)
Graf Yang6b3087c2009-01-07 23:14:39 +08001027 case IRQ_SUPPLE_0:
1028 case IRQ_SUPPLE_1:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001029 irq_set_handler(irq, handle_percpu_irq);
Graf Yang6b3087c2009-01-07 23:14:39 +08001030 break;
1031#endif
Graf Yang179413142009-08-18 04:29:33 +00001032
Yi Licb191712009-12-30 07:12:50 +00001033#ifdef CONFIG_TICKSOURCE_CORETMR
1034 case IRQ_CORETMR:
1035# ifdef CONFIG_SMP
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001036 irq_set_handler(irq, handle_percpu_irq);
Yi Licb191712009-12-30 07:12:50 +00001037# else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001038 irq_set_handler(irq, handle_simple_irq);
Yi Licb191712009-12-30 07:12:50 +00001039# endif
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001040 break;
Yi Licb191712009-12-30 07:12:50 +00001041#endif
1042
1043#ifdef CONFIG_TICKSOURCE_GPTMR0
Philippe Geruma40494a2009-06-16 05:25:42 +02001044 case IRQ_TIMER0:
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001045 irq_set_handler(irq, handle_simple_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001046 break;
Graf Yang179413142009-08-18 04:29:33 +00001047#endif
Yi Licb191712009-12-30 07:12:50 +00001048
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001049 default:
Yi Licb191712009-12-30 07:12:50 +00001050#ifdef CONFIG_IPIPE
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001051 irq_set_handler(irq, handle_level_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001052#else
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001053 irq_set_handler(irq, handle_simple_irq);
Mike Frysingerfc6bd7b2011-04-15 01:35:53 -04001054#endif
Philippe Geruma40494a2009-06-16 05:25:42 +02001055 break;
Bryan Wu1394f032007-05-06 14:50:22 -07001056 }
Bryan Wu1394f032007-05-06 14:50:22 -07001057 }
Michael Hennerich464abc52008-02-25 13:50:20 +08001058
Mike Frysingerf58c3272011-04-15 03:08:20 -04001059 init_mach_irq();
Bryan Wu1394f032007-05-06 14:50:22 -07001060
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001061#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
Michael Hennerichaec59c92010-02-19 15:09:10 +00001062 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001063 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
Michael Hennerichaec59c92010-02-19 15:09:10 +00001064 handle_level_irq);
1065#endif
Michael Hennerich464abc52008-02-25 13:50:20 +08001066 /* if configured as edge, then will be changed to do_edge_IRQ */
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001067#ifdef CONFIG_GPIO_ADI
Michael Hennerichaec59c92010-02-19 15:09:10 +00001068 for (irq = GPIO_IRQ_BASE;
1069 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
Thomas Gleixner43f2f112011-03-24 17:22:30 +01001070 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
Michael Hennerich464abc52008-02-25 13:50:20 +08001071 handle_level_irq);
Sonic Zhang54e4ff42013-05-30 18:37:28 +08001072#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001073 bfin_write_IMASK(0);
1074 CSYNC();
1075 ilat = bfin_read_ILAT();
1076 CSYNC();
1077 bfin_write_ILAT(ilat);
1078 CSYNC();
1079
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001080 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
Mike Frysinger40059782008-11-18 17:48:22 +08001081 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
Bryan Wu1394f032007-05-06 14:50:22 -07001082 * local_irq_enable()
1083 */
1084 program_IAR();
1085 /* Therefore it's better to setup IARs before interrupts enabled */
1086 search_IAR();
1087
1088 /* Enable interrupts IVG7-15 */
Mike Frysinger40059782008-11-18 17:48:22 +08001089 bfin_irq_flags |= IMASK_IVG15 |
Steven Miao4f6b6002012-05-16 17:56:51 +08001090 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1091 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1092
Bryan Wu1394f032007-05-06 14:50:22 -07001093
Michael Hennerich349ebbc2009-04-15 08:48:08 +00001094 /* This implicitly covers ANOMALY_05000171
1095 * Boot-ROM code modifies SICA_IWRx wakeup registers
1096 */
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001097#ifdef SIC_IWR0
Michael Hennerich56f5f592008-08-06 17:55:32 +08001098 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001099# ifdef SIC_IWR1
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001100 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
Michael Hennerich55546ac2008-08-13 17:41:13 +08001101 * will screw up the bootrom as it relies on MDMA0/1 waking it
1102 * up from IDLE instructions. See this report for more info:
1103 * http://blackfin.uclinux.org/gf/tracker/4323
1104 */
Mike Frysingerb7e11292008-11-18 17:48:22 +08001105 if (ANOMALY_05000435)
1106 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1107 else
1108 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Mike Frysingerbe1d8542009-02-04 16:49:45 +08001109# endif
1110# ifdef SIC_IWR2
Michael Hennerich56f5f592008-08-06 17:55:32 +08001111 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001112# endif
1113#else
Michael Hennerich56f5f592008-08-06 17:55:32 +08001114 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001115#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001116 return 0;
1117}
1118
1119#ifdef CONFIG_DO_IRQ_L1
Mike Frysingera055b2b2007-11-15 21:12:32 +08001120__attribute__((l1_text))
Bryan Wu1394f032007-05-06 14:50:22 -07001121#endif
Mike Frysinger6b108042011-03-30 01:35:41 -04001122static int vec_to_irq(int vec)
1123{
1124 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1125 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1126 unsigned long sic_status[3];
Mike Frysinger6b108042011-03-30 01:35:41 -04001127 if (likely(vec == EVT_IVTMR_P))
1128 return IRQ_CORETMR;
Mike Frysinger6b108042011-03-30 01:35:41 -04001129#ifdef SIC_ISR
1130 sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1131#else
1132 if (smp_processor_id()) {
1133# ifdef SICB_ISR0
1134 /* This will be optimized out in UP mode. */
1135 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1136 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1137# endif
1138 } else {
1139 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1140 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1141 }
1142#endif
1143#ifdef SIC_ISR2
1144 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1145#endif
1146
1147 for (;; ivg++) {
1148 if (ivg >= ivg_stop)
1149 return -1;
1150#ifdef SIC_ISR
1151 if (sic_status[0] & ivg->isrflag)
1152#else
1153 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1154#endif
1155 return ivg->irqno;
1156 }
1157}
1158
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001159#else /* SEC_GCTL */
1160
1161/*
1162 * This function should be called during kernel startup to initialize
1163 * the BFin IRQ handling routines.
1164 */
1165
1166int __init init_arch_irq(void)
1167{
1168 int irq;
1169 unsigned long ilat = 0;
1170
1171 bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1172
1173 local_irq_disable();
1174
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001175 for (irq = 0; irq <= SYS_IRQS; irq++) {
1176 if (irq <= IRQ_CORETMR) {
Sonic Zhang86794b42012-12-14 11:19:24 +08001177 irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1178 handle_simple_irq);
1179#if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001180 if (irq == IRQ_CORETMR)
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001181 irq_set_handler(irq, handle_percpu_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001182#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001183 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001184 irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
Sonic Zhang86794b42012-12-14 11:19:24 +08001185 handle_percpu_irq);
1186 } else {
1187 irq_set_chip(irq, &bfin_sec_irqchip);
Sonic Zhang1b601232013-12-04 15:27:47 +08001188 irq_set_handler(irq, handle_fasteoi_irq);
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001189 __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1190 }
1191 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001192
1193 bfin_write_IMASK(0);
1194 CSYNC();
1195 ilat = bfin_read_ILAT();
1196 CSYNC();
1197 bfin_write_ILAT(ilat);
1198 CSYNC();
1199
1200 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1201
Sonic Zhange0a59312012-06-29 18:19:29 +08001202 bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1203
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001204 /* Enable interrupts IVG7-15 */
1205 bfin_irq_flags |= IMASK_IVG15 |
1206 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1207 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1208
1209
1210 bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
Sonic Zhang86794b42012-12-14 11:19:24 +08001211 bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1212 bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001213 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1214 udelay(100);
1215 bfin_write_SEC_GCTL(SEC_GCTL_EN);
1216 bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1217 bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1218
1219 init_software_driven_irq();
Steven Miao36c47232012-12-21 14:34:16 +08001220
1221#ifdef CONFIG_PM
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001222 register_syscore_ops(&sec_pm_syscore_ops);
Steven Miao36c47232012-12-21 14:34:16 +08001223#endif
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001224
Sonic Zhang1b601232013-12-04 15:27:47 +08001225 bfin_fault_irq.handler = bfin_fault_routine;
1226#ifdef CONFIG_L1_PARITY_CHECK
1227 setup_irq(IRQ_C0_NMI_L1_PARITY_ERR, &bfin_fault_irq);
1228#endif
1229 setup_irq(IRQ_C0_DBL_FAULT, &bfin_fault_irq);
1230 setup_irq(IRQ_SEC_ERR, &bfin_fault_irq);
1231
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001232 return 0;
1233}
1234
1235#ifdef CONFIG_DO_IRQ_L1
1236__attribute__((l1_text))
1237#endif
1238static int vec_to_irq(int vec)
1239{
1240 if (likely(vec == EVT_IVTMR_P))
1241 return IRQ_CORETMR;
1242
1243 return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1244}
1245#endif /* SEC_GCTL */
1246
Mike Frysinger6b108042011-03-30 01:35:41 -04001247#ifdef CONFIG_DO_IRQ_L1
1248__attribute__((l1_text))
1249#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001250void do_irq(int vec, struct pt_regs *fp)
1251{
Mike Frysinger6b108042011-03-30 01:35:41 -04001252 int irq = vec_to_irq(vec);
1253 if (irq == -1)
1254 return;
1255 asm_do_IRQ(irq, fp);
Bryan Wu1394f032007-05-06 14:50:22 -07001256}
Yi Li6a01f232009-01-07 23:14:39 +08001257
1258#ifdef CONFIG_IPIPE
1259
1260int __ipipe_get_irq_priority(unsigned irq)
1261{
1262 int ient, prio;
1263
1264 if (irq <= IRQ_CORETMR)
1265 return irq;
1266
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001267#ifdef SEC_GCTL
1268 if (irq >= BFIN_IRQ(0))
1269 return IVG11;
1270#else
Yi Li6a01f232009-01-07 23:14:39 +08001271 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1272 struct ivgx *ivg = ivg_table + ient;
1273 if (ivg->irqno == irq) {
1274 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1275 if (ivg7_13[prio].ifirst <= ivg &&
1276 ivg7_13[prio].istop > ivg)
1277 return IVG7 + prio;
1278 }
1279 }
1280 }
Sonic Zhang11b27cb2012-06-28 19:16:48 +08001281#endif
Yi Li6a01f232009-01-07 23:14:39 +08001282
1283 return IVG15;
1284}
1285
Yi Li6a01f232009-01-07 23:14:39 +08001286/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1287#ifdef CONFIG_DO_IRQ_L1
1288__attribute__((l1_text))
1289#endif
1290asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1291{
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001292 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
Philippe Geruma40494a2009-06-16 05:25:42 +02001293 struct ipipe_domain *this_domain = __ipipe_current_domain;
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001294 int irq, s = 0;
Yi Li6a01f232009-01-07 23:14:39 +08001295
Mike Frysinger6b108042011-03-30 01:35:41 -04001296 irq = vec_to_irq(vec);
1297 if (irq == -1)
1298 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001299
1300 if (irq == IRQ_SYSTMR) {
Philippe Geruma40494a2009-06-16 05:25:42 +02001301#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
Yi Li6a01f232009-01-07 23:14:39 +08001302 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001303#endif
Yi Li6a01f232009-01-07 23:14:39 +08001304 /* This is basically what we need from the register frame. */
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001305 __this_cpu_write(__ipipe_tick_regs.ipend, regs->ipend);
1306 __this_cpu_write(__ipipe_tick_regs.pc, regs->pc);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001307 if (this_domain != ipipe_root_domain)
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001308 __this_cpu_and(__ipipe_tick_regs.ipend, ~0x10);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001309 else
Christoph Lameter7e788ab2014-08-17 12:30:52 -05001310 __this_cpu_or(__ipipe_tick_regs.ipend, 0x10);
Yi Li6a01f232009-01-07 23:14:39 +08001311 }
1312
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001313 /*
1314 * We don't want Linux interrupt handlers to run at the
1315 * current core priority level (i.e. < EVT15), since this
1316 * might delay other interrupts handled by a high priority
1317 * domain. Here is what we do instead:
1318 *
1319 * - we raise the SYNCDEFER bit to prevent
1320 * __ipipe_handle_irq() to sync the pipeline for the root
1321 * stage for the incoming interrupt. Upon return, that IRQ is
1322 * pending in the interrupt log.
1323 *
1324 * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1325 * that _schedule_and_signal_from_int will eventually sync the
1326 * pipeline from EVT15.
1327 */
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001328 if (this_domain == ipipe_root_domain) {
1329 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1330 barrier();
1331 }
Yi Li6a01f232009-01-07 23:14:39 +08001332
1333 ipipe_trace_irq_entry(irq);
1334 __ipipe_handle_irq(irq, regs);
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001335 ipipe_trace_irq_exit(irq);
Yi Li6a01f232009-01-07 23:14:39 +08001336
Philippe Gerum5b5da4c2011-03-17 02:12:48 -04001337 if (user_mode(regs) &&
1338 !ipipe_test_foreign_stack() &&
1339 (current->ipipe_flags & PF_EVTRET) != 0) {
1340 /*
1341 * Testing for user_regs() does NOT fully eliminate
1342 * foreign stack contexts, because of the forged
1343 * interrupt returns we do through
1344 * __ipipe_call_irqtail. In that case, we might have
1345 * preempted a foreign stack context in a high
1346 * priority domain, with a single interrupt level now
1347 * pending after the irqtail unwinding is done. In
1348 * which case user_mode() is now true, and the event
1349 * gets dispatched spuriously.
1350 */
1351 current->ipipe_flags &= ~PF_EVTRET;
1352 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1353 }
1354
Philippe Gerum9bd50df2009-03-04 16:52:38 +08001355 if (this_domain == ipipe_root_domain) {
1356 set_thread_flag(TIF_IRQ_SYNC);
1357 if (!s) {
1358 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1359 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1360 }
1361 }
Yi Li6a01f232009-01-07 23:14:39 +08001362
Graf Yang1fa9be72009-05-15 11:01:59 +00001363 return 0;
Yi Li6a01f232009-01-07 23:14:39 +08001364}
1365
1366#endif /* CONFIG_IPIPE */