blob: 2f581521eb9ba9b2e93707eee069cd18a9e322e1 [file] [log] [blame]
Stephen Rothwellfc68e862007-08-22 13:44:58 +10001/*
2 * Low level routines for legacy iSeries support.
3 *
4 * Extracted from head_64.S
5 *
6 * PowerPC version
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
8 *
9 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
10 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
11 * Adapted for Power Macintosh by Paul Mackerras.
12 * Low-level exception handlers and MMU support
13 * rewritten by Paul Mackerras.
14 * Copyright (C) 1996 Paul Mackerras.
15 *
16 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
17 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
18 *
19 * This file contains the low-level support and setup for the
20 * PowerPC-64 platform, including trap and interrupt dispatch.
21 *
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License
24 * as published by the Free Software Foundation; either version
25 * 2 of the License, or (at your option) any later version.
26 */
27
28#include <asm/reg.h>
29#include <asm/ppc_asm.h>
30#include <asm/asm-offsets.h>
31#include <asm/thread_info.h>
32#include <asm/ptrace.h>
Stephen Rothwelldc8f5712007-08-22 13:47:24 +100033#include <asm/cputable.h>
Stephen Rothwellfc68e862007-08-22 13:44:58 +100034
Stephen Rothwell7180e3e2007-08-22 13:48:37 +100035#include "exception.h"
36
Stephen Rothwellfc68e862007-08-22 13:44:58 +100037 .text
38
39 .globl system_reset_iSeries
40system_reset_iSeries:
Paul Mackerrase31aa452008-08-30 11:41:12 +100041 bl .relative_toc
Stephen Rothwell3eb9cf02008-04-10 16:39:18 +100042 mfspr r13,SPRN_SPRG3 /* Get alpaca address */
Paul Mackerrase31aa452008-08-30 11:41:12 +100043 LOAD_REG_ADDR(r23, alpaca)
Stephen Rothwell3eb9cf02008-04-10 16:39:18 +100044 li r0,ALPACA_SIZE
45 sub r23,r13,r23
46 divdu r23,r23,r0 /* r23 has cpu number */
Paul Mackerrase31aa452008-08-30 11:41:12 +100047 LOAD_REG_ADDR(r13, paca)
Stephen Rothwell3eb9cf02008-04-10 16:39:18 +100048 mulli r0,r23,PACA_SIZE
49 add r13,r13,r0
50 mtspr SPRN_SPRG3,r13 /* Save it away for the future */
Stephen Rothwellfc68e862007-08-22 13:44:58 +100051 mfmsr r24
52 ori r24,r24,MSR_RI
53 mtmsrd r24 /* RI on */
Stephen Rothwell3eb9cf02008-04-10 16:39:18 +100054 mr r24,r23
Stephen Rothwellfc68e862007-08-22 13:44:58 +100055 cmpwi 0,r24,0 /* Are we processor 0? */
56 bne 1f
57 b .__start_initialization_iSeries /* Start up the first processor */
581: mfspr r4,SPRN_CTRLF
59 li r5,CTRL_RUNLATCH /* Turn off the run light */
60 andc r4,r4,r5
61 mtspr SPRN_CTRLT,r4
62
Tony Breeds9cb82f22008-04-24 13:43:49 +100063/* Spin on __secondary_hold_spinloop until it is updated by the boot cpu. */
Paul Mackerrase31aa452008-08-30 11:41:12 +100064/* In the UP case we'll yield() later, and we will not access the paca anyway */
Tony Breeds9cb82f22008-04-24 13:43:49 +100065#ifdef CONFIG_SMP
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000661:
67 HMT_LOW
Paul Mackerrase31aa452008-08-30 11:41:12 +100068 LOAD_REG_ADDR(r23, __secondary_hold_spinloop)
Tony Breeds9cb82f22008-04-24 13:43:49 +100069 ld r23,0(r23)
70 sync
Paul Mackerrase31aa452008-08-30 11:41:12 +100071 LOAD_REG_ADDR(r3,current_set)
Tony Breeds9cb82f22008-04-24 13:43:49 +100072 sldi r28,r24,3 /* get current_set[cpu#] */
73 ldx r3,r3,r28
74 addi r1,r3,THREAD_SIZE
75 subi r1,r1,STACK_FRAME_OVERHEAD
76
77 cmpwi 0,r23,0 /* Keep poking the Hypervisor until */
78 bne 2f /* we're released */
79 /* Let the Hypervisor know we are alive */
80 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
81 lis r3,0x8002
82 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
83 li r0,-1 /* r0=-1 indicates a Hypervisor call */
84 sc /* Invoke the hypervisor via a system call */
85 b 1b
86#endif
87
882:
89 HMT_LOW
Stephen Rothwellfc68e862007-08-22 13:44:58 +100090#ifdef CONFIG_SMP
91 lbz r23,PACAPROCSTART(r13) /* Test if this processor
92 * should start */
93 sync
Paul Mackerrase31aa452008-08-30 11:41:12 +100094 LOAD_REG_ADDR(r3,current_set)
Stephen Rothwellfc68e862007-08-22 13:44:58 +100095 sldi r28,r24,3 /* get current_set[cpu#] */
96 ldx r3,r3,r28
97 addi r1,r3,THREAD_SIZE
98 subi r1,r1,STACK_FRAME_OVERHEAD
99
100 cmpwi 0,r23,0
101 beq iSeries_secondary_smp_loop /* Loop until told to go */
102 b __secondary_start /* Loop until told to go */
103iSeries_secondary_smp_loop:
104 /* Let the Hypervisor know we are alive */
105 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
106 lis r3,0x8002
107 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
108#else /* CONFIG_SMP */
109 /* Yield the processor. This is required for non-SMP kernels
110 which are running on multi-threaded machines. */
111 lis r3,0x8000
112 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
113 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
114 li r4,0 /* "yield timed" */
115 li r5,-1 /* "yield forever" */
116#endif /* CONFIG_SMP */
117 li r0,-1 /* r0=-1 indicates a Hypervisor call */
118 sc /* Invoke the hypervisor via a system call */
119 mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */
Tony Breeds9cb82f22008-04-24 13:43:49 +1000120 b 2b /* If SMP not configured, secondaries
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000121 * loop forever */
122
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000123/*** ISeries-LPAR interrupt handlers ***/
124
Stephen Rothwell5b072ba2007-08-22 13:49:41 +1000125 STD_EXCEPTION_ISERIES(machine_check, PACA_EXMC)
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000126
127 .globl data_access_iSeries
128data_access_iSeries:
129 mtspr SPRN_SPRG1,r13
130BEGIN_FTR_SECTION
131 mtspr SPRN_SPRG2,r12
132 mfspr r13,SPRN_DAR
133 mfspr r12,SPRN_DSISR
134 srdi r13,r13,60
135 rlwimi r13,r12,16,0x20
136 mfcr r12
137 cmpwi r13,0x2c
138 beq .do_stab_bolted_iSeries
139 mtcrf 0x80,r12
140 mfspr r12,SPRN_SPRG2
141END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
Stephen Rothwell7180e3e2007-08-22 13:48:37 +1000142 EXCEPTION_PROLOG_1(PACA_EXGEN)
143 EXCEPTION_PROLOG_ISERIES_1
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000144 b data_access_common
145
146.do_stab_bolted_iSeries:
147 mtcrf 0x80,r12
148 mfspr r12,SPRN_SPRG2
Stephen Rothwell7180e3e2007-08-22 13:48:37 +1000149 EXCEPTION_PROLOG_1(PACA_EXSLB)
150 EXCEPTION_PROLOG_ISERIES_1
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000151 b .do_stab_bolted
152
153 .globl data_access_slb_iSeries
154data_access_slb_iSeries:
155 mtspr SPRN_SPRG1,r13 /* save r13 */
156 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
157 std r3,PACA_EXSLB+EX_R3(r13)
158 mfspr r3,SPRN_DAR
159 std r9,PACA_EXSLB+EX_R9(r13)
160 mfcr r9
161#ifdef __DISABLED__
162 cmpdi r3,0
163 bge slb_miss_user_iseries
164#endif
165 std r10,PACA_EXSLB+EX_R10(r13)
166 std r11,PACA_EXSLB+EX_R11(r13)
167 std r12,PACA_EXSLB+EX_R12(r13)
168 mfspr r10,SPRN_SPRG1
169 std r10,PACA_EXSLB+EX_R13(r13)
170 ld r12,PACALPPACAPTR(r13)
171 ld r12,LPPACASRR1(r12)
172 b .slb_miss_realmode
173
Stephen Rothwell5b072ba2007-08-22 13:49:41 +1000174 STD_EXCEPTION_ISERIES(instruction_access, PACA_EXGEN)
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000175
176 .globl instruction_access_slb_iSeries
177instruction_access_slb_iSeries:
178 mtspr SPRN_SPRG1,r13 /* save r13 */
179 mfspr r13,SPRN_SPRG3 /* get paca address into r13 */
180 std r3,PACA_EXSLB+EX_R3(r13)
181 ld r3,PACALPPACAPTR(r13)
182 ld r3,LPPACASRR0(r3) /* get SRR0 value */
183 std r9,PACA_EXSLB+EX_R9(r13)
184 mfcr r9
185#ifdef __DISABLED__
186 cmpdi r3,0
187 bge slb_miss_user_iseries
188#endif
189 std r10,PACA_EXSLB+EX_R10(r13)
190 std r11,PACA_EXSLB+EX_R11(r13)
191 std r12,PACA_EXSLB+EX_R12(r13)
192 mfspr r10,SPRN_SPRG1
193 std r10,PACA_EXSLB+EX_R13(r13)
194 ld r12,PACALPPACAPTR(r13)
195 ld r12,LPPACASRR1(r12)
196 b .slb_miss_realmode
197
198#ifdef __DISABLED__
199slb_miss_user_iseries:
200 std r10,PACA_EXGEN+EX_R10(r13)
201 std r11,PACA_EXGEN+EX_R11(r13)
202 std r12,PACA_EXGEN+EX_R12(r13)
203 mfspr r10,SPRG1
204 ld r11,PACA_EXSLB+EX_R9(r13)
205 ld r12,PACA_EXSLB+EX_R3(r13)
206 std r10,PACA_EXGEN+EX_R13(r13)
207 std r11,PACA_EXGEN+EX_R9(r13)
208 std r12,PACA_EXGEN+EX_R3(r13)
Stephen Rothwell7180e3e2007-08-22 13:48:37 +1000209 EXCEPTION_PROLOG_ISERIES_1
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000210 b slb_miss_user_common
211#endif
212
Stephen Rothwell5b072ba2007-08-22 13:49:41 +1000213 MASKABLE_EXCEPTION_ISERIES(hardware_interrupt)
214 STD_EXCEPTION_ISERIES(alignment, PACA_EXGEN)
215 STD_EXCEPTION_ISERIES(program_check, PACA_EXGEN)
216 STD_EXCEPTION_ISERIES(fp_unavailable, PACA_EXGEN)
217 MASKABLE_EXCEPTION_ISERIES(decrementer)
218 STD_EXCEPTION_ISERIES(trap_0a, PACA_EXGEN)
219 STD_EXCEPTION_ISERIES(trap_0b, PACA_EXGEN)
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000220
221 .globl system_call_iSeries
222system_call_iSeries:
223 mr r9,r13
224 mfspr r13,SPRN_SPRG3
Stephen Rothwell7180e3e2007-08-22 13:48:37 +1000225 EXCEPTION_PROLOG_ISERIES_1
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000226 b system_call_common
227
Stephen Rothwell5b072ba2007-08-22 13:49:41 +1000228 STD_EXCEPTION_ISERIES(single_step, PACA_EXGEN)
229 STD_EXCEPTION_ISERIES(trap_0e, PACA_EXGEN)
230 STD_EXCEPTION_ISERIES(performance_monitor, PACA_EXGEN)
Stephen Rothwelldc8f5712007-08-22 13:47:24 +1000231
232decrementer_iSeries_masked:
233 /* We may not have a valid TOC pointer in here. */
234 li r11,1
235 ld r12,PACALPPACAPTR(r13)
236 stb r11,LPPACADECRINT(r12)
237 LOAD_REG_IMMEDIATE(r12, tb_ticks_per_jiffy)
238 lwz r12,0(r12)
239 mtspr SPRN_DEC,r12
240 /* fall through */
241
242hardware_interrupt_iSeries_masked:
243 mtcrf 0x80,r9 /* Restore regs */
244 ld r12,PACALPPACAPTR(r13)
245 ld r11,LPPACASRR0(r12)
246 ld r12,LPPACASRR1(r12)
247 mtspr SPRN_SRR0,r11
248 mtspr SPRN_SRR1,r12
249 ld r9,PACA_EXGEN+EX_R9(r13)
250 ld r10,PACA_EXGEN+EX_R10(r13)
251 ld r11,PACA_EXGEN+EX_R11(r13)
252 ld r12,PACA_EXGEN+EX_R12(r13)
253 ld r13,PACA_EXGEN+EX_R13(r13)
254 rfid
255 b . /* prevent speculative execution */
256
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000257_INIT_STATIC(__start_initialization_iSeries)
258 /* Clear out the BSS */
Paul Mackerrase31aa452008-08-30 11:41:12 +1000259 LOAD_REG_ADDR(r11,__bss_stop)
260 LOAD_REG_ADDR(r8,__bss_start)
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000261 sub r11,r11,r8 /* bss size */
262 addi r11,r11,7 /* round up to an even double word */
263 rldicl. r11,r11,61,3 /* shift right by 3 */
264 beq 4f
265 addi r8,r8,-8
266 li r0,0
267 mtctr r11 /* zero this many doublewords */
2683: stdu r0,8(r8)
269 bdnz 3b
2704:
Paul Mackerrase31aa452008-08-30 11:41:12 +1000271 LOAD_REG_ADDR(r1,init_thread_union)
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000272 addi r1,r1,THREAD_SIZE
273 li r0,0
274 stdu r0,-STACK_FRAME_OVERHEAD(r1)
275
Stephen Rothwellfc68e862007-08-22 13:44:58 +1000276 bl .iSeries_early_setup
277 bl .early_setup
278
279 /* relocation is on at this point */
280
281 b .start_here_common