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Ralf Baechle73b43902008-07-16 16:12:25 +01001/*
2 * Definitions for IDT RC323434 CPU.
3 */
4
5#ifndef _ASM_RC32434_RC32434_H_
6#define _ASM_RC32434_RC32434_H_
7
8#include <linux/delay.h>
9#include <linux/io.h>
10
11#define RC32434_REG_BASE 0x18000000
12#define RC32434_RST (1 << 15)
13
14#define IDT_CLOCK_MULT 2
15#define MIPS_CPU_TIMER_IRQ 7
16
17/* Interrupt Controller */
18#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
19#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
20#define IC_GROUP_OFFSET 0x0C
21
22#define NUM_INTR_GROUPS 5
23
24/* 16550 UARTs */
25#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
26 /* GRP3 IRQ numbers start here */
27#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32)
28 /* GRP4 IRQ numbers start here */
29#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32)
30 /* GRP5 IRQ numbers start here */
31#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32)
32#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
33
34
35#ifdef __MIPSEB__
36#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
37#else
38#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
39#endif
40
41#define RC32434_UART0_IRQ (GROUP3_IRQ_BASE + 0)
42
43/* cpu pipeline flush */
44static inline void rc32434_sync(void)
45{
46 __asm__ volatile ("sync");
47}
48
49static inline void rc32434_sync_udelay(int us)
50{
51 __asm__ volatile ("sync");
52 udelay(us);
53}
54
55static inline void rc32434_sync_delay(int ms)
56{
57 __asm__ volatile ("sync");
58 mdelay(ms);
59}
60
61#endif /* _ASM_RC32434_RC32434_H_ */