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LeafOS / LeafOS-Devices / android_kernel_samsung_exynos9820 / adc8d746caa67fff4b53ba3e5163a6cbacc3b523 / . / arch / mips / include / asm / mach-cavium-octeon / irq.h
blob: 5b05f186e3952744bb932508d631932209e9e530 [file] [log] [blame]
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __OCTEON_IRQ_H__
9#define __OCTEON_IRQ_H__
10
11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
David Daney0c326382011-03-25 12:38:51 -0700[diff] [blame]14enum octeon_irq {
15/* 1 - 8 represent the 8 MIPS standard interrupt sources */
16 OCTEON_IRQ_SW0 = 1,
17 OCTEON_IRQ_SW1,
18/* CIU0, CUI2, CIU4 are 3, 4, 5 */
19 OCTEON_IRQ_5 = 6,
20 OCTEON_IRQ_PERF,
21 OCTEON_IRQ_TIMER,
22/* sources in CIU_INTX_EN0 */
23 OCTEON_IRQ_WORKQ0,
24 OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
25 OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
26 OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
27 OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
28 OCTEON_IRQ_MBOX1,
29 OCTEON_IRQ_UART0,
30 OCTEON_IRQ_UART1,
31 OCTEON_IRQ_UART2,
32 OCTEON_IRQ_PCI_INT0,
33 OCTEON_IRQ_PCI_INT1,
34 OCTEON_IRQ_PCI_INT2,
35 OCTEON_IRQ_PCI_INT3,
36 OCTEON_IRQ_PCI_MSI0,
37 OCTEON_IRQ_PCI_MSI1,
38 OCTEON_IRQ_PCI_MSI2,
39 OCTEON_IRQ_PCI_MSI3,
40
41 OCTEON_IRQ_TWSI,
42 OCTEON_IRQ_TWSI2,
43 OCTEON_IRQ_RML,
44 OCTEON_IRQ_TRACE0,
45 OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
46 OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
47 OCTEON_IRQ_KEY_ZERO,
48 OCTEON_IRQ_TIMER0,
49 OCTEON_IRQ_TIMER1,
50 OCTEON_IRQ_TIMER2,
51 OCTEON_IRQ_TIMER3,
52 OCTEON_IRQ_USB0,
53 OCTEON_IRQ_USB1,
54 OCTEON_IRQ_PCM,
55 OCTEON_IRQ_MPI,
56 OCTEON_IRQ_POWIQ,
57 OCTEON_IRQ_IPDPPTHR,
58 OCTEON_IRQ_MII0,
59 OCTEON_IRQ_MII1,
60 OCTEON_IRQ_BOOTDMA,
61
62 OCTEON_IRQ_NAND,
63 OCTEON_IRQ_MIO, /* Summary of MIO_BOOT_ERR */
64 OCTEON_IRQ_IOB, /* Summary of IOB_INT_SUM */
65 OCTEON_IRQ_FPA, /* Summary of FPA_INT_SUM */
66 OCTEON_IRQ_POW, /* Summary of POW_ECC_ERR */
67 OCTEON_IRQ_L2C, /* Summary of L2C_INT_STAT */
68 OCTEON_IRQ_IPD, /* Summary of IPD_INT_SUM */
69 OCTEON_IRQ_PIP, /* Summary of PIP_INT_REG */
70 OCTEON_IRQ_PKO, /* Summary of PKO_REG_ERROR */
71 OCTEON_IRQ_ZIP, /* Summary of ZIP_ERROR */
72 OCTEON_IRQ_TIM, /* Summary of TIM_REG_ERROR */
73 OCTEON_IRQ_RAD, /* Summary of RAD_REG_ERROR */
74 OCTEON_IRQ_KEY, /* Summary of KEY_INT_SUM */
75 OCTEON_IRQ_DFA, /* Summary of DFA */
76 OCTEON_IRQ_USBCTL, /* Summary of USBN0_INT_SUM */
77 OCTEON_IRQ_SLI, /* Summary of SLI_INT_SUM */
78 OCTEON_IRQ_DPI, /* Summary of DPI_INT_SUM */
79 OCTEON_IRQ_AGX0, /* Summary of GMX0*+PCS0_INT*_REG */
80 OCTEON_IRQ_AGL = OCTEON_IRQ_AGX0 + 5,
81 OCTEON_IRQ_PTP,
82 OCTEON_IRQ_PEM0,
83 OCTEON_IRQ_PEM1,
84 OCTEON_IRQ_SRIO0,
85 OCTEON_IRQ_SRIO1,
86 OCTEON_IRQ_LMC0,
87 OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4, /* Summary of DFM */
88 OCTEON_IRQ_RST,
89};
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]90
91#ifdef CONFIG_PCI_MSI
David Daney0c326382011-03-25 12:38:51 -0700[diff] [blame]92/* 152 - 407 represent the MSI interrupts 0-255 */
93#define OCTEON_IRQ_MSI_BIT0 (OCTEON_IRQ_RST + 1)
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]94
David Daney0c326382011-03-25 12:38:51 -0700[diff] [blame]95#define OCTEON_IRQ_MSI_LAST (OCTEON_IRQ_MSI_BIT0 + 255)
96#define OCTEON_IRQ_LAST (OCTEON_IRQ_MSI_LAST + 1)
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]97#else
David Daney0c326382011-03-25 12:38:51 -0700[diff] [blame]98#define OCTEON_IRQ_LAST (OCTEON_IRQ_RST + 1)
David Daney5b3b1682009-01-08 16:46:40 -0800[diff] [blame]99#endif
100
101#endif