blob: bd0f33b77f5728781f558414eebf1eb02055a78d [file] [log] [blame]
Andre Przywara6bc37fa2016-01-18 10:24:31 +00001/*
2 * Copyright (C) 2016 ARM Ltd.
3 * based on the Allwinner H3 dtsi:
4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
Icenowy Zhenga004ee32016-11-22 23:58:29 +080045#include <dt-bindings/clock/sun50i-a64-ccu.h>
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +080046#include <dt-bindings/clock/sun8i-r-ccu.h>
Andre Przywara6bc37fa2016-01-18 10:24:31 +000047#include <dt-bindings/interrupt-controller/arm-gic.h>
Icenowy Zhenga004ee32016-11-22 23:58:29 +080048#include <dt-bindings/reset/sun50i-a64-ccu.h>
Andre Przywara6bc37fa2016-01-18 10:24:31 +000049
50/ {
51 interrupt-parent = <&gic>;
52 #address-cells = <1>;
53 #size-cells = <1>;
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu0: cpu@0 {
60 compatible = "arm,cortex-a53", "arm,armv8";
61 device_type = "cpu";
62 reg = <0>;
63 enable-method = "psci";
64 };
65
66 cpu1: cpu@1 {
67 compatible = "arm,cortex-a53", "arm,armv8";
68 device_type = "cpu";
69 reg = <1>;
70 enable-method = "psci";
71 };
72
73 cpu2: cpu@2 {
74 compatible = "arm,cortex-a53", "arm,armv8";
75 device_type = "cpu";
76 reg = <2>;
77 enable-method = "psci";
78 };
79
80 cpu3: cpu@3 {
81 compatible = "arm,cortex-a53", "arm,armv8";
82 device_type = "cpu";
83 reg = <3>;
84 enable-method = "psci";
85 };
86 };
87
88 osc24M: osc24M_clk {
89 #clock-cells = <0>;
90 compatible = "fixed-clock";
91 clock-frequency = <24000000>;
92 clock-output-names = "osc24M";
93 };
94
95 osc32k: osc32k_clk {
96 #clock-cells = <0>;
97 compatible = "fixed-clock";
98 clock-frequency = <32768>;
99 clock-output-names = "osc32k";
100 };
101
Icenowy Zheng791a9e02017-04-04 17:50:58 +0800102 iosc: internal-osc-clk {
103 #clock-cells = <0>;
104 compatible = "fixed-clock";
105 clock-frequency = <16000000>;
106 clock-accuracy = <300000000>;
107 clock-output-names = "iosc";
108 };
109
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000110 psci {
111 compatible = "arm,psci-0.2";
112 method = "smc";
113 };
114
115 timer {
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13
118 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
119 <GIC_PPI 14
120 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11
122 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
123 <GIC_PPI 10
124 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
125 };
126
127 soc {
128 compatible = "simple-bus";
129 #address-cells = <1>;
130 #size-cells = <1>;
131 ranges;
132
Corentin Labbe79b95362017-05-31 09:18:45 +0200133 syscon: syscon@1c00000 {
134 compatible = "allwinner,sun50i-a64-system-controller",
135 "syscon";
136 reg = <0x01c00000 0x1000>;
137 };
138
Andre Przywaraf3dff342016-10-06 02:25:22 +0100139 mmc0: mmc@1c0f000 {
140 compatible = "allwinner,sun50i-a64-mmc";
141 reg = <0x01c0f000 0x1000>;
142 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
143 clock-names = "ahb", "mmc";
144 resets = <&ccu RST_BUS_MMC0>;
145 reset-names = "ahb";
146 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard22be9922017-01-09 15:53:59 +0100147 max-frequency = <150000000>;
Andre Przywaraf3dff342016-10-06 02:25:22 +0100148 status = "disabled";
149 #address-cells = <1>;
150 #size-cells = <0>;
151 };
152
153 mmc1: mmc@1c10000 {
154 compatible = "allwinner,sun50i-a64-mmc";
155 reg = <0x01c10000 0x1000>;
156 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
157 clock-names = "ahb", "mmc";
158 resets = <&ccu RST_BUS_MMC1>;
159 reset-names = "ahb";
160 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard22be9922017-01-09 15:53:59 +0100161 max-frequency = <150000000>;
Andre Przywaraf3dff342016-10-06 02:25:22 +0100162 status = "disabled";
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
167 mmc2: mmc@1c11000 {
168 compatible = "allwinner,sun50i-a64-emmc";
169 reg = <0x01c11000 0x1000>;
170 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
171 clock-names = "ahb", "mmc";
172 resets = <&ccu RST_BUS_MMC2>;
173 reset-names = "ahb";
174 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
Maxime Ripard22be9922017-01-09 15:53:59 +0100175 max-frequency = <200000000>;
Andre Przywaraf3dff342016-10-06 02:25:22 +0100176 status = "disabled";
177 #address-cells = <1>;
178 #size-cells = <0>;
179 };
180
Icenowy Zheng972a3ec2016-11-23 00:59:01 +0800181 usb_otg: usb@01c19000 {
182 compatible = "allwinner,sun8i-a33-musb";
183 reg = <0x01c19000 0x0400>;
184 clocks = <&ccu CLK_BUS_OTG>;
185 resets = <&ccu RST_BUS_OTG>;
186 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
187 interrupt-names = "mc";
188 phys = <&usbphy 0>;
189 phy-names = "usb";
190 extcon = <&usbphy 0>;
191 status = "disabled";
192 };
193
Icenowy Zhenga004ee32016-11-22 23:58:29 +0800194 usbphy: phy@01c19400 {
195 compatible = "allwinner,sun50i-a64-usb-phy";
196 reg = <0x01c19400 0x14>,
Icenowy Zheng0d984792017-04-05 22:30:34 +0800197 <0x01c1a800 0x4>,
Icenowy Zhenga004ee32016-11-22 23:58:29 +0800198 <0x01c1b800 0x4>;
199 reg-names = "phy_ctrl",
Icenowy Zheng0d984792017-04-05 22:30:34 +0800200 "pmu0",
Icenowy Zhenga004ee32016-11-22 23:58:29 +0800201 "pmu1";
202 clocks = <&ccu CLK_USB_PHY0>,
203 <&ccu CLK_USB_PHY1>;
204 clock-names = "usb0_phy",
205 "usb1_phy";
206 resets = <&ccu RST_USB_PHY0>,
207 <&ccu RST_USB_PHY1>;
208 reset-names = "usb0_reset",
209 "usb1_reset";
210 status = "disabled";
211 #phy-cells = <1>;
212 };
213
Icenowy Zhengdc03a042017-04-14 21:15:54 +0800214 ehci0: usb@01c1a000 {
215 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
216 reg = <0x01c1a000 0x100>;
217 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&ccu CLK_BUS_OHCI0>,
219 <&ccu CLK_BUS_EHCI0>,
220 <&ccu CLK_USB_OHCI0>;
221 resets = <&ccu RST_BUS_OHCI0>,
222 <&ccu RST_BUS_EHCI0>;
223 status = "disabled";
224 };
225
226 ohci0: usb@01c1a400 {
227 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
228 reg = <0x01c1a400 0x100>;
229 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
230 clocks = <&ccu CLK_BUS_OHCI0>,
231 <&ccu CLK_USB_OHCI0>;
232 resets = <&ccu RST_BUS_OHCI0>;
233 status = "disabled";
234 };
235
Icenowy Zhenga004ee32016-11-22 23:58:29 +0800236 ehci1: usb@01c1b000 {
237 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
238 reg = <0x01c1b000 0x100>;
239 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&ccu CLK_BUS_OHCI1>,
241 <&ccu CLK_BUS_EHCI1>,
242 <&ccu CLK_USB_OHCI1>;
243 resets = <&ccu RST_BUS_OHCI1>,
244 <&ccu RST_BUS_EHCI1>;
245 phys = <&usbphy 1>;
246 phy-names = "usb";
247 status = "disabled";
248 };
249
250 ohci1: usb@01c1b400 {
251 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
252 reg = <0x01c1b400 0x100>;
253 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&ccu CLK_BUS_OHCI1>,
255 <&ccu CLK_USB_OHCI1>;
256 resets = <&ccu RST_BUS_OHCI1>;
257 phys = <&usbphy 1>;
258 phy-names = "usb";
259 status = "disabled";
260 };
261
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000262 ccu: clock@01c20000 {
263 compatible = "allwinner,sun50i-a64-ccu";
264 reg = <0x01c20000 0x400>;
265 clocks = <&osc24M>, <&osc32k>;
266 clock-names = "hosc", "losc";
267 #clock-cells = <1>;
268 #reset-cells = <1>;
269 };
270
271 pio: pinctrl@1c20800 {
272 compatible = "allwinner,sun50i-a64-pinctrl";
273 reg = <0x01c20800 0x400>;
274 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
Arnd Bergmannf98121f2016-11-30 15:08:55 +0100277 clocks = <&ccu 58>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000278 gpio-controller;
279 #gpio-cells = <3>;
280 interrupt-controller;
281 #interrupt-cells = <3>;
282
283 i2c1_pins: i2c1_pins {
284 pins = "PH2", "PH3";
285 function = "i2c1";
286 };
287
Maxime Riparda3e8f492017-01-09 16:39:15 +0100288 mmc0_pins: mmc0-pins {
289 pins = "PF0", "PF1", "PF2", "PF3",
290 "PF4", "PF5";
291 function = "mmc0";
292 drive-strength = <30>;
293 bias-pull-up;
294 };
295
296 mmc1_pins: mmc1-pins {
297 pins = "PG0", "PG1", "PG2", "PG3",
298 "PG4", "PG5";
299 function = "mmc1";
300 drive-strength = <30>;
301 bias-pull-up;
302 };
303
304 mmc2_pins: mmc2-pins {
305 pins = "PC1", "PC5", "PC6", "PC8", "PC9",
306 "PC10","PC11", "PC12", "PC13",
307 "PC14", "PC15", "PC16";
308 function = "mmc2";
309 drive-strength = <30>;
310 bias-pull-up;
311 };
312
Corentin Labbee53f67e2017-05-31 09:18:46 +0200313 rmii_pins: rmii_pins {
314 pins = "PD10", "PD11", "PD13", "PD14", "PD17",
315 "PD18", "PD19", "PD20", "PD22", "PD23";
316 function = "emac";
317 drive-strength = <40>;
318 };
319
320 rgmii_pins: rgmii_pins {
321 pins = "PD8", "PD9", "PD10", "PD11", "PD12",
322 "PD13", "PD15", "PD16", "PD17", "PD18",
323 "PD19", "PD20", "PD21", "PD22", "PD23";
324 function = "emac";
325 drive-strength = <40>;
326 };
327
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000328 uart0_pins_a: uart0@0 {
329 pins = "PB8", "PB9";
330 function = "uart0";
331 };
Andre Przywarae7ba7332017-01-10 01:22:32 +0000332
333 uart1_pins: uart1_pins {
334 pins = "PG6", "PG7";
335 function = "uart1";
336 };
337
338 uart1_rts_cts_pins: uart1_rts_cts_pins {
339 pins = "PG8", "PG9";
340 function = "uart1";
341 };
Andreas Färber79825712017-04-14 19:13:20 +0200342
343 uart2_pins: uart2-pins {
344 pins = "PB0", "PB1";
345 function = "uart2";
346 };
Andreas Färber2273aa12017-04-18 21:25:38 +0200347
348 uart3_pins: uart3-pins {
349 pins = "PD0", "PD1";
350 function = "uart3";
351 };
352
353 uart4_pins: uart4-pins {
354 pins = "PD2", "PD3";
355 function = "uart4";
356 };
357
358 uart4_rts_cts_pins: uart4-rts-cts-pins {
359 pins = "PD4", "PD5";
360 function = "uart4";
361 };
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000362 };
363
364 uart0: serial@1c28000 {
365 compatible = "snps,dw-apb-uart";
366 reg = <0x01c28000 0x400>;
367 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
368 reg-shift = <2>;
369 reg-io-width = <4>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800370 clocks = <&ccu CLK_BUS_UART0>;
371 resets = <&ccu RST_BUS_UART0>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000372 status = "disabled";
373 };
374
375 uart1: serial@1c28400 {
376 compatible = "snps,dw-apb-uart";
377 reg = <0x01c28400 0x400>;
378 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
379 reg-shift = <2>;
380 reg-io-width = <4>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800381 clocks = <&ccu CLK_BUS_UART1>;
382 resets = <&ccu RST_BUS_UART1>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000383 status = "disabled";
384 };
385
386 uart2: serial@1c28800 {
387 compatible = "snps,dw-apb-uart";
388 reg = <0x01c28800 0x400>;
389 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
390 reg-shift = <2>;
391 reg-io-width = <4>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800392 clocks = <&ccu CLK_BUS_UART2>;
393 resets = <&ccu RST_BUS_UART2>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000394 status = "disabled";
395 };
396
397 uart3: serial@1c28c00 {
398 compatible = "snps,dw-apb-uart";
399 reg = <0x01c28c00 0x400>;
400 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
401 reg-shift = <2>;
402 reg-io-width = <4>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800403 clocks = <&ccu CLK_BUS_UART3>;
404 resets = <&ccu RST_BUS_UART3>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000405 status = "disabled";
406 };
407
408 uart4: serial@1c29000 {
409 compatible = "snps,dw-apb-uart";
410 reg = <0x01c29000 0x400>;
411 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
412 reg-shift = <2>;
413 reg-io-width = <4>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800414 clocks = <&ccu CLK_BUS_UART4>;
415 resets = <&ccu RST_BUS_UART4>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000416 status = "disabled";
417 };
418
419 i2c0: i2c@1c2ac00 {
420 compatible = "allwinner,sun6i-a31-i2c";
421 reg = <0x01c2ac00 0x400>;
422 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800423 clocks = <&ccu CLK_BUS_I2C0>;
424 resets = <&ccu RST_BUS_I2C0>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000425 status = "disabled";
426 #address-cells = <1>;
427 #size-cells = <0>;
428 };
429
430 i2c1: i2c@1c2b000 {
431 compatible = "allwinner,sun6i-a31-i2c";
432 reg = <0x01c2b000 0x400>;
433 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800434 clocks = <&ccu CLK_BUS_I2C1>;
435 resets = <&ccu RST_BUS_I2C1>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000436 status = "disabled";
437 #address-cells = <1>;
438 #size-cells = <0>;
439 };
440
441 i2c2: i2c@1c2b400 {
442 compatible = "allwinner,sun6i-a31-i2c";
443 reg = <0x01c2b400 0x400>;
444 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800445 clocks = <&ccu CLK_BUS_I2C2>;
446 resets = <&ccu RST_BUS_I2C2>;
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000447 status = "disabled";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 };
451
Corentin Labbee53f67e2017-05-31 09:18:46 +0200452 emac: ethernet@1c30000 {
453 compatible = "allwinner,sun50i-a64-emac";
454 syscon = <&syscon>;
Corentin Labbe3a4bae52017-07-10 20:44:40 +0200455 reg = <0x01c30000 0x10000>;
Corentin Labbee53f67e2017-05-31 09:18:46 +0200456 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
457 interrupt-names = "macirq";
458 resets = <&ccu RST_BUS_EMAC>;
459 reset-names = "stmmaceth";
460 clocks = <&ccu CLK_BUS_EMAC>;
461 clock-names = "stmmaceth";
462 status = "disabled";
463 #address-cells = <1>;
464 #size-cells = <0>;
465
466 mdio: mdio {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 };
470 };
471
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000472 gic: interrupt-controller@1c81000 {
473 compatible = "arm,gic-400";
474 reg = <0x01c81000 0x1000>,
475 <0x01c82000 0x2000>,
476 <0x01c84000 0x2000>,
477 <0x01c86000 0x2000>;
478 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
479 interrupt-controller;
480 #interrupt-cells = <3>;
481 };
482
483 rtc: rtc@1f00000 {
484 compatible = "allwinner,sun6i-a31-rtc";
485 reg = <0x01f00000 0x54>;
486 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
488 };
Icenowy Zheng791a9e02017-04-04 17:50:58 +0800489
490 r_ccu: clock@1f01400 {
491 compatible = "allwinner,sun50i-a64-r-ccu";
492 reg = <0x01f01400 0x100>;
Chen-Yu Tsaif74994a2017-05-31 15:58:24 +0800493 clocks = <&osc24M>, <&osc32k>, <&iosc>,
494 <&ccu 11>;
495 clock-names = "hosc", "losc", "iosc", "pll-periph";
Icenowy Zheng791a9e02017-04-04 17:50:58 +0800496 #clock-cells = <1>;
497 #reset-cells = <1>;
498 };
Icenowy Zhengec427902017-04-04 17:51:00 +0800499
500 r_pio: pinctrl@01f02c00 {
501 compatible = "allwinner,sun50i-a64-r-pinctrl";
502 reg = <0x01f02c00 0x400>;
503 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsai494d8a22017-06-05 17:00:33 +0800504 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
Icenowy Zhengec427902017-04-04 17:51:00 +0800505 clock-names = "apb", "hosc", "losc";
506 gpio-controller;
507 #gpio-cells = <3>;
508 interrupt-controller;
509 #interrupt-cells = <3>;
Icenowy Zheng3b38fde2017-04-17 19:57:36 +0800510
511 r_rsb_pins: rsb@0 {
512 pins = "PL0", "PL1";
513 function = "s_rsb";
514 };
515 };
516
517 r_rsb: rsb@1f03400 {
518 compatible = "allwinner,sun8i-a23-rsb";
519 reg = <0x01f03400 0x400>;
520 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&r_ccu 6>;
522 clock-frequency = <3000000>;
523 resets = <&r_ccu 2>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&r_rsb_pins>;
526 status = "disabled";
527 #address-cells = <1>;
528 #size-cells = <0>;
Icenowy Zhengec427902017-04-04 17:51:00 +0800529 };
Andre Przywara6bc37fa2016-01-18 10:24:31 +0000530 };
531};