blob: 9fa8aa051f54b235ed516d32e2eca2c3c9d62b5e [file] [log] [blame]
Ingo Molnarc140df92008-01-30 13:30:09 +01001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Firmware replacement code.
Ingo Molnarc140df92008-01-30 13:30:09 +01003 *
Pavel Machek8caac562008-11-26 17:15:27 +01004 * Work around broken BIOSes that don't set an aperture, only set the
5 * aperture in the AGP bridge, or set too small aperture.
6 *
Ingo Molnarc140df92008-01-30 13:30:09 +01007 * If all fails map the aperture over some low memory. This is cheaper than
8 * doing bounce buffering. The memory is lost. This is done at early boot
9 * because only the bootmem allocator can allocate 32+MB.
10 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070011 * Copyright 2002 Andi Kleen, SuSE Labs.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080016#include <linux/memblock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/mmzone.h>
18#include <linux/pci_ids.h>
19#include <linux/pci.h>
20#include <linux/bitops.h>
Pavel Machek2050d452008-03-13 23:05:41 +010021#include <linux/suspend.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070022#include <asm/e820.h>
23#include <asm/io.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090024#include <asm/iommu.h>
Joerg Roedel395624f2007-10-24 12:49:47 +020025#include <asm/gart.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070026#include <asm/pci-direct.h>
Andi Kleenca8642f2006-01-11 22:44:27 +010027#include <asm/dma.h>
Andreas Herrmann23ac4ae2010-09-17 18:03:43 +020028#include <asm/amd_nb.h>
FUJITA Tomonoride957622009-11-10 19:46:14 +090029#include <asm/x86_init.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Joerg Roedelc387aa32011-04-18 15:45:43 +020031/*
32 * Using 512M as goal, in case kexec will load kernel_big
33 * that will do the on-position decompress, and could overlap with
34 * with the gart aperture that is used.
35 * Sequence:
36 * kernel_small
37 * ==> kexec (with kdump trigger path or gart still enabled)
38 * ==> kernel_small (gart area become e820_reserved)
39 * ==> kexec (with kdump trigger path or gart still enabled)
40 * ==> kerne_big (uncompressed size will be big than 64M or 128M)
41 * So don't use 512M below as gart iommu, leave the space for kernel
42 * code for safe.
43 */
44#define GART_MIN_ADDR (512ULL << 20)
45#define GART_MAX_ADDR (1ULL << 32)
46
Joerg Roedel0440d4c2007-10-24 12:49:50 +020047int gart_iommu_aperture;
Pavel Machek7de6a4c2008-03-13 11:03:58 +010048int gart_iommu_aperture_disabled __initdata;
49int gart_iommu_aperture_allowed __initdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51int fallback_aper_order __initdata = 1; /* 64MB */
Pavel Machek7de6a4c2008-03-13 11:03:58 +010052int fallback_aper_force __initdata;
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
54int fix_aperture __initdata = 1;
55
Andrew Morton42442ed2005-06-08 15:49:25 -070056/* This code runs before the PCI subsystem is initialized, so just
57 access the northbridge directly. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070058
Ingo Molnarc140df92008-01-30 13:30:09 +010059static u32 __init allocate_aperture(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070060{
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 u32 aper_size;
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080062 unsigned long addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070063
Yinghai Lu7677b2e2008-04-14 20:40:37 -070064 /* aper_size should <= 1G */
65 if (fallback_aper_order > 5)
66 fallback_aper_order = 5;
Ingo Molnarc140df92008-01-30 13:30:09 +010067 aper_size = (32 * 1024 * 1024) << fallback_aper_order;
Linus Torvalds1da177e2005-04-16 15:20:36 -070068
Ingo Molnarc140df92008-01-30 13:30:09 +010069 /*
70 * Aperture has to be naturally aligned. This means a 2GB aperture
71 * won't have much chance of finding a place in the lower 4GB of
72 * memory. Unfortunately we cannot move it up because that would
73 * make the IOMMU useless.
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 */
Joerg Roedelc387aa32011-04-18 15:45:43 +020075 addr = memblock_find_in_range(GART_MIN_ADDR, GART_MAX_ADDR,
76 aper_size, aper_size);
Wang YanQing26bfc542013-04-16 09:37:34 +080077 if (!addr) {
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080078 printk(KERN_ERR
79 "Cannot allocate aperture memory hole (%lx,%uK)\n",
80 addr, aper_size>>10);
81 return 0;
82 }
Tejun Heo24aa0782011-07-12 11:16:06 +020083 memblock_reserve(addr, aper_size);
Ingo Molnar31183ba2008-01-30 13:30:10 +010084 printk(KERN_INFO "Mapping aperture over %d KB of RAM @ %lx\n",
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080085 aper_size >> 10, addr);
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080086 register_nosave_region(addr >> PAGE_SHIFT,
87 (addr+aper_size) >> PAGE_SHIFT);
Ingo Molnarc140df92008-01-30 13:30:09 +010088
Yinghai Lu32e3f2b2010-12-17 16:58:40 -080089 return (u32)addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -070090}
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
Andrew Morton42442ed2005-06-08 15:49:25 -070093/* Find a PCI capability */
Pavel Machekdd564d02008-05-27 18:03:56 +020094static u32 __init find_cap(int bus, int slot, int func, int cap)
Ingo Molnarc140df92008-01-30 13:30:09 +010095{
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 int bytes;
Ingo Molnarc140df92008-01-30 13:30:09 +010097 u8 pos;
98
Yinghai Lu55c0d722008-04-19 01:31:11 -070099 if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
Ingo Molnarc140df92008-01-30 13:30:09 +0100100 PCI_STATUS_CAP_LIST))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100102
Yinghai Lu55c0d722008-04-19 01:31:11 -0700103 pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
Ingo Molnarc140df92008-01-30 13:30:09 +0100104 for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 u8 id;
Ingo Molnarc140df92008-01-30 13:30:09 +0100106
107 pos &= ~3;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700108 id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 if (id == 0xff)
110 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100111 if (id == cap)
112 return pos;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700113 pos = read_pci_config_byte(bus, slot, func,
Ingo Molnarc140df92008-01-30 13:30:09 +0100114 pos+PCI_CAP_LIST_NEXT);
115 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100117}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118
119/* Read a standard AGPv3 bridge header */
Pavel Machekdd564d02008-05-27 18:03:56 +0200120static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
Ingo Molnarc140df92008-01-30 13:30:09 +0100121{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 u32 apsize;
123 u32 apsizereg;
124 int nbits;
125 u32 aper_low, aper_hi;
126 u64 aper;
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700127 u32 old_order;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128
Yinghai Lu55c0d722008-04-19 01:31:11 -0700129 printk(KERN_INFO "AGP bridge at %02x:%02x:%02x\n", bus, slot, func);
130 apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 if (apsizereg == 0xffffffff) {
Ingo Molnar31183ba2008-01-30 13:30:10 +0100132 printk(KERN_ERR "APSIZE in AGP bridge unreadable\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 return 0;
134 }
135
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700136 /* old_order could be the value from NB gart setting */
137 old_order = *order;
138
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 apsize = apsizereg & 0xfff;
140 /* Some BIOS use weird encodings not in the AGPv3 table. */
Ingo Molnarc140df92008-01-30 13:30:09 +0100141 if (apsize & 0xff)
142 apsize |= 0xf00;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143 nbits = hweight16(apsize);
144 *order = 7 - nbits;
145 if ((int)*order < 0) /* < 32MB */
146 *order = 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100147
Yinghai Lu55c0d722008-04-19 01:31:11 -0700148 aper_low = read_pci_config(bus, slot, func, 0x10);
149 aper_hi = read_pci_config(bus, slot, func, 0x14);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700150 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
151
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700152 /*
153 * On some sick chips, APSIZE is 0. It means it wants 4G
154 * so let double check that order, and lets trust AMD NB settings:
155 */
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700156 printk(KERN_INFO "Aperture from AGP @ %Lx old size %u MB\n",
157 aper, 32 << old_order);
158 if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
Yinghai Lu1edc1ab2008-04-13 01:11:41 -0700159 printk(KERN_INFO "Aperture size %u MB (APSIZE %x) is not right, using settings from NB\n",
160 32 << *order, apsizereg);
161 *order = old_order;
162 }
163
Ingo Molnar31183ba2008-01-30 13:30:10 +0100164 printk(KERN_INFO "Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
165 aper, 32 << *order, apsizereg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700167 if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
Ingo Molnarc140df92008-01-30 13:30:09 +0100168 return 0;
169 return (u32)aper;
170}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171
Ingo Molnarc140df92008-01-30 13:30:09 +0100172/*
173 * Look for an AGP bridge. Windows only expects the aperture in the
174 * AGP bridge and some BIOS forget to initialize the Northbridge too.
175 * Work around this here.
176 *
177 * Do an PCI bus scan by hand because we're running before the PCI
178 * subsystem.
179 *
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200180 * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
Ingo Molnarc140df92008-01-30 13:30:09 +0100181 * generically. It's probably overkill to always scan all slots because
182 * the AGP bridges should be always an own bus on the HT hierarchy,
183 * but do it here for future safety.
184 */
Pavel Machekdd564d02008-05-27 18:03:56 +0200185static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186{
Yinghai Lu55c0d722008-04-19 01:31:11 -0700187 int bus, slot, func;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188
189 /* Poor man's PCI discovery */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700190 for (bus = 0; bus < 256; bus++) {
Ingo Molnarc140df92008-01-30 13:30:09 +0100191 for (slot = 0; slot < 32; slot++) {
192 for (func = 0; func < 8; func++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 u32 class, cap;
194 u8 type;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700195 class = read_pci_config(bus, slot, func,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 PCI_CLASS_REVISION);
197 if (class == 0xffffffff)
Ingo Molnarc140df92008-01-30 13:30:09 +0100198 break;
199
200 switch (class >> 16) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 case PCI_CLASS_BRIDGE_HOST:
202 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
203 /* AGP bridge? */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700204 cap = find_cap(bus, slot, func,
Ingo Molnarc140df92008-01-30 13:30:09 +0100205 PCI_CAP_ID_AGP);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 if (!cap)
207 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100208 *valid_agp = 1;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700209 return read_agp(bus, slot, func, cap,
Ingo Molnarc140df92008-01-30 13:30:09 +0100210 order);
211 }
212
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213 /* No multi-function device? */
Yinghai Lu55c0d722008-04-19 01:31:11 -0700214 type = read_pci_config_byte(bus, slot, func,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215 PCI_HEADER_TYPE);
216 if (!(type & 0x80))
217 break;
Ingo Molnarc140df92008-01-30 13:30:09 +0100218 }
219 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220 }
Ingo Molnar31183ba2008-01-30 13:30:10 +0100221 printk(KERN_INFO "No AGP bridge found\n");
Ingo Molnarc140df92008-01-30 13:30:09 +0100222
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223 return 0;
224}
225
Yinghai Luaaf23042008-01-30 13:33:09 +0100226static int gart_fix_e820 __initdata = 1;
227
228static int __init parse_gart_mem(char *p)
229{
230 if (!p)
231 return -EINVAL;
232
233 if (!strncmp(p, "off", 3))
234 gart_fix_e820 = 0;
235 else if (!strncmp(p, "on", 2))
236 gart_fix_e820 = 1;
237
238 return 0;
239}
240early_param("gart_fix_e820", parse_gart_mem);
241
242void __init early_gart_iommu_check(void)
243{
244 /*
245 * in case it is enabled before, esp for kexec/kdump,
246 * previous kernel already enable that. memset called
247 * by allocate_aperture/__alloc_bootmem_nopanic cause restart.
248 * or second kernel have different position for GART hole. and new
249 * kernel could use hole as RAM that is still used by GART set by
250 * first kernel
251 * or BIOS forget to put that in reserved.
252 * try to update e820 to make that region as reserved.
253 */
Andi Kleenfa10ba62010-07-20 15:19:49 -0700254 u32 agp_aper_order = 0;
Yinghai Luf3eee542009-12-14 11:52:15 +0900255 int i, fix, slot, valid_agp = 0;
Yinghai Luaaf23042008-01-30 13:33:09 +0100256 u32 ctl;
257 u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
258 u64 aper_base = 0, last_aper_base = 0;
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200259 int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
Yinghai Luaaf23042008-01-30 13:33:09 +0100260
261 if (!early_pci_allowed())
262 return;
263
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200264 /* This is mostly duplicate of iommu_hole_init */
Andi Kleenfa10ba62010-07-20 15:19:49 -0700265 search_agp_bridge(&agp_aper_order, &valid_agp);
Yinghai Luf3eee542009-12-14 11:52:15 +0900266
Yinghai Luaaf23042008-01-30 13:33:09 +0100267 fix = 0;
Jan Beulich24d9b702011-01-10 16:20:23 +0000268 for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700269 int bus;
270 int dev_base, dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100271
Jan Beulich24d9b702011-01-10 16:20:23 +0000272 bus = amd_nb_bus_dev_ranges[i].bus;
273 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
274 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100275
Yinghai Lu55c0d722008-04-19 01:31:11 -0700276 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200277 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700278 continue;
279
280 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
Borislav Petkov57ab43e2010-09-03 18:39:39 +0200281 aper_enabled = ctl & GARTEN;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700282 aper_order = (ctl >> 1) & 7;
283 aper_size = (32 * 1024 * 1024) << aper_order;
284 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
285 aper_base <<= 25;
286
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200287 if (last_valid) {
288 if ((aper_order != last_aper_order) ||
289 (aper_base != last_aper_base) ||
290 (aper_enabled != last_aper_enabled)) {
291 fix = 1;
292 break;
293 }
Yinghai Lu55c0d722008-04-19 01:31:11 -0700294 }
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200295
Yinghai Lu55c0d722008-04-19 01:31:11 -0700296 last_aper_order = aper_order;
297 last_aper_base = aper_base;
298 last_aper_enabled = aper_enabled;
Pavel Machekfa5b8a32008-05-26 20:40:47 +0200299 last_valid = 1;
Yinghai Luaaf23042008-01-30 13:33:09 +0100300 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100301 }
302
303 if (!fix && !aper_enabled)
304 return;
305
306 if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
307 fix = 1;
308
309 if (gart_fix_e820 && !fix && aper_enabled) {
Yinghai Lu07545572008-06-21 03:50:47 -0700310 if (e820_any_mapped(aper_base, aper_base + aper_size,
311 E820_RAM)) {
Pavel Machek0abbc782008-05-20 16:27:17 +0200312 /* reserve it, so we can reuse it in second kernel */
Yinghai Luaaf23042008-01-30 13:33:09 +0100313 printk(KERN_INFO "update e820 for GART\n");
Yinghai Lud0be6bd2008-06-15 18:58:51 -0700314 e820_add_region(aper_base, aper_size, E820_RESERVED);
Yinghai Luaaf23042008-01-30 13:33:09 +0100315 update_e820();
316 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100317 }
318
Yinghai Luf3eee542009-12-14 11:52:15 +0900319 if (valid_agp)
Pavel Machek4f384f82008-05-26 21:17:30 +0200320 return;
321
Yinghai Luf3eee542009-12-14 11:52:15 +0900322 /* disable them all at first */
Jan Beulich24d9b702011-01-10 16:20:23 +0000323 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700324 int bus;
325 int dev_base, dev_limit;
Yinghai Luaaf23042008-01-30 13:33:09 +0100326
Jan Beulich24d9b702011-01-10 16:20:23 +0000327 bus = amd_nb_bus_dev_ranges[i].bus;
328 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
329 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700330
331 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200332 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700333 continue;
334
335 ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
Borislav Petkov57ab43e2010-09-03 18:39:39 +0200336 ctl &= ~GARTEN;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700337 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
338 }
Yinghai Luaaf23042008-01-30 13:33:09 +0100339 }
340
341}
342
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700343static int __initdata printed_gart_size_msg;
344
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400345int __init gart_iommu_hole_init(void)
Ingo Molnarc140df92008-01-30 13:30:09 +0100346{
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700347 u32 agp_aper_base = 0, agp_aper_order = 0;
Andi Kleen50895c52005-11-05 17:25:53 +0100348 u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700349 u64 aper_base, last_aper_base = 0;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700350 int fix, slot, valid_agp = 0;
351 int i, node;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352
Joerg Roedel0440d4c2007-10-24 12:49:50 +0200353 if (gart_iommu_aperture_disabled || !fix_aperture ||
354 !early_pci_allowed())
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400355 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356
Dan Aloni753811d2007-07-21 17:11:36 +0200357 printk(KERN_INFO "Checking aperture...\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700359 if (!fallback_aper_force)
360 agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
361
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 fix = 0;
Yinghai Lu47db4c32008-01-30 13:33:18 +0100363 node = 0;
Jan Beulich24d9b702011-01-10 16:20:23 +0000364 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700365 int bus;
366 int dev_base, dev_limit;
Joerg Roedel4b838732010-04-07 12:57:35 +0200367 u32 ctl;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700368
Jan Beulich24d9b702011-01-10 16:20:23 +0000369 bus = amd_nb_bus_dev_ranges[i].bus;
370 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
371 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372
Yinghai Lu55c0d722008-04-19 01:31:11 -0700373 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200374 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700375 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376
Yinghai Lu55c0d722008-04-19 01:31:11 -0700377 iommu_detected = 1;
378 gart_iommu_aperture = 1;
FUJITA Tomonoride957622009-11-10 19:46:14 +0900379 x86_init.iommu.iommu_init = gart_iommu_init;
Ingo Molnarc140df92008-01-30 13:30:09 +0100380
Joerg Roedel4b838732010-04-07 12:57:35 +0200381 ctl = read_pci_config(bus, slot, 3,
382 AMD64_GARTAPERTURECTL);
383
384 /*
385 * Before we do anything else disable the GART. It may
386 * still be enabled if we boot into a crash-kernel here.
387 * Reconfiguring the GART while it is enabled could have
388 * unknown side-effects.
389 */
390 ctl &= ~GARTEN;
391 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
392
393 aper_order = (ctl >> 1) & 7;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700394 aper_size = (32 * 1024 * 1024) << aper_order;
395 aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
396 aper_base <<= 25;
397
398 printk(KERN_INFO "Node %d: aperture @ %Lx size %u MB\n",
399 node, aper_base, aper_size >> 20);
400 node++;
401
402 if (!aperture_valid(aper_base, aper_size, 64<<20)) {
403 if (valid_agp && agp_aper_base &&
404 agp_aper_base == aper_base &&
405 agp_aper_order == aper_order) {
406 /* the same between two setting from NB and agp */
Yinghai Luc987d122008-06-24 22:14:09 -0700407 if (!no_iommu &&
408 max_pfn > MAX_DMA32_PFN &&
409 !printed_gart_size_msg) {
Yinghai Lu55c0d722008-04-19 01:31:11 -0700410 printk(KERN_ERR "you are using iommu with agp, but GART size is less than 64M\n");
411 printk(KERN_ERR "please increase GART size in your BIOS setup\n");
412 printk(KERN_ERR "if BIOS doesn't have that option, contact your HW vendor!\n");
413 printed_gart_size_msg = 1;
414 }
415 } else {
416 fix = 1;
417 goto out;
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700418 }
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700419 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420
Yinghai Lu55c0d722008-04-19 01:31:11 -0700421 if ((last_aper_order && aper_order != last_aper_order) ||
422 (last_aper_base && aper_base != last_aper_base)) {
423 fix = 1;
424 goto out;
425 }
426 last_aper_order = aper_order;
427 last_aper_base = aper_base;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700428 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100429 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430
Yinghai Lu55c0d722008-04-19 01:31:11 -0700431out:
Aaron Durbin56dd6692006-09-26 10:52:40 +0200432 if (!fix && !fallback_aper_force) {
Bjorn Helgaas707d4ee2014-03-18 14:26:12 -0600433 if (last_aper_base)
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400434 return 1;
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400435 return 0;
Aaron Durbin56dd6692006-09-26 10:52:40 +0200436 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437
Yinghai Lu8c9fd912008-04-13 18:42:31 -0700438 if (!fallback_aper_force) {
439 aper_alloc = agp_aper_base;
440 aper_order = agp_aper_order;
441 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100442
443 if (aper_alloc) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 /* Got the aperture from the AGP bridge */
Yinghai Luc987d122008-06-24 22:14:09 -0700445 } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 force_iommu ||
447 valid_agp ||
Ingo Molnarc140df92008-01-30 13:30:09 +0100448 fallback_aper_force) {
Adam Jackson9b156842008-09-29 14:52:03 -0400449 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100450 "Your BIOS doesn't leave a aperture memory hole\n");
Adam Jackson9b156842008-09-29 14:52:03 -0400451 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100452 "Please enable the IOMMU option in the BIOS setup\n");
Adam Jackson9b156842008-09-29 14:52:03 -0400453 printk(KERN_INFO
Ingo Molnar31183ba2008-01-30 13:30:10 +0100454 "This costs you %d MB of RAM\n",
455 32 << fallback_aper_order);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456
457 aper_order = fallback_aper_order;
458 aper_alloc = allocate_aperture();
Ingo Molnarc140df92008-01-30 13:30:09 +0100459 if (!aper_alloc) {
460 /*
461 * Could disable AGP and IOMMU here, but it's
462 * probably not worth it. But the later users
463 * cannot deal with bad apertures and turning
464 * on the aperture over memory causes very
465 * strange problems, so it's better to panic
466 * early.
467 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700468 panic("Not enough memory for aperture");
469 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100470 } else {
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400471 return 0;
Ingo Molnarc140df92008-01-30 13:30:09 +0100472 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473
474 /* Fix up the north bridges */
Jan Beulich24d9b702011-01-10 16:20:23 +0000475 for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
Borislav Petkov260133a2010-09-03 18:39:40 +0200476 int bus, dev_base, dev_limit;
477
478 /*
479 * Don't enable translation yet but enable GART IO and CPU
480 * accesses and set DISTLBWALKPRB since GART table memory is UC.
481 */
Joerg Roedelc34151a2011-04-18 15:45:45 +0200482 u32 ctl = aper_order << 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700483
Jan Beulich24d9b702011-01-10 16:20:23 +0000484 bus = amd_nb_bus_dev_ranges[i].bus;
485 dev_base = amd_nb_bus_dev_ranges[i].dev_base;
486 dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
Yinghai Lu55c0d722008-04-19 01:31:11 -0700487 for (slot = dev_base; slot < dev_limit; slot++) {
Hans Rosenfeldeec1d4f2010-10-29 17:14:30 +0200488 if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
Yinghai Lu55c0d722008-04-19 01:31:11 -0700489 continue;
490
Borislav Petkov260133a2010-09-03 18:39:40 +0200491 write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
Yinghai Lu55c0d722008-04-19 01:31:11 -0700492 write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
493 }
Ingo Molnarc140df92008-01-30 13:30:09 +0100494 }
Rafael J. Wysocki6703f6d2008-06-10 00:10:48 +0200495
496 set_up_gart_resume(aper_order, aper_alloc);
Konrad Rzeszutek Wilk480125b2010-08-26 13:57:57 -0400497
498 return 1;
Ingo Molnarc140df92008-01-30 13:30:09 +0100499}