blob: bc5a709d2f0afd3fb160aac6041b1d10714f4f78 [file] [log] [blame]
Tim Zimmermann5c435c12021-03-18 09:19:56 +01001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __PCIE_EXYNOS_HOST_V1_H
14#define __PCIE_EXYNOS_HOST_V1_H
15
16#define MAX_TIMEOUT 2400 /* about 24 ms */
17#define MAX_TIMEOUT_LANECHANGE 10000
18#define ID_MASK 0xffff
19#define TPUT_THRESHOLD 150
20#define MAX_RC_NUM 2
21
22#if defined(CONFIG_SOC_EXYNOS8890)
23#define PCI_DEVICE_ID_EXYNOS 0xa544
24#define GPIO_DEBUG_SFR 0x15601068
25#else
26#define PCI_DEVICE_ID_EXYNOS 0xecec
27#define GPIO_DEBUG_SFR 0x0
28#endif
29
30// 1234567
31//#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp)
32
33#define to_exynos_pcie(x) dev_get_drvdata((x)->dev)
34
35#define PCIE_BUS_PRIV_DATA(pdev) \
36 ((struct pcie_port *)pdev->bus->sysdata)
37
38#define MAX_PCIE_PIN_STATE 2
39#define PCIE_PIN_DEFAULT 0
40#define PCIE_PIN_IDLE 1
41
42struct regmap;
43
44struct exynos_pcie_clks {
45 struct clk *pcie_clks[10];
46 struct clk *phy_clks[3];
47};
48
49enum exynos_pcie_state {
50 STATE_LINK_DOWN = 0,
51 STATE_LINK_UP_TRY,
52 STATE_LINK_DOWN_TRY,
53 STATE_LINK_UP,
54};
55
56struct pcie_phyops {
57 void (*phy_check_rx_elecidle)(void *phy_pcs_base_regs, int val,
58 int ch_num);
59 void (*phy_all_pwrdn)(void *phy_base_regs, void *phy_pcs_base_regs,
60 void *sysreg_base_regs, int ch_num);
61 void (*phy_all_pwrdn_clear)(void *phy_base_regs,
62 void *phy_pcs_base_regs,
63 void *sysreg_base_regs, int ch_num);
64 void (*phy_config)(void *phy_base_regs, void *phy_pcs_base_regs,
65 void *sysreg_base_regs, void *elbi_base_regs,
66 void *dbi_base_regs, int ch_num);
67 void (*phy_config_regmap)(void *phy_base_regs, void *phy_pcs_base_regs,
68 struct regmap *sysreg_phandle,
69 void *elbi_base_regs, int ch_num);
70};
71
72struct exynos_pcie {
73 struct dw_pcie *pci;
74 void __iomem *elbi_base;
75 void __iomem *phy_base;
76 void __iomem *sysreg_base;
77 void __iomem *rc_dbi_base;
78 void __iomem *phy_pcs_base;
79 void __iomem *ia_base;
80 struct regmap *pmureg;
81 struct regmap *sysreg;
82 int perst_gpio;
83 int ch_num;
84 int pcie_clk_num;
85 int phy_clk_num;
86 enum exynos_pcie_state state;
87 int probe_ok;
88 int l1ss_enable;
89 int linkdown_cnt;
90 int idle_ip_index;
91 bool use_msi;
92 bool use_cache_coherency;
93 bool use_sicd;
94 bool atu_ok;
95 bool use_sysmmu;
96 bool use_ia;
97 spinlock_t conf_lock;
98 struct workqueue_struct *pcie_wq;
99 struct exynos_pcie_clks clks;
100 struct pci_dev *pci_dev;
101 struct pci_saved_state *pci_saved_configs;
102 struct notifier_block power_mode_nb;
103 struct notifier_block ss_dma_mon_nb;
104 struct delayed_work dislink_work;
105 struct exynos_pcie_register_event *event_reg;
106#ifdef CONFIG_PM_DEVFREQ
107 unsigned int int_min_lock;
108#endif
109 u32 ip_ver;
110 struct pcie_phyops phy_ops;
111 int l1ss_ctrl_id_state;
112 int ep_device_type;
113 int max_link_speed;
114
115 struct pinctrl *pcie_pinctrl;
116 struct pinctrl_state *pin_state[MAX_PCIE_PIN_STATE];
117};
118
119/* PCIe ELBI registers */
120#define PCIE_IRQ0 0x000
121#define IRQ_INTA_ASSERT (0x1 << 14)
122#define IRQ_INTB_ASSERT (0x1 << 16)
123#define IRQ_INTC_ASSERT (0x1 << 18)
124#define IRQ_INTD_ASSERT (0x1 << 20)
125#define IRQ_RADM_PM_TO_ACK (0x1 << 29)
126#define PCIE_IRQ1 0x004
127#define IRQ_LINK_DOWN_EVT1_1 (0x1 << 10)
128#define PCIE_IRQ2 0x008
129#define IRQ_LINK_DOWN (0x1 << 14)
130#define IRQ_MSI_FALLING_ASSERT (0x1 << 16)
131#define IRQ_MSI_RISING_ASSERT (0x1 << 17)
132#define PCIE_IRQ0_EN 0x010
133#define PCIE_IRQ1_EN 0x014
134#define IRQ_LINKDOWN_ENABLE_EVT1_1 (0x1 << 10)
135#define PCIE_IRQ2_EN 0x018
136#define IRQ_LINKDOWN_ENABLE (0x1 << 14)
137#define IRQ_MSI_CTRL_EN_FALLING_EDG (0x1 << 16)
138#define IRQ_MSI_CTRL_EN_RISING_EDG (0x1 << 17)
139#define PCIE_APP_LTSSM_ENABLE 0x054
140#define PCIE_ELBI_LTSSM_DISABLE 0x0
141#define PCIE_ELBI_LTSSM_ENABLE 0x1
142#define PCIE_APP_REQ_EXIT_L1 0x06C
143#define XMIT_PME_TURNOFF 0x118
144#define PCIE_ELBI_RDLH_LINKUP 0x2C8
145#define PCIE_CXPL_DEBUG_INFO_H 0x2CC
146#define PCIE_PM_DSTATE 0x2E8
147#define PCIE_LINKDOWN_RST_CTRL_SEL 0x3A0
148#define PCIE_LINKDOWN_RST_MANUAL (0x1 << 1)
149#define PCIE_LINKDOWN_RST_FSM (0x1 << 0)
150#define PCIE_SOFT_RESET 0x3A4
151#define SOFT_CORE_RESET (0x1 << 0)
152#define SOFT_PWR_RESET (0x1 << 1)
153#define SOFT_STICKY_RESET (0x1 << 2)
154#define SOFT_NON_STICKY_RESET (0x1 << 3)
155#define SOFT_PHY_RESET (0x1 << 4)
156#define PCIE_QCH_SEL 0x3A8
157#define CLOCK_GATING_IN_L12 0x1
158#define CLOCK_NOT_GATING 0x3
159#define CLOCK_GATING_MASK 0x3
160#define CLOCK_GATING_PMU_L1 (0x1 << 11)
161#define CLOCK_GATING_PMU_L23READY (0x1 << 10)
162#define CLOCK_GATING_PMU_DETECT_QUIET (0x1 << 9)
163#define CLOCK_GATING_PMU_L12 (0x1 << 8)
164#define CLOCK_GATING_PMU_ALL (0xF << 8)
165#define CLOCK_GATING_PMU_MASK (0xF << 8)
166#define CLOCK_GATING_APB_L1 (0x1 << 7)
167#define CLOCK_GATING_APB_L23READY (0x1 << 6)
168#define CLOCK_GATING_APB_DETECT_QUIET (0x1 << 5)
169#define CLOCK_GATING_APB_L12 (0X1 << 4)
170#define CLOCK_GATING_APB_ALL (0xF << 4)
171#define CLOCK_GATING_APB_MASK (0xF << 4)
172#define CLOCK_GATING_AXI_L1 (0x1 << 3)
173#define CLOCK_GATING_AXI_L23READY (0x1 << 2)
174#define CLOCK_GATING_AXI_DETECT_QUIET (0x1 << 1)
175#define CLOCK_GATING_AXI_L12 (0x1 << 0)
176#define CLOCK_GATING_AXI_ALL (0xF << 0)
177#define CLOCK_GATING_AXI_MASK (0xF << 0)
178#define PCIE_APP_REQ_EXIT_L1_MODE 0x3BC
179#define APP_REQ_EXIT_L1_MODE 0x1
180#define L1_REQ_NAK_CONTROL (0x3 << 4) /* 123456 Todo check this bit in not exist in user manual */
181#define L1_REQ_NAK_CONTROL_MASTER (0x1 << 4)
182#define PCIE_SW_WAKE 0x3D4
183#define PCIE_STATE_HISTORY_CHECK 0xC00
184#define HISTORY_BUFFER_ENABLE 0x3
185#define HISTORY_BUFFER_CLEAR (0x1 << 1)
186#define PCIE_STATE_POWER_S 0xC04
187#define PCIE_STATE_POWER_M 0xC08
188#define PCIE_HISTORY_REG(x) (0xC0C + ((x) * 0x4)) /*history_reg0 : 0xC0C*/
189#define LTSSM_STATE(x) (((x) >> 16) & 0x3f)
190#define PM_DSTATE(x) (((x) >> 8) & 0x7)
191#define L1SUB_STATE(x) (((x) >> 0) & 0x7)
192#define PCIE_DMA_MONITOR1 0x460
193#define PCIE_DMA_MONITOR2 0x464
194#define PCIE_DMA_MONITOR3 0x468
195#define FSYS1_MON_SEL_MASK 0xf
196#define PCIE_MON_SEL_MASK 0xff
197
198/* PCIe PMU registers */
199#define IDLE_IP3_STATE 0x3EC
200#define IDLE_IP_RC1_SHIFT (31)
201#define IDLE_IP_RC0_SHIFT (30)
202#define IDLE_IP3_MASK 0x3FC
203#define PCIE_PHY_CONTROL 0x071C
204#define PCIE_PHY_CONTROL_MASK 0x1
205
206/* PCIe DBI registers */
207#define PM_CAP_OFFSET 0x40
208#define PCIE_CAP_OFFSET 0x70
209#define PCIE_LINK_CTRL_STAT 0x80
210#define PCIE_CAP_NEGO_LINK_WIDTH_MASK 0x3f
211#define PCI_EXP_LNKCAP_MLW_X1 (0x1 << 4)
212#define PCI_EXP_LNKCAP_L1EL_64USEC (0x7 << 15)
213#define PCI_EXP_LNKCTL2_TLS 0xf
214#define PCI_EXP_LNKCTL2_TLS_2_5GB 0x1
215#define PCI_EXP_LNKCTL2_TLS_5_0GB 0x2
216#define PCI_EXP_LNKCTL2_TLS_8_0GB 0x3
217#define PCIE_LINK_L1SS_CONTROL 0x168
218#define PORT_LINK_TCOMMON_32US (0x20 << 8)
219#define LTR_L12_THRESHOLD_SCALE_1NS (0x0 << 29) /* Latency Tolerance Reporting */
220#define LTR_L12_THRESHOLD_SCALE_32NS (0x1 << 29) /* Latency Tolerance Reporting */
221#define LTR_L12_THRESHOLD_SCALE_1024NS (0x2 << 29) /* Latency Tolerance Reporting */
222#define LTR_L12_THRESHOLD_SCALE_32768NS (0x3 << 29) /* Latency Tolerance Reporting */
223#define LTR_L12_THRESHOLD_VALUE_160 (0xa0 << 16) /* Latency Tolerance Reporting */
224#define PCIE_LINK_L1SS_CONTROL2 0x16C
225#define PORT_LINK_L1SS_ENABLE (0xf << 0)
226#define PORT_LINK_TPOWERON_90US (0x49 << 0)
227#define PORT_LINK_TPOWERON_130US (0x69 << 0)
228#define PORT_LINK_TPOWERON_3100US (0xfa << 0)
229#define PORT_LINK_L1SS_T_PCLKACK (0x3 << 6)
230#define PORT_LINK_L1SS_T_L1_2 (0x4 << 2)
231#define PORT_LINK_L1SS_T_POWER_OFF (0x2 << 0)
232#define PCIE_ACK_F_ASPM_CONTROL 0x70C
233#define PCIE_L1_ENTERANCE_LATENCY (0x7 << 27)
234#define PCIE_L1_ENTERANCE_LATENCY_8us (0x3 << 27)
235#define PCIE_L1_ENTERANCE_LATENCY_16us (0x4 << 27)
236#define PCIE_L1_ENTERANCE_LATENCY_32us (0x5 << 27)
237#define PCIE_L1_ENTERANCE_LATENCY_64us (0x7 << 27)
238#define PCIE_PORT_LINK_CONTROL 0x710
239
240#define PCIE_MISC_CONTROL 0x8BC
241#define DBI_RO_WR_EN 0x1
242
243#define PCIE_AUX_CLK_FREQ_OFF 0xB40
244#define PCIE_AUX_CLK_FREQ_24MHZ 0x18
245#define PCIE_AUX_CLK_FREQ_26MHZ 0x1A
246#define PCIE_L1_SUBSTATES_OFF 0xB44
247#define PCIE_L1_SUB_VAL 0xEA
248
249#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
250#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
251
252#define MULTI_LANE_CONTROL_OFF 0x8C0
253#define TARGET_LINK_WIDTH_MASK 0xffffffc0
254#define DIRECT_LINK_WIDTH_CHANGE_MASK 0x40
255
256#define PCIE_ATU_VIEWPORT 0x900
257#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
258#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
259#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
260#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
261#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
262#define PCIE_ATU_CR1 0x904
263#define PCIE_ATU_TYPE_MEM (0x0 << 0)
264#define PCIE_ATU_TYPE_IO (0x2 << 0)
265#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
266#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
267#define PCIE_ATU_CR2 0x908
268#define PCIE_ATU_ENABLE (0x1 << 31)
269#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
270#define PCIE_ATU_LOWER_BASE 0x90C
271#define PCIE_ATU_UPPER_BASE 0x910
272#define PCIE_ATU_LIMIT 0x914
273#define PCIE_ATU_LOWER_TARGET 0x918
274#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
275#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
276#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
277#define PCIE_ATU_UPPER_TARGET 0x91C
278
279#define PCIE_MSI_ADDR_LO 0x820
280#define PCIE_MSI_ADDR_HI 0x824
281#define PCIE_MSI_INTR0_ENABLE 0x828
282#define PCIE_MSI_INTR0_MASK 0x82C
283#define PCIE_MSI_INTR0_STATUS 0x830
284
285/* PCIe SYSREG registers */
286#define PCIE_WIFI0_PCIE_PHY_CONTROL 0xC
287#define BIFURCATION_MODE_DISABLE (0x1 << 16)
288#define LINK1_ENABLE (0x1 << 15)
289#define LINK0_ENABLE (0x1 << 14)
290#define PCS_LANE1_ENABLE (0x1 << 13)
291#define PCS_LANE0_ENABLE (0x1 << 12)
292
293#define PCIE_SYSREG_SHARABILITY_CTRL 0x700
294#define PCIE_SYSREG_SHARABLE_OFFSET 8
295#define PCIE_SYSREG_SHARABLE_ENABLE 0x3
296#define PCIE_SYSREG_SHARABLE_DISABLE 0x0
297
298/* Definitions for WIFI L1.2 */
299#define WIFI_L1SS_CAPID 0x240
300#define WIFI_L1SS_CAP 0x244
301#define WIFI_L1SS_CONTROL 0x248
302#define WIFI_L1SS_CONTROL2 0x24C
303#define WIFI_L1SS_LINKCTRL 0xBC
304#define WIFI_LINK_STATUS 0xBE
305#define WIFI_PM_MNG_STATUS_CON 0x4C
306
307/* LINK Control Register */
308#define WIFI_ASPM_CONTROL_MASK (0x3 << 0)
309#define WIFI_ASPM_L1_ENTRY_EN (0x2 << 0)
310#define WIFI_USE_SAME_REF_CLK (0x1 << 6)
311#define WIFI_CLK_REQ_EN (0x1 << 8)
312
313/* L1SSS Control Register */
314#define WIFI_ALL_PM_ENABEL (0xf << 0)
315#define WIFI_PCIPM_L12_EN (0x1 << 0)
316#define WIFI_PCIPM_L11_EN (0x1 << 1)
317#define WIFI_ASPM_L12_EN (0x1 << 2)
318#define WIFI_ASPM_L11_EN (0x1 << 3)
319#define WIFI_COMMON_RESTORE_TIME (0xa << 8) /* Default Value */
320
321/* ETC definitions */
322#define IGNORE_ELECIDLE 1
323#define ENABLE_ELECIDLE 0
324#define PCIE_DISABLE_CLOCK 0
325#define PCIE_ENABLE_CLOCK 1
326#define PCIE_IS_IDLE 1
327#define PCIE_IS_ACTIVE 0
328
329/* PCIe PHY definitions */
330#define PHY_PLL_STATE 0xBC
331#define CHK_PHY_PLL_LOCK 0x3
332
333/* 123456 I will be modified */
334/* For Set NCLK OFF to avoid system hang */
335#define EXYNOS_PCIE_MAX_NAME_LEN 10
336#define PCIE_L12ERR_CTRL 0x2F0
337#define NCLK_OFF_OFFSET 0x2
338
339
340#define PCIE_ATU_CR1_OUTBOUND0 0x300000
341#define PCIE_ATU_CR2_OUTBOUND0 0x300004
342#define PCIE_ATU_LOWER_BASE_OUTBOUND0 0x300008
343#define PCIE_ATU_UPPER_BASE_OUTBOUND0 0x30000C
344#define PCIE_ATU_LIMIT_OUTBOUND0 0x300010
345#define PCIE_ATU_LOWER_TARGET_OUTBOUND0 0x300014
346#define PCIE_ATU_UPPER_TARGET_OUTBOUND0 0x300018
347
348#define PCIE_ATU_CR1_OUTBOUND1 0x300200
349#define PCIE_ATU_CR2_OUTBOUND1 0x300204
350#define PCIE_ATU_LOWER_BASE_OUTBOUND1 0x300208
351#define PCIE_ATU_UPPER_BASE_OUTBOUND1 0x30020C
352#define PCIE_ATU_LIMIT_OUTBOUND1 0x300210
353#define PCIE_ATU_LOWER_TARGET_OUTBOUND1 0x300214
354#define PCIE_ATU_UPPER_TARGET_OUTBOUND1 0x300218
355
356void exynos_host_v1_pcie_phy_init(struct pcie_port *pp);
357
358#ifdef CONFIG_EXYNOS_PCIE_IOMMU
359extern void pcie_sysmmu_enable(int ch_num);
360extern void pcie_sysmmu_disable(int ch_num);
361extern int pcie_iommu_map(int ch_num, unsigned long iova, phys_addr_t paddr,
362 size_t size, int prot);
363extern size_t pcie_iommu_unmap(int ch_num, unsigned long iova, size_t size);
364
365extern struct dma_map_ops exynos_pcie_dma_ops;
366#else
367static void __maybe_unused pcie_sysmmu_enable(int ch_num)
368{
369 pr_err("PCIe SysMMU is NOT Enabled!!!\n");
370}
371static void __maybe_unused pcie_sysmmu_disable(int ch_num)
372{
373 pr_err("PCIe SysMMU is NOT Enabled!!!\n");
374}
375static int __maybe_unused pcie_iommu_map(int ch_num, unsigned long iova, phys_addr_t paddr,
376 size_t size, int prot)
377{
378 pr_err("PCIe SysMMU is NOT Enabled!!!\n");
379
380 return -ENODEV;
381}
382static size_t __maybe_unused pcie_iommu_unmap(int ch_num, unsigned long iova, size_t size)
383{
384 pr_err("PCIe SysMMU is NOT Enabled!!!\n");
385
386 return -ENODEV;
387}
388#endif
389
390#endif