blob: 07b8dae0f46e5366f684e871dc3e97334901dc90 [file] [log] [blame]
Andy Fleming2654d632006-08-18 18:04:34 -05001/*
Roy Zang02edff52007-07-10 18:46:47 +08002 * MPC8548 CDS Device Tree Source
Andy Fleming2654d632006-08-18 18:04:34 -05003 *
Kumar Gala32f960e2008-04-17 01:28:15 -05004 * Copyright 2006, 2008 Freescale Semiconductor Inc.
Andy Fleming2654d632006-08-18 18:04:34 -05005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
Kumar Gala53e23dc2011-11-04 00:26:10 -050012/include/ "fsl/mpc8548si-pre.dtsi"
Andy Fleming2654d632006-08-18 18:04:34 -050013
14/ {
15 model = "MPC8548CDS";
Kumar Gala52094872007-02-17 16:04:23 -060016 compatible = "MPC8548CDS", "MPC85xxCDS";
Andy Fleming2654d632006-08-18 18:04:34 -050017
Kumar Galaea082fa2007-12-12 01:46:12 -060018 aliases {
19 ethernet0 = &enet0;
20 ethernet1 = &enet1;
Kumar Galaea082fa2007-12-12 01:46:12 -060021 ethernet2 = &enet2;
22 ethernet3 = &enet3;
Kumar Galaea082fa2007-12-12 01:46:12 -060023 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 pci2 = &pci2;
28 };
29
Andy Fleming2654d632006-08-18 18:04:34 -050030 memory {
31 device_type = "memory";
Kumar Gala53e23dc2011-11-04 00:26:10 -050032 reg = <0 0 0x0 0x8000000>; // 128M at 0x0
Andy Fleming2654d632006-08-18 18:04:34 -050033 };
34
Kumar Gala53e23dc2011-11-04 00:26:10 -050035 lbc: localbus@e0005000 {
36 reg = <0 0xe0005000 0 0x1000>;
37 };
Andy Fleming2654d632006-08-18 18:04:34 -050038
Kumar Gala53e23dc2011-11-04 00:26:10 -050039 soc: soc8548@e0000000 {
40 ranges = <0 0x0 0xe0000000 0x100000>;
Dave Jiang50cf6702007-05-10 10:03:05 -070041
Andy Fleming2654d632006-08-18 18:04:34 -050042 i2c@3000 {
Anton Vorontsovc69328d2009-07-09 22:36:44 +040043 eeprom@50 {
44 compatible = "atmel,24c64";
45 reg = <0x50>;
46 };
47
48 eeprom@56 {
49 compatible = "atmel,24c64";
50 reg = <0x56>;
51 };
52
53 eeprom@57 {
54 compatible = "atmel,24c64";
55 reg = <0x57>;
56 };
Andy Fleming2654d632006-08-18 18:04:34 -050057 };
58
Kumar Galaec9686c2007-12-11 23:17:24 -060059 i2c@3100 {
Anton Vorontsovc69328d2009-07-09 22:36:44 +040060 eeprom@50 {
61 compatible = "atmel,24c64";
62 reg = <0x50>;
63 };
Kumar Galaec9686c2007-12-11 23:17:24 -060064 };
65
Kumar Galae77b28e2007-12-12 00:28:35 -060066 enet0: ethernet@24000 {
Andy Flemingb31a1d82008-12-16 15:29:15 -080067 tbi-handle = <&tbi0>;
Kumar Gala52094872007-02-17 16:04:23 -060068 phy-handle = <&phy0>;
Kumar Gala53e23dc2011-11-04 00:26:10 -050069 };
Anton Vorontsov84ba4a52009-03-19 21:01:48 +030070
Kumar Gala53e23dc2011-11-04 00:26:10 -050071 mdio@24520 {
72 phy0: ethernet-phy@0 {
73 interrupts = <5 1 0 0>;
74 reg = <0x0>;
75 device_type = "ethernet-phy";
76 };
77 phy1: ethernet-phy@1 {
78 interrupts = <5 1 0 0>;
79 reg = <0x1>;
80 device_type = "ethernet-phy";
81 };
82 phy2: ethernet-phy@2 {
83 interrupts = <5 1 0 0>;
84 reg = <0x2>;
85 device_type = "ethernet-phy";
86 };
87 phy3: ethernet-phy@3 {
88 interrupts = <5 1 0 0>;
89 reg = <0x3>;
90 device_type = "ethernet-phy";
91 };
92 tbi0: tbi-phy@11 {
93 reg = <0x11>;
94 device_type = "tbi-phy";
Anton Vorontsov84ba4a52009-03-19 21:01:48 +030095 };
Andy Fleming2654d632006-08-18 18:04:34 -050096 };
97
Kumar Galae77b28e2007-12-12 00:28:35 -060098 enet1: ethernet@25000 {
Andy Flemingb31a1d82008-12-16 15:29:15 -080099 tbi-handle = <&tbi1>;
Kumar Gala52094872007-02-17 16:04:23 -0600100 phy-handle = <&phy1>;
Kumar Gala53e23dc2011-11-04 00:26:10 -0500101 };
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300102
Kumar Gala53e23dc2011-11-04 00:26:10 -0500103 mdio@25520 {
104 tbi1: tbi-phy@11 {
105 reg = <0x11>;
106 device_type = "tbi-phy";
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300107 };
Andy Fleming2654d632006-08-18 18:04:34 -0500108 };
109
Kumar Galae77b28e2007-12-12 00:28:35 -0600110 enet2: ethernet@26000 {
Andy Flemingb31a1d82008-12-16 15:29:15 -0800111 tbi-handle = <&tbi2>;
Kumar Gala52094872007-02-17 16:04:23 -0600112 phy-handle = <&phy2>;
Kumar Gala53e23dc2011-11-04 00:26:10 -0500113 };
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300114
Kumar Gala53e23dc2011-11-04 00:26:10 -0500115 mdio@26520 {
116 tbi2: tbi-phy@11 {
117 reg = <0x11>;
118 device_type = "tbi-phy";
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300119 };
Andy Fleming2654d632006-08-18 18:04:34 -0500120 };
121
Kumar Galae77b28e2007-12-12 00:28:35 -0600122 enet3: ethernet@27000 {
Andy Flemingb31a1d82008-12-16 15:29:15 -0800123 tbi-handle = <&tbi3>;
Kumar Gala52094872007-02-17 16:04:23 -0600124 phy-handle = <&phy3>;
Kumar Gala53e23dc2011-11-04 00:26:10 -0500125 };
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300126
Kumar Gala53e23dc2011-11-04 00:26:10 -0500127 mdio@27520 {
128 tbi3: tbi-phy@11 {
129 reg = <0x11>;
130 device_type = "tbi-phy";
Anton Vorontsov84ba4a52009-03-19 21:01:48 +0300131 };
Andy Fleming2654d632006-08-18 18:04:34 -0500132 };
Andy Fleming2654d632006-08-18 18:04:34 -0500133 };
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500134
Kumar Galaea082fa2007-12-12 01:46:12 -0600135 pci0: pci@e0008000 {
Kumar Gala53e23dc2011-11-04 00:26:10 -0500136 reg = <0 0xe0008000 0 0x1000>;
137 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x10000000
138 0x1000000 0x0 0x00000000 0 0xe2000000 0x0 0x800000>;
139 clock-frequency = <66666666>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500140 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500141 interrupt-map = <
142 /* IDSEL 0x4 (PCIX Slot 2) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500143 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
144 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
145 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
146 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500147
148 /* IDSEL 0x5 (PCIX Slot 3) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500149 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
150 0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
151 0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
152 0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500153
154 /* IDSEL 0x6 (PCIX Slot 4) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500155 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
156 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
157 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
158 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500159
160 /* IDSEL 0x8 (PCIX Slot 5) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500161 0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
162 0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
163 0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
164 0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500165
166 /* IDSEL 0xC (Tsi310 bridge) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500167 0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
168 0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
169 0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
170 0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500171
172 /* IDSEL 0x14 (Slot 2) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500173 0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
174 0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
175 0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
176 0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500177
178 /* IDSEL 0x15 (Slot 3) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500179 0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
180 0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
181 0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
182 0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500183
184 /* IDSEL 0x16 (Slot 4) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500185 0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
186 0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
187 0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
188 0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500189
190 /* IDSEL 0x18 (Slot 5) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500191 0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
192 0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
193 0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
194 0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500195
196 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500197 0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
198 0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
199 0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
200 0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500201
202 pci_bridge@1c {
Kumar Gala32f960e2008-04-17 01:28:15 -0500203 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500204 interrupt-map = <
205
206 /* IDSEL 0x00 (PrPMC Site) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500207 0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
208 0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
209 0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
210 0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500211
212 /* IDSEL 0x04 (VIA chip) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500213 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
214 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
215 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
216 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500217
218 /* IDSEL 0x05 (8139) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500219 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500220
221 /* IDSEL 0x06 (Slot 6) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500222 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
223 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
224 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
225 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500226
227 /* IDESL 0x07 (Slot 7) */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500228 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
229 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
230 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
231 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500232
Kumar Gala32f960e2008-04-17 01:28:15 -0500233 reg = <0xe000 0x0 0x0 0x0 0x0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500234 #interrupt-cells = <1>;
235 #size-cells = <2>;
236 #address-cells = <3>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500237 ranges = <0x2000000 0x0 0x80000000
238 0x2000000 0x0 0x80000000
239 0x0 0x20000000
240 0x1000000 0x0 0x0
241 0x1000000 0x0 0x0
242 0x0 0x80000>;
243 clock-frequency = <33333333>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500244
245 isa@4 {
246 device_type = "isa";
247 #interrupt-cells = <2>;
248 #size-cells = <1>;
249 #address-cells = <2>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500250 reg = <0x2000 0x0 0x0 0x0 0x0>;
251 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500252 interrupt-parent = <&i8259>;
253
254 i8259: interrupt-controller@20 {
255 interrupt-controller;
256 device_type = "interrupt-controller";
Kumar Gala32f960e2008-04-17 01:28:15 -0500257 reg = <0x1 0x20 0x2
258 0x1 0xa0 0x2
259 0x1 0x4d0 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500260 #address-cells = <0>;
261 #interrupt-cells = <2>;
262 compatible = "chrp,iic";
Kumar Gala53e23dc2011-11-04 00:26:10 -0500263 interrupts = <0 1 0 0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500264 interrupt-parent = <&mpic>;
265 };
266
267 rtc@70 {
268 compatible = "pnpPNP,b00";
Kumar Gala32f960e2008-04-17 01:28:15 -0500269 reg = <0x1 0x70 0x2>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500270 };
271 };
272 };
273 };
274
Kumar Galaea082fa2007-12-12 01:46:12 -0600275 pci1: pci@e0009000 {
Kumar Gala53e23dc2011-11-04 00:26:10 -0500276 reg = <0 0xe0009000 0 0x1000>;
277 ranges = <0x2000000 0x0 0x90000000 0 0x90000000 0x0 0x10000000
278 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x800000>;
279 clock-frequency = <66666666>;
Kumar Gala32f960e2008-04-17 01:28:15 -0500280 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500281 interrupt-map = <
282
283 /* IDSEL 0x15 */
Kumar Gala53e23dc2011-11-04 00:26:10 -0500284 0xa800 0x0 0x0 0x1 &mpic 0xb 0x1 0 0
285 0xa800 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
286 0xa800 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
287 0xa800 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500288 };
289
Kumar Galaea082fa2007-12-12 01:46:12 -0600290 pci2: pcie@e000a000 {
Kumar Gala53e23dc2011-11-04 00:26:10 -0500291 reg = <0 0xe000a000 0 0x1000>;
292 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
293 0x1000000 0x0 0x00000000 0 0xe3000000 0x0 0x100000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500294 pcie@0 {
Kumar Gala32f960e2008-04-17 01:28:15 -0500295 ranges = <0x2000000 0x0 0xa0000000
296 0x2000000 0x0 0xa0000000
297 0x0 0x20000000
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500298
Kumar Gala32f960e2008-04-17 01:28:15 -0500299 0x1000000 0x0 0x0
300 0x1000000 0x0 0x0
Kumar Galaad168802008-06-06 10:35:13 -0500301 0x0 0x100000>;
Kumar Gala1b3c5cda2007-09-12 18:23:46 -0500302 };
303 };
Andy Fleming2654d632006-08-18 18:04:34 -0500304};
Kumar Gala53e23dc2011-11-04 00:26:10 -0500305
306/include/ "fsl/mpc8548si-post.dtsi"