Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/kernel/entry-armv.S |
| 3 | * |
| 4 | * Copyright (C) 1996,1997,1998 Russell King. |
| 5 | * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk) |
Hyok S. Choi | afeb90c | 2006-01-13 21:05:25 +0000 | [diff] [blame] | 6 | * nommu support by Hyok S. Choi (hyok.choi@samsung.com) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * Low-level vector interface routines |
| 13 | * |
Nicolas Pitre | 70b6f2b | 2007-12-04 14:33:33 +0100 | [diff] [blame] | 14 | * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction |
| 15 | * that causes it to save wrong values... Be aware! |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | |
Paul Gortmaker | 9b9cf81 | 2015-05-01 20:13:42 -0400 | [diff] [blame] | 18 | #include <linux/init.h> |
| 19 | |
Rob Herring | 6f6f6a7 | 2012-03-10 10:30:31 -0600 | [diff] [blame] | 20 | #include <asm/assembler.h> |
Nicolas Pitre | f09b997 | 2005-10-29 21:44:55 +0100 | [diff] [blame] | 21 | #include <asm/memory.h> |
Russell King | 753790e | 2011-02-06 15:32:24 +0000 | [diff] [blame] | 22 | #include <asm/glue-df.h> |
| 23 | #include <asm/glue-pf.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <asm/vfpmacros.h> |
Rob Herring | 243c865 | 2012-02-08 18:26:34 -0600 | [diff] [blame] | 25 | #ifndef CONFIG_MULTI_IRQ_HANDLER |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 26 | #include <mach/entry-macro.S> |
Rob Herring | 243c865 | 2012-02-08 18:26:34 -0600 | [diff] [blame] | 27 | #endif |
Russell King | d6551e8 | 2006-06-21 13:31:52 +0100 | [diff] [blame] | 28 | #include <asm/thread_notify.h> |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 29 | #include <asm/unwind.h> |
Russell King | cc20d42 | 2009-11-09 23:53:29 +0000 | [diff] [blame] | 30 | #include <asm/unistd.h> |
Tony Lindgren | f159f4e | 2010-07-05 14:53:10 +0100 | [diff] [blame] | 31 | #include <asm/tls.h> |
David Howells | 9f97da7 | 2012-03-28 18:30:01 +0100 | [diff] [blame] | 32 | #include <asm/system_info.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 33 | |
| 34 | #include "entry-header.S" |
Magnus Damm | cd544ce | 2010-12-22 13:20:08 +0100 | [diff] [blame] | 35 | #include <asm/entry-macro-multi.S> |
Wang Nan | a0266c2 | 2015-01-05 19:29:25 +0800 | [diff] [blame] | 36 | #include <asm/probes.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | |
| 38 | /* |
Russell King | d9600c9 | 2011-06-26 10:34:02 +0100 | [diff] [blame] | 39 | * Interrupt handling. |
Russell King | 187a51a | 2005-05-21 18:14:44 +0100 | [diff] [blame] | 40 | */ |
| 41 | .macro irq_handler |
eric miao | 5210864 | 2010-12-13 09:42:34 +0100 | [diff] [blame] | 42 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
Russell King | d9600c9 | 2011-06-26 10:34:02 +0100 | [diff] [blame] | 43 | ldr r1, =handle_arch_irq |
eric miao | 5210864 | 2010-12-13 09:42:34 +0100 | [diff] [blame] | 44 | mov r0, sp |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 45 | badr lr, 9997f |
Marc Zyngier | abeb24a | 2011-09-06 09:23:26 +0100 | [diff] [blame] | 46 | ldr pc, [r1] |
| 47 | #else |
Magnus Damm | cd544ce | 2010-12-22 13:20:08 +0100 | [diff] [blame] | 48 | arch_irq_handler_default |
Marc Zyngier | abeb24a | 2011-09-06 09:23:26 +0100 | [diff] [blame] | 49 | #endif |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 50 | 9997: |
Russell King | 187a51a | 2005-05-21 18:14:44 +0100 | [diff] [blame] | 51 | .endm |
| 52 | |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 53 | .macro pabt_helper |
Russell King | 8dfe7ac | 2011-06-26 12:37:35 +0100 | [diff] [blame] | 54 | @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5 |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 55 | #ifdef MULTI_PABORT |
Russell King | 0402bec | 2011-06-25 15:46:08 +0100 | [diff] [blame] | 56 | ldr ip, .LCprocfns |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 57 | mov lr, pc |
Russell King | 0402bec | 2011-06-25 15:46:08 +0100 | [diff] [blame] | 58 | ldr pc, [ip, #PROCESSOR_PABT_FUNC] |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 59 | #else |
| 60 | bl CPU_PABORT_HANDLER |
| 61 | #endif |
| 62 | .endm |
| 63 | |
| 64 | .macro dabt_helper |
| 65 | |
| 66 | @ |
| 67 | @ Call the processor-specific abort handler: |
| 68 | @ |
Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 69 | @ r2 - pt_regs |
Russell King | 3e287be | 2011-06-26 14:35:07 +0100 | [diff] [blame] | 70 | @ r4 - aborted context pc |
| 71 | @ r5 - aborted context psr |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 72 | @ |
| 73 | @ The abort handler must return the aborted address in r0, and |
| 74 | @ the fault status register in r1. r9 must be preserved. |
| 75 | @ |
| 76 | #ifdef MULTI_DABORT |
Russell King | 0402bec | 2011-06-25 15:46:08 +0100 | [diff] [blame] | 77 | ldr ip, .LCprocfns |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 78 | mov lr, pc |
Russell King | 0402bec | 2011-06-25 15:46:08 +0100 | [diff] [blame] | 79 | ldr pc, [ip, #PROCESSOR_DABT_FUNC] |
Russell King | ac8b9c1 | 2011-06-26 10:22:08 +0100 | [diff] [blame] | 80 | #else |
| 81 | bl CPU_DABORT_HANDLER |
| 82 | #endif |
| 83 | .endm |
| 84 | |
Nicolas Pitre | 785d3cd | 2007-12-03 15:27:56 -0500 | [diff] [blame] | 85 | #ifdef CONFIG_KPROBES |
| 86 | .section .kprobes.text,"ax",%progbits |
| 87 | #else |
| 88 | .text |
| 89 | #endif |
| 90 | |
Russell King | 187a51a | 2005-05-21 18:14:44 +0100 | [diff] [blame] | 91 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | * Invalid mode handlers |
| 93 | */ |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 94 | .macro inv_entry, reason |
| 95 | sub sp, sp, #S_FRAME_SIZE |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 96 | ARM( stmib sp, {r1 - lr} ) |
| 97 | THUMB( stmia sp, {r0 - r12} ) |
| 98 | THUMB( str sp, [sp, #S_SP] ) |
| 99 | THUMB( str lr, [sp, #S_LR] ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | mov r1, #\reason |
| 101 | .endm |
| 102 | |
| 103 | __pabt_invalid: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 104 | inv_entry BAD_PREFETCH |
| 105 | b common_invalid |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 106 | ENDPROC(__pabt_invalid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | |
| 108 | __dabt_invalid: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 109 | inv_entry BAD_DATA |
| 110 | b common_invalid |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 111 | ENDPROC(__dabt_invalid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | |
| 113 | __irq_invalid: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 114 | inv_entry BAD_IRQ |
| 115 | b common_invalid |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 116 | ENDPROC(__irq_invalid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 117 | |
| 118 | __und_invalid: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 119 | inv_entry BAD_UNDEFINSTR |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 120 | |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 121 | @ |
| 122 | @ XXX fall through to common_invalid |
| 123 | @ |
| 124 | |
| 125 | @ |
| 126 | @ common_invalid - generic code for failed exception (re-entrant version of handlers) |
| 127 | @ |
| 128 | common_invalid: |
| 129 | zero_fp |
| 130 | |
| 131 | ldmia r0, {r4 - r6} |
| 132 | add r0, sp, #S_PC @ here for interlock avoidance |
| 133 | mov r7, #-1 @ "" "" "" "" |
| 134 | str r4, [sp] @ save preserved r0 |
| 135 | stmia r0, {r5 - r7} @ lr_<exception>, |
| 136 | @ cpsr_<exception>, "old_r0" |
| 137 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | mov r0, sp |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 139 | b bad_mode |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 140 | ENDPROC(__und_invalid) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | |
| 142 | /* |
| 143 | * SVC mode handlers |
| 144 | */ |
Nicolas Pitre | 2dede2d | 2006-01-14 16:18:08 +0000 | [diff] [blame] | 145 | |
| 146 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) |
| 147 | #define SPFIX(code...) code |
| 148 | #else |
| 149 | #define SPFIX(code...) |
| 150 | #endif |
| 151 | |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 152 | .macro svc_entry, stack_hole=0, trace=1, uaccess=1 |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 153 | UNWIND(.fnstart ) |
| 154 | UNWIND(.save {r0 - pc} ) |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 155 | sub sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4) |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 156 | #ifdef CONFIG_THUMB2_KERNEL |
| 157 | SPFIX( str r0, [sp] ) @ temporarily saved |
| 158 | SPFIX( mov r0, sp ) |
| 159 | SPFIX( tst r0, #4 ) @ test original stack alignment |
| 160 | SPFIX( ldr r0, [sp] ) @ restored |
| 161 | #else |
Nicolas Pitre | 2dede2d | 2006-01-14 16:18:08 +0000 | [diff] [blame] | 162 | SPFIX( tst sp, #4 ) |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 163 | #endif |
| 164 | SPFIX( subeq sp, sp, #4 ) |
| 165 | stmia sp, {r1 - r12} |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 166 | |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 167 | ldmia r0, {r3 - r5} |
| 168 | add r7, sp, #S_SP - 4 @ here for interlock avoidance |
| 169 | mov r6, #-1 @ "" "" "" "" |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 170 | add r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4) |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 171 | SPFIX( addeq r2, r2, #4 ) |
| 172 | str r3, [sp, #-4]! @ save the "real" r0 copied |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 173 | @ from the exception stack |
| 174 | |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 175 | mov r3, lr |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 176 | |
| 177 | @ |
| 178 | @ We are now ready to fill in the remaining blanks on the stack: |
| 179 | @ |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 180 | @ r2 - sp_svc |
| 181 | @ r3 - lr_svc |
| 182 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
| 183 | @ r5 - spsr_<exception> |
| 184 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | @ |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 186 | stmia r7, {r2 - r6} |
Russell King | f2741b7 | 2011-06-25 17:35:19 +0100 | [diff] [blame] | 187 | |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 188 | uaccess_save r0 |
| 189 | .if \uaccess |
| 190 | uaccess_disable r0 |
| 191 | .endif |
| 192 | |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 193 | .if \trace |
Russell King | f2741b7 | 2011-06-25 17:35:19 +0100 | [diff] [blame] | 194 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 195 | bl trace_hardirqs_off |
| 196 | #endif |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 197 | .endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 198 | .endm |
| 199 | |
| 200 | .align 5 |
| 201 | __dabt_svc: |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 202 | svc_entry uaccess=0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 203 | mov r2, sp |
Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 204 | dabt_helper |
Marc Zyngier | e16b31b | 2013-11-04 11:42:29 +0100 | [diff] [blame] | 205 | THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 206 | svc_exit r5 @ return from exception |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 207 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 208 | ENDPROC(__dabt_svc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | |
| 210 | .align 5 |
| 211 | __irq_svc: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 212 | svc_entry |
Russell King | 1613cc1 | 2011-06-25 10:57:57 +0100 | [diff] [blame] | 213 | irq_handler |
| 214 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 215 | #ifdef CONFIG_PREEMPT |
Russell King | 706fdd9 | 2005-05-21 18:15:45 +0100 | [diff] [blame] | 216 | get_thread_info tsk |
| 217 | ldr r8, [tsk, #TI_PREEMPT] @ get preempt count |
Russell King | 706fdd9 | 2005-05-21 18:15:45 +0100 | [diff] [blame] | 218 | ldr r0, [tsk, #TI_FLAGS] @ get flags |
Russell King | 28fab1a | 2008-04-13 17:47:35 +0100 | [diff] [blame] | 219 | teq r8, #0 @ if preempt count != 0 |
| 220 | movne r0, #0 @ force flags to 0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 221 | tst r0, #_TIF_NEED_RESCHED |
| 222 | blne svc_preempt |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | #endif |
Russell King | 30891c9 | 2011-06-26 12:47:08 +0100 | [diff] [blame] | 224 | |
Russell King | 9b56feb | 2013-03-28 12:57:40 +0000 | [diff] [blame] | 225 | svc_exit r5, irq = 1 @ return from exception |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 226 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 227 | ENDPROC(__irq_svc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | |
| 229 | .ltorg |
| 230 | |
| 231 | #ifdef CONFIG_PREEMPT |
| 232 | svc_preempt: |
Russell King | 28fab1a | 2008-04-13 17:47:35 +0100 | [diff] [blame] | 233 | mov r8, lr |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 234 | 1: bl preempt_schedule_irq @ irq en/disable is done inside |
Russell King | 706fdd9 | 2005-05-21 18:15:45 +0100 | [diff] [blame] | 235 | ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 236 | tst r0, #_TIF_NEED_RESCHED |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 237 | reteq r8 @ go again |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | b 1b |
| 239 | #endif |
| 240 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 241 | __und_fault: |
| 242 | @ Correct the PC such that it is pointing at the instruction |
| 243 | @ which caused the fault. If the faulting instruction was ARM |
| 244 | @ the PC will be pointing at the next instruction, and have to |
| 245 | @ subtract 4. Otherwise, it is Thumb, and the PC will be |
| 246 | @ pointing at the second half of the Thumb instruction. We |
| 247 | @ have to subtract 2. |
| 248 | ldr r2, [r0, #S_PC] |
| 249 | sub r2, r2, r1 |
| 250 | str r2, [r0, #S_PC] |
| 251 | b do_undefinstr |
| 252 | ENDPROC(__und_fault) |
| 253 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 254 | .align 5 |
| 255 | __und_svc: |
Nicolas Pitre | d30a0c8 | 2007-12-14 15:56:01 -0500 | [diff] [blame] | 256 | #ifdef CONFIG_KPROBES |
| 257 | @ If a kprobe is about to simulate a "stmdb sp..." instruction, |
| 258 | @ it obviously needs free stack space which then will belong to |
| 259 | @ the saved context. |
Wang Nan | a0266c2 | 2015-01-05 19:29:25 +0800 | [diff] [blame] | 260 | svc_entry MAX_STACK_SIZE |
Nicolas Pitre | d30a0c8 | 2007-12-14 15:56:01 -0500 | [diff] [blame] | 261 | #else |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 262 | svc_entry |
Nicolas Pitre | d30a0c8 | 2007-12-14 15:56:01 -0500 | [diff] [blame] | 263 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | @ |
| 265 | @ call emulation code, which returns using r9 if it has emulated |
| 266 | @ the instruction, or the more conventional lr if we are to treat |
| 267 | @ this as a real undefined instruction |
| 268 | @ |
| 269 | @ r0 - instruction |
| 270 | @ |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 271 | #ifndef CONFIG_THUMB2_KERNEL |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 272 | ldr r0, [r4, #-4] |
Catalin Marinas | 83e686e | 2009-09-18 23:27:07 +0100 | [diff] [blame] | 273 | #else |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 274 | mov r1, #2 |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 275 | ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2 |
Dave Martin | 8551918 | 2011-08-19 17:59:27 +0100 | [diff] [blame] | 276 | cmp r0, #0xe800 @ 32-bit instruction if xx >= 0 |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 277 | blo __und_svc_fault |
| 278 | ldrh r9, [r4] @ bottom 16 bits |
| 279 | add r4, r4, #2 |
| 280 | str r4, [sp, #S_PC] |
| 281 | orr r0, r9, r0, lsl #16 |
Catalin Marinas | 83e686e | 2009-09-18 23:27:07 +0100 | [diff] [blame] | 282 | #endif |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 283 | badr r9, __und_svc_finish |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 284 | mov r2, r4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | bl call_fpe |
| 286 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 287 | mov r1, #4 @ PC correction to apply |
| 288 | __und_svc_fault: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | mov r0, sp @ struct pt_regs *regs |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 290 | bl __und_fault |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 292 | __und_svc_finish: |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 293 | ldr r5, [sp, #S_PSR] @ Get SVC cpsr |
| 294 | svc_exit r5 @ return from exception |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 295 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 296 | ENDPROC(__und_svc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | |
| 298 | .align 5 |
| 299 | __pabt_svc: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 300 | svc_entry |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 301 | mov r2, sp @ regs |
Russell King | 8dfe7ac | 2011-06-26 12:37:35 +0100 | [diff] [blame] | 302 | pabt_helper |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 303 | svc_exit r5 @ return from exception |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 304 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 305 | ENDPROC(__pabt_svc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | |
| 307 | .align 5 |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 308 | __fiq_svc: |
| 309 | svc_entry trace=0 |
| 310 | mov r0, sp @ struct pt_regs *regs |
| 311 | bl handle_fiq_as_nmi |
| 312 | svc_exit_via_fiq |
| 313 | UNWIND(.fnend ) |
| 314 | ENDPROC(__fiq_svc) |
| 315 | |
| 316 | .align 5 |
Russell King | 49f680e | 2005-05-31 18:02:00 +0100 | [diff] [blame] | 317 | .LCcralign: |
| 318 | .word cr_alignment |
Paul Brook | 48d7927 | 2008-04-18 22:43:07 +0100 | [diff] [blame] | 319 | #ifdef MULTI_DABORT |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | .LCprocfns: |
| 321 | .word processor |
| 322 | #endif |
| 323 | .LCfp: |
| 324 | .word fp_enter |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 325 | |
| 326 | /* |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 327 | * Abort mode handlers |
| 328 | */ |
| 329 | |
| 330 | @ |
| 331 | @ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode |
| 332 | @ and reuses the same macros. However in abort mode we must also |
| 333 | @ save/restore lr_abt and spsr_abt to make nested aborts safe. |
| 334 | @ |
| 335 | .align 5 |
| 336 | __fiq_abt: |
| 337 | svc_entry trace=0 |
| 338 | |
| 339 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 340 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 341 | THUMB( msr cpsr_c, r0 ) |
| 342 | mov r1, lr @ Save lr_abt |
| 343 | mrs r2, spsr @ Save spsr_abt, abort is now safe |
| 344 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 345 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 346 | THUMB( msr cpsr_c, r0 ) |
| 347 | stmfd sp!, {r1 - r2} |
| 348 | |
| 349 | add r0, sp, #8 @ struct pt_regs *regs |
| 350 | bl handle_fiq_as_nmi |
| 351 | |
| 352 | ldmfd sp!, {r1 - r2} |
| 353 | ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 354 | THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 355 | THUMB( msr cpsr_c, r0 ) |
| 356 | mov lr, r1 @ Restore lr_abt, abort is unsafe |
| 357 | msr spsr_cxsf, r2 @ Restore spsr_abt |
| 358 | ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 359 | THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT ) |
| 360 | THUMB( msr cpsr_c, r0 ) |
| 361 | |
| 362 | svc_exit_via_fiq |
| 363 | UNWIND(.fnend ) |
| 364 | ENDPROC(__fiq_abt) |
| 365 | |
| 366 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | * User mode handlers |
Nicolas Pitre | 2dede2d | 2006-01-14 16:18:08 +0000 | [diff] [blame] | 368 | * |
| 369 | * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | */ |
Nicolas Pitre | 2dede2d | 2006-01-14 16:18:08 +0000 | [diff] [blame] | 371 | |
| 372 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7) |
| 373 | #error "sizeof(struct pt_regs) must be a multiple of 8" |
| 374 | #endif |
| 375 | |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 376 | .macro usr_entry, trace=1, uaccess=1 |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 377 | UNWIND(.fnstart ) |
| 378 | UNWIND(.cantunwind ) @ don't unwind the user space |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 379 | sub sp, sp, #S_FRAME_SIZE |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 380 | ARM( stmib sp, {r1 - r12} ) |
| 381 | THUMB( stmia sp, {r0 - r12} ) |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 382 | |
Russell King | 195b58a | 2014-08-28 13:08:14 +0100 | [diff] [blame] | 383 | ATRAP( mrc p15, 0, r7, c1, c0, 0) |
| 384 | ATRAP( ldr r8, .LCcralign) |
| 385 | |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 386 | ldmia r0, {r3 - r5} |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 387 | add r0, sp, #S_PC @ here for interlock avoidance |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 388 | mov r6, #-1 @ "" "" "" "" |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 389 | |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 390 | str r3, [sp] @ save the "real" r0 copied |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 391 | @ from the exception stack |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | |
Russell King | 195b58a | 2014-08-28 13:08:14 +0100 | [diff] [blame] | 393 | ATRAP( ldr r8, [r8, #0]) |
| 394 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | @ |
| 396 | @ We are now ready to fill in the remaining blanks on the stack: |
| 397 | @ |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 398 | @ r4 - lr_<exception>, already fixed up for correct return/restart |
| 399 | @ r5 - spsr_<exception> |
| 400 | @ r6 - orig_r0 (see pt_regs definition in ptrace.h) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | @ |
| 402 | @ Also, separately save sp_usr and lr_usr |
| 403 | @ |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 404 | stmia r0, {r4 - r6} |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 405 | ARM( stmdb r0, {sp, lr}^ ) |
| 406 | THUMB( store_user_sp_lr r0, r1, S_SP - S_PC ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 408 | .if \uaccess |
| 409 | uaccess_disable ip |
| 410 | .endif |
| 411 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 412 | @ Enable the alignment trap while in kernel mode |
Russell King | 195b58a | 2014-08-28 13:08:14 +0100 | [diff] [blame] | 413 | ATRAP( teq r8, r7) |
| 414 | ATRAP( mcrne p15, 0, r8, c1, c0, 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | |
| 416 | @ |
| 417 | @ Clear FP to mark the first stack frame |
| 418 | @ |
| 419 | zero_fp |
Russell King | f2741b7 | 2011-06-25 17:35:19 +0100 | [diff] [blame] | 420 | |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 421 | .if \trace |
Russell King | 11b8b25 | 2015-07-03 12:42:36 +0100 | [diff] [blame] | 422 | #ifdef CONFIG_TRACE_IRQFLAGS |
Russell King | f2741b7 | 2011-06-25 17:35:19 +0100 | [diff] [blame] | 423 | bl trace_hardirqs_off |
| 424 | #endif |
Kevin Hilman | b008848 | 2013-03-28 22:54:40 +0100 | [diff] [blame] | 425 | ct_user_exit save = 0 |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 426 | .endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 427 | .endm |
| 428 | |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 429 | .macro kuser_cmpxchg_check |
Russell King | db695c0 | 2015-09-21 19:34:28 +0100 | [diff] [blame] | 430 | #if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS) |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 431 | #ifndef CONFIG_MMU |
| 432 | #warning "NPTL on non MMU needs fixing" |
| 433 | #else |
| 434 | @ Make sure our user space atomic helper is restarted |
| 435 | @ if it was interrupted in a critical region. Here we |
| 436 | @ perform a quick test inline since it should be false |
| 437 | @ 99.9999% of the time. The rest is done out of line. |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 438 | cmp r4, #TASK_SIZE |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 439 | blhs kuser_cmpxchg64_fixup |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 440 | #endif |
| 441 | #endif |
| 442 | .endm |
| 443 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | .align 5 |
| 445 | __dabt_usr: |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 446 | usr_entry uaccess=0 |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 447 | kuser_cmpxchg_check |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | mov r2, sp |
Russell King | da74047 | 2011-06-26 16:01:26 +0100 | [diff] [blame] | 449 | dabt_helper |
| 450 | b ret_from_exception |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 451 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 452 | ENDPROC(__dabt_usr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | |
| 454 | .align 5 |
| 455 | __irq_usr: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 456 | usr_entry |
Russell King | bc08960 | 2011-06-25 18:28:19 +0100 | [diff] [blame] | 457 | kuser_cmpxchg_check |
Russell King | 187a51a | 2005-05-21 18:14:44 +0100 | [diff] [blame] | 458 | irq_handler |
Russell King | 1613cc1 | 2011-06-25 10:57:57 +0100 | [diff] [blame] | 459 | get_thread_info tsk |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 460 | mov why, #0 |
Ming Lei | 9fc2552 | 2011-06-05 02:24:58 +0100 | [diff] [blame] | 461 | b ret_to_user_from_irq |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 462 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 463 | ENDPROC(__irq_usr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | |
| 465 | .ltorg |
| 466 | |
| 467 | .align 5 |
| 468 | __und_usr: |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 469 | usr_entry uaccess=0 |
Russell King | bc08960 | 2011-06-25 18:28:19 +0100 | [diff] [blame] | 470 | |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 471 | mov r2, r4 |
| 472 | mov r3, r5 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 474 | @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the |
| 475 | @ faulting instruction depending on Thumb mode. |
| 476 | @ r3 = regs->ARM_cpsr |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | @ |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 478 | @ The emulation code returns using r9 if it has emulated the |
| 479 | @ instruction, or the more conventional lr if we are to treat |
| 480 | @ this as a real undefined instruction |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | @ |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 482 | badr r9, ret_from_exception |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 483 | |
Catalin Marinas | 1417a6b | 2014-04-22 16:14:29 +0100 | [diff] [blame] | 484 | @ IRQs must be enabled before attempting to read the instruction from |
| 485 | @ user space since that could cause a page/translation fault if the |
| 486 | @ page table was modified by another CPU. |
| 487 | enable_irq |
| 488 | |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 489 | tst r3, #PSR_T_BIT @ Thumb mode? |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 490 | bne __und_usr_thumb |
| 491 | sub r4, r2, #4 @ ARM instr at LR - 4 |
| 492 | 1: ldrt r0, [r4] |
Ben Dooks | 457c240 | 2013-02-12 18:59:57 +0000 | [diff] [blame] | 493 | ARM_BE8(rev r0, r0) @ little endian instruction |
| 494 | |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 495 | uaccess_disable ip |
| 496 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 497 | @ r0 = 32-bit ARM instruction which caused the exception |
| 498 | @ r2 = PC value for the following instruction (:= regs->ARM_pc) |
| 499 | @ r4 = PC value for the faulting instruction |
| 500 | @ lr = 32-bit undefined instruction function |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 501 | badr lr, __und_usr_fault_32 |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 502 | b call_fpe |
| 503 | |
| 504 | __und_usr_thumb: |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 505 | @ Thumb instruction |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 506 | sub r4, r2, #2 @ First half of thumb instr at LR - 2 |
Dave Martin | ef4c536 | 2011-08-19 18:00:08 +0100 | [diff] [blame] | 507 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
| 508 | /* |
| 509 | * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms |
| 510 | * can never be supported in a single kernel, this code is not applicable at |
| 511 | * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be |
| 512 | * made about .arch directives. |
| 513 | */ |
| 514 | #if __LINUX_ARM_ARCH__ < 7 |
| 515 | /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */ |
| 516 | #define NEED_CPU_ARCHITECTURE |
| 517 | ldr r5, .LCcpu_architecture |
| 518 | ldr r5, [r5] |
| 519 | cmp r5, #CPU_ARCH_ARMv7 |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 520 | blo __und_usr_fault_16 @ 16bit undefined instruction |
Dave Martin | ef4c536 | 2011-08-19 18:00:08 +0100 | [diff] [blame] | 521 | /* |
| 522 | * The following code won't get run unless the running CPU really is v7, so |
| 523 | * coding round the lack of ldrht on older arches is pointless. Temporarily |
| 524 | * override the assembler target arch with the minimum required instead: |
| 525 | */ |
| 526 | .arch armv6t2 |
| 527 | #endif |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 528 | 2: ldrht r5, [r4] |
Victor Kamensky | f8fe23e | 2014-01-21 06:45:11 +0100 | [diff] [blame] | 529 | ARM_BE8(rev16 r5, r5) @ little endian instruction |
Dave Martin | 8551918 | 2011-08-19 17:59:27 +0100 | [diff] [blame] | 530 | cmp r5, #0xe800 @ 32bit instruction if xx != 0 |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 531 | blo __und_usr_fault_16_pan @ 16bit undefined instruction |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 532 | 3: ldrht r0, [r2] |
Victor Kamensky | f8fe23e | 2014-01-21 06:45:11 +0100 | [diff] [blame] | 533 | ARM_BE8(rev16 r0, r0) @ little endian instruction |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 534 | uaccess_disable ip |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 535 | add r2, r2, #2 @ r2 is PC + 2, make it PC + 4 |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 536 | str r2, [sp, #S_PC] @ it's a 2x16bit instr, update |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 537 | orr r0, r0, r5, lsl #16 |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 538 | badr lr, __und_usr_fault_32 |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 539 | @ r0 = the two 16-bit Thumb instructions which caused the exception |
| 540 | @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc) |
| 541 | @ r4 = PC value for the first 16-bit Thumb instruction |
| 542 | @ lr = 32bit undefined instruction function |
Dave Martin | ef4c536 | 2011-08-19 18:00:08 +0100 | [diff] [blame] | 543 | |
| 544 | #if __LINUX_ARM_ARCH__ < 7 |
| 545 | /* If the target arch was overridden, change it back: */ |
| 546 | #ifdef CONFIG_CPU_32v6K |
| 547 | .arch armv6k |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 548 | #else |
Dave Martin | ef4c536 | 2011-08-19 18:00:08 +0100 | [diff] [blame] | 549 | .arch armv6 |
| 550 | #endif |
| 551 | #endif /* __LINUX_ARM_ARCH__ < 7 */ |
| 552 | #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */ |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 553 | b __und_usr_fault_16 |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 554 | #endif |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 555 | UNWIND(.fnend) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 556 | ENDPROC(__und_usr) |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 557 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | /* |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 559 | * The out of line fixup for the ldrt instructions above. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | */ |
Ard Biesheuvel | c4a84ae | 2015-03-24 10:41:09 +0100 | [diff] [blame] | 561 | .pushsection .text.fixup, "ax" |
Will Deacon | 667d1b4 | 2012-06-15 16:49:58 +0100 | [diff] [blame] | 562 | .align 2 |
Arun K S | 3780f7a | 2014-05-19 11:43:00 +0100 | [diff] [blame] | 563 | 4: str r4, [sp, #S_PC] @ retry current instruction |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 564 | ret r9 |
Russell King | 4260415 | 2010-04-19 10:15:03 +0100 | [diff] [blame] | 565 | .popsection |
| 566 | .pushsection __ex_table,"a" |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 567 | .long 1b, 4b |
Guennadi Liakhovetski | c89cefe | 2011-11-22 23:42:12 +0100 | [diff] [blame] | 568 | #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7 |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 569 | .long 2b, 4b |
| 570 | .long 3b, 4b |
| 571 | #endif |
Russell King | 4260415 | 2010-04-19 10:15:03 +0100 | [diff] [blame] | 572 | .popsection |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 573 | |
| 574 | /* |
| 575 | * Check whether the instruction is a co-processor instruction. |
| 576 | * If yes, we need to call the relevant co-processor handler. |
| 577 | * |
| 578 | * Note that we don't do a full check here for the co-processor |
| 579 | * instructions; all instructions with bit 27 set are well |
| 580 | * defined. The only instructions that should fault are the |
| 581 | * co-processor instructions. However, we have to watch out |
| 582 | * for the ARM6/ARM7 SWI bug. |
| 583 | * |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 584 | * NEON is a special case that has to be handled here. Not all |
| 585 | * NEON instructions are co-processor instructions, so we have |
| 586 | * to make a special case of checking for them. Plus, there's |
| 587 | * five groups of them, so we have a table of mask/opcode pairs |
| 588 | * to check against, and if any match then we branch off into the |
| 589 | * NEON handler code. |
| 590 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 591 | * Emulators may wish to make use of the following registers: |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 592 | * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) |
| 593 | * r2 = PC value to resume execution after successful emulation |
Russell King | db6ccbb6 | 2007-01-06 22:53:48 +0000 | [diff] [blame] | 594 | * r9 = normal "successful" return address |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 595 | * r10 = this threads thread_info structure |
Russell King | db6ccbb6 | 2007-01-06 22:53:48 +0000 | [diff] [blame] | 596 | * lr = unrecognised instruction return address |
Catalin Marinas | 1417a6b | 2014-04-22 16:14:29 +0100 | [diff] [blame] | 597 | * IRQs enabled, FIQs enabled. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 598 | */ |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 599 | @ |
| 600 | @ Fall-through from Thumb-2 __und_usr |
| 601 | @ |
| 602 | #ifdef CONFIG_NEON |
Russell King | d3f7958 | 2013-02-23 17:53:52 +0000 | [diff] [blame] | 603 | get_thread_info r10 @ get current thread |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 604 | adr r6, .LCneon_thumb_opcodes |
| 605 | b 2f |
| 606 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 607 | call_fpe: |
Russell King | d3f7958 | 2013-02-23 17:53:52 +0000 | [diff] [blame] | 608 | get_thread_info r10 @ get current thread |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 609 | #ifdef CONFIG_NEON |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 610 | adr r6, .LCneon_arm_opcodes |
Russell King | d3f7958 | 2013-02-23 17:53:52 +0000 | [diff] [blame] | 611 | 2: ldr r5, [r6], #4 @ mask value |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 612 | ldr r7, [r6], #4 @ opcode bits matching in mask |
Russell King | d3f7958 | 2013-02-23 17:53:52 +0000 | [diff] [blame] | 613 | cmp r5, #0 @ end mask? |
| 614 | beq 1f |
| 615 | and r8, r0, r5 |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 616 | cmp r8, r7 @ NEON instruction? |
| 617 | bne 2b |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 618 | mov r7, #1 |
| 619 | strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used |
| 620 | strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used |
| 621 | b do_vfp @ let VFP handler handle this |
| 622 | 1: |
| 623 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27 |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 625 | tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2 |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 626 | reteq lr |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 627 | and r8, r0, #0x00000f00 @ mask out CP number |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 628 | THUMB( lsr r8, r8, #8 ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 629 | mov r7, #1 |
| 630 | add r6, r10, #TI_USED_CP |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 631 | ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[] |
| 632 | THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[] |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | #ifdef CONFIG_IWMMXT |
| 634 | @ Test if we need to give access to iWMMXt coprocessors |
| 635 | ldr r5, [r10, #TI_FLAGS] |
| 636 | rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only |
| 637 | movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1) |
| 638 | bcs iwmmxt_task_enable |
| 639 | #endif |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 640 | ARM( add pc, pc, r8, lsr #6 ) |
| 641 | THUMB( lsl r8, r8, #2 ) |
| 642 | THUMB( add pc, r8 ) |
| 643 | nop |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 644 | |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 645 | ret.w lr @ CP#0 |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 646 | W(b) do_fpe @ CP#1 (FPE) |
| 647 | W(b) do_fpe @ CP#2 (FPE) |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 648 | ret.w lr @ CP#3 |
Lennert Buytenhek | c17fad1 | 2006-06-27 23:03:03 +0100 | [diff] [blame] | 649 | #ifdef CONFIG_CRUNCH |
| 650 | b crunch_task_enable @ CP#4 (MaverickCrunch) |
| 651 | b crunch_task_enable @ CP#5 (MaverickCrunch) |
| 652 | b crunch_task_enable @ CP#6 (MaverickCrunch) |
| 653 | #else |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 654 | ret.w lr @ CP#4 |
| 655 | ret.w lr @ CP#5 |
| 656 | ret.w lr @ CP#6 |
Lennert Buytenhek | c17fad1 | 2006-06-27 23:03:03 +0100 | [diff] [blame] | 657 | #endif |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 658 | ret.w lr @ CP#7 |
| 659 | ret.w lr @ CP#8 |
| 660 | ret.w lr @ CP#9 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | #ifdef CONFIG_VFP |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 662 | W(b) do_vfp @ CP#10 (VFP) |
| 663 | W(b) do_vfp @ CP#11 (VFP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 664 | #else |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 665 | ret.w lr @ CP#10 (VFP) |
| 666 | ret.w lr @ CP#11 (VFP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 667 | #endif |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 668 | ret.w lr @ CP#12 |
| 669 | ret.w lr @ CP#13 |
| 670 | ret.w lr @ CP#14 (Debug) |
| 671 | ret.w lr @ CP#15 (Control) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 672 | |
Dave Martin | ef4c536 | 2011-08-19 18:00:08 +0100 | [diff] [blame] | 673 | #ifdef NEED_CPU_ARCHITECTURE |
| 674 | .align 2 |
| 675 | .LCcpu_architecture: |
| 676 | .word __cpu_architecture |
| 677 | #endif |
| 678 | |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 679 | #ifdef CONFIG_NEON |
| 680 | .align 6 |
| 681 | |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 682 | .LCneon_arm_opcodes: |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 683 | .word 0xfe000000 @ mask |
| 684 | .word 0xf2000000 @ opcode |
| 685 | |
| 686 | .word 0xff100000 @ mask |
| 687 | .word 0xf4000000 @ opcode |
| 688 | |
| 689 | .word 0x00000000 @ mask |
| 690 | .word 0x00000000 @ opcode |
Paul Brook | cb170a4 | 2008-04-18 22:43:08 +0100 | [diff] [blame] | 691 | |
| 692 | .LCneon_thumb_opcodes: |
| 693 | .word 0xef000000 @ mask |
| 694 | .word 0xef000000 @ opcode |
| 695 | |
| 696 | .word 0xff100000 @ mask |
| 697 | .word 0xf9000000 @ opcode |
| 698 | |
| 699 | .word 0x00000000 @ mask |
| 700 | .word 0x00000000 @ opcode |
Catalin Marinas | b5872db | 2008-01-10 19:16:17 +0100 | [diff] [blame] | 701 | #endif |
| 702 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 703 | do_fpe: |
| 704 | ldr r4, .LCfp |
| 705 | add r10, r10, #TI_FPSTATE @ r10 = workspace |
| 706 | ldr pc, [r4] @ Call FP module USR entry point |
| 707 | |
| 708 | /* |
| 709 | * The FP module is called with these registers set: |
| 710 | * r0 = instruction |
| 711 | * r2 = PC+4 |
| 712 | * r9 = normal "successful" return address |
| 713 | * r10 = FP workspace |
| 714 | * lr = unrecognised FP instruction return address |
| 715 | */ |
| 716 | |
Santosh Shilimkar | 124efc2 | 2010-04-30 10:45:46 +0100 | [diff] [blame] | 717 | .pushsection .data |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | ENTRY(fp_enter) |
Russell King | db6ccbb6 | 2007-01-06 22:53:48 +0000 | [diff] [blame] | 719 | .word no_fp |
Santosh Shilimkar | 124efc2 | 2010-04-30 10:45:46 +0100 | [diff] [blame] | 720 | .popsection |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 721 | |
Catalin Marinas | 83e686e | 2009-09-18 23:27:07 +0100 | [diff] [blame] | 722 | ENTRY(no_fp) |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 723 | ret lr |
Catalin Marinas | 83e686e | 2009-09-18 23:27:07 +0100 | [diff] [blame] | 724 | ENDPROC(no_fp) |
Russell King | db6ccbb6 | 2007-01-06 22:53:48 +0000 | [diff] [blame] | 725 | |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 726 | __und_usr_fault_32: |
| 727 | mov r1, #4 |
| 728 | b 1f |
Russell King | 2190fed | 2015-08-20 10:32:02 +0100 | [diff] [blame] | 729 | __und_usr_fault_16_pan: |
| 730 | uaccess_disable ip |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 731 | __und_usr_fault_16: |
| 732 | mov r1, #2 |
Catalin Marinas | 1417a6b | 2014-04-22 16:14:29 +0100 | [diff] [blame] | 733 | 1: mov r0, sp |
Russell King | 14327c6 | 2015-04-21 14:17:25 +0100 | [diff] [blame] | 734 | badr lr, ret_from_exception |
Russell King | 15ac49b | 2012-07-30 19:42:10 +0100 | [diff] [blame] | 735 | b __und_fault |
| 736 | ENDPROC(__und_usr_fault_32) |
| 737 | ENDPROC(__und_usr_fault_16) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 738 | |
| 739 | .align 5 |
| 740 | __pabt_usr: |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 741 | usr_entry |
Kirill A. Shutemov | 4fb2847 | 2009-09-25 13:39:47 +0100 | [diff] [blame] | 742 | mov r2, sp @ regs |
Russell King | 8dfe7ac | 2011-06-26 12:37:35 +0100 | [diff] [blame] | 743 | pabt_helper |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 744 | UNWIND(.fnend ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | /* fall through */ |
| 746 | /* |
| 747 | * This is the return code to user mode for abort handlers |
| 748 | */ |
| 749 | ENTRY(ret_from_exception) |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 750 | UNWIND(.fnstart ) |
| 751 | UNWIND(.cantunwind ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 752 | get_thread_info tsk |
| 753 | mov why, #0 |
| 754 | b ret_to_user |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 755 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 756 | ENDPROC(__pabt_usr) |
| 757 | ENDPROC(ret_from_exception) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 759 | .align 5 |
| 760 | __fiq_usr: |
| 761 | usr_entry trace=0 |
| 762 | kuser_cmpxchg_check |
| 763 | mov r0, sp @ struct pt_regs *regs |
| 764 | bl handle_fiq_as_nmi |
| 765 | get_thread_info tsk |
| 766 | restore_user_regs fast = 0, offset = 0 |
| 767 | UNWIND(.fnend ) |
| 768 | ENDPROC(__fiq_usr) |
| 769 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | /* |
| 771 | * Register switch for ARMv3 and ARMv4 processors |
| 772 | * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info |
| 773 | * previous and next are guaranteed not to be the same. |
| 774 | */ |
| 775 | ENTRY(__switch_to) |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 776 | UNWIND(.fnstart ) |
| 777 | UNWIND(.cantunwind ) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | add ip, r1, #TI_CPU_SAVE |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 779 | ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack |
| 780 | THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack |
| 781 | THUMB( str sp, [ip], #4 ) |
| 782 | THUMB( str lr, [ip], #4 ) |
André Hentschel | a4780ad | 2013-06-18 23:23:26 +0100 | [diff] [blame] | 783 | ldr r4, [r2, #TI_TP_VALUE] |
| 784 | ldr r5, [r2, #TI_TP_VALUE + 4] |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 785 | #ifdef CONFIG_CPU_USE_DOMAINS |
Russell King | 1eef5d2 | 2015-08-19 21:23:48 +0100 | [diff] [blame] | 786 | mrc p15, 0, r6, c3, c0, 0 @ Get domain register |
| 787 | str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register |
Russell King | d6551e8 | 2006-06-21 13:31:52 +0100 | [diff] [blame] | 788 | ldr r6, [r2, #TI_CPU_DOMAIN] |
Hyok S. Choi | afeb90c | 2006-01-13 21:05:25 +0000 | [diff] [blame] | 789 | #endif |
André Hentschel | a4780ad | 2013-06-18 23:23:26 +0100 | [diff] [blame] | 790 | switch_tls r1, r4, r5, r3, r7 |
Nicolas Pitre | df0698b | 2010-06-07 21:50:33 -0400 | [diff] [blame] | 791 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
| 792 | ldr r7, [r2, #TI_TASK] |
| 793 | ldr r8, =__stack_chk_guard |
| 794 | ldr r7, [r7, #TSK_STACK_CANARY] |
| 795 | #endif |
Catalin Marinas | 247055a | 2010-09-13 16:03:21 +0100 | [diff] [blame] | 796 | #ifdef CONFIG_CPU_USE_DOMAINS |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 797 | mcr p15, 0, r6, c3, c0, 0 @ Set domain register |
Hyok S. Choi | afeb90c | 2006-01-13 21:05:25 +0000 | [diff] [blame] | 798 | #endif |
Russell King | d6551e8 | 2006-06-21 13:31:52 +0100 | [diff] [blame] | 799 | mov r5, r0 |
| 800 | add r4, r2, #TI_CPU_SAVE |
| 801 | ldr r0, =thread_notify_head |
| 802 | mov r1, #THREAD_NOTIFY_SWITCH |
| 803 | bl atomic_notifier_call_chain |
Nicolas Pitre | df0698b | 2010-06-07 21:50:33 -0400 | [diff] [blame] | 804 | #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP) |
| 805 | str r7, [r8] |
| 806 | #endif |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 807 | THUMB( mov ip, r4 ) |
Russell King | d6551e8 | 2006-06-21 13:31:52 +0100 | [diff] [blame] | 808 | mov r0, r5 |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 809 | ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously |
| 810 | THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously |
| 811 | THUMB( ldr sp, [ip], #4 ) |
| 812 | THUMB( ldr pc, [ip] ) |
Catalin Marinas | c4c5716 | 2009-02-16 11:42:09 +0100 | [diff] [blame] | 813 | UNWIND(.fnend ) |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 814 | ENDPROC(__switch_to) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 815 | |
| 816 | __INIT |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 817 | |
| 818 | /* |
| 819 | * User helpers. |
| 820 | * |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 821 | * Each segment is 32-byte aligned and will be moved to the top of the high |
| 822 | * vector page. New segments (if ever needed) must be added in front of |
| 823 | * existing ones. This mechanism should be used only for things that are |
| 824 | * really small and justified, and not be abused freely. |
| 825 | * |
Nicolas Pitre | 37b8304 | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 826 | * See Documentation/arm/kernel_user_helpers.txt for formal definitions. |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 827 | */ |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 828 | THUMB( .arm ) |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 829 | |
Nicolas Pitre | ba9b5d7 | 2006-08-18 17:20:15 +0100 | [diff] [blame] | 830 | .macro usr_ret, reg |
| 831 | #ifdef CONFIG_ARM_THUMB |
| 832 | bx \reg |
| 833 | #else |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 834 | ret \reg |
Nicolas Pitre | ba9b5d7 | 2006-08-18 17:20:15 +0100 | [diff] [blame] | 835 | #endif |
| 836 | .endm |
| 837 | |
Russell King | 5b43e7a | 2013-07-04 11:32:04 +0100 | [diff] [blame] | 838 | .macro kuser_pad, sym, size |
| 839 | .if (. - \sym) & 3 |
| 840 | .rept 4 - (. - \sym) & 3 |
| 841 | .byte 0 |
| 842 | .endr |
| 843 | .endif |
| 844 | .rept (\size - (. - \sym)) / 4 |
| 845 | .word 0xe7fddef1 |
| 846 | .endr |
| 847 | .endm |
| 848 | |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 849 | #ifdef CONFIG_KUSER_HELPERS |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 850 | .align 5 |
| 851 | .globl __kuser_helper_start |
| 852 | __kuser_helper_start: |
| 853 | |
| 854 | /* |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 855 | * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular |
| 856 | * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point. |
Nicolas Pitre | 7c612bf | 2005-12-19 22:20:51 +0000 | [diff] [blame] | 857 | */ |
| 858 | |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 859 | __kuser_cmpxchg64: @ 0xffff0f60 |
| 860 | |
Russell King | db695c0 | 2015-09-21 19:34:28 +0100 | [diff] [blame] | 861 | #if defined(CONFIG_CPU_32v6K) |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 862 | |
| 863 | stmfd sp!, {r4, r5, r6, r7} |
| 864 | ldrd r4, r5, [r0] @ load old val |
| 865 | ldrd r6, r7, [r1] @ load new val |
| 866 | smp_dmb arm |
| 867 | 1: ldrexd r0, r1, [r2] @ load current val |
| 868 | eors r3, r0, r4 @ compare with oldval (1) |
| 869 | eoreqs r3, r1, r5 @ compare with oldval (2) |
| 870 | strexdeq r3, r6, r7, [r2] @ store newval if eq |
| 871 | teqeq r3, #1 @ success? |
| 872 | beq 1b @ if no then retry |
| 873 | smp_dmb arm |
| 874 | rsbs r0, r3, #0 @ set returned val and C flag |
| 875 | ldmfd sp!, {r4, r5, r6, r7} |
Will Deacon | 5a97d0a | 2012-02-03 11:08:05 +0100 | [diff] [blame] | 876 | usr_ret lr |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 877 | |
| 878 | #elif !defined(CONFIG_SMP) |
| 879 | |
| 880 | #ifdef CONFIG_MMU |
| 881 | |
| 882 | /* |
| 883 | * The only thing that can break atomicity in this cmpxchg64 |
| 884 | * implementation is either an IRQ or a data abort exception |
| 885 | * causing another process/thread to be scheduled in the middle of |
| 886 | * the critical sequence. The same strategy as for cmpxchg is used. |
| 887 | */ |
| 888 | stmfd sp!, {r4, r5, r6, lr} |
| 889 | ldmia r0, {r4, r5} @ load old val |
| 890 | ldmia r1, {r6, lr} @ load new val |
| 891 | 1: ldmia r2, {r0, r1} @ load current val |
| 892 | eors r3, r0, r4 @ compare with oldval (1) |
| 893 | eoreqs r3, r1, r5 @ compare with oldval (2) |
| 894 | 2: stmeqia r2, {r6, lr} @ store newval if eq |
| 895 | rsbs r0, r3, #0 @ set return val and C flag |
| 896 | ldmfd sp!, {r4, r5, r6, pc} |
| 897 | |
| 898 | .text |
| 899 | kuser_cmpxchg64_fixup: |
| 900 | @ Called from kuser_cmpxchg_fixup. |
Russell King | 3ad5515 | 2011-07-22 23:09:07 +0100 | [diff] [blame] | 901 | @ r4 = address of interrupted insn (must be preserved). |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 902 | @ sp = saved regs. r7 and r8 are clobbered. |
| 903 | @ 1b = first critical insn, 2b = last critical insn. |
Russell King | 3ad5515 | 2011-07-22 23:09:07 +0100 | [diff] [blame] | 904 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 905 | mov r7, #0xffff0fff |
| 906 | sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64))) |
Russell King | 3ad5515 | 2011-07-22 23:09:07 +0100 | [diff] [blame] | 907 | subs r8, r4, r7 |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 908 | rsbcss r8, r8, #(2b - 1b) |
| 909 | strcs r7, [sp, #S_PC] |
| 910 | #if __LINUX_ARM_ARCH__ < 6 |
| 911 | bcc kuser_cmpxchg32_fixup |
| 912 | #endif |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 913 | ret lr |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 914 | .previous |
| 915 | |
| 916 | #else |
| 917 | #warning "NPTL on non MMU needs fixing" |
| 918 | mov r0, #-1 |
| 919 | adds r0, r0, #0 |
| 920 | usr_ret lr |
| 921 | #endif |
| 922 | |
| 923 | #else |
| 924 | #error "incoherent kernel configuration" |
| 925 | #endif |
| 926 | |
Russell King | 5b43e7a | 2013-07-04 11:32:04 +0100 | [diff] [blame] | 927 | kuser_pad __kuser_cmpxchg64, 64 |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 928 | |
Nicolas Pitre | 7c612bf | 2005-12-19 22:20:51 +0000 | [diff] [blame] | 929 | __kuser_memory_barrier: @ 0xffff0fa0 |
Dave Martin | ed3768a | 2010-12-01 15:39:23 +0100 | [diff] [blame] | 930 | smp_dmb arm |
Nicolas Pitre | ba9b5d7 | 2006-08-18 17:20:15 +0100 | [diff] [blame] | 931 | usr_ret lr |
Nicolas Pitre | 7c612bf | 2005-12-19 22:20:51 +0000 | [diff] [blame] | 932 | |
Russell King | 5b43e7a | 2013-07-04 11:32:04 +0100 | [diff] [blame] | 933 | kuser_pad __kuser_memory_barrier, 32 |
Nicolas Pitre | 7c612bf | 2005-12-19 22:20:51 +0000 | [diff] [blame] | 934 | |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 935 | __kuser_cmpxchg: @ 0xffff0fc0 |
| 936 | |
Russell King | db695c0 | 2015-09-21 19:34:28 +0100 | [diff] [blame] | 937 | #if __LINUX_ARM_ARCH__ < 6 |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 938 | |
Nicolas Pitre | 49bca4c | 2006-02-08 21:19:37 +0000 | [diff] [blame] | 939 | #ifdef CONFIG_MMU |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 940 | |
| 941 | /* |
| 942 | * The only thing that can break atomicity in this cmpxchg |
| 943 | * implementation is either an IRQ or a data abort exception |
| 944 | * causing another process/thread to be scheduled in the middle |
| 945 | * of the critical sequence. To prevent this, code is added to |
| 946 | * the IRQ and data abort exception handlers to set the pc back |
| 947 | * to the beginning of the critical section if it is found to be |
| 948 | * within that critical section (see kuser_cmpxchg_fixup). |
| 949 | */ |
| 950 | 1: ldr r3, [r2] @ load current val |
| 951 | subs r3, r3, r0 @ compare with oldval |
| 952 | 2: streq r1, [r2] @ store newval if eq |
| 953 | rsbs r0, r3, #0 @ set return val and C flag |
| 954 | usr_ret lr |
| 955 | |
| 956 | .text |
Nicolas Pitre | 40fb79c | 2011-06-19 23:36:03 -0400 | [diff] [blame] | 957 | kuser_cmpxchg32_fixup: |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 958 | @ Called from kuser_cmpxchg_check macro. |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 959 | @ r4 = address of interrupted insn (must be preserved). |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 960 | @ sp = saved regs. r7 and r8 are clobbered. |
| 961 | @ 1b = first critical insn, 2b = last critical insn. |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 962 | @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b. |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 963 | mov r7, #0xffff0fff |
| 964 | sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg))) |
Russell King | b059bdc | 2011-06-25 15:44:20 +0100 | [diff] [blame] | 965 | subs r8, r4, r7 |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 966 | rsbcss r8, r8, #(2b - 1b) |
| 967 | strcs r7, [sp, #S_PC] |
Russell King | 6ebbf2c | 2014-06-30 16:29:12 +0100 | [diff] [blame] | 968 | ret lr |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 969 | .previous |
| 970 | |
Nicolas Pitre | 49bca4c | 2006-02-08 21:19:37 +0000 | [diff] [blame] | 971 | #else |
| 972 | #warning "NPTL on non MMU needs fixing" |
| 973 | mov r0, #-1 |
| 974 | adds r0, r0, #0 |
Nicolas Pitre | ba9b5d7 | 2006-08-18 17:20:15 +0100 | [diff] [blame] | 975 | usr_ret lr |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 976 | #endif |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 977 | |
| 978 | #else |
| 979 | |
Dave Martin | ed3768a | 2010-12-01 15:39:23 +0100 | [diff] [blame] | 980 | smp_dmb arm |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 981 | 1: ldrex r3, [r2] |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 982 | subs r3, r3, r0 |
| 983 | strexeq r3, r1, [r2] |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 984 | teqeq r3, #1 |
| 985 | beq 1b |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 986 | rsbs r0, r3, #0 |
Nicolas Pitre | b49c0f2 | 2007-11-20 17:20:29 +0100 | [diff] [blame] | 987 | /* beware -- each __kuser slot must be 8 instructions max */ |
Russell King | f00ec48 | 2010-09-04 10:47:48 +0100 | [diff] [blame] | 988 | ALT_SMP(b __kuser_memory_barrier) |
| 989 | ALT_UP(usr_ret lr) |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 990 | |
| 991 | #endif |
| 992 | |
Russell King | 5b43e7a | 2013-07-04 11:32:04 +0100 | [diff] [blame] | 993 | kuser_pad __kuser_cmpxchg, 32 |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 994 | |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 995 | __kuser_get_tls: @ 0xffff0fe0 |
Tony Lindgren | f159f4e | 2010-07-05 14:53:10 +0100 | [diff] [blame] | 996 | ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init |
Nicolas Pitre | ba9b5d7 | 2006-08-18 17:20:15 +0100 | [diff] [blame] | 997 | usr_ret lr |
Tony Lindgren | f159f4e | 2010-07-05 14:53:10 +0100 | [diff] [blame] | 998 | mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code |
Russell King | 5b43e7a | 2013-07-04 11:32:04 +0100 | [diff] [blame] | 999 | kuser_pad __kuser_get_tls, 16 |
| 1000 | .rep 3 |
Tony Lindgren | f159f4e | 2010-07-05 14:53:10 +0100 | [diff] [blame] | 1001 | .word 0 @ 0xffff0ff0 software TLS value, then |
| 1002 | .endr @ pad up to __kuser_helper_version |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 1003 | |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 1004 | __kuser_helper_version: @ 0xffff0ffc |
| 1005 | .word ((__kuser_helper_end - __kuser_helper_start) >> 5) |
| 1006 | |
| 1007 | .globl __kuser_helper_end |
| 1008 | __kuser_helper_end: |
| 1009 | |
Russell King | f6f91b0 | 2013-07-23 18:37:00 +0100 | [diff] [blame] | 1010 | #endif |
| 1011 | |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 1012 | THUMB( .thumb ) |
Nicolas Pitre | 2d2669b | 2005-04-29 22:08:33 +0100 | [diff] [blame] | 1013 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1014 | /* |
| 1015 | * Vector stubs. |
| 1016 | * |
Russell King | 19accfd | 2013-07-04 11:40:32 +0100 | [diff] [blame] | 1017 | * This code is copied to 0xffff1000 so we can use branches in the |
| 1018 | * vectors, rather than ldr's. Note that this code must not exceed |
| 1019 | * a page size. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1020 | * |
| 1021 | * Common stub entry macro: |
| 1022 | * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 1023 | * |
| 1024 | * SP points to a minimal amount of processor-private memory, the address |
| 1025 | * of which is copied into r0 for the mode specific abort handler. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1026 | */ |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1027 | .macro vector_stub, name, mode, correction=0 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | .align 5 |
| 1029 | |
| 1030 | vector_\name: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1031 | .if \correction |
| 1032 | sub lr, lr, #\correction |
| 1033 | .endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1034 | |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 1035 | @ |
| 1036 | @ Save r0, lr_<exception> (parent PC) and spsr_<exception> |
| 1037 | @ (parent CPSR) |
| 1038 | @ |
| 1039 | stmia sp, {r0, lr} @ save r0, lr |
| 1040 | mrs lr, spsr |
| 1041 | str lr, [sp, #8] @ save spsr |
| 1042 | |
| 1043 | @ |
| 1044 | @ Prepare for SVC32 mode. IRQs remain disabled. |
| 1045 | @ |
| 1046 | mrs r0, cpsr |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 1047 | eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE) |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 1048 | msr spsr_cxsf, r0 |
| 1049 | |
| 1050 | @ |
| 1051 | @ the branch table must immediately follow this code |
| 1052 | @ |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 1053 | and lr, lr, #0x0f |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 1054 | THUMB( adr r0, 1f ) |
| 1055 | THUMB( ldr lr, [r0, lr, lsl #2] ) |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1056 | mov r0, sp |
Catalin Marinas | b86040a | 2009-07-24 12:32:54 +0100 | [diff] [blame] | 1057 | ARM( ldr lr, [pc, lr, lsl #2] ) |
Russell King | ccea7a1 | 2005-05-31 22:22:32 +0100 | [diff] [blame] | 1058 | movs pc, lr @ branch to handler in SVC mode |
Catalin Marinas | 93ed397 | 2008-08-28 11:22:32 +0100 | [diff] [blame] | 1059 | ENDPROC(vector_\name) |
Catalin Marinas | 88987ef | 2009-07-24 12:32:52 +0100 | [diff] [blame] | 1060 | |
| 1061 | .align 2 |
| 1062 | @ handler addresses follow this label |
| 1063 | 1: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1064 | .endm |
| 1065 | |
Russell King | b9b32bf | 2013-07-04 12:03:31 +0100 | [diff] [blame] | 1066 | .section .stubs, "ax", %progbits |
Russell King | 19accfd | 2013-07-04 11:40:32 +0100 | [diff] [blame] | 1067 | @ This must be the first word |
| 1068 | .word vector_swi |
| 1069 | |
| 1070 | vector_rst: |
| 1071 | ARM( swi SYS_ERROR0 ) |
| 1072 | THUMB( svc #0 ) |
| 1073 | THUMB( nop ) |
| 1074 | b vector_und |
| 1075 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1076 | /* |
| 1077 | * Interrupt dispatcher |
| 1078 | */ |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1079 | vector_stub irq, IRQ_MODE, 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1080 | |
| 1081 | .long __irq_usr @ 0 (USR_26 / USR_32) |
| 1082 | .long __irq_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1083 | .long __irq_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1084 | .long __irq_svc @ 3 (SVC_26 / SVC_32) |
| 1085 | .long __irq_invalid @ 4 |
| 1086 | .long __irq_invalid @ 5 |
| 1087 | .long __irq_invalid @ 6 |
| 1088 | .long __irq_invalid @ 7 |
| 1089 | .long __irq_invalid @ 8 |
| 1090 | .long __irq_invalid @ 9 |
| 1091 | .long __irq_invalid @ a |
| 1092 | .long __irq_invalid @ b |
| 1093 | .long __irq_invalid @ c |
| 1094 | .long __irq_invalid @ d |
| 1095 | .long __irq_invalid @ e |
| 1096 | .long __irq_invalid @ f |
| 1097 | |
| 1098 | /* |
| 1099 | * Data abort dispatcher |
| 1100 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC |
| 1101 | */ |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1102 | vector_stub dabt, ABT_MODE, 8 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1103 | |
| 1104 | .long __dabt_usr @ 0 (USR_26 / USR_32) |
| 1105 | .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1106 | .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1107 | .long __dabt_svc @ 3 (SVC_26 / SVC_32) |
| 1108 | .long __dabt_invalid @ 4 |
| 1109 | .long __dabt_invalid @ 5 |
| 1110 | .long __dabt_invalid @ 6 |
| 1111 | .long __dabt_invalid @ 7 |
| 1112 | .long __dabt_invalid @ 8 |
| 1113 | .long __dabt_invalid @ 9 |
| 1114 | .long __dabt_invalid @ a |
| 1115 | .long __dabt_invalid @ b |
| 1116 | .long __dabt_invalid @ c |
| 1117 | .long __dabt_invalid @ d |
| 1118 | .long __dabt_invalid @ e |
| 1119 | .long __dabt_invalid @ f |
| 1120 | |
| 1121 | /* |
| 1122 | * Prefetch abort dispatcher |
| 1123 | * Enter in ABT mode, spsr = USR CPSR, lr = USR PC |
| 1124 | */ |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1125 | vector_stub pabt, ABT_MODE, 4 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1126 | |
| 1127 | .long __pabt_usr @ 0 (USR_26 / USR_32) |
| 1128 | .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1129 | .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1130 | .long __pabt_svc @ 3 (SVC_26 / SVC_32) |
| 1131 | .long __pabt_invalid @ 4 |
| 1132 | .long __pabt_invalid @ 5 |
| 1133 | .long __pabt_invalid @ 6 |
| 1134 | .long __pabt_invalid @ 7 |
| 1135 | .long __pabt_invalid @ 8 |
| 1136 | .long __pabt_invalid @ 9 |
| 1137 | .long __pabt_invalid @ a |
| 1138 | .long __pabt_invalid @ b |
| 1139 | .long __pabt_invalid @ c |
| 1140 | .long __pabt_invalid @ d |
| 1141 | .long __pabt_invalid @ e |
| 1142 | .long __pabt_invalid @ f |
| 1143 | |
| 1144 | /* |
| 1145 | * Undef instr entry dispatcher |
| 1146 | * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC |
| 1147 | */ |
Nicolas Pitre | b7ec479 | 2005-11-06 14:42:37 +0000 | [diff] [blame] | 1148 | vector_stub und, UND_MODE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1149 | |
| 1150 | .long __und_usr @ 0 (USR_26 / USR_32) |
| 1151 | .long __und_invalid @ 1 (FIQ_26 / FIQ_32) |
| 1152 | .long __und_invalid @ 2 (IRQ_26 / IRQ_32) |
| 1153 | .long __und_svc @ 3 (SVC_26 / SVC_32) |
| 1154 | .long __und_invalid @ 4 |
| 1155 | .long __und_invalid @ 5 |
| 1156 | .long __und_invalid @ 6 |
| 1157 | .long __und_invalid @ 7 |
| 1158 | .long __und_invalid @ 8 |
| 1159 | .long __und_invalid @ 9 |
| 1160 | .long __und_invalid @ a |
| 1161 | .long __und_invalid @ b |
| 1162 | .long __und_invalid @ c |
| 1163 | .long __und_invalid @ d |
| 1164 | .long __und_invalid @ e |
| 1165 | .long __und_invalid @ f |
| 1166 | |
| 1167 | .align 5 |
| 1168 | |
| 1169 | /*============================================================================= |
Russell King | 19accfd | 2013-07-04 11:40:32 +0100 | [diff] [blame] | 1170 | * Address exception handler |
| 1171 | *----------------------------------------------------------------------------- |
| 1172 | * These aren't too critical. |
| 1173 | * (they're not supposed to happen, and won't happen in 32-bit data mode). |
| 1174 | */ |
| 1175 | |
| 1176 | vector_addrexcptn: |
| 1177 | b vector_addrexcptn |
| 1178 | |
| 1179 | /*============================================================================= |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 1180 | * FIQ "NMI" handler |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1181 | *----------------------------------------------------------------------------- |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 1182 | * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86 |
| 1183 | * systems. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1184 | */ |
Daniel Thompson | c0e7f7e | 2014-09-17 17:12:06 +0100 | [diff] [blame] | 1185 | vector_stub fiq, FIQ_MODE, 4 |
| 1186 | |
| 1187 | .long __fiq_usr @ 0 (USR_26 / USR_32) |
| 1188 | .long __fiq_svc @ 1 (FIQ_26 / FIQ_32) |
| 1189 | .long __fiq_svc @ 2 (IRQ_26 / IRQ_32) |
| 1190 | .long __fiq_svc @ 3 (SVC_26 / SVC_32) |
| 1191 | .long __fiq_svc @ 4 |
| 1192 | .long __fiq_svc @ 5 |
| 1193 | .long __fiq_svc @ 6 |
| 1194 | .long __fiq_abt @ 7 |
| 1195 | .long __fiq_svc @ 8 |
| 1196 | .long __fiq_svc @ 9 |
| 1197 | .long __fiq_svc @ a |
| 1198 | .long __fiq_svc @ b |
| 1199 | .long __fiq_svc @ c |
| 1200 | .long __fiq_svc @ d |
| 1201 | .long __fiq_svc @ e |
| 1202 | .long __fiq_svc @ f |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1203 | |
Ard Biesheuvel | 31b96ca | 2016-02-10 11:41:08 +0100 | [diff] [blame] | 1204 | .globl vector_fiq |
Russell King | e39e3f3 | 2013-07-09 01:03:17 +0100 | [diff] [blame] | 1205 | |
Russell King | b9b32bf | 2013-07-04 12:03:31 +0100 | [diff] [blame] | 1206 | .section .vectors, "ax", %progbits |
Ard Biesheuvel | b48da55 | 2016-02-05 10:04:47 +0100 | [diff] [blame] | 1207 | .L__vectors_start: |
Russell King | b9b32bf | 2013-07-04 12:03:31 +0100 | [diff] [blame] | 1208 | W(b) vector_rst |
| 1209 | W(b) vector_und |
Ard Biesheuvel | b48da55 | 2016-02-05 10:04:47 +0100 | [diff] [blame] | 1210 | W(ldr) pc, .L__vectors_start + 0x1000 |
Russell King | b9b32bf | 2013-07-04 12:03:31 +0100 | [diff] [blame] | 1211 | W(b) vector_pabt |
| 1212 | W(b) vector_dabt |
| 1213 | W(b) vector_addrexcptn |
| 1214 | W(b) vector_irq |
| 1215 | W(b) vector_fiq |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | |
| 1217 | .data |
| 1218 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1219 | .globl cr_alignment |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1220 | cr_alignment: |
| 1221 | .space 4 |
eric miao | 5210864 | 2010-12-13 09:42:34 +0100 | [diff] [blame] | 1222 | |
| 1223 | #ifdef CONFIG_MULTI_IRQ_HANDLER |
| 1224 | .globl handle_arch_irq |
| 1225 | handle_arch_irq: |
| 1226 | .space 4 |
| 1227 | #endif |