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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
Hyok S. Choiafeb90c2006-01-13 21:05:25 +00006 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
Nicolas Pitre70b6f2b2007-12-04 14:33:33 +010014 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070017
Paul Gortmaker9b9cf812015-05-01 20:13:42 -040018#include <linux/init.h>
19
Rob Herring6f6f6a72012-03-10 10:30:31 -060020#include <asm/assembler.h>
Nicolas Pitref09b9972005-10-29 21:44:55 +010021#include <asm/memory.h>
Russell King753790e2011-02-06 15:32:24 +000022#include <asm/glue-df.h>
23#include <asm/glue-pf.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/vfpmacros.h>
Rob Herring243c8652012-02-08 18:26:34 -060025#ifndef CONFIG_MULTI_IRQ_HANDLER
Russell Kinga09e64f2008-08-05 16:14:15 +010026#include <mach/entry-macro.S>
Rob Herring243c8652012-02-08 18:26:34 -060027#endif
Russell Kingd6551e82006-06-21 13:31:52 +010028#include <asm/thread_notify.h>
Catalin Marinasc4c57162009-02-16 11:42:09 +010029#include <asm/unwind.h>
Russell Kingcc20d422009-11-09 23:53:29 +000030#include <asm/unistd.h>
Tony Lindgrenf159f4e2010-07-05 14:53:10 +010031#include <asm/tls.h>
David Howells9f97da72012-03-28 18:30:01 +010032#include <asm/system_info.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34#include "entry-header.S"
Magnus Dammcd544ce2010-12-22 13:20:08 +010035#include <asm/entry-macro-multi.S>
Wang Nana0266c22015-01-05 19:29:25 +080036#include <asm/probes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070037
38/*
Russell Kingd9600c92011-06-26 10:34:02 +010039 * Interrupt handling.
Russell King187a51a2005-05-21 18:14:44 +010040 */
41 .macro irq_handler
eric miao52108642010-12-13 09:42:34 +010042#ifdef CONFIG_MULTI_IRQ_HANDLER
Russell Kingd9600c92011-06-26 10:34:02 +010043 ldr r1, =handle_arch_irq
eric miao52108642010-12-13 09:42:34 +010044 mov r0, sp
Russell King14327c62015-04-21 14:17:25 +010045 badr lr, 9997f
Marc Zyngierabeb24a2011-09-06 09:23:26 +010046 ldr pc, [r1]
47#else
Magnus Dammcd544ce2010-12-22 13:20:08 +010048 arch_irq_handler_default
Marc Zyngierabeb24a2011-09-06 09:23:26 +010049#endif
Russell Kingf00ec482010-09-04 10:47:48 +0100509997:
Russell King187a51a2005-05-21 18:14:44 +010051 .endm
52
Russell Kingac8b9c12011-06-26 10:22:08 +010053 .macro pabt_helper
Russell King8dfe7ac2011-06-26 12:37:35 +010054 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
Russell Kingac8b9c12011-06-26 10:22:08 +010055#ifdef MULTI_PABORT
Russell King0402bec2011-06-25 15:46:08 +010056 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010057 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010058 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010059#else
60 bl CPU_PABORT_HANDLER
61#endif
62 .endm
63
64 .macro dabt_helper
65
66 @
67 @ Call the processor-specific abort handler:
68 @
Russell Kingda740472011-06-26 16:01:26 +010069 @ r2 - pt_regs
Russell King3e287be2011-06-26 14:35:07 +010070 @ r4 - aborted context pc
71 @ r5 - aborted context psr
Russell Kingac8b9c12011-06-26 10:22:08 +010072 @
73 @ The abort handler must return the aborted address in r0, and
74 @ the fault status register in r1. r9 must be preserved.
75 @
76#ifdef MULTI_DABORT
Russell King0402bec2011-06-25 15:46:08 +010077 ldr ip, .LCprocfns
Russell Kingac8b9c12011-06-26 10:22:08 +010078 mov lr, pc
Russell King0402bec2011-06-25 15:46:08 +010079 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
Russell Kingac8b9c12011-06-26 10:22:08 +010080#else
81 bl CPU_DABORT_HANDLER
82#endif
83 .endm
84
Nicolas Pitre785d3cd2007-12-03 15:27:56 -050085#ifdef CONFIG_KPROBES
86 .section .kprobes.text,"ax",%progbits
87#else
88 .text
89#endif
90
Russell King187a51a2005-05-21 18:14:44 +010091/*
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 * Invalid mode handlers
93 */
Russell Kingccea7a12005-05-31 22:22:32 +010094 .macro inv_entry, reason
95 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +010096 ARM( stmib sp, {r1 - lr} )
97 THUMB( stmia sp, {r0 - r12} )
98 THUMB( str sp, [sp, #S_SP] )
99 THUMB( str lr, [sp, #S_LR] )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 mov r1, #\reason
101 .endm
102
103__pabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100104 inv_entry BAD_PREFETCH
105 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100106ENDPROC(__pabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108__dabt_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100109 inv_entry BAD_DATA
110 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100111ENDPROC(__dabt_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
113__irq_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100114 inv_entry BAD_IRQ
115 b common_invalid
Catalin Marinas93ed3972008-08-28 11:22:32 +0100116ENDPROC(__irq_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
118__und_invalid:
Russell Kingccea7a12005-05-31 22:22:32 +0100119 inv_entry BAD_UNDEFINSTR
Linus Torvalds1da177e2005-04-16 15:20:36 -0700120
Russell Kingccea7a12005-05-31 22:22:32 +0100121 @
122 @ XXX fall through to common_invalid
123 @
124
125@
126@ common_invalid - generic code for failed exception (re-entrant version of handlers)
127@
128common_invalid:
129 zero_fp
130
131 ldmia r0, {r4 - r6}
132 add r0, sp, #S_PC @ here for interlock avoidance
133 mov r7, #-1 @ "" "" "" ""
134 str r4, [sp] @ save preserved r0
135 stmia r0, {r5 - r7} @ lr_<exception>,
136 @ cpsr_<exception>, "old_r0"
137
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 mov r0, sp
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 b bad_mode
Catalin Marinas93ed3972008-08-28 11:22:32 +0100140ENDPROC(__und_invalid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142/*
143 * SVC mode handlers
144 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000145
146#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
147#define SPFIX(code...) code
148#else
149#define SPFIX(code...)
150#endif
151
Russell King2190fed2015-08-20 10:32:02 +0100152 .macro svc_entry, stack_hole=0, trace=1, uaccess=1
Catalin Marinasc4c57162009-02-16 11:42:09 +0100153 UNWIND(.fnstart )
154 UNWIND(.save {r0 - pc} )
Russell King2190fed2015-08-20 10:32:02 +0100155 sub sp, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
Catalin Marinasb86040a2009-07-24 12:32:54 +0100156#ifdef CONFIG_THUMB2_KERNEL
157 SPFIX( str r0, [sp] ) @ temporarily saved
158 SPFIX( mov r0, sp )
159 SPFIX( tst r0, #4 ) @ test original stack alignment
160 SPFIX( ldr r0, [sp] ) @ restored
161#else
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000162 SPFIX( tst sp, #4 )
Catalin Marinasb86040a2009-07-24 12:32:54 +0100163#endif
164 SPFIX( subeq sp, sp, #4 )
165 stmia sp, {r1 - r12}
Russell Kingccea7a12005-05-31 22:22:32 +0100166
Russell Kingb059bdc2011-06-25 15:44:20 +0100167 ldmia r0, {r3 - r5}
168 add r7, sp, #S_SP - 4 @ here for interlock avoidance
169 mov r6, #-1 @ "" "" "" ""
Russell King2190fed2015-08-20 10:32:02 +0100170 add r2, sp, #(S_FRAME_SIZE + 8 + \stack_hole - 4)
Russell Kingb059bdc2011-06-25 15:44:20 +0100171 SPFIX( addeq r2, r2, #4 )
172 str r3, [sp, #-4]! @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100173 @ from the exception stack
174
Russell Kingb059bdc2011-06-25 15:44:20 +0100175 mov r3, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700176
177 @
178 @ We are now ready to fill in the remaining blanks on the stack:
179 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100180 @ r2 - sp_svc
181 @ r3 - lr_svc
182 @ r4 - lr_<exception>, already fixed up for correct return/restart
183 @ r5 - spsr_<exception>
184 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100186 stmia r7, {r2 - r6}
Russell Kingf2741b72011-06-25 17:35:19 +0100187
Russell King2190fed2015-08-20 10:32:02 +0100188 uaccess_save r0
189 .if \uaccess
190 uaccess_disable r0
191 .endif
192
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100193 .if \trace
Russell Kingf2741b72011-06-25 17:35:19 +0100194#ifdef CONFIG_TRACE_IRQFLAGS
195 bl trace_hardirqs_off
196#endif
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100197 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 .endm
199
200 .align 5
201__dabt_svc:
Russell King2190fed2015-08-20 10:32:02 +0100202 svc_entry uaccess=0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 mov r2, sp
Russell Kingda740472011-06-26 16:01:26 +0100204 dabt_helper
Marc Zyngiere16b31b2013-11-04 11:42:29 +0100205 THUMB( ldr r5, [sp, #S_PSR] ) @ potentially updated CPSR
Russell Kingb059bdc2011-06-25 15:44:20 +0100206 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100207 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100208ENDPROC(__dabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209
210 .align 5
211__irq_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100212 svc_entry
Russell King1613cc12011-06-25 10:57:57 +0100213 irq_handler
214
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215#ifdef CONFIG_PREEMPT
Russell King706fdd92005-05-21 18:15:45 +0100216 get_thread_info tsk
217 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
Russell King706fdd92005-05-21 18:15:45 +0100218 ldr r0, [tsk, #TI_FLAGS] @ get flags
Russell King28fab1a2008-04-13 17:47:35 +0100219 teq r8, #0 @ if preempt count != 0
220 movne r0, #0 @ force flags to 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221 tst r0, #_TIF_NEED_RESCHED
222 blne svc_preempt
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223#endif
Russell King30891c92011-06-26 12:47:08 +0100224
Russell King9b56feb2013-03-28 12:57:40 +0000225 svc_exit r5, irq = 1 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100226 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100227ENDPROC(__irq_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228
229 .ltorg
230
231#ifdef CONFIG_PREEMPT
232svc_preempt:
Russell King28fab1a2008-04-13 17:47:35 +0100233 mov r8, lr
Linus Torvalds1da177e2005-04-16 15:20:36 -07002341: bl preempt_schedule_irq @ irq en/disable is done inside
Russell King706fdd92005-05-21 18:15:45 +0100235 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236 tst r0, #_TIF_NEED_RESCHED
Russell King6ebbf2c2014-06-30 16:29:12 +0100237 reteq r8 @ go again
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 b 1b
239#endif
240
Russell King15ac49b2012-07-30 19:42:10 +0100241__und_fault:
242 @ Correct the PC such that it is pointing at the instruction
243 @ which caused the fault. If the faulting instruction was ARM
244 @ the PC will be pointing at the next instruction, and have to
245 @ subtract 4. Otherwise, it is Thumb, and the PC will be
246 @ pointing at the second half of the Thumb instruction. We
247 @ have to subtract 2.
248 ldr r2, [r0, #S_PC]
249 sub r2, r2, r1
250 str r2, [r0, #S_PC]
251 b do_undefinstr
252ENDPROC(__und_fault)
253
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 .align 5
255__und_svc:
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500256#ifdef CONFIG_KPROBES
257 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
258 @ it obviously needs free stack space which then will belong to
259 @ the saved context.
Wang Nana0266c22015-01-05 19:29:25 +0800260 svc_entry MAX_STACK_SIZE
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500261#else
Russell Kingccea7a12005-05-31 22:22:32 +0100262 svc_entry
Nicolas Pitred30a0c82007-12-14 15:56:01 -0500263#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264 @
265 @ call emulation code, which returns using r9 if it has emulated
266 @ the instruction, or the more conventional lr if we are to treat
267 @ this as a real undefined instruction
268 @
269 @ r0 - instruction
270 @
Russell King15ac49b2012-07-30 19:42:10 +0100271#ifndef CONFIG_THUMB2_KERNEL
Russell Kingb059bdc2011-06-25 15:44:20 +0100272 ldr r0, [r4, #-4]
Catalin Marinas83e686e2009-09-18 23:27:07 +0100273#else
Russell King15ac49b2012-07-30 19:42:10 +0100274 mov r1, #2
Russell Kingb059bdc2011-06-25 15:44:20 +0100275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
Dave Martin85519182011-08-19 17:59:27 +0100276 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
Russell King15ac49b2012-07-30 19:42:10 +0100277 blo __und_svc_fault
278 ldrh r9, [r4] @ bottom 16 bits
279 add r4, r4, #2
280 str r4, [sp, #S_PC]
281 orr r0, r9, r0, lsl #16
Catalin Marinas83e686e2009-09-18 23:27:07 +0100282#endif
Russell King14327c62015-04-21 14:17:25 +0100283 badr r9, __und_svc_finish
Russell Kingb059bdc2011-06-25 15:44:20 +0100284 mov r2, r4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 bl call_fpe
286
Russell King15ac49b2012-07-30 19:42:10 +0100287 mov r1, #4 @ PC correction to apply
288__und_svc_fault:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289 mov r0, sp @ struct pt_regs *regs
Russell King15ac49b2012-07-30 19:42:10 +0100290 bl __und_fault
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291
Russell King15ac49b2012-07-30 19:42:10 +0100292__und_svc_finish:
Russell Kingb059bdc2011-06-25 15:44:20 +0100293 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
294 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100295 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100296ENDPROC(__und_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298 .align 5
299__pabt_svc:
Russell Kingccea7a12005-05-31 22:22:32 +0100300 svc_entry
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100301 mov r2, sp @ regs
Russell King8dfe7ac2011-06-26 12:37:35 +0100302 pabt_helper
Russell Kingb059bdc2011-06-25 15:44:20 +0100303 svc_exit r5 @ return from exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100304 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100305ENDPROC(__pabt_svc)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306
307 .align 5
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100308__fiq_svc:
309 svc_entry trace=0
310 mov r0, sp @ struct pt_regs *regs
311 bl handle_fiq_as_nmi
312 svc_exit_via_fiq
313 UNWIND(.fnend )
314ENDPROC(__fiq_svc)
315
316 .align 5
Russell King49f680e2005-05-31 18:02:00 +0100317.LCcralign:
318 .word cr_alignment
Paul Brook48d79272008-04-18 22:43:07 +0100319#ifdef MULTI_DABORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320.LCprocfns:
321 .word processor
322#endif
323.LCfp:
324 .word fp_enter
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325
326/*
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100327 * Abort mode handlers
328 */
329
330@
331@ Taking a FIQ in abort mode is similar to taking a FIQ in SVC mode
332@ and reuses the same macros. However in abort mode we must also
333@ save/restore lr_abt and spsr_abt to make nested aborts safe.
334@
335 .align 5
336__fiq_abt:
337 svc_entry trace=0
338
339 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
340 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
341 THUMB( msr cpsr_c, r0 )
342 mov r1, lr @ Save lr_abt
343 mrs r2, spsr @ Save spsr_abt, abort is now safe
344 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
345 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
346 THUMB( msr cpsr_c, r0 )
347 stmfd sp!, {r1 - r2}
348
349 add r0, sp, #8 @ struct pt_regs *regs
350 bl handle_fiq_as_nmi
351
352 ldmfd sp!, {r1 - r2}
353 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
354 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
355 THUMB( msr cpsr_c, r0 )
356 mov lr, r1 @ Restore lr_abt, abort is unsafe
357 msr spsr_cxsf, r2 @ Restore spsr_abt
358 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
359 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
360 THUMB( msr cpsr_c, r0 )
361
362 svc_exit_via_fiq
363 UNWIND(.fnend )
364ENDPROC(__fiq_abt)
365
366/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 * User mode handlers
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000368 *
369 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370 */
Nicolas Pitre2dede2d2006-01-14 16:18:08 +0000371
372#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
373#error "sizeof(struct pt_regs) must be a multiple of 8"
374#endif
375
Russell King2190fed2015-08-20 10:32:02 +0100376 .macro usr_entry, trace=1, uaccess=1
Catalin Marinasc4c57162009-02-16 11:42:09 +0100377 UNWIND(.fnstart )
378 UNWIND(.cantunwind ) @ don't unwind the user space
Russell Kingccea7a12005-05-31 22:22:32 +0100379 sub sp, sp, #S_FRAME_SIZE
Catalin Marinasb86040a2009-07-24 12:32:54 +0100380 ARM( stmib sp, {r1 - r12} )
381 THUMB( stmia sp, {r0 - r12} )
Russell Kingccea7a12005-05-31 22:22:32 +0100382
Russell King195b58a2014-08-28 13:08:14 +0100383 ATRAP( mrc p15, 0, r7, c1, c0, 0)
384 ATRAP( ldr r8, .LCcralign)
385
Russell Kingb059bdc2011-06-25 15:44:20 +0100386 ldmia r0, {r3 - r5}
Russell Kingccea7a12005-05-31 22:22:32 +0100387 add r0, sp, #S_PC @ here for interlock avoidance
Russell Kingb059bdc2011-06-25 15:44:20 +0100388 mov r6, #-1 @ "" "" "" ""
Russell Kingccea7a12005-05-31 22:22:32 +0100389
Russell Kingb059bdc2011-06-25 15:44:20 +0100390 str r3, [sp] @ save the "real" r0 copied
Russell Kingccea7a12005-05-31 22:22:32 +0100391 @ from the exception stack
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
Russell King195b58a2014-08-28 13:08:14 +0100393 ATRAP( ldr r8, [r8, #0])
394
Linus Torvalds1da177e2005-04-16 15:20:36 -0700395 @
396 @ We are now ready to fill in the remaining blanks on the stack:
397 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100398 @ r4 - lr_<exception>, already fixed up for correct return/restart
399 @ r5 - spsr_<exception>
400 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 @
402 @ Also, separately save sp_usr and lr_usr
403 @
Russell Kingb059bdc2011-06-25 15:44:20 +0100404 stmia r0, {r4 - r6}
Catalin Marinasb86040a2009-07-24 12:32:54 +0100405 ARM( stmdb r0, {sp, lr}^ )
406 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700407
Russell King2190fed2015-08-20 10:32:02 +0100408 .if \uaccess
409 uaccess_disable ip
410 .endif
411
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412 @ Enable the alignment trap while in kernel mode
Russell King195b58a2014-08-28 13:08:14 +0100413 ATRAP( teq r8, r7)
414 ATRAP( mcrne p15, 0, r8, c1, c0, 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415
416 @
417 @ Clear FP to mark the first stack frame
418 @
419 zero_fp
Russell Kingf2741b72011-06-25 17:35:19 +0100420
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100421 .if \trace
Russell King11b8b252015-07-03 12:42:36 +0100422#ifdef CONFIG_TRACE_IRQFLAGS
Russell Kingf2741b72011-06-25 17:35:19 +0100423 bl trace_hardirqs_off
424#endif
Kevin Hilmanb0088482013-03-28 22:54:40 +0100425 ct_user_exit save = 0
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100426 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427 .endm
428
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100429 .macro kuser_cmpxchg_check
Russell Kingdb695c02015-09-21 19:34:28 +0100430#if !defined(CONFIG_CPU_32v6K) && defined(CONFIG_KUSER_HELPERS)
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100431#ifndef CONFIG_MMU
432#warning "NPTL on non MMU needs fixing"
433#else
434 @ Make sure our user space atomic helper is restarted
435 @ if it was interrupted in a critical region. Here we
436 @ perform a quick test inline since it should be false
437 @ 99.9999% of the time. The rest is done out of line.
Russell Kingb059bdc2011-06-25 15:44:20 +0100438 cmp r4, #TASK_SIZE
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400439 blhs kuser_cmpxchg64_fixup
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100440#endif
441#endif
442 .endm
443
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444 .align 5
445__dabt_usr:
Russell King2190fed2015-08-20 10:32:02 +0100446 usr_entry uaccess=0
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100447 kuser_cmpxchg_check
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 mov r2, sp
Russell Kingda740472011-06-26 16:01:26 +0100449 dabt_helper
450 b ret_from_exception
Catalin Marinasc4c57162009-02-16 11:42:09 +0100451 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100452ENDPROC(__dabt_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
454 .align 5
455__irq_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100456 usr_entry
Russell Kingbc089602011-06-25 18:28:19 +0100457 kuser_cmpxchg_check
Russell King187a51a2005-05-21 18:14:44 +0100458 irq_handler
Russell King1613cc12011-06-25 10:57:57 +0100459 get_thread_info tsk
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460 mov why, #0
Ming Lei9fc25522011-06-05 02:24:58 +0100461 b ret_to_user_from_irq
Catalin Marinasc4c57162009-02-16 11:42:09 +0100462 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100463ENDPROC(__irq_usr)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464
465 .ltorg
466
467 .align 5
468__und_usr:
Russell King2190fed2015-08-20 10:32:02 +0100469 usr_entry uaccess=0
Russell Kingbc089602011-06-25 18:28:19 +0100470
Russell Kingb059bdc2011-06-25 15:44:20 +0100471 mov r2, r4
472 mov r3, r5
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473
Russell King15ac49b2012-07-30 19:42:10 +0100474 @ r2 = regs->ARM_pc, which is either 2 or 4 bytes ahead of the
475 @ faulting instruction depending on Thumb mode.
476 @ r3 = regs->ARM_cpsr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 @
Russell King15ac49b2012-07-30 19:42:10 +0100478 @ The emulation code returns using r9 if it has emulated the
479 @ instruction, or the more conventional lr if we are to treat
480 @ this as a real undefined instruction
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 @
Russell King14327c62015-04-21 14:17:25 +0100482 badr r9, ret_from_exception
Russell King15ac49b2012-07-30 19:42:10 +0100483
Catalin Marinas1417a6b2014-04-22 16:14:29 +0100484 @ IRQs must be enabled before attempting to read the instruction from
485 @ user space since that could cause a page/translation fault if the
486 @ page table was modified by another CPU.
487 enable_irq
488
Paul Brookcb170a42008-04-18 22:43:08 +0100489 tst r3, #PSR_T_BIT @ Thumb mode?
Russell King15ac49b2012-07-30 19:42:10 +0100490 bne __und_usr_thumb
491 sub r4, r2, #4 @ ARM instr at LR - 4
4921: ldrt r0, [r4]
Ben Dooks457c2402013-02-12 18:59:57 +0000493 ARM_BE8(rev r0, r0) @ little endian instruction
494
Russell King2190fed2015-08-20 10:32:02 +0100495 uaccess_disable ip
496
Russell King15ac49b2012-07-30 19:42:10 +0100497 @ r0 = 32-bit ARM instruction which caused the exception
498 @ r2 = PC value for the following instruction (:= regs->ARM_pc)
499 @ r4 = PC value for the faulting instruction
500 @ lr = 32-bit undefined instruction function
Russell King14327c62015-04-21 14:17:25 +0100501 badr lr, __und_usr_fault_32
Russell King15ac49b2012-07-30 19:42:10 +0100502 b call_fpe
503
504__und_usr_thumb:
Paul Brookcb170a42008-04-18 22:43:08 +0100505 @ Thumb instruction
Russell King15ac49b2012-07-30 19:42:10 +0100506 sub r4, r2, #2 @ First half of thumb instr at LR - 2
Dave Martinef4c5362011-08-19 18:00:08 +0100507#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
508/*
509 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
510 * can never be supported in a single kernel, this code is not applicable at
511 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
512 * made about .arch directives.
513 */
514#if __LINUX_ARM_ARCH__ < 7
515/* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
516#define NEED_CPU_ARCHITECTURE
517 ldr r5, .LCcpu_architecture
518 ldr r5, [r5]
519 cmp r5, #CPU_ARCH_ARMv7
Russell King15ac49b2012-07-30 19:42:10 +0100520 blo __und_usr_fault_16 @ 16bit undefined instruction
Dave Martinef4c5362011-08-19 18:00:08 +0100521/*
522 * The following code won't get run unless the running CPU really is v7, so
523 * coding round the lack of ldrht on older arches is pointless. Temporarily
524 * override the assembler target arch with the minimum required instead:
525 */
526 .arch armv6t2
527#endif
Russell King15ac49b2012-07-30 19:42:10 +01005282: ldrht r5, [r4]
Victor Kamenskyf8fe23e2014-01-21 06:45:11 +0100529ARM_BE8(rev16 r5, r5) @ little endian instruction
Dave Martin85519182011-08-19 17:59:27 +0100530 cmp r5, #0xe800 @ 32bit instruction if xx != 0
Russell King2190fed2015-08-20 10:32:02 +0100531 blo __und_usr_fault_16_pan @ 16bit undefined instruction
Russell King15ac49b2012-07-30 19:42:10 +01005323: ldrht r0, [r2]
Victor Kamenskyf8fe23e2014-01-21 06:45:11 +0100533ARM_BE8(rev16 r0, r0) @ little endian instruction
Russell King2190fed2015-08-20 10:32:02 +0100534 uaccess_disable ip
Paul Brookcb170a42008-04-18 22:43:08 +0100535 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
Russell King15ac49b2012-07-30 19:42:10 +0100536 str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
Paul Brookcb170a42008-04-18 22:43:08 +0100537 orr r0, r0, r5, lsl #16
Russell King14327c62015-04-21 14:17:25 +0100538 badr lr, __und_usr_fault_32
Russell King15ac49b2012-07-30 19:42:10 +0100539 @ r0 = the two 16-bit Thumb instructions which caused the exception
540 @ r2 = PC value for the following Thumb instruction (:= regs->ARM_pc)
541 @ r4 = PC value for the first 16-bit Thumb instruction
542 @ lr = 32bit undefined instruction function
Dave Martinef4c5362011-08-19 18:00:08 +0100543
544#if __LINUX_ARM_ARCH__ < 7
545/* If the target arch was overridden, change it back: */
546#ifdef CONFIG_CPU_32v6K
547 .arch armv6k
Paul Brookcb170a42008-04-18 22:43:08 +0100548#else
Dave Martinef4c5362011-08-19 18:00:08 +0100549 .arch armv6
550#endif
551#endif /* __LINUX_ARM_ARCH__ < 7 */
552#else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
Russell King15ac49b2012-07-30 19:42:10 +0100553 b __und_usr_fault_16
Paul Brookcb170a42008-04-18 22:43:08 +0100554#endif
Russell King15ac49b2012-07-30 19:42:10 +0100555 UNWIND(.fnend)
Catalin Marinas93ed3972008-08-28 11:22:32 +0100556ENDPROC(__und_usr)
Paul Brookcb170a42008-04-18 22:43:08 +0100557
Linus Torvalds1da177e2005-04-16 15:20:36 -0700558/*
Russell King15ac49b2012-07-30 19:42:10 +0100559 * The out of line fixup for the ldrt instructions above.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560 */
Ard Biesheuvelc4a84ae2015-03-24 10:41:09 +0100561 .pushsection .text.fixup, "ax"
Will Deacon667d1b42012-06-15 16:49:58 +0100562 .align 2
Arun K S3780f7a2014-05-19 11:43:00 +01005634: str r4, [sp, #S_PC] @ retry current instruction
Russell King6ebbf2c2014-06-30 16:29:12 +0100564 ret r9
Russell King42604152010-04-19 10:15:03 +0100565 .popsection
566 .pushsection __ex_table,"a"
Paul Brookcb170a42008-04-18 22:43:08 +0100567 .long 1b, 4b
Guennadi Liakhovetskic89cefe2011-11-22 23:42:12 +0100568#if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
Paul Brookcb170a42008-04-18 22:43:08 +0100569 .long 2b, 4b
570 .long 3b, 4b
571#endif
Russell King42604152010-04-19 10:15:03 +0100572 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573
574/*
575 * Check whether the instruction is a co-processor instruction.
576 * If yes, we need to call the relevant co-processor handler.
577 *
578 * Note that we don't do a full check here for the co-processor
579 * instructions; all instructions with bit 27 set are well
580 * defined. The only instructions that should fault are the
581 * co-processor instructions. However, we have to watch out
582 * for the ARM6/ARM7 SWI bug.
583 *
Catalin Marinasb5872db2008-01-10 19:16:17 +0100584 * NEON is a special case that has to be handled here. Not all
585 * NEON instructions are co-processor instructions, so we have
586 * to make a special case of checking for them. Plus, there's
587 * five groups of them, so we have a table of mask/opcode pairs
588 * to check against, and if any match then we branch off into the
589 * NEON handler code.
590 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700591 * Emulators may wish to make use of the following registers:
Russell King15ac49b2012-07-30 19:42:10 +0100592 * r0 = instruction opcode (32-bit ARM or two 16-bit Thumb)
593 * r2 = PC value to resume execution after successful emulation
Russell Kingdb6ccbb62007-01-06 22:53:48 +0000594 * r9 = normal "successful" return address
Russell King15ac49b2012-07-30 19:42:10 +0100595 * r10 = this threads thread_info structure
Russell Kingdb6ccbb62007-01-06 22:53:48 +0000596 * lr = unrecognised instruction return address
Catalin Marinas1417a6b2014-04-22 16:14:29 +0100597 * IRQs enabled, FIQs enabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598 */
Paul Brookcb170a42008-04-18 22:43:08 +0100599 @
600 @ Fall-through from Thumb-2 __und_usr
601 @
602#ifdef CONFIG_NEON
Russell Kingd3f79582013-02-23 17:53:52 +0000603 get_thread_info r10 @ get current thread
Paul Brookcb170a42008-04-18 22:43:08 +0100604 adr r6, .LCneon_thumb_opcodes
605 b 2f
606#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700607call_fpe:
Russell Kingd3f79582013-02-23 17:53:52 +0000608 get_thread_info r10 @ get current thread
Catalin Marinasb5872db2008-01-10 19:16:17 +0100609#ifdef CONFIG_NEON
Paul Brookcb170a42008-04-18 22:43:08 +0100610 adr r6, .LCneon_arm_opcodes
Russell Kingd3f79582013-02-23 17:53:52 +00006112: ldr r5, [r6], #4 @ mask value
Catalin Marinasb5872db2008-01-10 19:16:17 +0100612 ldr r7, [r6], #4 @ opcode bits matching in mask
Russell Kingd3f79582013-02-23 17:53:52 +0000613 cmp r5, #0 @ end mask?
614 beq 1f
615 and r8, r0, r5
Catalin Marinasb5872db2008-01-10 19:16:17 +0100616 cmp r8, r7 @ NEON instruction?
617 bne 2b
Catalin Marinasb5872db2008-01-10 19:16:17 +0100618 mov r7, #1
619 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
620 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
621 b do_vfp @ let VFP handler handle this
6221:
623#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
Paul Brookcb170a42008-04-18 22:43:08 +0100625 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
Russell King6ebbf2c2014-06-30 16:29:12 +0100626 reteq lr
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 and r8, r0, #0x00000f00 @ mask out CP number
Catalin Marinasb86040a2009-07-24 12:32:54 +0100628 THUMB( lsr r8, r8, #8 )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700629 mov r7, #1
630 add r6, r10, #TI_USED_CP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100631 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
632 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633#ifdef CONFIG_IWMMXT
634 @ Test if we need to give access to iWMMXt coprocessors
635 ldr r5, [r10, #TI_FLAGS]
636 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
637 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
638 bcs iwmmxt_task_enable
639#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100640 ARM( add pc, pc, r8, lsr #6 )
641 THUMB( lsl r8, r8, #2 )
642 THUMB( add pc, r8 )
643 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700644
Russell King6ebbf2c2014-06-30 16:29:12 +0100645 ret.w lr @ CP#0
Catalin Marinasb86040a2009-07-24 12:32:54 +0100646 W(b) do_fpe @ CP#1 (FPE)
647 W(b) do_fpe @ CP#2 (FPE)
Russell King6ebbf2c2014-06-30 16:29:12 +0100648 ret.w lr @ CP#3
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100649#ifdef CONFIG_CRUNCH
650 b crunch_task_enable @ CP#4 (MaverickCrunch)
651 b crunch_task_enable @ CP#5 (MaverickCrunch)
652 b crunch_task_enable @ CP#6 (MaverickCrunch)
653#else
Russell King6ebbf2c2014-06-30 16:29:12 +0100654 ret.w lr @ CP#4
655 ret.w lr @ CP#5
656 ret.w lr @ CP#6
Lennert Buytenhekc17fad12006-06-27 23:03:03 +0100657#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100658 ret.w lr @ CP#7
659 ret.w lr @ CP#8
660 ret.w lr @ CP#9
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661#ifdef CONFIG_VFP
Catalin Marinasb86040a2009-07-24 12:32:54 +0100662 W(b) do_vfp @ CP#10 (VFP)
663 W(b) do_vfp @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664#else
Russell King6ebbf2c2014-06-30 16:29:12 +0100665 ret.w lr @ CP#10 (VFP)
666 ret.w lr @ CP#11 (VFP)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100668 ret.w lr @ CP#12
669 ret.w lr @ CP#13
670 ret.w lr @ CP#14 (Debug)
671 ret.w lr @ CP#15 (Control)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672
Dave Martinef4c5362011-08-19 18:00:08 +0100673#ifdef NEED_CPU_ARCHITECTURE
674 .align 2
675.LCcpu_architecture:
676 .word __cpu_architecture
677#endif
678
Catalin Marinasb5872db2008-01-10 19:16:17 +0100679#ifdef CONFIG_NEON
680 .align 6
681
Paul Brookcb170a42008-04-18 22:43:08 +0100682.LCneon_arm_opcodes:
Catalin Marinasb5872db2008-01-10 19:16:17 +0100683 .word 0xfe000000 @ mask
684 .word 0xf2000000 @ opcode
685
686 .word 0xff100000 @ mask
687 .word 0xf4000000 @ opcode
688
689 .word 0x00000000 @ mask
690 .word 0x00000000 @ opcode
Paul Brookcb170a42008-04-18 22:43:08 +0100691
692.LCneon_thumb_opcodes:
693 .word 0xef000000 @ mask
694 .word 0xef000000 @ opcode
695
696 .word 0xff100000 @ mask
697 .word 0xf9000000 @ opcode
698
699 .word 0x00000000 @ mask
700 .word 0x00000000 @ opcode
Catalin Marinasb5872db2008-01-10 19:16:17 +0100701#endif
702
Linus Torvalds1da177e2005-04-16 15:20:36 -0700703do_fpe:
704 ldr r4, .LCfp
705 add r10, r10, #TI_FPSTATE @ r10 = workspace
706 ldr pc, [r4] @ Call FP module USR entry point
707
708/*
709 * The FP module is called with these registers set:
710 * r0 = instruction
711 * r2 = PC+4
712 * r9 = normal "successful" return address
713 * r10 = FP workspace
714 * lr = unrecognised FP instruction return address
715 */
716
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100717 .pushsection .data
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718ENTRY(fp_enter)
Russell Kingdb6ccbb62007-01-06 22:53:48 +0000719 .word no_fp
Santosh Shilimkar124efc22010-04-30 10:45:46 +0100720 .popsection
Linus Torvalds1da177e2005-04-16 15:20:36 -0700721
Catalin Marinas83e686e2009-09-18 23:27:07 +0100722ENTRY(no_fp)
Russell King6ebbf2c2014-06-30 16:29:12 +0100723 ret lr
Catalin Marinas83e686e2009-09-18 23:27:07 +0100724ENDPROC(no_fp)
Russell Kingdb6ccbb62007-01-06 22:53:48 +0000725
Russell King15ac49b2012-07-30 19:42:10 +0100726__und_usr_fault_32:
727 mov r1, #4
728 b 1f
Russell King2190fed2015-08-20 10:32:02 +0100729__und_usr_fault_16_pan:
730 uaccess_disable ip
Russell King15ac49b2012-07-30 19:42:10 +0100731__und_usr_fault_16:
732 mov r1, #2
Catalin Marinas1417a6b2014-04-22 16:14:29 +01007331: mov r0, sp
Russell King14327c62015-04-21 14:17:25 +0100734 badr lr, ret_from_exception
Russell King15ac49b2012-07-30 19:42:10 +0100735 b __und_fault
736ENDPROC(__und_usr_fault_32)
737ENDPROC(__und_usr_fault_16)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700738
739 .align 5
740__pabt_usr:
Russell Kingccea7a12005-05-31 22:22:32 +0100741 usr_entry
Kirill A. Shutemov4fb28472009-09-25 13:39:47 +0100742 mov r2, sp @ regs
Russell King8dfe7ac2011-06-26 12:37:35 +0100743 pabt_helper
Catalin Marinasc4c57162009-02-16 11:42:09 +0100744 UNWIND(.fnend )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745 /* fall through */
746/*
747 * This is the return code to user mode for abort handlers
748 */
749ENTRY(ret_from_exception)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100750 UNWIND(.fnstart )
751 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752 get_thread_info tsk
753 mov why, #0
754 b ret_to_user
Catalin Marinasc4c57162009-02-16 11:42:09 +0100755 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100756ENDPROC(__pabt_usr)
757ENDPROC(ret_from_exception)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700758
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +0100759 .align 5
760__fiq_usr:
761 usr_entry trace=0
762 kuser_cmpxchg_check
763 mov r0, sp @ struct pt_regs *regs
764 bl handle_fiq_as_nmi
765 get_thread_info tsk
766 restore_user_regs fast = 0, offset = 0
767 UNWIND(.fnend )
768ENDPROC(__fiq_usr)
769
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770/*
771 * Register switch for ARMv3 and ARMv4 processors
772 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
773 * previous and next are guaranteed not to be the same.
774 */
775ENTRY(__switch_to)
Catalin Marinasc4c57162009-02-16 11:42:09 +0100776 UNWIND(.fnstart )
777 UNWIND(.cantunwind )
Linus Torvalds1da177e2005-04-16 15:20:36 -0700778 add ip, r1, #TI_CPU_SAVE
Catalin Marinasb86040a2009-07-24 12:32:54 +0100779 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
780 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
781 THUMB( str sp, [ip], #4 )
782 THUMB( str lr, [ip], #4 )
André Hentschela4780ad2013-06-18 23:23:26 +0100783 ldr r4, [r2, #TI_TP_VALUE]
784 ldr r5, [r2, #TI_TP_VALUE + 4]
Catalin Marinas247055a2010-09-13 16:03:21 +0100785#ifdef CONFIG_CPU_USE_DOMAINS
Russell King1eef5d22015-08-19 21:23:48 +0100786 mrc p15, 0, r6, c3, c0, 0 @ Get domain register
787 str r6, [r1, #TI_CPU_DOMAIN] @ Save old domain register
Russell Kingd6551e82006-06-21 13:31:52 +0100788 ldr r6, [r2, #TI_CPU_DOMAIN]
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000789#endif
André Hentschela4780ad2013-06-18 23:23:26 +0100790 switch_tls r1, r4, r5, r3, r7
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400791#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
792 ldr r7, [r2, #TI_TASK]
793 ldr r8, =__stack_chk_guard
794 ldr r7, [r7, #TSK_STACK_CANARY]
795#endif
Catalin Marinas247055a2010-09-13 16:03:21 +0100796#ifdef CONFIG_CPU_USE_DOMAINS
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
Hyok S. Choiafeb90c2006-01-13 21:05:25 +0000798#endif
Russell Kingd6551e82006-06-21 13:31:52 +0100799 mov r5, r0
800 add r4, r2, #TI_CPU_SAVE
801 ldr r0, =thread_notify_head
802 mov r1, #THREAD_NOTIFY_SWITCH
803 bl atomic_notifier_call_chain
Nicolas Pitredf0698b2010-06-07 21:50:33 -0400804#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
805 str r7, [r8]
806#endif
Catalin Marinasb86040a2009-07-24 12:32:54 +0100807 THUMB( mov ip, r4 )
Russell Kingd6551e82006-06-21 13:31:52 +0100808 mov r0, r5
Catalin Marinasb86040a2009-07-24 12:32:54 +0100809 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
810 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
811 THUMB( ldr sp, [ip], #4 )
812 THUMB( ldr pc, [ip] )
Catalin Marinasc4c57162009-02-16 11:42:09 +0100813 UNWIND(.fnend )
Catalin Marinas93ed3972008-08-28 11:22:32 +0100814ENDPROC(__switch_to)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700815
816 __INIT
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100817
818/*
819 * User helpers.
820 *
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100821 * Each segment is 32-byte aligned and will be moved to the top of the high
822 * vector page. New segments (if ever needed) must be added in front of
823 * existing ones. This mechanism should be used only for things that are
824 * really small and justified, and not be abused freely.
825 *
Nicolas Pitre37b83042011-06-19 23:36:03 -0400826 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100827 */
Catalin Marinasb86040a2009-07-24 12:32:54 +0100828 THUMB( .arm )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100829
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100830 .macro usr_ret, reg
831#ifdef CONFIG_ARM_THUMB
832 bx \reg
833#else
Russell King6ebbf2c2014-06-30 16:29:12 +0100834 ret \reg
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100835#endif
836 .endm
837
Russell King5b43e7a2013-07-04 11:32:04 +0100838 .macro kuser_pad, sym, size
839 .if (. - \sym) & 3
840 .rept 4 - (. - \sym) & 3
841 .byte 0
842 .endr
843 .endif
844 .rept (\size - (. - \sym)) / 4
845 .word 0xe7fddef1
846 .endr
847 .endm
848
Russell Kingf6f91b02013-07-23 18:37:00 +0100849#ifdef CONFIG_KUSER_HELPERS
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100850 .align 5
851 .globl __kuser_helper_start
852__kuser_helper_start:
853
854/*
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400855 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
856 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000857 */
858
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400859__kuser_cmpxchg64: @ 0xffff0f60
860
Russell Kingdb695c02015-09-21 19:34:28 +0100861#if defined(CONFIG_CPU_32v6K)
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400862
863 stmfd sp!, {r4, r5, r6, r7}
864 ldrd r4, r5, [r0] @ load old val
865 ldrd r6, r7, [r1] @ load new val
866 smp_dmb arm
8671: ldrexd r0, r1, [r2] @ load current val
868 eors r3, r0, r4 @ compare with oldval (1)
869 eoreqs r3, r1, r5 @ compare with oldval (2)
870 strexdeq r3, r6, r7, [r2] @ store newval if eq
871 teqeq r3, #1 @ success?
872 beq 1b @ if no then retry
873 smp_dmb arm
874 rsbs r0, r3, #0 @ set returned val and C flag
875 ldmfd sp!, {r4, r5, r6, r7}
Will Deacon5a97d0a2012-02-03 11:08:05 +0100876 usr_ret lr
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400877
878#elif !defined(CONFIG_SMP)
879
880#ifdef CONFIG_MMU
881
882 /*
883 * The only thing that can break atomicity in this cmpxchg64
884 * implementation is either an IRQ or a data abort exception
885 * causing another process/thread to be scheduled in the middle of
886 * the critical sequence. The same strategy as for cmpxchg is used.
887 */
888 stmfd sp!, {r4, r5, r6, lr}
889 ldmia r0, {r4, r5} @ load old val
890 ldmia r1, {r6, lr} @ load new val
8911: ldmia r2, {r0, r1} @ load current val
892 eors r3, r0, r4 @ compare with oldval (1)
893 eoreqs r3, r1, r5 @ compare with oldval (2)
8942: stmeqia r2, {r6, lr} @ store newval if eq
895 rsbs r0, r3, #0 @ set return val and C flag
896 ldmfd sp!, {r4, r5, r6, pc}
897
898 .text
899kuser_cmpxchg64_fixup:
900 @ Called from kuser_cmpxchg_fixup.
Russell King3ad55152011-07-22 23:09:07 +0100901 @ r4 = address of interrupted insn (must be preserved).
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400902 @ sp = saved regs. r7 and r8 are clobbered.
903 @ 1b = first critical insn, 2b = last critical insn.
Russell King3ad55152011-07-22 23:09:07 +0100904 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400905 mov r7, #0xffff0fff
906 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
Russell King3ad55152011-07-22 23:09:07 +0100907 subs r8, r4, r7
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400908 rsbcss r8, r8, #(2b - 1b)
909 strcs r7, [sp, #S_PC]
910#if __LINUX_ARM_ARCH__ < 6
911 bcc kuser_cmpxchg32_fixup
912#endif
Russell King6ebbf2c2014-06-30 16:29:12 +0100913 ret lr
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400914 .previous
915
916#else
917#warning "NPTL on non MMU needs fixing"
918 mov r0, #-1
919 adds r0, r0, #0
920 usr_ret lr
921#endif
922
923#else
924#error "incoherent kernel configuration"
925#endif
926
Russell King5b43e7a2013-07-04 11:32:04 +0100927 kuser_pad __kuser_cmpxchg64, 64
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400928
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000929__kuser_memory_barrier: @ 0xffff0fa0
Dave Martined3768a2010-12-01 15:39:23 +0100930 smp_dmb arm
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100931 usr_ret lr
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000932
Russell King5b43e7a2013-07-04 11:32:04 +0100933 kuser_pad __kuser_memory_barrier, 32
Nicolas Pitre7c612bf2005-12-19 22:20:51 +0000934
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100935__kuser_cmpxchg: @ 0xffff0fc0
936
Russell Kingdb695c02015-09-21 19:34:28 +0100937#if __LINUX_ARM_ARCH__ < 6
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100938
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000939#ifdef CONFIG_MMU
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100940
941 /*
942 * The only thing that can break atomicity in this cmpxchg
943 * implementation is either an IRQ or a data abort exception
944 * causing another process/thread to be scheduled in the middle
945 * of the critical sequence. To prevent this, code is added to
946 * the IRQ and data abort exception handlers to set the pc back
947 * to the beginning of the critical section if it is found to be
948 * within that critical section (see kuser_cmpxchg_fixup).
949 */
9501: ldr r3, [r2] @ load current val
951 subs r3, r3, r0 @ compare with oldval
9522: streq r1, [r2] @ store newval if eq
953 rsbs r0, r3, #0 @ set return val and C flag
954 usr_ret lr
955
956 .text
Nicolas Pitre40fb79c2011-06-19 23:36:03 -0400957kuser_cmpxchg32_fixup:
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100958 @ Called from kuser_cmpxchg_check macro.
Russell Kingb059bdc2011-06-25 15:44:20 +0100959 @ r4 = address of interrupted insn (must be preserved).
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100960 @ sp = saved regs. r7 and r8 are clobbered.
961 @ 1b = first critical insn, 2b = last critical insn.
Russell Kingb059bdc2011-06-25 15:44:20 +0100962 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100963 mov r7, #0xffff0fff
964 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
Russell Kingb059bdc2011-06-25 15:44:20 +0100965 subs r8, r4, r7
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100966 rsbcss r8, r8, #(2b - 1b)
967 strcs r7, [sp, #S_PC]
Russell King6ebbf2c2014-06-30 16:29:12 +0100968 ret lr
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100969 .previous
970
Nicolas Pitre49bca4c2006-02-08 21:19:37 +0000971#else
972#warning "NPTL on non MMU needs fixing"
973 mov r0, #-1
974 adds r0, r0, #0
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100975 usr_ret lr
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100976#endif
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100977
978#else
979
Dave Martined3768a2010-12-01 15:39:23 +0100980 smp_dmb arm
Nicolas Pitreb49c0f22007-11-20 17:20:29 +01009811: ldrex r3, [r2]
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100982 subs r3, r3, r0
983 strexeq r3, r1, [r2]
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100984 teqeq r3, #1
985 beq 1b
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100986 rsbs r0, r3, #0
Nicolas Pitreb49c0f22007-11-20 17:20:29 +0100987 /* beware -- each __kuser slot must be 8 instructions max */
Russell Kingf00ec482010-09-04 10:47:48 +0100988 ALT_SMP(b __kuser_memory_barrier)
989 ALT_UP(usr_ret lr)
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100990
991#endif
992
Russell King5b43e7a2013-07-04 11:32:04 +0100993 kuser_pad __kuser_cmpxchg, 32
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100994
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100995__kuser_get_tls: @ 0xffff0fe0
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100996 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
Nicolas Pitreba9b5d72006-08-18 17:20:15 +0100997 usr_ret lr
Tony Lindgrenf159f4e2010-07-05 14:53:10 +0100998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
Russell King5b43e7a2013-07-04 11:32:04 +0100999 kuser_pad __kuser_get_tls, 16
1000 .rep 3
Tony Lindgrenf159f4e2010-07-05 14:53:10 +01001001 .word 0 @ 0xffff0ff0 software TLS value, then
1002 .endr @ pad up to __kuser_helper_version
Nicolas Pitre2d2669b2005-04-29 22:08:33 +01001003
Nicolas Pitre2d2669b2005-04-29 22:08:33 +01001004__kuser_helper_version: @ 0xffff0ffc
1005 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1006
1007 .globl __kuser_helper_end
1008__kuser_helper_end:
1009
Russell Kingf6f91b02013-07-23 18:37:00 +01001010#endif
1011
Catalin Marinasb86040a2009-07-24 12:32:54 +01001012 THUMB( .thumb )
Nicolas Pitre2d2669b2005-04-29 22:08:33 +01001013
Linus Torvalds1da177e2005-04-16 15:20:36 -07001014/*
1015 * Vector stubs.
1016 *
Russell King19accfd2013-07-04 11:40:32 +01001017 * This code is copied to 0xffff1000 so we can use branches in the
1018 * vectors, rather than ldr's. Note that this code must not exceed
1019 * a page size.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020 *
1021 * Common stub entry macro:
1022 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
Russell Kingccea7a12005-05-31 22:22:32 +01001023 *
1024 * SP points to a minimal amount of processor-private memory, the address
1025 * of which is copied into r0 for the mode specific abort handler.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001027 .macro vector_stub, name, mode, correction=0
Linus Torvalds1da177e2005-04-16 15:20:36 -07001028 .align 5
1029
1030vector_\name:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001031 .if \correction
1032 sub lr, lr, #\correction
1033 .endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034
Russell Kingccea7a12005-05-31 22:22:32 +01001035 @
1036 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1037 @ (parent CPSR)
1038 @
1039 stmia sp, {r0, lr} @ save r0, lr
1040 mrs lr, spsr
1041 str lr, [sp, #8] @ save spsr
1042
1043 @
1044 @ Prepare for SVC32 mode. IRQs remain disabled.
1045 @
1046 mrs r0, cpsr
Catalin Marinasb86040a2009-07-24 12:32:54 +01001047 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
Russell Kingccea7a12005-05-31 22:22:32 +01001048 msr spsr_cxsf, r0
1049
1050 @
1051 @ the branch table must immediately follow this code
1052 @
Russell Kingccea7a12005-05-31 22:22:32 +01001053 and lr, lr, #0x0f
Catalin Marinasb86040a2009-07-24 12:32:54 +01001054 THUMB( adr r0, 1f )
1055 THUMB( ldr lr, [r0, lr, lsl #2] )
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001056 mov r0, sp
Catalin Marinasb86040a2009-07-24 12:32:54 +01001057 ARM( ldr lr, [pc, lr, lsl #2] )
Russell Kingccea7a12005-05-31 22:22:32 +01001058 movs pc, lr @ branch to handler in SVC mode
Catalin Marinas93ed3972008-08-28 11:22:32 +01001059ENDPROC(vector_\name)
Catalin Marinas88987ef2009-07-24 12:32:52 +01001060
1061 .align 2
1062 @ handler addresses follow this label
10631:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 .endm
1065
Russell Kingb9b32bf2013-07-04 12:03:31 +01001066 .section .stubs, "ax", %progbits
Russell King19accfd2013-07-04 11:40:32 +01001067 @ This must be the first word
1068 .word vector_swi
1069
1070vector_rst:
1071 ARM( swi SYS_ERROR0 )
1072 THUMB( svc #0 )
1073 THUMB( nop )
1074 b vector_und
1075
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076/*
1077 * Interrupt dispatcher
1078 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001079 vector_stub irq, IRQ_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001080
1081 .long __irq_usr @ 0 (USR_26 / USR_32)
1082 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1083 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1084 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1085 .long __irq_invalid @ 4
1086 .long __irq_invalid @ 5
1087 .long __irq_invalid @ 6
1088 .long __irq_invalid @ 7
1089 .long __irq_invalid @ 8
1090 .long __irq_invalid @ 9
1091 .long __irq_invalid @ a
1092 .long __irq_invalid @ b
1093 .long __irq_invalid @ c
1094 .long __irq_invalid @ d
1095 .long __irq_invalid @ e
1096 .long __irq_invalid @ f
1097
1098/*
1099 * Data abort dispatcher
1100 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1101 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001102 vector_stub dabt, ABT_MODE, 8
Linus Torvalds1da177e2005-04-16 15:20:36 -07001103
1104 .long __dabt_usr @ 0 (USR_26 / USR_32)
1105 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1106 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1107 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1108 .long __dabt_invalid @ 4
1109 .long __dabt_invalid @ 5
1110 .long __dabt_invalid @ 6
1111 .long __dabt_invalid @ 7
1112 .long __dabt_invalid @ 8
1113 .long __dabt_invalid @ 9
1114 .long __dabt_invalid @ a
1115 .long __dabt_invalid @ b
1116 .long __dabt_invalid @ c
1117 .long __dabt_invalid @ d
1118 .long __dabt_invalid @ e
1119 .long __dabt_invalid @ f
1120
1121/*
1122 * Prefetch abort dispatcher
1123 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1124 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001125 vector_stub pabt, ABT_MODE, 4
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126
1127 .long __pabt_usr @ 0 (USR_26 / USR_32)
1128 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1129 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1130 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1131 .long __pabt_invalid @ 4
1132 .long __pabt_invalid @ 5
1133 .long __pabt_invalid @ 6
1134 .long __pabt_invalid @ 7
1135 .long __pabt_invalid @ 8
1136 .long __pabt_invalid @ 9
1137 .long __pabt_invalid @ a
1138 .long __pabt_invalid @ b
1139 .long __pabt_invalid @ c
1140 .long __pabt_invalid @ d
1141 .long __pabt_invalid @ e
1142 .long __pabt_invalid @ f
1143
1144/*
1145 * Undef instr entry dispatcher
1146 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1147 */
Nicolas Pitreb7ec4792005-11-06 14:42:37 +00001148 vector_stub und, UND_MODE
Linus Torvalds1da177e2005-04-16 15:20:36 -07001149
1150 .long __und_usr @ 0 (USR_26 / USR_32)
1151 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1152 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1153 .long __und_svc @ 3 (SVC_26 / SVC_32)
1154 .long __und_invalid @ 4
1155 .long __und_invalid @ 5
1156 .long __und_invalid @ 6
1157 .long __und_invalid @ 7
1158 .long __und_invalid @ 8
1159 .long __und_invalid @ 9
1160 .long __und_invalid @ a
1161 .long __und_invalid @ b
1162 .long __und_invalid @ c
1163 .long __und_invalid @ d
1164 .long __und_invalid @ e
1165 .long __und_invalid @ f
1166
1167 .align 5
1168
1169/*=============================================================================
Russell King19accfd2013-07-04 11:40:32 +01001170 * Address exception handler
1171 *-----------------------------------------------------------------------------
1172 * These aren't too critical.
1173 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1174 */
1175
1176vector_addrexcptn:
1177 b vector_addrexcptn
1178
1179/*=============================================================================
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +01001180 * FIQ "NMI" handler
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181 *-----------------------------------------------------------------------------
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +01001182 * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1183 * systems.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001184 */
Daniel Thompsonc0e7f7e2014-09-17 17:12:06 +01001185 vector_stub fiq, FIQ_MODE, 4
1186
1187 .long __fiq_usr @ 0 (USR_26 / USR_32)
1188 .long __fiq_svc @ 1 (FIQ_26 / FIQ_32)
1189 .long __fiq_svc @ 2 (IRQ_26 / IRQ_32)
1190 .long __fiq_svc @ 3 (SVC_26 / SVC_32)
1191 .long __fiq_svc @ 4
1192 .long __fiq_svc @ 5
1193 .long __fiq_svc @ 6
1194 .long __fiq_abt @ 7
1195 .long __fiq_svc @ 8
1196 .long __fiq_svc @ 9
1197 .long __fiq_svc @ a
1198 .long __fiq_svc @ b
1199 .long __fiq_svc @ c
1200 .long __fiq_svc @ d
1201 .long __fiq_svc @ e
1202 .long __fiq_svc @ f
Linus Torvalds1da177e2005-04-16 15:20:36 -07001203
Ard Biesheuvel31b96ca2016-02-10 11:41:08 +01001204 .globl vector_fiq
Russell Kinge39e3f32013-07-09 01:03:17 +01001205
Russell Kingb9b32bf2013-07-04 12:03:31 +01001206 .section .vectors, "ax", %progbits
Ard Biesheuvelb48da552016-02-05 10:04:47 +01001207.L__vectors_start:
Russell Kingb9b32bf2013-07-04 12:03:31 +01001208 W(b) vector_rst
1209 W(b) vector_und
Ard Biesheuvelb48da552016-02-05 10:04:47 +01001210 W(ldr) pc, .L__vectors_start + 0x1000
Russell Kingb9b32bf2013-07-04 12:03:31 +01001211 W(b) vector_pabt
1212 W(b) vector_dabt
1213 W(b) vector_addrexcptn
1214 W(b) vector_irq
1215 W(b) vector_fiq
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216
1217 .data
1218
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219 .globl cr_alignment
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220cr_alignment:
1221 .space 4
eric miao52108642010-12-13 09:42:34 +01001222
1223#ifdef CONFIG_MULTI_IRQ_HANDLER
1224 .globl handle_arch_irq
1225handle_arch_irq:
1226 .space 4
1227#endif