blob: 51a48741d4c015aff87904b26471d887bd271831 [file] [log] [blame]
Andreas Färberfdfe7f42017-02-15 11:15:20 +01001/*
2 * Actions Semi S500 SoC
3 *
4 * Copyright (c) 2016-2017 Andreas Färber
5 *
6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 */
8
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10
11/ {
12 compatible = "actions,s500";
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 };
19
20 chosen {
21 };
22
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 cpu0: cpu@0 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <0x0>;
Andreas Färberad90c2b2017-02-26 17:24:54 +010031 enable-method = "actions,s500-smp";
Andreas Färberfdfe7f42017-02-15 11:15:20 +010032 };
33
34 cpu1: cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 reg = <0x1>;
Andreas Färberad90c2b2017-02-26 17:24:54 +010038 enable-method = "actions,s500-smp";
Andreas Färberfdfe7f42017-02-15 11:15:20 +010039 };
40
41 cpu2: cpu@2 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a9";
44 reg = <0x2>;
Andreas Färberad90c2b2017-02-26 17:24:54 +010045 enable-method = "actions,s500-smp";
Andreas Färberfdfe7f42017-02-15 11:15:20 +010046 };
47
48 cpu3: cpu@3 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a9";
51 reg = <0x3>;
Andreas Färberad90c2b2017-02-26 17:24:54 +010052 enable-method = "actions,s500-smp";
Andreas Färberfdfe7f42017-02-15 11:15:20 +010053 };
54 };
55
56 arm-pmu {
57 compatible = "arm,cortex-a9-pmu";
58 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
63 };
64
65 hosc: hosc {
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 #clock-cells = <0>;
69 };
70
71 soc {
72 compatible = "simple-bus";
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 scu: scu@b0020000 {
78 compatible = "arm,cortex-a9-scu";
79 reg = <0xb0020000 0x100>;
80 };
81
82 global_timer: timer@b0020200 {
83 compatible = "arm,cortex-a9-global-timer";
84 reg = <0xb0020200 0x100>;
85 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
86 status = "disabled";
87 };
88
89 twd_timer: timer@b0020600 {
90 compatible = "arm,cortex-a9-twd-timer";
91 reg = <0xb0020600 0x20>;
92 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
93 status = "disabled";
94 };
95
96 twd_wdt: wdt@b0020620 {
97 compatible = "arm,cortex-a9-twd-wdt";
98 reg = <0xb0020620 0xe0>;
99 interrupts = <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
100 status = "disabled";
101 };
102
103 gic: interrupt-controller@b0021000 {
104 compatible = "arm,cortex-a9-gic";
105 reg = <0xb0021000 0x1000>,
106 <0xb0020100 0x0100>;
107 interrupt-controller;
108 #interrupt-cells = <3>;
109 };
110
111 l2: cache-controller@b0022000 {
112 compatible = "arm,pl310-cache";
113 reg = <0xb0022000 0x1000>;
114 cache-unified;
115 cache-level = <2>;
116 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
117 arm,tag-latency = <3 3 2>;
118 arm,data-latency = <5 3 3>;
119 };
120
121 uart0: serial@b0120000 {
122 compatible = "actions,s500-uart", "actions,owl-uart";
123 reg = <0xb0120000 0x2000>;
124 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
125 status = "disabled";
126 };
127
128 uart1: serial@b0122000 {
129 compatible = "actions,s500-uart", "actions,owl-uart";
130 reg = <0xb0122000 0x2000>;
131 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
132 status = "disabled";
133 };
134
135 uart2: serial@b0124000 {
136 compatible = "actions,s500-uart", "actions,owl-uart";
137 reg = <0xb0124000 0x2000>;
138 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
139 status = "disabled";
140 };
141
142 uart3: serial@b0126000 {
143 compatible = "actions,s500-uart", "actions,owl-uart";
144 reg = <0xb0126000 0x2000>;
145 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
146 status = "disabled";
147 };
148
149 uart4: serial@b0128000 {
150 compatible = "actions,s500-uart", "actions,owl-uart";
151 reg = <0xb0128000 0x2000>;
152 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
153 status = "disabled";
154 };
155
156 uart5: serial@b012a000 {
157 compatible = "actions,s500-uart", "actions,owl-uart";
158 reg = <0xb012a000 0x2000>;
159 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
160 status = "disabled";
161 };
162
163 uart6: serial@b012c000 {
164 compatible = "actions,s500-uart", "actions,owl-uart";
165 reg = <0xb012c000 0x2000>;
166 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
167 status = "disabled";
168 };
169
170 timer: timer@b0168000 {
171 compatible = "actions,s500-timer";
172 reg = <0xb0168000 0x8000>;
173 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
177 interrupt-names = "2hz0", "2hz1", "timer0", "timer1";
178 };
Andreas Färber740f6beb2017-02-26 04:08:53 +0100179
180 sps: power-controller@b01b0100 {
181 compatible = "actions,s500-sps";
182 reg = <0xb01b0100 0x100>;
183 #power-domain-cells = <1>;
184 };
Andreas Färberfdfe7f42017-02-15 11:15:20 +0100185 };
186};