Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Support PCI/PCIe on PowerNV platforms |
| 3 | * |
| 4 | * Copyright 2011 Benjamin Herrenschmidt, IBM Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version |
| 9 | * 2 of the License, or (at your option) any later version. |
| 10 | */ |
| 11 | |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 12 | #undef DEBUG |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 13 | |
| 14 | #include <linux/kernel.h> |
| 15 | #include <linux/pci.h> |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 16 | #include <linux/crash_dump.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 17 | #include <linux/delay.h> |
| 18 | #include <linux/string.h> |
| 19 | #include <linux/init.h> |
| 20 | #include <linux/bootmem.h> |
| 21 | #include <linux/irq.h> |
| 22 | #include <linux/io.h> |
| 23 | #include <linux/msi.h> |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 24 | #include <linux/memblock.h> |
Alexey Kardashevskiy | ac9a588 | 2015-06-05 16:34:56 +1000 | [diff] [blame] | 25 | #include <linux/iommu.h> |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 26 | #include <linux/rculist.h> |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 27 | #include <linux/sizes.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 28 | |
| 29 | #include <asm/sections.h> |
| 30 | #include <asm/io.h> |
| 31 | #include <asm/prom.h> |
| 32 | #include <asm/pci-bridge.h> |
| 33 | #include <asm/machdep.h> |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 34 | #include <asm/msi_bitmap.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 35 | #include <asm/ppc-pci.h> |
| 36 | #include <asm/opal.h> |
| 37 | #include <asm/iommu.h> |
| 38 | #include <asm/tce.h> |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 39 | #include <asm/xics.h> |
Michael Ellerman | 7644d58 | 2017-02-10 12:04:56 +1100 | [diff] [blame] | 40 | #include <asm/debugfs.h> |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 41 | #include <asm/firmware.h> |
Ian Munsie | 80c49c7 | 2014-10-08 19:54:57 +1100 | [diff] [blame] | 42 | #include <asm/pnv-pci.h> |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 43 | #include <asm/mmzone.h> |
Ian Munsie | 80c49c7 | 2014-10-08 19:54:57 +1100 | [diff] [blame] | 44 | |
Michael Neuling | ec249dd | 2015-05-27 16:07:16 +1000 | [diff] [blame] | 45 | #include <misc/cxl-base.h> |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 46 | |
| 47 | #include "powernv.h" |
| 48 | #include "pci.h" |
| 49 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 50 | #define PNV_IODA1_M64_NUM 16 /* Number of M64 BARs */ |
| 51 | #define PNV_IODA1_M64_SEGS 8 /* Segments per M64 BAR */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 52 | #define PNV_IODA1_DMA32_SEGSIZE 0x10000000 |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 53 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 54 | #define POWERNV_IOMMU_DEFAULT_LEVELS 1 |
| 55 | #define POWERNV_IOMMU_MAX_LEVELS 5 |
| 56 | |
Gavin Shan | 9497a1c | 2016-06-21 12:35:56 +1000 | [diff] [blame] | 57 | static const char * const pnv_phb_names[] = { "IODA1", "IODA2", "NPU" }; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 58 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl); |
| 59 | |
Alexey Kardashevskiy | 7d623e4 | 2016-04-29 18:55:21 +1000 | [diff] [blame] | 60 | void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level, |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 61 | const char *fmt, ...) |
| 62 | { |
| 63 | struct va_format vaf; |
| 64 | va_list args; |
| 65 | char pfix[32]; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 66 | |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 67 | va_start(args, fmt); |
| 68 | |
| 69 | vaf.fmt = fmt; |
| 70 | vaf.va = &args; |
| 71 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 72 | if (pe->flags & PNV_IODA_PE_DEV) |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 73 | strlcpy(pfix, dev_name(&pe->pdev->dev), sizeof(pfix)); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 74 | else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 75 | sprintf(pfix, "%04x:%02x ", |
| 76 | pci_domain_nr(pe->pbus), pe->pbus->number); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 77 | #ifdef CONFIG_PCI_IOV |
| 78 | else if (pe->flags & PNV_IODA_PE_VF) |
| 79 | sprintf(pfix, "%04x:%02x:%2x.%d", |
| 80 | pci_domain_nr(pe->parent_dev->bus), |
| 81 | (pe->rid & 0xff00) >> 8, |
| 82 | PCI_SLOT(pe->rid), PCI_FUNC(pe->rid)); |
| 83 | #endif /* CONFIG_PCI_IOV*/ |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 84 | |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 85 | printk("%spci %s: [PE# %.2x] %pV", |
Joe Perches | 6d31c2f | 2014-09-21 10:55:06 -0700 | [diff] [blame] | 86 | level, pfix, pe->pe_number, &vaf); |
| 87 | |
| 88 | va_end(args); |
| 89 | } |
| 90 | |
Thadeu Lima de Souza Cascardo | 4e28784 | 2014-10-23 19:19:35 -0200 | [diff] [blame] | 91 | static bool pnv_iommu_bypass_disabled __read_mostly; |
| 92 | |
| 93 | static int __init iommu_setup(char *str) |
| 94 | { |
| 95 | if (!str) |
| 96 | return -EINVAL; |
| 97 | |
| 98 | while (*str) { |
| 99 | if (!strncmp(str, "nobypass", 8)) { |
| 100 | pnv_iommu_bypass_disabled = true; |
| 101 | pr_info("PowerNV: IOMMU bypass window disabled.\n"); |
| 102 | break; |
| 103 | } |
| 104 | str += strcspn(str, ","); |
| 105 | if (*str == ',') |
| 106 | str++; |
| 107 | } |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | early_param("iommu", iommu_setup); |
| 112 | |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 113 | static inline bool pnv_pci_is_m64(struct pnv_phb *phb, struct resource *r) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 114 | { |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 115 | /* |
| 116 | * WARNING: We cannot rely on the resource flags. The Linux PCI |
| 117 | * allocation code sometimes decides to put a 64-bit prefetchable |
| 118 | * BAR in the 32-bit window, so we have to compare the addresses. |
| 119 | * |
| 120 | * For simplicity we only test resource start. |
| 121 | */ |
| 122 | return (r->start >= phb->ioda.m64_base && |
| 123 | r->start < (phb->ioda.m64_base + phb->ioda.m64_size)); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 124 | } |
| 125 | |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 126 | static inline bool pnv_pci_is_m64_flags(unsigned long resource_flags) |
| 127 | { |
| 128 | unsigned long flags = (IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); |
| 129 | |
| 130 | return (resource_flags & flags) == flags; |
| 131 | } |
| 132 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 133 | static struct pnv_ioda_pe *pnv_ioda_init_pe(struct pnv_phb *phb, int pe_no) |
| 134 | { |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 135 | s64 rc; |
| 136 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 137 | phb->ioda.pe_array[pe_no].phb = phb; |
| 138 | phb->ioda.pe_array[pe_no].pe_number = pe_no; |
| 139 | |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 140 | /* |
| 141 | * Clear the PE frozen state as it might be put into frozen state |
| 142 | * in the last PCI remove path. It's not harmful to do so when the |
| 143 | * PE is already in unfrozen state. |
| 144 | */ |
| 145 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, |
| 146 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
Russell Currey | d4791db | 2016-11-16 12:12:26 +1100 | [diff] [blame] | 147 | if (rc != OPAL_SUCCESS && rc != OPAL_UNSUPPORTED) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 148 | pr_warn("%s: Error %lld unfreezing PHB#%x-PE#%x\n", |
Gavin Shan | 313483d | 2016-09-28 14:34:56 +1000 | [diff] [blame] | 149 | __func__, rc, phb->hose->global_number, pe_no); |
| 150 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 151 | return &phb->ioda.pe_array[pe_no]; |
| 152 | } |
| 153 | |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 154 | static void pnv_ioda_reserve_pe(struct pnv_phb *phb, int pe_no) |
| 155 | { |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 156 | if (!(pe_no >= 0 && pe_no < phb->ioda.total_pe_num)) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 157 | pr_warn("%s: Invalid PE %x on PHB#%x\n", |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 158 | __func__, pe_no, phb->hose->global_number); |
| 159 | return; |
| 160 | } |
| 161 | |
Gavin Shan | e9dc4d7 | 2015-06-19 12:26:16 +1000 | [diff] [blame] | 162 | if (test_and_set_bit(pe_no, phb->ioda.pe_alloc)) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 163 | pr_debug("%s: PE %x was reserved on PHB#%x\n", |
Gavin Shan | e9dc4d7 | 2015-06-19 12:26:16 +1000 | [diff] [blame] | 164 | __func__, pe_no, phb->hose->global_number); |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 165 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 166 | pnv_ioda_init_pe(phb, pe_no); |
Gavin Shan | 4b82ab1 | 2014-11-12 13:36:07 +1100 | [diff] [blame] | 167 | } |
| 168 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 169 | static struct pnv_ioda_pe *pnv_ioda_alloc_pe(struct pnv_phb *phb) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 170 | { |
Andrzej Hajda | 6096481 | 2016-08-17 12:03:05 +0200 | [diff] [blame] | 171 | long pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 172 | |
Gavin Shan | 9fcd6f4 | 2016-05-20 16:41:30 +1000 | [diff] [blame] | 173 | for (pe = phb->ioda.total_pe_num - 1; pe >= 0; pe--) { |
| 174 | if (!test_and_set_bit(pe, phb->ioda.pe_alloc)) |
| 175 | return pnv_ioda_init_pe(phb, pe); |
| 176 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 177 | |
Gavin Shan | 9fcd6f4 | 2016-05-20 16:41:30 +1000 | [diff] [blame] | 178 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 179 | } |
| 180 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 181 | static void pnv_ioda_free_pe(struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 182 | { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 183 | struct pnv_phb *phb = pe->phb; |
Gavin Shan | caa58f8 | 2016-09-06 14:17:18 +1000 | [diff] [blame] | 184 | unsigned int pe_num = pe->pe_number; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 185 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 186 | WARN_ON(pe->pdev); |
| 187 | |
| 188 | memset(pe, 0, sizeof(struct pnv_ioda_pe)); |
Gavin Shan | caa58f8 | 2016-09-06 14:17:18 +1000 | [diff] [blame] | 189 | clear_bit(pe_num, phb->ioda.pe_alloc); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 190 | } |
| 191 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 192 | /* The default M64 BAR is shared by all PEs */ |
| 193 | static int pnv_ioda2_init_m64(struct pnv_phb *phb) |
| 194 | { |
| 195 | const char *desc; |
| 196 | struct resource *r; |
| 197 | s64 rc; |
| 198 | |
| 199 | /* Configure the default M64 BAR */ |
| 200 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
| 201 | OPAL_M64_WINDOW_TYPE, |
| 202 | phb->ioda.m64_bar_idx, |
| 203 | phb->ioda.m64_base, |
| 204 | 0, /* unused */ |
| 205 | phb->ioda.m64_size); |
| 206 | if (rc != OPAL_SUCCESS) { |
| 207 | desc = "configuring"; |
| 208 | goto fail; |
| 209 | } |
| 210 | |
| 211 | /* Enable the default M64 BAR */ |
| 212 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
| 213 | OPAL_M64_WINDOW_TYPE, |
| 214 | phb->ioda.m64_bar_idx, |
| 215 | OPAL_ENABLE_M64_SPLIT); |
| 216 | if (rc != OPAL_SUCCESS) { |
| 217 | desc = "enabling"; |
| 218 | goto fail; |
| 219 | } |
| 220 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 221 | /* |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 222 | * Exclude the segments for reserved and root bus PE, which |
| 223 | * are first or last two PEs. |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 224 | */ |
| 225 | r = &phb->hose->mem_resources[1]; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 226 | if (phb->ioda.reserved_pe_idx == 0) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 227 | r->start += (2 * phb->ioda.m64_segsize); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 228 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 229 | r->end -= (2 * phb->ioda.m64_segsize); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 230 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 231 | pr_warn(" Cannot strip M64 segment for reserved PE#%x\n", |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 232 | phb->ioda.reserved_pe_idx); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 233 | |
| 234 | return 0; |
| 235 | |
| 236 | fail: |
| 237 | pr_warn(" Failure %lld %s M64 BAR#%d\n", |
| 238 | rc, desc, phb->ioda.m64_bar_idx); |
| 239 | opal_pci_phb_mmio_enable(phb->opal_id, |
| 240 | OPAL_M64_WINDOW_TYPE, |
| 241 | phb->ioda.m64_bar_idx, |
| 242 | OPAL_DISABLE_M64); |
| 243 | return -EIO; |
| 244 | } |
| 245 | |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 246 | static void pnv_ioda_reserve_dev_m64_pe(struct pci_dev *pdev, |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 247 | unsigned long *pe_bitmap) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 248 | { |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 249 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 250 | struct pnv_phb *phb = hose->private_data; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 251 | struct resource *r; |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 252 | resource_size_t base, sgsz, start, end; |
| 253 | int segno, i; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 254 | |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 255 | base = phb->ioda.m64_base; |
| 256 | sgsz = phb->ioda.m64_segsize; |
| 257 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
| 258 | r = &pdev->resource[i]; |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 259 | if (!r->parent || !pnv_pci_is_m64(phb, r)) |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 260 | continue; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 261 | |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 262 | start = _ALIGN_DOWN(r->start - base, sgsz); |
| 263 | end = _ALIGN_UP(r->end - base, sgsz); |
| 264 | for (segno = start / sgsz; segno < end / sgsz; segno++) { |
| 265 | if (pe_bitmap) |
| 266 | set_bit(segno, pe_bitmap); |
| 267 | else |
| 268 | pnv_ioda_reserve_pe(phb, segno); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 269 | } |
| 270 | } |
| 271 | } |
| 272 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 273 | static int pnv_ioda1_init_m64(struct pnv_phb *phb) |
| 274 | { |
| 275 | struct resource *r; |
| 276 | int index; |
| 277 | |
| 278 | /* |
| 279 | * There are 16 M64 BARs, each of which has 8 segments. So |
| 280 | * there are as many M64 segments as the maximum number of |
| 281 | * PEs, which is 128. |
| 282 | */ |
| 283 | for (index = 0; index < PNV_IODA1_M64_NUM; index++) { |
| 284 | unsigned long base, segsz = phb->ioda.m64_segsize; |
| 285 | int64_t rc; |
| 286 | |
| 287 | base = phb->ioda.m64_base + |
| 288 | index * PNV_IODA1_M64_SEGS * segsz; |
| 289 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
| 290 | OPAL_M64_WINDOW_TYPE, index, base, 0, |
| 291 | PNV_IODA1_M64_SEGS * segsz); |
| 292 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 293 | pr_warn(" Error %lld setting M64 PHB#%x-BAR#%d\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 294 | rc, phb->hose->global_number, index); |
| 295 | goto fail; |
| 296 | } |
| 297 | |
| 298 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
| 299 | OPAL_M64_WINDOW_TYPE, index, |
| 300 | OPAL_ENABLE_M64_SPLIT); |
| 301 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 302 | pr_warn(" Error %lld enabling M64 PHB#%x-BAR#%d\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 303 | rc, phb->hose->global_number, index); |
| 304 | goto fail; |
| 305 | } |
| 306 | } |
| 307 | |
| 308 | /* |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 309 | * Exclude the segments for reserved and root bus PE, which |
| 310 | * are first or last two PEs. |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 311 | */ |
| 312 | r = &phb->hose->mem_resources[1]; |
| 313 | if (phb->ioda.reserved_pe_idx == 0) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 314 | r->start += (2 * phb->ioda.m64_segsize); |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 315 | else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 316 | r->end -= (2 * phb->ioda.m64_segsize); |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 317 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 318 | WARN(1, "Wrong reserved PE#%x on PHB#%x\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 319 | phb->ioda.reserved_pe_idx, phb->hose->global_number); |
| 320 | |
| 321 | return 0; |
| 322 | |
| 323 | fail: |
| 324 | for ( ; index >= 0; index--) |
| 325 | opal_pci_phb_mmio_enable(phb->opal_id, |
| 326 | OPAL_M64_WINDOW_TYPE, index, OPAL_DISABLE_M64); |
| 327 | |
| 328 | return -EIO; |
| 329 | } |
| 330 | |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 331 | static void pnv_ioda_reserve_m64_pe(struct pci_bus *bus, |
| 332 | unsigned long *pe_bitmap, |
| 333 | bool all) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 334 | { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 335 | struct pci_dev *pdev; |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 336 | |
| 337 | list_for_each_entry(pdev, &bus->devices, bus_list) { |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 338 | pnv_ioda_reserve_dev_m64_pe(pdev, pe_bitmap); |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 339 | |
| 340 | if (all && pdev->subordinate) |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 341 | pnv_ioda_reserve_m64_pe(pdev->subordinate, |
| 342 | pe_bitmap, all); |
Gavin Shan | 96a2f92 | 2015-06-19 12:26:17 +1000 | [diff] [blame] | 343 | } |
| 344 | } |
| 345 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 346 | static struct pnv_ioda_pe *pnv_ioda_pick_m64_pe(struct pci_bus *bus, bool all) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 347 | { |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 348 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 349 | struct pnv_phb *phb = hose->private_data; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 350 | struct pnv_ioda_pe *master_pe, *pe; |
| 351 | unsigned long size, *pe_alloc; |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 352 | int i; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 353 | |
| 354 | /* Root bus shouldn't use M64 */ |
| 355 | if (pci_is_root_bus(bus)) |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 356 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 357 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 358 | /* Allocate bitmap */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 359 | size = _ALIGN_UP(phb->ioda.total_pe_num / 8, sizeof(unsigned long)); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 360 | pe_alloc = kzalloc(size, GFP_KERNEL); |
| 361 | if (!pe_alloc) { |
| 362 | pr_warn("%s: Out of memory !\n", |
| 363 | __func__); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 364 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 365 | } |
| 366 | |
Gavin Shan | 26ba248 | 2015-06-19 12:26:19 +1000 | [diff] [blame] | 367 | /* Figure out reserved PE numbers by the PE */ |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 368 | pnv_ioda_reserve_m64_pe(bus, pe_alloc, all); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 369 | |
| 370 | /* |
| 371 | * the current bus might not own M64 window and that's all |
| 372 | * contributed by its child buses. For the case, we needn't |
| 373 | * pick M64 dependent PE#. |
| 374 | */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 375 | if (bitmap_empty(pe_alloc, phb->ioda.total_pe_num)) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 376 | kfree(pe_alloc); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 377 | return NULL; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 378 | } |
| 379 | |
| 380 | /* |
| 381 | * Figure out the master PE and put all slave PEs to master |
| 382 | * PE's list to form compound PE. |
| 383 | */ |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 384 | master_pe = NULL; |
| 385 | i = -1; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 386 | while ((i = find_next_bit(pe_alloc, phb->ioda.total_pe_num, i + 1)) < |
| 387 | phb->ioda.total_pe_num) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 388 | pe = &phb->ioda.pe_array[i]; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 389 | |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 390 | phb->ioda.m64_segmap[pe->pe_number] = pe->pe_number; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 391 | if (!master_pe) { |
| 392 | pe->flags |= PNV_IODA_PE_MASTER; |
| 393 | INIT_LIST_HEAD(&pe->slaves); |
| 394 | master_pe = pe; |
| 395 | } else { |
| 396 | pe->flags |= PNV_IODA_PE_SLAVE; |
| 397 | pe->master = master_pe; |
| 398 | list_add_tail(&pe->list, &master_pe->slaves); |
| 399 | } |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 400 | |
| 401 | /* |
| 402 | * P7IOC supports M64DT, which helps mapping M64 segment |
| 403 | * to one particular PE#. However, PHB3 has fixed mapping |
| 404 | * between M64 segment and PE#. In order to have same logic |
| 405 | * for P7IOC and PHB3, we enforce fixed mapping between M64 |
| 406 | * segment and PE# on P7IOC. |
| 407 | */ |
| 408 | if (phb->type == PNV_PHB_IODA1) { |
| 409 | int64_t rc; |
| 410 | |
| 411 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 412 | pe->pe_number, OPAL_M64_WINDOW_TYPE, |
| 413 | pe->pe_number / PNV_IODA1_M64_SEGS, |
| 414 | pe->pe_number % PNV_IODA1_M64_SEGS); |
| 415 | if (rc != OPAL_SUCCESS) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 416 | pr_warn("%s: Error %lld mapping M64 for PHB#%x-PE#%x\n", |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 417 | __func__, rc, phb->hose->global_number, |
| 418 | pe->pe_number); |
| 419 | } |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | kfree(pe_alloc); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 423 | return master_pe; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 424 | } |
| 425 | |
| 426 | static void __init pnv_ioda_parse_m64_window(struct pnv_phb *phb) |
| 427 | { |
| 428 | struct pci_controller *hose = phb->hose; |
| 429 | struct device_node *dn = hose->dn; |
| 430 | struct resource *res; |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 431 | u32 m64_range[2], i; |
Gavin Shan | 0e7736c | 2016-08-02 14:10:35 +1000 | [diff] [blame] | 432 | const __be32 *r; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 433 | u64 pci_addr; |
| 434 | |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 435 | if (phb->type != PNV_PHB_IODA1 && phb->type != PNV_PHB_IODA2) { |
Gavin Shan | 1665c4a | 2014-11-12 13:36:04 +1100 | [diff] [blame] | 436 | pr_info(" Not support M64 window\n"); |
| 437 | return; |
| 438 | } |
| 439 | |
Stewart Smith | e4d54f7 | 2015-12-09 17:18:20 +1100 | [diff] [blame] | 440 | if (!firmware_has_feature(FW_FEATURE_OPAL)) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 441 | pr_info(" Firmware too old to support M64 window\n"); |
| 442 | return; |
| 443 | } |
| 444 | |
| 445 | r = of_get_property(dn, "ibm,opal-m64-window", NULL); |
| 446 | if (!r) { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 447 | pr_info(" No <ibm,opal-m64-window> on %pOF\n", |
| 448 | dn); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 449 | return; |
| 450 | } |
| 451 | |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 452 | /* |
| 453 | * Find the available M64 BAR range and pickup the last one for |
| 454 | * covering the whole 64-bits space. We support only one range. |
| 455 | */ |
| 456 | if (of_property_read_u32_array(dn, "ibm,opal-available-m64-ranges", |
| 457 | m64_range, 2)) { |
| 458 | /* In absence of the property, assume 0..15 */ |
| 459 | m64_range[0] = 0; |
| 460 | m64_range[1] = 16; |
| 461 | } |
| 462 | /* We only support 64 bits in our allocator */ |
| 463 | if (m64_range[1] > 63) { |
| 464 | pr_warn("%s: Limiting M64 range to 63 (from %d) on PHB#%x\n", |
| 465 | __func__, m64_range[1], phb->hose->global_number); |
| 466 | m64_range[1] = 63; |
| 467 | } |
| 468 | /* Empty range, no m64 */ |
| 469 | if (m64_range[1] <= m64_range[0]) { |
| 470 | pr_warn("%s: M64 empty, disabling M64 usage on PHB#%x\n", |
| 471 | __func__, phb->hose->global_number); |
| 472 | return; |
| 473 | } |
| 474 | |
| 475 | /* Configure M64 informations */ |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 476 | res = &hose->mem_resources[1]; |
Gavin Shan | e80c4e7 | 2015-10-22 12:03:08 +1100 | [diff] [blame] | 477 | res->name = dn->full_name; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 478 | res->start = of_translate_address(dn, r + 2); |
| 479 | res->end = res->start + of_read_number(r + 4, 2) - 1; |
| 480 | res->flags = (IORESOURCE_MEM | IORESOURCE_MEM_64 | IORESOURCE_PREFETCH); |
| 481 | pci_addr = of_read_number(r, 2); |
| 482 | hose->mem_offset[1] = res->start - pci_addr; |
| 483 | |
| 484 | phb->ioda.m64_size = resource_size(res); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 485 | phb->ioda.m64_segsize = phb->ioda.m64_size / phb->ioda.total_pe_num; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 486 | phb->ioda.m64_base = pci_addr; |
| 487 | |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 488 | /* This lines up nicely with the display from processing OF ranges */ |
| 489 | pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx (M64 #%d..%d)\n", |
| 490 | res->start, res->end, pci_addr, m64_range[0], |
| 491 | m64_range[0] + m64_range[1] - 1); |
| 492 | |
| 493 | /* Mark all M64 used up by default */ |
| 494 | phb->ioda.m64_bar_alloc = (unsigned long)-1; |
Wei Yang | e9863e6 | 2014-12-12 12:39:37 +0800 | [diff] [blame] | 495 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 496 | /* Use last M64 BAR to cover M64 window */ |
Benjamin Herrenschmidt | a1339fa | 2016-07-08 16:37:16 +1000 | [diff] [blame] | 497 | m64_range[1]--; |
| 498 | phb->ioda.m64_bar_idx = m64_range[0] + m64_range[1]; |
| 499 | |
| 500 | pr_info(" Using M64 #%d as default window\n", phb->ioda.m64_bar_idx); |
| 501 | |
| 502 | /* Mark remaining ones free */ |
| 503 | for (i = m64_range[0]; i < m64_range[1]; i++) |
| 504 | clear_bit(i, &phb->ioda.m64_bar_alloc); |
| 505 | |
| 506 | /* |
| 507 | * Setup init functions for M64 based on IODA version, IODA3 uses |
| 508 | * the IODA2 code. |
| 509 | */ |
Gavin Shan | 9945155 | 2016-05-05 12:02:13 +1000 | [diff] [blame] | 510 | if (phb->type == PNV_PHB_IODA1) |
| 511 | phb->init_m64 = pnv_ioda1_init_m64; |
| 512 | else |
| 513 | phb->init_m64 = pnv_ioda2_init_m64; |
Gavin Shan | c430670 | 2016-05-03 15:41:30 +1000 | [diff] [blame] | 514 | phb->reserve_m64_pe = pnv_ioda_reserve_m64_pe; |
| 515 | phb->pick_m64_pe = pnv_ioda_pick_m64_pe; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 516 | } |
| 517 | |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 518 | static void pnv_ioda_freeze_pe(struct pnv_phb *phb, int pe_no) |
| 519 | { |
| 520 | struct pnv_ioda_pe *pe = &phb->ioda.pe_array[pe_no]; |
| 521 | struct pnv_ioda_pe *slave; |
| 522 | s64 rc; |
| 523 | |
| 524 | /* Fetch master PE */ |
| 525 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 526 | pe = pe->master; |
Gavin Shan | ec8e4e9 | 2014-11-12 13:36:10 +1100 | [diff] [blame] | 527 | if (WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER))) |
| 528 | return; |
| 529 | |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 530 | pe_no = pe->pe_number; |
| 531 | } |
| 532 | |
| 533 | /* Freeze master PE */ |
| 534 | rc = opal_pci_eeh_freeze_set(phb->opal_id, |
| 535 | pe_no, |
| 536 | OPAL_EEH_ACTION_SET_FREEZE_ALL); |
| 537 | if (rc != OPAL_SUCCESS) { |
| 538 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", |
| 539 | __func__, rc, phb->hose->global_number, pe_no); |
| 540 | return; |
| 541 | } |
| 542 | |
| 543 | /* Freeze slave PEs */ |
| 544 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 545 | return; |
| 546 | |
| 547 | list_for_each_entry(slave, &pe->slaves, list) { |
| 548 | rc = opal_pci_eeh_freeze_set(phb->opal_id, |
| 549 | slave->pe_number, |
| 550 | OPAL_EEH_ACTION_SET_FREEZE_ALL); |
| 551 | if (rc != OPAL_SUCCESS) |
| 552 | pr_warn("%s: Failure %lld freezing PHB#%x-PE#%x\n", |
| 553 | __func__, rc, phb->hose->global_number, |
| 554 | slave->pe_number); |
| 555 | } |
| 556 | } |
| 557 | |
Anton Blanchard | e51df2c | 2014-08-20 08:55:18 +1000 | [diff] [blame] | 558 | static int pnv_ioda_unfreeze_pe(struct pnv_phb *phb, int pe_no, int opt) |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 559 | { |
| 560 | struct pnv_ioda_pe *pe, *slave; |
| 561 | s64 rc; |
| 562 | |
| 563 | /* Find master PE */ |
| 564 | pe = &phb->ioda.pe_array[pe_no]; |
| 565 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 566 | pe = pe->master; |
| 567 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); |
| 568 | pe_no = pe->pe_number; |
| 569 | } |
| 570 | |
| 571 | /* Clear frozen state for master PE */ |
| 572 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no, opt); |
| 573 | if (rc != OPAL_SUCCESS) { |
| 574 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", |
| 575 | __func__, rc, opt, phb->hose->global_number, pe_no); |
| 576 | return -EIO; |
| 577 | } |
| 578 | |
| 579 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 580 | return 0; |
| 581 | |
| 582 | /* Clear frozen state for slave PEs */ |
| 583 | list_for_each_entry(slave, &pe->slaves, list) { |
| 584 | rc = opal_pci_eeh_freeze_clear(phb->opal_id, |
| 585 | slave->pe_number, |
| 586 | opt); |
| 587 | if (rc != OPAL_SUCCESS) { |
| 588 | pr_warn("%s: Failure %lld clear %d on PHB#%x-PE#%x\n", |
| 589 | __func__, rc, opt, phb->hose->global_number, |
| 590 | slave->pe_number); |
| 591 | return -EIO; |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no) |
| 599 | { |
| 600 | struct pnv_ioda_pe *slave, *pe; |
Alexey Kardashevskiy | a355ad5 | 2018-11-19 15:25:17 +1100 | [diff] [blame] | 601 | u8 fstate = 0, state; |
| 602 | __be16 pcierr = 0; |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 603 | s64 rc; |
| 604 | |
| 605 | /* Sanity check on PE number */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 606 | if (pe_no < 0 || pe_no >= phb->ioda.total_pe_num) |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 607 | return OPAL_EEH_STOPPED_PERM_UNAVAIL; |
| 608 | |
| 609 | /* |
| 610 | * Fetch the master PE and the PE instance might be |
| 611 | * not initialized yet. |
| 612 | */ |
| 613 | pe = &phb->ioda.pe_array[pe_no]; |
| 614 | if (pe->flags & PNV_IODA_PE_SLAVE) { |
| 615 | pe = pe->master; |
| 616 | WARN_ON(!pe || !(pe->flags & PNV_IODA_PE_MASTER)); |
| 617 | pe_no = pe->pe_number; |
| 618 | } |
| 619 | |
| 620 | /* Check the master PE */ |
| 621 | rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, |
| 622 | &state, &pcierr, NULL); |
| 623 | if (rc != OPAL_SUCCESS) { |
| 624 | pr_warn("%s: Failure %lld getting " |
| 625 | "PHB#%x-PE#%x state\n", |
| 626 | __func__, rc, |
| 627 | phb->hose->global_number, pe_no); |
| 628 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; |
| 629 | } |
| 630 | |
| 631 | /* Check the slave PE */ |
| 632 | if (!(pe->flags & PNV_IODA_PE_MASTER)) |
| 633 | return state; |
| 634 | |
| 635 | list_for_each_entry(slave, &pe->slaves, list) { |
| 636 | rc = opal_pci_eeh_freeze_status(phb->opal_id, |
| 637 | slave->pe_number, |
| 638 | &fstate, |
| 639 | &pcierr, |
| 640 | NULL); |
| 641 | if (rc != OPAL_SUCCESS) { |
| 642 | pr_warn("%s: Failure %lld getting " |
| 643 | "PHB#%x-PE#%x state\n", |
| 644 | __func__, rc, |
| 645 | phb->hose->global_number, slave->pe_number); |
| 646 | return OPAL_EEH_STOPPED_TEMP_UNAVAIL; |
| 647 | } |
| 648 | |
| 649 | /* |
| 650 | * Override the result based on the ascending |
| 651 | * priority. |
| 652 | */ |
| 653 | if (fstate > state) |
| 654 | state = fstate; |
| 655 | } |
| 656 | |
| 657 | return state; |
| 658 | } |
| 659 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 660 | /* Currently those 2 are only used when MSIs are enabled, this will change |
| 661 | * but in the meantime, we need to protect them to avoid warnings |
| 662 | */ |
| 663 | #ifdef CONFIG_PCI_MSI |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 664 | struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 665 | { |
| 666 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 667 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 668 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 669 | |
| 670 | if (!pdn) |
| 671 | return NULL; |
| 672 | if (pdn->pe_number == IODA_INVALID_PE) |
| 673 | return NULL; |
| 674 | return &phb->ioda.pe_array[pdn->pe_number]; |
| 675 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 676 | #endif /* CONFIG_PCI_MSI */ |
| 677 | |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 678 | static int pnv_ioda_set_one_peltv(struct pnv_phb *phb, |
| 679 | struct pnv_ioda_pe *parent, |
| 680 | struct pnv_ioda_pe *child, |
| 681 | bool is_add) |
| 682 | { |
| 683 | const char *desc = is_add ? "adding" : "removing"; |
| 684 | uint8_t op = is_add ? OPAL_ADD_PE_TO_DOMAIN : |
| 685 | OPAL_REMOVE_PE_FROM_DOMAIN; |
| 686 | struct pnv_ioda_pe *slave; |
| 687 | long rc; |
| 688 | |
| 689 | /* Parent PE affects child PE */ |
| 690 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, |
| 691 | child->pe_number, op); |
| 692 | if (rc != OPAL_SUCCESS) { |
| 693 | pe_warn(child, "OPAL error %ld %s to parent PELTV\n", |
| 694 | rc, desc); |
| 695 | return -ENXIO; |
| 696 | } |
| 697 | |
| 698 | if (!(child->flags & PNV_IODA_PE_MASTER)) |
| 699 | return 0; |
| 700 | |
| 701 | /* Compound case: parent PE affects slave PEs */ |
| 702 | list_for_each_entry(slave, &child->slaves, list) { |
| 703 | rc = opal_pci_set_peltv(phb->opal_id, parent->pe_number, |
| 704 | slave->pe_number, op); |
| 705 | if (rc != OPAL_SUCCESS) { |
| 706 | pe_warn(slave, "OPAL error %ld %s to parent PELTV\n", |
| 707 | rc, desc); |
| 708 | return -ENXIO; |
| 709 | } |
| 710 | } |
| 711 | |
| 712 | return 0; |
| 713 | } |
| 714 | |
| 715 | static int pnv_ioda_set_peltv(struct pnv_phb *phb, |
| 716 | struct pnv_ioda_pe *pe, |
| 717 | bool is_add) |
| 718 | { |
| 719 | struct pnv_ioda_pe *slave; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 720 | struct pci_dev *pdev = NULL; |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 721 | int ret; |
| 722 | |
| 723 | /* |
| 724 | * Clear PE frozen state. If it's master PE, we need |
| 725 | * clear slave PE frozen state as well. |
| 726 | */ |
| 727 | if (is_add) { |
| 728 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
| 729 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 730 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 731 | list_for_each_entry(slave, &pe->slaves, list) |
| 732 | opal_pci_eeh_freeze_clear(phb->opal_id, |
| 733 | slave->pe_number, |
| 734 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 735 | } |
| 736 | } |
| 737 | |
| 738 | /* |
| 739 | * Associate PE in PELT. We need add the PE into the |
| 740 | * corresponding PELT-V as well. Otherwise, the error |
| 741 | * originated from the PE might contribute to other |
| 742 | * PEs. |
| 743 | */ |
| 744 | ret = pnv_ioda_set_one_peltv(phb, pe, pe, is_add); |
| 745 | if (ret) |
| 746 | return ret; |
| 747 | |
| 748 | /* For compound PEs, any one affects all of them */ |
| 749 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 750 | list_for_each_entry(slave, &pe->slaves, list) { |
| 751 | ret = pnv_ioda_set_one_peltv(phb, slave, pe, is_add); |
| 752 | if (ret) |
| 753 | return ret; |
| 754 | } |
| 755 | } |
| 756 | |
| 757 | if (pe->flags & (PNV_IODA_PE_BUS_ALL | PNV_IODA_PE_BUS)) |
| 758 | pdev = pe->pbus->self; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 759 | else if (pe->flags & PNV_IODA_PE_DEV) |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 760 | pdev = pe->pdev->bus->self; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 761 | #ifdef CONFIG_PCI_IOV |
| 762 | else if (pe->flags & PNV_IODA_PE_VF) |
Gavin Shan | 283e2d8 | 2015-06-22 13:45:47 +1000 | [diff] [blame] | 763 | pdev = pe->parent_dev; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 764 | #endif /* CONFIG_PCI_IOV */ |
Gavin Shan | b131a84 | 2014-11-12 13:36:08 +1100 | [diff] [blame] | 765 | while (pdev) { |
| 766 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 767 | struct pnv_ioda_pe *parent; |
| 768 | |
| 769 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
| 770 | parent = &phb->ioda.pe_array[pdn->pe_number]; |
| 771 | ret = pnv_ioda_set_one_peltv(phb, parent, pe, is_add); |
| 772 | if (ret) |
| 773 | return ret; |
| 774 | } |
| 775 | |
| 776 | pdev = pdev->bus->self; |
| 777 | } |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 782 | static int pnv_ioda_deconfigure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
| 783 | { |
| 784 | struct pci_dev *parent; |
| 785 | uint8_t bcomp, dcomp, fcomp; |
| 786 | int64_t rc; |
| 787 | long rid_end, rid; |
| 788 | |
| 789 | /* Currently, we just deconfigure VF PE. Bus PE will always there.*/ |
| 790 | if (pe->pbus) { |
| 791 | int count; |
| 792 | |
| 793 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; |
| 794 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; |
| 795 | parent = pe->pbus->self; |
| 796 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
| 797 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; |
| 798 | else |
| 799 | count = 1; |
| 800 | |
| 801 | switch(count) { |
| 802 | case 1: bcomp = OpalPciBusAll; break; |
| 803 | case 2: bcomp = OpalPciBus7Bits; break; |
| 804 | case 4: bcomp = OpalPciBus6Bits; break; |
| 805 | case 8: bcomp = OpalPciBus5Bits; break; |
| 806 | case 16: bcomp = OpalPciBus4Bits; break; |
| 807 | case 32: bcomp = OpalPciBus3Bits; break; |
| 808 | default: |
| 809 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
| 810 | count); |
| 811 | /* Do an exact match only */ |
| 812 | bcomp = OpalPciBusAll; |
| 813 | } |
| 814 | rid_end = pe->rid + (count << 8); |
| 815 | } else { |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 816 | #ifdef CONFIG_PCI_IOV |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 817 | if (pe->flags & PNV_IODA_PE_VF) |
| 818 | parent = pe->parent_dev; |
| 819 | else |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 820 | #endif |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 821 | parent = pe->pdev->bus->self; |
| 822 | bcomp = OpalPciBusAll; |
| 823 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; |
| 824 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; |
| 825 | rid_end = pe->rid + 1; |
| 826 | } |
| 827 | |
| 828 | /* Clear the reverse map */ |
| 829 | for (rid = pe->rid; rid < rid_end; rid++) |
Gavin Shan | c127562 | 2016-05-20 16:41:29 +1000 | [diff] [blame] | 830 | phb->ioda.pe_rmap[rid] = IODA_INVALID_PE; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 831 | |
| 832 | /* Release from all parents PELT-V */ |
| 833 | while (parent) { |
| 834 | struct pci_dn *pdn = pci_get_pdn(parent); |
| 835 | if (pdn && pdn->pe_number != IODA_INVALID_PE) { |
| 836 | rc = opal_pci_set_peltv(phb->opal_id, pdn->pe_number, |
| 837 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); |
| 838 | /* XXX What to do in case of error ? */ |
| 839 | } |
| 840 | parent = parent->bus->self; |
| 841 | } |
| 842 | |
Gavin Shan | f951e51 | 2015-06-23 17:01:13 +1000 | [diff] [blame] | 843 | opal_pci_eeh_freeze_clear(phb->opal_id, pe->pe_number, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 844 | OPAL_EEH_ACTION_CLEAR_FREEZE_ALL); |
| 845 | |
| 846 | /* Disassociate PE in PELT */ |
| 847 | rc = opal_pci_set_peltv(phb->opal_id, pe->pe_number, |
| 848 | pe->pe_number, OPAL_REMOVE_PE_FROM_DOMAIN); |
| 849 | if (rc) |
| 850 | pe_warn(pe, "OPAL error %ld remove self from PELTV\n", rc); |
| 851 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
| 852 | bcomp, dcomp, fcomp, OPAL_UNMAP_PE); |
| 853 | if (rc) |
| 854 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); |
| 855 | |
| 856 | pe->pbus = NULL; |
| 857 | pe->pdev = NULL; |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 858 | #ifdef CONFIG_PCI_IOV |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 859 | pe->parent_dev = NULL; |
Gavin Shan | 93e01a5 | 2016-05-20 16:41:34 +1000 | [diff] [blame] | 860 | #endif |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 861 | |
| 862 | return 0; |
| 863 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 864 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 865 | static int pnv_ioda_configure_pe(struct pnv_phb *phb, struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 866 | { |
| 867 | struct pci_dev *parent; |
| 868 | uint8_t bcomp, dcomp, fcomp; |
| 869 | long rc, rid_end, rid; |
| 870 | |
| 871 | /* Bus validation ? */ |
| 872 | if (pe->pbus) { |
| 873 | int count; |
| 874 | |
| 875 | dcomp = OPAL_IGNORE_RID_DEVICE_NUMBER; |
| 876 | fcomp = OPAL_IGNORE_RID_FUNCTION_NUMBER; |
| 877 | parent = pe->pbus->self; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 878 | if (pe->flags & PNV_IODA_PE_BUS_ALL) |
| 879 | count = pe->pbus->busn_res.end - pe->pbus->busn_res.start + 1; |
| 880 | else |
| 881 | count = 1; |
| 882 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 883 | switch(count) { |
| 884 | case 1: bcomp = OpalPciBusAll; break; |
| 885 | case 2: bcomp = OpalPciBus7Bits; break; |
| 886 | case 4: bcomp = OpalPciBus6Bits; break; |
| 887 | case 8: bcomp = OpalPciBus5Bits; break; |
| 888 | case 16: bcomp = OpalPciBus4Bits; break; |
| 889 | case 32: bcomp = OpalPciBus3Bits; break; |
| 890 | default: |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 891 | dev_err(&pe->pbus->dev, "Number of subordinate buses %d unsupported\n", |
| 892 | count); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 893 | /* Do an exact match only */ |
| 894 | bcomp = OpalPciBusAll; |
| 895 | } |
| 896 | rid_end = pe->rid + (count << 8); |
| 897 | } else { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 898 | #ifdef CONFIG_PCI_IOV |
| 899 | if (pe->flags & PNV_IODA_PE_VF) |
| 900 | parent = pe->parent_dev; |
| 901 | else |
| 902 | #endif /* CONFIG_PCI_IOV */ |
| 903 | parent = pe->pdev->bus->self; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 904 | bcomp = OpalPciBusAll; |
| 905 | dcomp = OPAL_COMPARE_RID_DEVICE_NUMBER; |
| 906 | fcomp = OPAL_COMPARE_RID_FUNCTION_NUMBER; |
| 907 | rid_end = pe->rid + 1; |
| 908 | } |
| 909 | |
Gavin Shan | 631ad69 | 2013-11-04 16:32:46 +0800 | [diff] [blame] | 910 | /* |
| 911 | * Associate PE in PELT. We need add the PE into the |
| 912 | * corresponding PELT-V as well. Otherwise, the error |
| 913 | * originated from the PE might contribute to other |
| 914 | * PEs. |
| 915 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 916 | rc = opal_pci_set_pe(phb->opal_id, pe->pe_number, pe->rid, |
| 917 | bcomp, dcomp, fcomp, OPAL_MAP_PE); |
| 918 | if (rc) { |
| 919 | pe_err(pe, "OPAL error %ld trying to setup PELT table\n", rc); |
| 920 | return -ENXIO; |
| 921 | } |
Gavin Shan | 631ad69 | 2013-11-04 16:32:46 +0800 | [diff] [blame] | 922 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 923 | /* |
| 924 | * Configure PELTV. NPUs don't have a PELTV table so skip |
| 925 | * configuration on them. |
| 926 | */ |
| 927 | if (phb->type != PNV_PHB_NPU) |
| 928 | pnv_ioda_set_peltv(phb, pe, true); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 929 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 930 | /* Setup reverse map */ |
| 931 | for (rid = pe->rid; rid < rid_end; rid++) |
| 932 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
| 933 | |
| 934 | /* Setup one MVTs on IODA1 */ |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 935 | if (phb->type != PNV_PHB_IODA1) { |
| 936 | pe->mve_number = 0; |
| 937 | goto out; |
| 938 | } |
| 939 | |
| 940 | pe->mve_number = pe->pe_number; |
| 941 | rc = opal_pci_set_mve(phb->opal_id, pe->mve_number, pe->pe_number); |
| 942 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 943 | pe_err(pe, "OPAL error %ld setting up MVE %x\n", |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 944 | rc, pe->mve_number); |
| 945 | pe->mve_number = -1; |
| 946 | } else { |
| 947 | rc = opal_pci_set_mve_enable(phb->opal_id, |
| 948 | pe->mve_number, OPAL_ENABLE_MVE); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 949 | if (rc) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 950 | pe_err(pe, "OPAL error %ld enabling MVE %x\n", |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 951 | rc, pe->mve_number); |
| 952 | pe->mve_number = -1; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 953 | } |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 954 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 955 | |
Gavin Shan | 4773f76 | 2014-11-12 13:36:09 +1100 | [diff] [blame] | 956 | out: |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 957 | return 0; |
| 958 | } |
| 959 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 960 | #ifdef CONFIG_PCI_IOV |
| 961 | static int pnv_pci_vf_resource_shift(struct pci_dev *dev, int offset) |
| 962 | { |
| 963 | struct pci_dn *pdn = pci_get_pdn(dev); |
| 964 | int i; |
| 965 | struct resource *res, res2; |
| 966 | resource_size_t size; |
| 967 | u16 num_vfs; |
| 968 | |
| 969 | if (!dev->is_physfn) |
| 970 | return -EINVAL; |
| 971 | |
| 972 | /* |
| 973 | * "offset" is in VFs. The M64 windows are sized so that when they |
| 974 | * are segmented, each segment is the same size as the IOV BAR. |
| 975 | * Each segment is in a separate PE, and the high order bits of the |
| 976 | * address are the PE number. Therefore, each VF's BAR is in a |
| 977 | * separate PE, and changing the IOV BAR start address changes the |
| 978 | * range of PEs the VFs are in. |
| 979 | */ |
| 980 | num_vfs = pdn->num_vfs; |
| 981 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 982 | res = &dev->resource[i + PCI_IOV_RESOURCES]; |
| 983 | if (!res->flags || !res->parent) |
| 984 | continue; |
| 985 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 986 | /* |
| 987 | * The actual IOV BAR range is determined by the start address |
| 988 | * and the actual size for num_vfs VFs BAR. This check is to |
| 989 | * make sure that after shifting, the range will not overlap |
| 990 | * with another device. |
| 991 | */ |
| 992 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
| 993 | res2.flags = res->flags; |
| 994 | res2.start = res->start + (size * offset); |
| 995 | res2.end = res2.start + (size * num_vfs) - 1; |
| 996 | |
| 997 | if (res2.end > res->end) { |
| 998 | dev_err(&dev->dev, "VF BAR%d: %pR would extend past %pR (trying to enable %d VFs shifted by %d)\n", |
| 999 | i, &res2, res, num_vfs, offset); |
| 1000 | return -EBUSY; |
| 1001 | } |
| 1002 | } |
| 1003 | |
| 1004 | /* |
| 1005 | * After doing so, there would be a "hole" in the /proc/iomem when |
| 1006 | * offset is a positive value. It looks like the device return some |
| 1007 | * mmio back to the system, which actually no one could use it. |
| 1008 | */ |
| 1009 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 1010 | res = &dev->resource[i + PCI_IOV_RESOURCES]; |
| 1011 | if (!res->flags || !res->parent) |
| 1012 | continue; |
| 1013 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1014 | size = pci_iov_resource_size(dev, i + PCI_IOV_RESOURCES); |
| 1015 | res2 = *res; |
| 1016 | res->start += size * offset; |
| 1017 | |
Wei Yang | 74703cc | 2015-07-20 18:14:58 +0800 | [diff] [blame] | 1018 | dev_info(&dev->dev, "VF BAR%d: %pR shifted to %pR (%sabling %d VFs shifted by %d)\n", |
| 1019 | i, &res2, res, (offset > 0) ? "En" : "Dis", |
| 1020 | num_vfs, offset); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1021 | pci_update_resource(dev, i + PCI_IOV_RESOURCES); |
| 1022 | } |
| 1023 | return 0; |
| 1024 | } |
| 1025 | #endif /* CONFIG_PCI_IOV */ |
| 1026 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 1027 | static struct pnv_ioda_pe *pnv_ioda_setup_dev_PE(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1028 | { |
| 1029 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 1030 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1031 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1032 | struct pnv_ioda_pe *pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1033 | |
| 1034 | if (!pdn) { |
| 1035 | pr_err("%s: Device tree node not associated properly\n", |
| 1036 | pci_name(dev)); |
| 1037 | return NULL; |
| 1038 | } |
| 1039 | if (pdn->pe_number != IODA_INVALID_PE) |
| 1040 | return NULL; |
| 1041 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1042 | pe = pnv_ioda_alloc_pe(phb); |
| 1043 | if (!pe) { |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1044 | pr_warning("%s: Not enough PE# available, disabling device\n", |
| 1045 | pci_name(dev)); |
| 1046 | return NULL; |
| 1047 | } |
| 1048 | |
| 1049 | /* NOTE: We get only one ref to the pci_dev for the pdn, not for the |
| 1050 | * pointer in the PE data structure, both should be destroyed at the |
| 1051 | * same time. However, this needs to be looked at more closely again |
| 1052 | * once we actually start removing things (Hotplug, SR-IOV, ...) |
| 1053 | * |
| 1054 | * At some point we want to remove the PDN completely anyways |
| 1055 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1056 | pci_dev_get(dev); |
| 1057 | pdn->pcidev = dev; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1058 | pdn->pe_number = pe->pe_number; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1059 | pe->flags = PNV_IODA_PE_DEV; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1060 | pe->pdev = dev; |
| 1061 | pe->pbus = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1062 | pe->mve_number = -1; |
| 1063 | pe->rid = dev->bus->number << 8 | pdn->devfn; |
| 1064 | |
| 1065 | pe_info(pe, "Associated device to PE\n"); |
| 1066 | |
| 1067 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1068 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1069 | pnv_ioda_free_pe(pe); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1070 | pdn->pe_number = IODA_INVALID_PE; |
| 1071 | pe->pdev = NULL; |
| 1072 | pci_dev_put(dev); |
| 1073 | return NULL; |
| 1074 | } |
| 1075 | |
Alexey Kardashevskiy | 1d4e89c | 2016-05-12 15:47:10 +1000 | [diff] [blame] | 1076 | /* Put PE to the list */ |
| 1077 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
| 1078 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1079 | return pe; |
| 1080 | } |
| 1081 | |
| 1082 | static void pnv_ioda_setup_same_PE(struct pci_bus *bus, struct pnv_ioda_pe *pe) |
| 1083 | { |
| 1084 | struct pci_dev *dev; |
| 1085 | |
| 1086 | list_for_each_entry(dev, &bus->devices, bus_list) { |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1087 | struct pci_dn *pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1088 | |
| 1089 | if (pdn == NULL) { |
| 1090 | pr_warn("%s: No device node associated with device !\n", |
| 1091 | pci_name(dev)); |
| 1092 | continue; |
| 1093 | } |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1094 | |
| 1095 | /* |
| 1096 | * In partial hotplug case, the PCI device might be still |
| 1097 | * associated with the PE and needn't attach it to the PE |
| 1098 | * again. |
| 1099 | */ |
| 1100 | if (pdn->pe_number != IODA_INVALID_PE) |
| 1101 | continue; |
| 1102 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 1103 | pe->device_count++; |
Alistair Popple | 94973b2 | 2015-12-17 13:43:11 +1100 | [diff] [blame] | 1104 | pdn->pcidev = dev; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1105 | pdn->pe_number = pe->pe_number; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1106 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1107 | pnv_ioda_setup_same_PE(dev->subordinate, pe); |
| 1108 | } |
| 1109 | } |
| 1110 | |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1111 | /* |
| 1112 | * There're 2 types of PCI bus sensitive PEs: One that is compromised of |
| 1113 | * single PCI bus. Another one that contains the primary PCI bus and its |
| 1114 | * subordinate PCI devices and buses. The second type of PE is normally |
| 1115 | * orgiriated by PCIe-to-PCI bridge or PLX switch downstream ports. |
| 1116 | */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1117 | static struct pnv_ioda_pe *pnv_ioda_setup_bus_PE(struct pci_bus *bus, bool all) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1118 | { |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1119 | struct pci_controller *hose = pci_bus_to_host(bus); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1120 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1121 | struct pnv_ioda_pe *pe = NULL; |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1122 | unsigned int pe_num; |
| 1123 | |
| 1124 | /* |
| 1125 | * In partial hotplug case, the PE instance might be still alive. |
| 1126 | * We should reuse it instead of allocating a new one. |
| 1127 | */ |
| 1128 | pe_num = phb->ioda.pe_rmap[bus->number << 8]; |
| 1129 | if (pe_num != IODA_INVALID_PE) { |
| 1130 | pe = &phb->ioda.pe_array[pe_num]; |
| 1131 | pnv_ioda_setup_same_PE(bus, pe); |
| 1132 | return NULL; |
| 1133 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1134 | |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 1135 | /* PE number for root bus should have been reserved */ |
| 1136 | if (pci_is_root_bus(bus) && |
| 1137 | phb->ioda.root_pe_idx != IODA_INVALID_PE) |
| 1138 | pe = &phb->ioda.pe_array[phb->ioda.root_pe_idx]; |
| 1139 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1140 | /* Check if PE is determined by M64 */ |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 1141 | if (!pe && phb->pick_m64_pe) |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1142 | pe = phb->pick_m64_pe(bus, all); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1143 | |
| 1144 | /* The PE number isn't pinned by M64 */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1145 | if (!pe) |
| 1146 | pe = pnv_ioda_alloc_pe(phb); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1147 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1148 | if (!pe) { |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1149 | pr_warning("%s: Not enough PE# available for PCI bus %04x:%02x\n", |
| 1150 | __func__, pci_domain_nr(bus), bus->number); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1151 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1152 | } |
| 1153 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1154 | pe->flags |= (all ? PNV_IODA_PE_BUS_ALL : PNV_IODA_PE_BUS); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1155 | pe->pbus = bus; |
| 1156 | pe->pdev = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1157 | pe->mve_number = -1; |
Yinghai Lu | b918c62 | 2012-05-17 18:51:11 -0700 | [diff] [blame] | 1158 | pe->rid = bus->busn_res.start << 8; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1159 | |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1160 | if (all) |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1161 | pe_info(pe, "Secondary bus %d..%d associated with PE#%x\n", |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1162 | bus->busn_res.start, bus->busn_res.end, pe->pe_number); |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1163 | else |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1164 | pe_info(pe, "Secondary bus %d associated with PE#%x\n", |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1165 | bus->busn_res.start, pe->pe_number); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1166 | |
| 1167 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1168 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1169 | pnv_ioda_free_pe(pe); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1170 | pe->pbus = NULL; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1171 | return NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1172 | } |
| 1173 | |
| 1174 | /* Associate it with all child devices */ |
| 1175 | pnv_ioda_setup_same_PE(bus, pe); |
| 1176 | |
Gavin Shan | 7ebdf95 | 2012-08-20 03:49:15 +0000 | [diff] [blame] | 1177 | /* Put PE to the list */ |
| 1178 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1179 | |
| 1180 | return pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1181 | } |
| 1182 | |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1183 | static struct pnv_ioda_pe *pnv_ioda_setup_npu_PE(struct pci_dev *npu_pdev) |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1184 | { |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1185 | int pe_num, found_pe = false, rc; |
| 1186 | long rid; |
| 1187 | struct pnv_ioda_pe *pe; |
| 1188 | struct pci_dev *gpu_pdev; |
| 1189 | struct pci_dn *npu_pdn; |
| 1190 | struct pci_controller *hose = pci_bus_to_host(npu_pdev->bus); |
| 1191 | struct pnv_phb *phb = hose->private_data; |
| 1192 | |
| 1193 | /* |
| 1194 | * Due to a hardware errata PE#0 on the NPU is reserved for |
| 1195 | * error handling. This means we only have three PEs remaining |
| 1196 | * which need to be assigned to four links, implying some |
| 1197 | * links must share PEs. |
| 1198 | * |
| 1199 | * To achieve this we assign PEs such that NPUs linking the |
| 1200 | * same GPU get assigned the same PE. |
| 1201 | */ |
| 1202 | gpu_pdev = pnv_pci_get_gpu_dev(npu_pdev); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1203 | for (pe_num = 0; pe_num < phb->ioda.total_pe_num; pe_num++) { |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1204 | pe = &phb->ioda.pe_array[pe_num]; |
| 1205 | if (!pe->pdev) |
| 1206 | continue; |
| 1207 | |
| 1208 | if (pnv_pci_get_gpu_dev(pe->pdev) == gpu_pdev) { |
| 1209 | /* |
| 1210 | * This device has the same peer GPU so should |
| 1211 | * be assigned the same PE as the existing |
| 1212 | * peer NPU. |
| 1213 | */ |
| 1214 | dev_info(&npu_pdev->dev, |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1215 | "Associating to existing PE %x\n", pe_num); |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1216 | pci_dev_get(npu_pdev); |
| 1217 | npu_pdn = pci_get_pdn(npu_pdev); |
| 1218 | rid = npu_pdev->bus->number << 8 | npu_pdn->devfn; |
| 1219 | npu_pdn->pcidev = npu_pdev; |
| 1220 | npu_pdn->pe_number = pe_num; |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1221 | phb->ioda.pe_rmap[rid] = pe->pe_number; |
| 1222 | |
| 1223 | /* Map the PE to this link */ |
| 1224 | rc = opal_pci_set_pe(phb->opal_id, pe_num, rid, |
| 1225 | OpalPciBusAll, |
| 1226 | OPAL_COMPARE_RID_DEVICE_NUMBER, |
| 1227 | OPAL_COMPARE_RID_FUNCTION_NUMBER, |
| 1228 | OPAL_MAP_PE); |
| 1229 | WARN_ON(rc != OPAL_SUCCESS); |
| 1230 | found_pe = true; |
| 1231 | break; |
| 1232 | } |
| 1233 | } |
| 1234 | |
| 1235 | if (!found_pe) |
| 1236 | /* |
| 1237 | * Could not find an existing PE so allocate a new |
| 1238 | * one. |
| 1239 | */ |
| 1240 | return pnv_ioda_setup_dev_PE(npu_pdev); |
| 1241 | else |
| 1242 | return pe; |
| 1243 | } |
| 1244 | |
| 1245 | static void pnv_ioda_setup_npu_PEs(struct pci_bus *bus) |
| 1246 | { |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1247 | struct pci_dev *pdev; |
| 1248 | |
| 1249 | list_for_each_entry(pdev, &bus->devices, bus_list) |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1250 | pnv_ioda_setup_npu_PE(pdev); |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1251 | } |
| 1252 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 1253 | static void pnv_pci_ioda_setup_PEs(void) |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1254 | { |
| 1255 | struct pci_controller *hose, *tmp; |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1256 | struct pnv_phb *phb; |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 1257 | |
| 1258 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 1259 | phb = hose->private_data; |
Alistair Popple | 08f48f3 | 2016-01-11 16:53:50 +1100 | [diff] [blame] | 1260 | if (phb->type == PNV_PHB_NPU) { |
| 1261 | /* PE#0 is needed for error reporting */ |
| 1262 | pnv_ioda_reserve_pe(phb, 0); |
Alistair Popple | b521549 | 2016-01-11 16:53:49 +1100 | [diff] [blame] | 1263 | pnv_ioda_setup_npu_PEs(hose->bus); |
Alistair Popple | 1ab66d1 | 2017-04-03 19:51:44 +1000 | [diff] [blame] | 1264 | if (phb->model == PNV_PHB_MODEL_NPU2) |
| 1265 | pnv_npu2_init(phb); |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 1266 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1267 | } |
| 1268 | } |
| 1269 | |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1270 | #ifdef CONFIG_PCI_IOV |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1271 | static int pnv_pci_vf_release_m64(struct pci_dev *pdev, u16 num_vfs) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1272 | { |
| 1273 | struct pci_bus *bus; |
| 1274 | struct pci_controller *hose; |
| 1275 | struct pnv_phb *phb; |
| 1276 | struct pci_dn *pdn; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1277 | int i, j; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1278 | int m64_bars; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1279 | |
| 1280 | bus = pdev->bus; |
| 1281 | hose = pci_bus_to_host(bus); |
| 1282 | phb = hose->private_data; |
| 1283 | pdn = pci_get_pdn(pdev); |
| 1284 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1285 | if (pdn->m64_single_mode) |
| 1286 | m64_bars = num_vfs; |
| 1287 | else |
| 1288 | m64_bars = 1; |
| 1289 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1290 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1291 | for (j = 0; j < m64_bars; j++) { |
| 1292 | if (pdn->m64_map[j][i] == IODA_INVALID_M64) |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1293 | continue; |
| 1294 | opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1295 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 0); |
| 1296 | clear_bit(pdn->m64_map[j][i], &phb->ioda.m64_bar_alloc); |
| 1297 | pdn->m64_map[j][i] = IODA_INVALID_M64; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1298 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1299 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1300 | kfree(pdn->m64_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1301 | return 0; |
| 1302 | } |
| 1303 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1304 | static int pnv_pci_vf_assign_m64(struct pci_dev *pdev, u16 num_vfs) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1305 | { |
| 1306 | struct pci_bus *bus; |
| 1307 | struct pci_controller *hose; |
| 1308 | struct pnv_phb *phb; |
| 1309 | struct pci_dn *pdn; |
| 1310 | unsigned int win; |
| 1311 | struct resource *res; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1312 | int i, j; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1313 | int64_t rc; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1314 | int total_vfs; |
| 1315 | resource_size_t size, start; |
| 1316 | int pe_num; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1317 | int m64_bars; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1318 | |
| 1319 | bus = pdev->bus; |
| 1320 | hose = pci_bus_to_host(bus); |
| 1321 | phb = hose->private_data; |
| 1322 | pdn = pci_get_pdn(pdev); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1323 | total_vfs = pci_sriov_get_totalvfs(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1324 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1325 | if (pdn->m64_single_mode) |
| 1326 | m64_bars = num_vfs; |
| 1327 | else |
| 1328 | m64_bars = 1; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1329 | |
Markus Elfring | fb37e12 | 2016-08-24 22:26:37 +0200 | [diff] [blame] | 1330 | pdn->m64_map = kmalloc_array(m64_bars, |
| 1331 | sizeof(*pdn->m64_map), |
| 1332 | GFP_KERNEL); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1333 | if (!pdn->m64_map) |
| 1334 | return -ENOMEM; |
| 1335 | /* Initialize the m64_map to IODA_INVALID_M64 */ |
| 1336 | for (i = 0; i < m64_bars ; i++) |
| 1337 | for (j = 0; j < PCI_SRIOV_NUM_BARS; j++) |
| 1338 | pdn->m64_map[i][j] = IODA_INVALID_M64; |
| 1339 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1340 | |
| 1341 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 1342 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 1343 | if (!res->flags || !res->parent) |
| 1344 | continue; |
| 1345 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1346 | for (j = 0; j < m64_bars; j++) { |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1347 | do { |
| 1348 | win = find_next_zero_bit(&phb->ioda.m64_bar_alloc, |
| 1349 | phb->ioda.m64_bar_idx + 1, 0); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1350 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1351 | if (win >= phb->ioda.m64_bar_idx + 1) |
| 1352 | goto m64_failed; |
| 1353 | } while (test_and_set_bit(win, &phb->ioda.m64_bar_alloc)); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1354 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1355 | pdn->m64_map[j][i] = win; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1356 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1357 | if (pdn->m64_single_mode) { |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1358 | size = pci_iov_resource_size(pdev, |
| 1359 | PCI_IOV_RESOURCES + i); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1360 | start = res->start + size * j; |
| 1361 | } else { |
| 1362 | size = resource_size(res); |
| 1363 | start = res->start; |
| 1364 | } |
| 1365 | |
| 1366 | /* Map the M64 here */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1367 | if (pdn->m64_single_mode) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1368 | pe_num = pdn->pe_num_map[j]; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1369 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 1370 | pe_num, OPAL_M64_WINDOW_TYPE, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1371 | pdn->m64_map[j][i], 0); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1372 | } |
| 1373 | |
| 1374 | rc = opal_pci_set_phb_mem_window(phb->opal_id, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1375 | OPAL_M64_WINDOW_TYPE, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1376 | pdn->m64_map[j][i], |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1377 | start, |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1378 | 0, /* unused */ |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1379 | size); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1380 | |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1381 | |
| 1382 | if (rc != OPAL_SUCCESS) { |
| 1383 | dev_err(&pdev->dev, "Failed to map M64 window #%d: %lld\n", |
| 1384 | win, rc); |
| 1385 | goto m64_failed; |
| 1386 | } |
| 1387 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1388 | if (pdn->m64_single_mode) |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1389 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1390 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 2); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1391 | else |
| 1392 | rc = opal_pci_phb_mmio_enable(phb->opal_id, |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1393 | OPAL_M64_WINDOW_TYPE, pdn->m64_map[j][i], 1); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1394 | |
| 1395 | if (rc != OPAL_SUCCESS) { |
| 1396 | dev_err(&pdev->dev, "Failed to enable M64 window #%d: %llx\n", |
| 1397 | win, rc); |
| 1398 | goto m64_failed; |
| 1399 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1400 | } |
| 1401 | } |
| 1402 | return 0; |
| 1403 | |
| 1404 | m64_failed: |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1405 | pnv_pci_vf_release_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1406 | return -EBUSY; |
| 1407 | } |
| 1408 | |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1409 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
| 1410 | int num); |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1411 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1412 | static void pnv_pci_ioda2_release_dma_pe(struct pci_dev *dev, struct pnv_ioda_pe *pe) |
| 1413 | { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1414 | struct iommu_table *tbl; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1415 | int64_t rc; |
| 1416 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1417 | tbl = pe->table_group.tables[0]; |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1418 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1419 | if (rc) |
| 1420 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); |
| 1421 | |
Alexey Kardashevskiy | c035e37 | 2015-06-05 16:35:21 +1000 | [diff] [blame] | 1422 | pnv_pci_ioda2_set_bypass(pe, false); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 1423 | if (pe->table_group.group) { |
| 1424 | iommu_group_put(pe->table_group.group); |
| 1425 | BUG_ON(pe->table_group.group); |
Alexey Kardashevskiy | ac9a588 | 2015-06-05 16:34:56 +1000 | [diff] [blame] | 1426 | } |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 1427 | iommu_tce_table_put(tbl); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1428 | } |
| 1429 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1430 | static void pnv_ioda_release_vf_PE(struct pci_dev *pdev) |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1431 | { |
| 1432 | struct pci_bus *bus; |
| 1433 | struct pci_controller *hose; |
| 1434 | struct pnv_phb *phb; |
| 1435 | struct pnv_ioda_pe *pe, *pe_n; |
| 1436 | struct pci_dn *pdn; |
| 1437 | |
| 1438 | bus = pdev->bus; |
| 1439 | hose = pci_bus_to_host(bus); |
| 1440 | phb = hose->private_data; |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1441 | pdn = pci_get_pdn(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1442 | |
| 1443 | if (!pdev->is_physfn) |
| 1444 | return; |
| 1445 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1446 | list_for_each_entry_safe(pe, pe_n, &phb->ioda.pe_list, list) { |
| 1447 | if (pe->parent_dev != pdev) |
| 1448 | continue; |
| 1449 | |
| 1450 | pnv_pci_ioda2_release_dma_pe(pdev, pe); |
| 1451 | |
| 1452 | /* Remove from list */ |
| 1453 | mutex_lock(&phb->ioda.pe_list_mutex); |
| 1454 | list_del(&pe->list); |
| 1455 | mutex_unlock(&phb->ioda.pe_list_mutex); |
| 1456 | |
| 1457 | pnv_ioda_deconfigure_pe(phb, pe); |
| 1458 | |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1459 | pnv_ioda_free_pe(pe); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1460 | } |
| 1461 | } |
| 1462 | |
| 1463 | void pnv_pci_sriov_disable(struct pci_dev *pdev) |
| 1464 | { |
| 1465 | struct pci_bus *bus; |
| 1466 | struct pci_controller *hose; |
| 1467 | struct pnv_phb *phb; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1468 | struct pnv_ioda_pe *pe; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1469 | struct pci_dn *pdn; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1470 | u16 num_vfs, i; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1471 | |
| 1472 | bus = pdev->bus; |
| 1473 | hose = pci_bus_to_host(bus); |
| 1474 | phb = hose->private_data; |
| 1475 | pdn = pci_get_pdn(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1476 | num_vfs = pdn->num_vfs; |
| 1477 | |
| 1478 | /* Release VF PEs */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1479 | pnv_ioda_release_vf_PE(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1480 | |
| 1481 | if (phb->type == PNV_PHB_IODA2) { |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1482 | if (!pdn->m64_single_mode) |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1483 | pnv_pci_vf_resource_shift(pdev, -*pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1484 | |
| 1485 | /* Release M64 windows */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1486 | pnv_pci_vf_release_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1487 | |
| 1488 | /* Release PE numbers */ |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1489 | if (pdn->m64_single_mode) { |
| 1490 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1491 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
| 1492 | continue; |
| 1493 | |
| 1494 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; |
| 1495 | pnv_ioda_free_pe(pe); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1496 | } |
| 1497 | } else |
| 1498 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
| 1499 | /* Releasing pe_num_map */ |
| 1500 | kfree(pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1501 | } |
| 1502 | } |
| 1503 | |
| 1504 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
| 1505 | struct pnv_ioda_pe *pe); |
| 1506 | static void pnv_ioda_setup_vf_PE(struct pci_dev *pdev, u16 num_vfs) |
| 1507 | { |
| 1508 | struct pci_bus *bus; |
| 1509 | struct pci_controller *hose; |
| 1510 | struct pnv_phb *phb; |
| 1511 | struct pnv_ioda_pe *pe; |
| 1512 | int pe_num; |
| 1513 | u16 vf_index; |
| 1514 | struct pci_dn *pdn; |
| 1515 | |
| 1516 | bus = pdev->bus; |
| 1517 | hose = pci_bus_to_host(bus); |
| 1518 | phb = hose->private_data; |
| 1519 | pdn = pci_get_pdn(pdev); |
| 1520 | |
| 1521 | if (!pdev->is_physfn) |
| 1522 | return; |
| 1523 | |
| 1524 | /* Reserve PE for each VF */ |
| 1525 | for (vf_index = 0; vf_index < num_vfs; vf_index++) { |
Oliver O'Halloran | ad28e1b | 2019-10-28 19:54:22 +1100 | [diff] [blame] | 1526 | int vf_devfn = pci_iov_virtfn_devfn(pdev, vf_index); |
| 1527 | int vf_bus = pci_iov_virtfn_bus(pdev, vf_index); |
| 1528 | struct pci_dn *vf_pdn; |
| 1529 | |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1530 | if (pdn->m64_single_mode) |
| 1531 | pe_num = pdn->pe_num_map[vf_index]; |
| 1532 | else |
| 1533 | pe_num = *pdn->pe_num_map + vf_index; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1534 | |
| 1535 | pe = &phb->ioda.pe_array[pe_num]; |
| 1536 | pe->pe_number = pe_num; |
| 1537 | pe->phb = phb; |
| 1538 | pe->flags = PNV_IODA_PE_VF; |
| 1539 | pe->pbus = NULL; |
| 1540 | pe->parent_dev = pdev; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1541 | pe->mve_number = -1; |
Oliver O'Halloran | ad28e1b | 2019-10-28 19:54:22 +1100 | [diff] [blame] | 1542 | pe->rid = (vf_bus << 8) | vf_devfn; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1543 | |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 1544 | pe_info(pe, "VF %04d:%02d:%02d.%d associated with PE#%x\n", |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1545 | hose->global_number, pdev->bus->number, |
Oliver O'Halloran | ad28e1b | 2019-10-28 19:54:22 +1100 | [diff] [blame] | 1546 | PCI_SLOT(vf_devfn), PCI_FUNC(vf_devfn), pe_num); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1547 | |
| 1548 | if (pnv_ioda_configure_pe(phb, pe)) { |
| 1549 | /* XXX What do we do here ? */ |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1550 | pnv_ioda_free_pe(pe); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1551 | pe->pdev = NULL; |
| 1552 | continue; |
| 1553 | } |
| 1554 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1555 | /* Put PE to the list */ |
| 1556 | mutex_lock(&phb->ioda.pe_list_mutex); |
| 1557 | list_add_tail(&pe->list, &phb->ioda.pe_list); |
| 1558 | mutex_unlock(&phb->ioda.pe_list_mutex); |
| 1559 | |
Oliver O'Halloran | ad28e1b | 2019-10-28 19:54:22 +1100 | [diff] [blame] | 1560 | /* associate this pe to it's pdn */ |
| 1561 | list_for_each_entry(vf_pdn, &pdn->parent->child_list, list) { |
| 1562 | if (vf_pdn->busno == vf_bus && |
| 1563 | vf_pdn->devfn == vf_devfn) { |
| 1564 | vf_pdn->pe_number = pe_num; |
| 1565 | break; |
| 1566 | } |
| 1567 | } |
| 1568 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1569 | pnv_pci_ioda2_setup_dma_pe(phb, pe); |
| 1570 | } |
| 1571 | } |
| 1572 | |
| 1573 | int pnv_pci_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
| 1574 | { |
| 1575 | struct pci_bus *bus; |
| 1576 | struct pci_controller *hose; |
| 1577 | struct pnv_phb *phb; |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1578 | struct pnv_ioda_pe *pe; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1579 | struct pci_dn *pdn; |
| 1580 | int ret; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1581 | u16 i; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1582 | |
| 1583 | bus = pdev->bus; |
| 1584 | hose = pci_bus_to_host(bus); |
| 1585 | phb = hose->private_data; |
| 1586 | pdn = pci_get_pdn(pdev); |
| 1587 | |
| 1588 | if (phb->type == PNV_PHB_IODA2) { |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 1589 | if (!pdn->vfs_expanded) { |
| 1590 | dev_info(&pdev->dev, "don't support this SRIOV device" |
| 1591 | " with non 64bit-prefetchable IOV BAR\n"); |
| 1592 | return -ENOSPC; |
| 1593 | } |
| 1594 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1595 | /* |
| 1596 | * When M64 BARs functions in Single PE mode, the number of VFs |
| 1597 | * could be enabled must be less than the number of M64 BARs. |
| 1598 | */ |
| 1599 | if (pdn->m64_single_mode && num_vfs > phb->ioda.m64_bar_idx) { |
| 1600 | dev_info(&pdev->dev, "Not enough M64 BAR for VFs\n"); |
| 1601 | return -EBUSY; |
| 1602 | } |
| 1603 | |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1604 | /* Allocating pe_num_map */ |
| 1605 | if (pdn->m64_single_mode) |
Markus Elfring | fb37e12 | 2016-08-24 22:26:37 +0200 | [diff] [blame] | 1606 | pdn->pe_num_map = kmalloc_array(num_vfs, |
| 1607 | sizeof(*pdn->pe_num_map), |
| 1608 | GFP_KERNEL); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1609 | else |
| 1610 | pdn->pe_num_map = kmalloc(sizeof(*pdn->pe_num_map), GFP_KERNEL); |
| 1611 | |
| 1612 | if (!pdn->pe_num_map) |
| 1613 | return -ENOMEM; |
| 1614 | |
| 1615 | if (pdn->m64_single_mode) |
| 1616 | for (i = 0; i < num_vfs; i++) |
| 1617 | pdn->pe_num_map[i] = IODA_INVALID_PE; |
| 1618 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1619 | /* Calculate available PE for required VFs */ |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1620 | if (pdn->m64_single_mode) { |
| 1621 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1622 | pe = pnv_ioda_alloc_pe(phb); |
| 1623 | if (!pe) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1624 | ret = -EBUSY; |
| 1625 | goto m64_failed; |
| 1626 | } |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1627 | |
| 1628 | pdn->pe_num_map[i] = pe->pe_number; |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1629 | } |
| 1630 | } else { |
| 1631 | mutex_lock(&phb->ioda.pe_alloc_mutex); |
| 1632 | *pdn->pe_num_map = bitmap_find_next_zero_area( |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1633 | phb->ioda.pe_alloc, phb->ioda.total_pe_num, |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1634 | 0, num_vfs, 0); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 1635 | if (*pdn->pe_num_map >= phb->ioda.total_pe_num) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1636 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
| 1637 | dev_info(&pdev->dev, "Failed to enable VF%d\n", num_vfs); |
| 1638 | kfree(pdn->pe_num_map); |
| 1639 | return -EBUSY; |
| 1640 | } |
| 1641 | bitmap_set(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1642 | mutex_unlock(&phb->ioda.pe_alloc_mutex); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1643 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1644 | pdn->num_vfs = num_vfs; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1645 | |
| 1646 | /* Assign M64 window accordingly */ |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1647 | ret = pnv_pci_vf_assign_m64(pdev, num_vfs); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1648 | if (ret) { |
| 1649 | dev_info(&pdev->dev, "Not enough M64 window resources\n"); |
| 1650 | goto m64_failed; |
| 1651 | } |
| 1652 | |
| 1653 | /* |
| 1654 | * When using one M64 BAR to map one IOV BAR, we need to shift |
| 1655 | * the IOV BAR according to the PE# allocated to the VFs. |
| 1656 | * Otherwise, the PE# for the VF will conflict with others. |
| 1657 | */ |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1658 | if (!pdn->m64_single_mode) { |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1659 | ret = pnv_pci_vf_resource_shift(pdev, *pdn->pe_num_map); |
Wei Yang | 02639b0 | 2015-03-25 16:23:59 +0800 | [diff] [blame] | 1660 | if (ret) |
| 1661 | goto m64_failed; |
| 1662 | } |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1663 | } |
| 1664 | |
| 1665 | /* Setup VF PEs */ |
| 1666 | pnv_ioda_setup_vf_PE(pdev, num_vfs); |
| 1667 | |
| 1668 | return 0; |
| 1669 | |
| 1670 | m64_failed: |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1671 | if (pdn->m64_single_mode) { |
| 1672 | for (i = 0; i < num_vfs; i++) { |
Gavin Shan | 1e91677 | 2016-05-03 15:41:36 +1000 | [diff] [blame] | 1673 | if (pdn->pe_num_map[i] == IODA_INVALID_PE) |
| 1674 | continue; |
| 1675 | |
| 1676 | pe = &phb->ioda.pe_array[pdn->pe_num_map[i]]; |
| 1677 | pnv_ioda_free_pe(pe); |
Wei Yang | be283ee | 2015-10-22 09:22:19 +0800 | [diff] [blame] | 1678 | } |
| 1679 | } else |
| 1680 | bitmap_clear(phb->ioda.pe_alloc, *pdn->pe_num_map, num_vfs); |
| 1681 | |
| 1682 | /* Releasing pe_num_map */ |
| 1683 | kfree(pdn->pe_num_map); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1684 | |
| 1685 | return ret; |
| 1686 | } |
| 1687 | |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1688 | int pcibios_sriov_disable(struct pci_dev *pdev) |
| 1689 | { |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1690 | pnv_pci_sriov_disable(pdev); |
| 1691 | |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1692 | /* Release PCI data */ |
| 1693 | remove_dev_pci_data(pdev); |
| 1694 | return 0; |
| 1695 | } |
| 1696 | |
| 1697 | int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs) |
| 1698 | { |
| 1699 | /* Allocate PCI data */ |
| 1700 | add_dev_pci_data(pdev); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 1701 | |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 1702 | return pnv_pci_sriov_enable(pdev, num_vfs); |
Gavin Shan | a8b2f82 | 2015-03-25 16:23:52 +0800 | [diff] [blame] | 1703 | } |
| 1704 | #endif /* CONFIG_PCI_IOV */ |
| 1705 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1706 | static void pnv_pci_ioda_dma_dev_setup(struct pnv_phb *phb, struct pci_dev *pdev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1707 | { |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 1708 | struct pci_dn *pdn = pci_get_pdn(pdev); |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1709 | struct pnv_ioda_pe *pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1710 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1711 | /* |
| 1712 | * The function can be called while the PE# |
| 1713 | * hasn't been assigned. Do nothing for the |
| 1714 | * case. |
| 1715 | */ |
| 1716 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 1717 | return; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1718 | |
Gavin Shan | 959c9bd | 2013-04-25 19:21:02 +0000 | [diff] [blame] | 1719 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1720 | WARN_ON(get_dma_ops(&pdev->dev) != &dma_iommu_ops); |
Alexey Kardashevskiy | 0e1ffef | 2015-08-27 16:01:16 +1000 | [diff] [blame] | 1721 | set_dma_offset(&pdev->dev, pe->tce_bypass_base); |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1722 | set_iommu_table_base(&pdev->dev, pe->table_group.tables[0]); |
Alexey Kardashevskiy | 4617082 | 2015-06-05 16:34:54 +1000 | [diff] [blame] | 1723 | /* |
| 1724 | * Note: iommu_add_device() will fail here as |
| 1725 | * for physical PE: the device is already added by now; |
| 1726 | * for virtual PE: sysfs entries are not ready yet and |
| 1727 | * tce_iommu_bus_notifier will add the device to a group later. |
| 1728 | */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 1729 | } |
| 1730 | |
Russell Currey | a0f9862 | 2017-06-21 17:18:03 +1000 | [diff] [blame] | 1731 | static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) |
| 1732 | { |
| 1733 | unsigned short vendor = 0; |
| 1734 | struct pci_dev *pdev; |
| 1735 | |
| 1736 | if (pe->device_count == 1) |
| 1737 | return true; |
| 1738 | |
| 1739 | /* pe->pdev should be set if it's a single device, pe->pbus if not */ |
| 1740 | if (!pe->pbus) |
| 1741 | return true; |
| 1742 | |
| 1743 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
| 1744 | if (!vendor) { |
| 1745 | vendor = pdev->vendor; |
| 1746 | continue; |
| 1747 | } |
| 1748 | |
| 1749 | if (pdev->vendor != vendor) |
| 1750 | return false; |
| 1751 | } |
| 1752 | |
| 1753 | return true; |
| 1754 | } |
| 1755 | |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1756 | /* |
| 1757 | * Reconfigure TVE#0 to be usable as 64-bit DMA space. |
| 1758 | * |
| 1759 | * The first 4GB of virtual memory for a PE is reserved for 32-bit accesses. |
| 1760 | * Devices can only access more than that if bit 59 of the PCI address is set |
| 1761 | * by hardware, which indicates TVE#1 should be used instead of TVE#0. |
| 1762 | * Many PCI devices are not capable of addressing that many bits, and as a |
| 1763 | * result are limited to the 4GB of virtual memory made available to 32-bit |
| 1764 | * devices in TVE#0. |
| 1765 | * |
| 1766 | * In order to work around this, reconfigure TVE#0 to be suitable for 64-bit |
| 1767 | * devices by configuring the virtual memory past the first 4GB inaccessible |
| 1768 | * by 64-bit DMAs. This should only be used by devices that want more than |
| 1769 | * 4GB, and only on PEs that have no 32-bit devices. |
| 1770 | * |
| 1771 | * Currently this will only work on PHB3 (POWER8). |
| 1772 | */ |
| 1773 | static int pnv_pci_ioda_dma_64bit_bypass(struct pnv_ioda_pe *pe) |
| 1774 | { |
| 1775 | u64 window_size, table_size, tce_count, addr; |
| 1776 | struct page *table_pages; |
| 1777 | u64 tce_order = 28; /* 256MB TCEs */ |
| 1778 | __be64 *tces; |
| 1779 | s64 rc; |
| 1780 | |
| 1781 | /* |
| 1782 | * Window size needs to be a power of two, but needs to account for |
| 1783 | * shifting memory by the 4GB offset required to skip 32bit space. |
| 1784 | */ |
| 1785 | window_size = roundup_pow_of_two(memory_hotplug_max() + (1ULL << 32)); |
| 1786 | tce_count = window_size >> tce_order; |
| 1787 | table_size = tce_count << 3; |
| 1788 | |
| 1789 | if (table_size < PAGE_SIZE) |
| 1790 | table_size = PAGE_SIZE; |
| 1791 | |
| 1792 | table_pages = alloc_pages_node(pe->phb->hose->node, GFP_KERNEL, |
| 1793 | get_order(table_size)); |
| 1794 | if (!table_pages) |
| 1795 | goto err; |
| 1796 | |
| 1797 | tces = page_address(table_pages); |
| 1798 | if (!tces) |
| 1799 | goto err; |
| 1800 | |
| 1801 | memset(tces, 0, table_size); |
| 1802 | |
| 1803 | for (addr = 0; addr < memory_hotplug_max(); addr += (1 << tce_order)) { |
| 1804 | tces[(addr + (1ULL << 32)) >> tce_order] = |
| 1805 | cpu_to_be64(addr | TCE_PCI_READ | TCE_PCI_WRITE); |
| 1806 | } |
| 1807 | |
| 1808 | rc = opal_pci_map_pe_dma_window(pe->phb->opal_id, |
| 1809 | pe->pe_number, |
| 1810 | /* reconfigure window 0 */ |
| 1811 | (pe->pe_number << 1) + 0, |
| 1812 | 1, |
| 1813 | __pa(tces), |
| 1814 | table_size, |
| 1815 | 1 << tce_order); |
| 1816 | if (rc == OPAL_SUCCESS) { |
| 1817 | pe_info(pe, "Using 64-bit DMA iommu bypass (through TVE#0)\n"); |
| 1818 | return 0; |
| 1819 | } |
| 1820 | err: |
| 1821 | pe_err(pe, "Error configuring 64-bit DMA bypass\n"); |
| 1822 | return -EIO; |
| 1823 | } |
| 1824 | |
Daniel Axtens | 763d2d8 | 2015-04-28 15:12:07 +1000 | [diff] [blame] | 1825 | static int pnv_pci_ioda_dma_set_mask(struct pci_dev *pdev, u64 dma_mask) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1826 | { |
Daniel Axtens | 763d2d8 | 2015-04-28 15:12:07 +1000 | [diff] [blame] | 1827 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 1828 | struct pnv_phb *phb = hose->private_data; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1829 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 1830 | struct pnv_ioda_pe *pe; |
| 1831 | uint64_t top; |
| 1832 | bool bypass = false; |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1833 | s64 rc; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1834 | |
| 1835 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) |
| 1836 | return -ENODEV;; |
| 1837 | |
| 1838 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
| 1839 | if (pe->tce_bypass_enabled) { |
| 1840 | top = pe->tce_bypass_base + memblock_end_of_DRAM() - 1; |
| 1841 | bypass = (dma_mask >= top); |
| 1842 | } |
| 1843 | |
| 1844 | if (bypass) { |
| 1845 | dev_info(&pdev->dev, "Using 64-bit DMA iommu bypass\n"); |
| 1846 | set_dma_ops(&pdev->dev, &dma_direct_ops); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1847 | } else { |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1848 | /* |
| 1849 | * If the device can't set the TCE bypass bit but still wants |
| 1850 | * to access 4GB or more, on PHB3 we can reconfigure TVE#0 to |
| 1851 | * bypass the 32-bit region and be usable for 64-bit DMAs. |
| 1852 | * The device needs to be able to address all of this space. |
| 1853 | */ |
| 1854 | if (dma_mask >> 32 && |
| 1855 | dma_mask > (memory_hotplug_max() + (1ULL << 32)) && |
| 1856 | pnv_pci_ioda_pe_single_vendor(pe) && |
| 1857 | phb->model == PNV_PHB_MODEL_PHB3) { |
| 1858 | /* Configure the bypass mode */ |
| 1859 | rc = pnv_pci_ioda_dma_64bit_bypass(pe); |
| 1860 | if (rc) |
| 1861 | return rc; |
| 1862 | /* 4GB offset bypasses 32-bit space */ |
| 1863 | set_dma_offset(&pdev->dev, (1ULL << 32)); |
| 1864 | set_dma_ops(&pdev->dev, &dma_direct_ops); |
Alistair Popple | 253fd51 | 2017-07-26 15:26:40 +1000 | [diff] [blame] | 1865 | } else if (dma_mask >> 32 && dma_mask != DMA_BIT_MASK(64)) { |
| 1866 | /* |
| 1867 | * Fail the request if a DMA mask between 32 and 64 bits |
| 1868 | * was requested but couldn't be fulfilled. Ideally we |
| 1869 | * would do this for 64-bits but historically we have |
| 1870 | * always fallen back to 32-bits. |
| 1871 | */ |
| 1872 | return -ENOMEM; |
Russell Currey | 8e3f1b1 | 2017-06-21 17:18:04 +1000 | [diff] [blame] | 1873 | } else { |
| 1874 | dev_info(&pdev->dev, "Using 32-bit DMA via iommu\n"); |
| 1875 | set_dma_ops(&pdev->dev, &dma_iommu_ops); |
| 1876 | } |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1877 | } |
Brian W Hart | a32305b | 2014-07-31 14:24:37 -0500 | [diff] [blame] | 1878 | *pdev->dev.dma_mask = dma_mask; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1879 | |
| 1880 | /* Update peer npu devices */ |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 1881 | pnv_npu_try_dma_set_bypass(pdev, bypass); |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 1882 | |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 1883 | return 0; |
| 1884 | } |
| 1885 | |
Andrew Donnellan | 5352298 | 2015-08-07 13:45:54 +1000 | [diff] [blame] | 1886 | static u64 pnv_pci_ioda_dma_get_required_mask(struct pci_dev *pdev) |
Gavin Shan | fe7e85c | 2014-09-30 12:39:10 +1000 | [diff] [blame] | 1887 | { |
Andrew Donnellan | 5352298 | 2015-08-07 13:45:54 +1000 | [diff] [blame] | 1888 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 1889 | struct pnv_phb *phb = hose->private_data; |
Gavin Shan | fe7e85c | 2014-09-30 12:39:10 +1000 | [diff] [blame] | 1890 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 1891 | struct pnv_ioda_pe *pe; |
| 1892 | u64 end, mask; |
| 1893 | |
| 1894 | if (WARN_ON(!pdn || pdn->pe_number == IODA_INVALID_PE)) |
| 1895 | return 0; |
| 1896 | |
| 1897 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
| 1898 | if (!pe->tce_bypass_enabled) |
| 1899 | return __dma_get_required_mask(&pdev->dev); |
| 1900 | |
| 1901 | |
| 1902 | end = pe->tce_bypass_base + memblock_end_of_DRAM(); |
| 1903 | mask = 1ULL << (fls64(end) - 1); |
| 1904 | mask += mask - 1; |
| 1905 | |
| 1906 | return mask; |
| 1907 | } |
| 1908 | |
Gavin Shan | dff4a39 | 2014-07-15 17:00:55 +1000 | [diff] [blame] | 1909 | static void pnv_ioda_setup_bus_dma(struct pnv_ioda_pe *pe, |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1910 | struct pci_bus *bus, |
| 1911 | bool add_to_group) |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 1912 | { |
| 1913 | struct pci_dev *dev; |
| 1914 | |
| 1915 | list_for_each_entry(dev, &bus->devices, bus_list) { |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1916 | set_iommu_table_base(&dev->dev, pe->table_group.tables[0]); |
Benjamin Herrenschmidt | e91c251 | 2015-06-24 15:25:27 +1000 | [diff] [blame] | 1917 | set_dma_offset(&dev->dev, pe->tce_bypass_base); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1918 | if (add_to_group) |
| 1919 | iommu_add_device(&dev->dev); |
Gavin Shan | dff4a39 | 2014-07-15 17:00:55 +1000 | [diff] [blame] | 1920 | |
Alexey Kardashevskiy | 5c89a87 | 2015-06-18 11:41:36 +1000 | [diff] [blame] | 1921 | if ((pe->flags & PNV_IODA_PE_BUS_ALL) && dev->subordinate) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 1922 | pnv_ioda_setup_bus_dma(pe, dev->subordinate, |
| 1923 | add_to_group); |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 1924 | } |
| 1925 | } |
| 1926 | |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 1927 | static inline __be64 __iomem *pnv_ioda_get_inval_reg(struct pnv_phb *phb, |
| 1928 | bool real_mode) |
| 1929 | { |
| 1930 | return real_mode ? (__be64 __iomem *)(phb->regs_phys + 0x210) : |
| 1931 | (phb->regs + 0x210); |
| 1932 | } |
| 1933 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 1934 | static void pnv_pci_p7ioc_tce_invalidate(struct iommu_table *tbl, |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1935 | unsigned long index, unsigned long npages, bool rm) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1936 | { |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 1937 | struct iommu_table_group_link *tgl = list_first_entry_or_null( |
| 1938 | &tbl->it_group_list, struct iommu_table_group_link, |
| 1939 | next); |
| 1940 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 1941 | struct pnv_ioda_pe, table_group); |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 1942 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1943 | unsigned long start, end, inc; |
| 1944 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1945 | start = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset); |
| 1946 | end = __pa(((__be64 *)tbl->it_base) + index - tbl->it_offset + |
| 1947 | npages - 1); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1948 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 1949 | /* p7ioc-style invalidation, 2 TCEs per write */ |
| 1950 | start |= (1ull << 63); |
| 1951 | end |= (1ull << 63); |
| 1952 | inc = 16; |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1953 | end |= inc - 1; /* round up end to be different than start */ |
| 1954 | |
| 1955 | mb(); /* Ensure above stores are visible */ |
| 1956 | while (start <= end) { |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 1957 | if (rm) |
Benjamin Herrenschmidt | 3ad26e5 | 2013-10-11 18:23:53 +1100 | [diff] [blame] | 1958 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 1959 | else |
Benjamin Herrenschmidt | 3ad26e5 | 2013-10-11 18:23:53 +1100 | [diff] [blame] | 1960 | __raw_writeq(cpu_to_be64(start), invalidate); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 1961 | start += inc; |
| 1962 | } |
| 1963 | |
| 1964 | /* |
| 1965 | * The iommu layer will do another mb() for us on build() |
| 1966 | * and we don't care on free() |
| 1967 | */ |
| 1968 | } |
| 1969 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1970 | static int pnv_ioda1_tce_build(struct iommu_table *tbl, long index, |
| 1971 | long npages, unsigned long uaddr, |
| 1972 | enum dma_data_direction direction, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 1973 | unsigned long attrs) |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1974 | { |
| 1975 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
| 1976 | attrs); |
| 1977 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 1978 | if (!ret) |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 1979 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 1980 | |
| 1981 | return ret; |
| 1982 | } |
| 1983 | |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 1984 | #ifdef CONFIG_IOMMU_API |
| 1985 | static int pnv_ioda1_tce_xchg(struct iommu_table *tbl, long index, |
| 1986 | unsigned long *hpa, enum dma_data_direction *direction) |
| 1987 | { |
| 1988 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 1989 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 1990 | if (!ret) |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 1991 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, false); |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 1992 | |
| 1993 | return ret; |
| 1994 | } |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 1995 | |
| 1996 | static int pnv_ioda1_tce_xchg_rm(struct iommu_table *tbl, long index, |
| 1997 | unsigned long *hpa, enum dma_data_direction *direction) |
| 1998 | { |
| 1999 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2000 | |
| 2001 | if (!ret) |
| 2002 | pnv_pci_p7ioc_tce_invalidate(tbl, index, 1, true); |
| 2003 | |
| 2004 | return ret; |
| 2005 | } |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2006 | #endif |
| 2007 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2008 | static void pnv_ioda1_tce_free(struct iommu_table *tbl, long index, |
| 2009 | long npages) |
| 2010 | { |
| 2011 | pnv_tce_free(tbl, index, npages); |
| 2012 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2013 | pnv_pci_p7ioc_tce_invalidate(tbl, index, npages, false); |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2014 | } |
| 2015 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2016 | static struct iommu_table_ops pnv_ioda1_iommu_ops = { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2017 | .set = pnv_ioda1_tce_build, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2018 | #ifdef CONFIG_IOMMU_API |
| 2019 | .exchange = pnv_ioda1_tce_xchg, |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2020 | .exchange_rm = pnv_ioda1_tce_xchg_rm, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2021 | #endif |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2022 | .clear = pnv_ioda1_tce_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2023 | .get = pnv_tce_get, |
| 2024 | }; |
| 2025 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2026 | #define PHB3_TCE_KILL_INVAL_ALL PPC_BIT(0) |
| 2027 | #define PHB3_TCE_KILL_INVAL_PE PPC_BIT(1) |
| 2028 | #define PHB3_TCE_KILL_INVAL_ONE PPC_BIT(2) |
Alexey Kardashevskiy | bef9253 | 2016-04-29 18:55:17 +1000 | [diff] [blame] | 2029 | |
Alistair Popple | 6b3d12a | 2017-05-03 13:24:08 +1000 | [diff] [blame] | 2030 | static void pnv_pci_phb3_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2031 | { |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2032 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(phb, rm); |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2033 | const unsigned long val = PHB3_TCE_KILL_INVAL_ALL; |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2034 | |
| 2035 | mb(); /* Ensure previous TCE table stores are visible */ |
| 2036 | if (rm) |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2037 | __raw_rm_writeq(cpu_to_be64(val), invalidate); |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2038 | else |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2039 | __raw_writeq(cpu_to_be64(val), invalidate); |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2040 | } |
| 2041 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2042 | static inline void pnv_pci_phb3_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2043 | { |
| 2044 | /* 01xb - invalidate TCEs that match the specified PE# */ |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2045 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, false); |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2046 | unsigned long val = PHB3_TCE_KILL_INVAL_PE | (pe->pe_number & 0xFF); |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2047 | |
| 2048 | mb(); /* Ensure above stores are visible */ |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2049 | __raw_writeq(cpu_to_be64(val), invalidate); |
Alexey Kardashevskiy | 5780fb0 | 2015-06-05 16:35:12 +1000 | [diff] [blame] | 2050 | } |
| 2051 | |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2052 | static void pnv_pci_phb3_tce_invalidate(struct pnv_ioda_pe *pe, bool rm, |
| 2053 | unsigned shift, unsigned long index, |
| 2054 | unsigned long npages) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2055 | { |
Alexey Kardashevskiy | 4d90219 | 2016-08-03 18:40:45 +1000 | [diff] [blame] | 2056 | __be64 __iomem *invalidate = pnv_ioda_get_inval_reg(pe->phb, rm); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2057 | unsigned long start, end, inc; |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2058 | |
| 2059 | /* We'll invalidate DMA address in PE scope */ |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 2060 | start = PHB3_TCE_KILL_INVAL_ONE; |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 2061 | start |= (pe->pe_number & 0xFF); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2062 | end = start; |
| 2063 | |
| 2064 | /* Figure out the start, end and step */ |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2065 | start |= (index << shift); |
| 2066 | end |= ((index + npages - 1) << shift); |
Alexey Kardashevskiy | b0376c9 | 2014-06-06 18:44:01 +1000 | [diff] [blame] | 2067 | inc = (0x1ull << shift); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2068 | mb(); |
| 2069 | |
| 2070 | while (start <= end) { |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 2071 | if (rm) |
Benjamin Herrenschmidt | 3ad26e5 | 2013-10-11 18:23:53 +1100 | [diff] [blame] | 2072 | __raw_rm_writeq(cpu_to_be64(start), invalidate); |
Alexey Kardashevskiy | 8e0a161 | 2013-08-28 18:37:43 +1000 | [diff] [blame] | 2073 | else |
Benjamin Herrenschmidt | 3ad26e5 | 2013-10-11 18:23:53 +1100 | [diff] [blame] | 2074 | __raw_writeq(cpu_to_be64(start), invalidate); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2075 | start += inc; |
| 2076 | } |
| 2077 | } |
| 2078 | |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2079 | static inline void pnv_pci_ioda2_tce_invalidate_pe(struct pnv_ioda_pe *pe) |
| 2080 | { |
| 2081 | struct pnv_phb *phb = pe->phb; |
| 2082 | |
| 2083 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
| 2084 | pnv_pci_phb3_tce_invalidate_pe(pe); |
| 2085 | else |
| 2086 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL_PE, |
| 2087 | pe->pe_number, 0, 0, 0); |
| 2088 | } |
| 2089 | |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2090 | static void pnv_pci_ioda2_tce_invalidate(struct iommu_table *tbl, |
| 2091 | unsigned long index, unsigned long npages, bool rm) |
| 2092 | { |
| 2093 | struct iommu_table_group_link *tgl; |
| 2094 | |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2095 | list_for_each_entry_lockless(tgl, &tbl->it_group_list, next) { |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2096 | struct pnv_ioda_pe *pe = container_of(tgl->table_group, |
| 2097 | struct pnv_ioda_pe, table_group); |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2098 | struct pnv_phb *phb = pe->phb; |
| 2099 | unsigned int shift = tbl->it_page_shift; |
| 2100 | |
Alistair Popple | 616badd | 2017-01-10 15:41:44 +1100 | [diff] [blame] | 2101 | /* |
| 2102 | * NVLink1 can use the TCE kill register directly as |
| 2103 | * it's the same as PHB3. NVLink2 is different and |
| 2104 | * should go via the OPAL call. |
| 2105 | */ |
| 2106 | if (phb->model == PNV_PHB_MODEL_NPU) { |
Alexey Kardashevskiy | 0bbcdb4 | 2016-04-29 18:55:18 +1000 | [diff] [blame] | 2107 | /* |
| 2108 | * The NVLink hardware does not support TCE kill |
| 2109 | * per TCE entry so we have to invalidate |
| 2110 | * the entire cache for it. |
| 2111 | */ |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2112 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
Alexey Kardashevskiy | 8567486 | 2016-04-29 18:55:23 +1000 | [diff] [blame] | 2113 | continue; |
| 2114 | } |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2115 | if (phb->model == PNV_PHB_MODEL_PHB3 && phb->regs) |
| 2116 | pnv_pci_phb3_tce_invalidate(pe, rm, shift, |
| 2117 | index, npages); |
Benjamin Herrenschmidt | f0228c4 | 2016-07-08 16:37:15 +1000 | [diff] [blame] | 2118 | else |
| 2119 | opal_pci_tce_kill(phb->opal_id, |
| 2120 | OPAL_PCI_TCE_KILL_PAGES, |
| 2121 | pe->pe_number, 1u << shift, |
| 2122 | index << shift, npages); |
Alexey Kardashevskiy | e57080f | 2015-06-05 16:35:13 +1000 | [diff] [blame] | 2123 | } |
| 2124 | } |
| 2125 | |
Alistair Popple | 6b3d12a | 2017-05-03 13:24:08 +1000 | [diff] [blame] | 2126 | void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm) |
| 2127 | { |
| 2128 | if (phb->model == PNV_PHB_MODEL_NPU || phb->model == PNV_PHB_MODEL_PHB3) |
| 2129 | pnv_pci_phb3_tce_invalidate_entire(phb, rm); |
| 2130 | else |
| 2131 | opal_pci_tce_kill(phb->opal_id, OPAL_PCI_TCE_KILL, 0, 0, 0, 0); |
| 2132 | } |
| 2133 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2134 | static int pnv_ioda2_tce_build(struct iommu_table *tbl, long index, |
| 2135 | long npages, unsigned long uaddr, |
| 2136 | enum dma_data_direction direction, |
Krzysztof Kozlowski | 00085f1 | 2016-08-03 13:46:00 -0700 | [diff] [blame] | 2137 | unsigned long attrs) |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2138 | { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2139 | int ret = pnv_tce_build(tbl, index, npages, uaddr, direction, |
| 2140 | attrs); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2141 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2142 | if (!ret) |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2143 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
| 2144 | |
| 2145 | return ret; |
| 2146 | } |
| 2147 | |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2148 | #ifdef CONFIG_IOMMU_API |
| 2149 | static int pnv_ioda2_tce_xchg(struct iommu_table *tbl, long index, |
| 2150 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2151 | { |
| 2152 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2153 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2154 | if (!ret) |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2155 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, false); |
| 2156 | |
| 2157 | return ret; |
| 2158 | } |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2159 | |
| 2160 | static int pnv_ioda2_tce_xchg_rm(struct iommu_table *tbl, long index, |
| 2161 | unsigned long *hpa, enum dma_data_direction *direction) |
| 2162 | { |
| 2163 | long ret = pnv_tce_xchg(tbl, index, hpa, direction); |
| 2164 | |
| 2165 | if (!ret) |
| 2166 | pnv_pci_ioda2_tce_invalidate(tbl, index, 1, true); |
| 2167 | |
| 2168 | return ret; |
| 2169 | } |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2170 | #endif |
| 2171 | |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2172 | static void pnv_ioda2_tce_free(struct iommu_table *tbl, long index, |
| 2173 | long npages) |
| 2174 | { |
| 2175 | pnv_tce_free(tbl, index, npages); |
| 2176 | |
Benjamin Herrenschmidt | 08acce1 | 2016-07-08 16:37:13 +1000 | [diff] [blame] | 2177 | pnv_pci_ioda2_tce_invalidate(tbl, index, npages, false); |
Gavin Shan | 4cce955 | 2013-04-25 19:21:00 +0000 | [diff] [blame] | 2178 | } |
| 2179 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2180 | static void pnv_ioda2_table_free(struct iommu_table *tbl) |
| 2181 | { |
| 2182 | pnv_pci_ioda2_table_free_pages(tbl); |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2183 | } |
| 2184 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2185 | static struct iommu_table_ops pnv_ioda2_iommu_ops = { |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2186 | .set = pnv_ioda2_tce_build, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2187 | #ifdef CONFIG_IOMMU_API |
| 2188 | .exchange = pnv_ioda2_tce_xchg, |
Alexey Kardashevskiy | a540aa5 | 2017-03-22 15:21:48 +1100 | [diff] [blame] | 2189 | .exchange_rm = pnv_ioda2_tce_xchg_rm, |
Alexey Kardashevskiy | 05c6cfb | 2015-06-05 16:35:15 +1000 | [diff] [blame] | 2190 | #endif |
Alexey Kardashevskiy | decbda2 | 2015-06-05 16:35:07 +1000 | [diff] [blame] | 2191 | .clear = pnv_ioda2_tce_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2192 | .get = pnv_tce_get, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2193 | .free = pnv_ioda2_table_free, |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2194 | }; |
| 2195 | |
Gavin Shan | 801846d | 2016-05-03 15:41:34 +1000 | [diff] [blame] | 2196 | static int pnv_pci_ioda_dev_dma_weight(struct pci_dev *dev, void *data) |
| 2197 | { |
| 2198 | unsigned int *weight = (unsigned int *)data; |
| 2199 | |
| 2200 | /* This is quite simplistic. The "base" weight of a device |
| 2201 | * is 10. 0 means no DMA is to be accounted for it. |
| 2202 | */ |
| 2203 | if (dev->hdr_type != PCI_HEADER_TYPE_NORMAL) |
| 2204 | return 0; |
| 2205 | |
| 2206 | if (dev->class == PCI_CLASS_SERIAL_USB_UHCI || |
| 2207 | dev->class == PCI_CLASS_SERIAL_USB_OHCI || |
| 2208 | dev->class == PCI_CLASS_SERIAL_USB_EHCI) |
| 2209 | *weight += 3; |
| 2210 | else if ((dev->class >> 8) == PCI_CLASS_STORAGE_RAID) |
| 2211 | *weight += 15; |
| 2212 | else |
| 2213 | *weight += 10; |
| 2214 | |
| 2215 | return 0; |
| 2216 | } |
| 2217 | |
| 2218 | static unsigned int pnv_pci_ioda_pe_dma_weight(struct pnv_ioda_pe *pe) |
| 2219 | { |
| 2220 | unsigned int weight = 0; |
| 2221 | |
| 2222 | /* SRIOV VF has same DMA32 weight as its PF */ |
| 2223 | #ifdef CONFIG_PCI_IOV |
| 2224 | if ((pe->flags & PNV_IODA_PE_VF) && pe->parent_dev) { |
| 2225 | pnv_pci_ioda_dev_dma_weight(pe->parent_dev, &weight); |
| 2226 | return weight; |
| 2227 | } |
| 2228 | #endif |
| 2229 | |
| 2230 | if ((pe->flags & PNV_IODA_PE_DEV) && pe->pdev) { |
| 2231 | pnv_pci_ioda_dev_dma_weight(pe->pdev, &weight); |
| 2232 | } else if ((pe->flags & PNV_IODA_PE_BUS) && pe->pbus) { |
| 2233 | struct pci_dev *pdev; |
| 2234 | |
| 2235 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) |
| 2236 | pnv_pci_ioda_dev_dma_weight(pdev, &weight); |
| 2237 | } else if ((pe->flags & PNV_IODA_PE_BUS_ALL) && pe->pbus) { |
| 2238 | pci_walk_bus(pe->pbus, pnv_pci_ioda_dev_dma_weight, &weight); |
| 2239 | } |
| 2240 | |
| 2241 | return weight; |
| 2242 | } |
| 2243 | |
Gavin Shan | b30d936 | 2016-05-03 15:41:32 +1000 | [diff] [blame] | 2244 | static void pnv_pci_ioda1_setup_dma_pe(struct pnv_phb *phb, |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2245 | struct pnv_ioda_pe *pe) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2246 | { |
| 2247 | |
| 2248 | struct page *tce_mem = NULL; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2249 | struct iommu_table *tbl; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2250 | unsigned int weight, total_weight = 0; |
| 2251 | unsigned int tce32_segsz, base, segs, avail, i; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2252 | int64_t rc; |
| 2253 | void *addr; |
| 2254 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2255 | /* XXX FIXME: Handle 64-bit only DMA devices */ |
| 2256 | /* XXX FIXME: Provide 64-bit DMA facilities & non-4K TCE tables etc.. */ |
| 2257 | /* XXX FIXME: Allocate multi-level tables on PHB3 */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2258 | weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 2259 | if (!weight) |
| 2260 | return; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2261 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2262 | pci_walk_bus(phb->hose->bus, pnv_pci_ioda_dev_dma_weight, |
| 2263 | &total_weight); |
| 2264 | segs = (weight * phb->ioda.dma32_count) / total_weight; |
| 2265 | if (!segs) |
| 2266 | segs = 1; |
| 2267 | |
| 2268 | /* |
| 2269 | * Allocate contiguous DMA32 segments. We begin with the expected |
| 2270 | * number of segments. With one more attempt, the number of DMA32 |
| 2271 | * segments to be allocated is decreased by one until one segment |
| 2272 | * is allocated successfully. |
| 2273 | */ |
| 2274 | do { |
| 2275 | for (base = 0; base <= phb->ioda.dma32_count - segs; base++) { |
| 2276 | for (avail = 0, i = base; i < base + segs; i++) { |
| 2277 | if (phb->ioda.dma32_segmap[i] == |
| 2278 | IODA_INVALID_PE) |
| 2279 | avail++; |
| 2280 | } |
| 2281 | |
| 2282 | if (avail == segs) |
| 2283 | goto found; |
| 2284 | } |
| 2285 | } while (--segs); |
| 2286 | |
| 2287 | if (!segs) { |
| 2288 | pe_warn(pe, "No available DMA32 segments\n"); |
| 2289 | return; |
| 2290 | } |
| 2291 | |
| 2292 | found: |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2293 | tbl = pnv_pci_table_alloc(phb->hose->node); |
Alexey Kardashevskiy | 82eae1a | 2017-03-27 19:27:37 +1100 | [diff] [blame] | 2294 | if (WARN_ON(!tbl)) |
| 2295 | return; |
| 2296 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 2297 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
| 2298 | pe->pe_number); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2299 | pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2300 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2301 | /* Grab a 32-bit TCE table */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2302 | pe_info(pe, "DMA weight %d (%d), assigned (%d) %d DMA32 segments\n", |
| 2303 | weight, total_weight, base, segs); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2304 | pe_info(pe, " Setting up 32-bit TCE table at %08x..%08x\n", |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2305 | base * PNV_IODA1_DMA32_SEGSIZE, |
| 2306 | (base + segs) * PNV_IODA1_DMA32_SEGSIZE - 1); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2307 | |
| 2308 | /* XXX Currently, we allocate one big contiguous table for the |
| 2309 | * TCEs. We only really need one chunk per 256M of TCE space |
| 2310 | * (ie per segment) but that's an optimization for later, it |
| 2311 | * requires some added smarts with our get/put_tce implementation |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2312 | * |
| 2313 | * Each TCE page is 4KB in size and each TCE entry occupies 8 |
| 2314 | * bytes |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2315 | */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2316 | tce32_segsz = PNV_IODA1_DMA32_SEGSIZE >> (IOMMU_PAGE_SHIFT_4K - 3); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2317 | tce_mem = alloc_pages_node(phb->hose->node, GFP_KERNEL, |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2318 | get_order(tce32_segsz * segs)); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2319 | if (!tce_mem) { |
| 2320 | pe_err(pe, " Failed to allocate a 32-bit TCE memory\n"); |
| 2321 | goto fail; |
| 2322 | } |
| 2323 | addr = page_address(tce_mem); |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2324 | memset(addr, 0, tce32_segsz * segs); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2325 | |
| 2326 | /* Configure HW */ |
| 2327 | for (i = 0; i < segs; i++) { |
| 2328 | rc = opal_pci_map_pe_dma_window(phb->opal_id, |
| 2329 | pe->pe_number, |
| 2330 | base + i, 1, |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2331 | __pa(addr) + tce32_segsz * i, |
| 2332 | tce32_segsz, IOMMU_PAGE_SIZE_4K); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2333 | if (rc) { |
| 2334 | pe_err(pe, " Failed to configure 32-bit TCE table," |
| 2335 | " err %ld\n", rc); |
| 2336 | goto fail; |
| 2337 | } |
| 2338 | } |
| 2339 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 2340 | /* Setup DMA32 segment mapping */ |
| 2341 | for (i = base; i < base + segs; i++) |
| 2342 | phb->ioda.dma32_segmap[i] = pe->pe_number; |
| 2343 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2344 | /* Setup linux iommu table */ |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2345 | pnv_pci_setup_iommu_table(tbl, addr, tce32_segsz * segs, |
| 2346 | base * PNV_IODA1_DMA32_SEGSIZE, |
| 2347 | IOMMU_PAGE_SHIFT_4K); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2348 | |
Alexey Kardashevskiy | da004c3 | 2015-06-05 16:35:06 +1000 | [diff] [blame] | 2349 | tbl->it_ops = &pnv_ioda1_iommu_ops; |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2350 | pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift; |
| 2351 | pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2352 | iommu_init_table(tbl, phb->hose->node); |
| 2353 | |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 2354 | if (pe->flags & PNV_IODA_PE_DEV) { |
Alexey Kardashevskiy | 4617082 | 2015-06-05 16:34:54 +1000 | [diff] [blame] | 2355 | /* |
| 2356 | * Setting table base here only for carrying iommu_group |
| 2357 | * further down to let iommu_add_device() do the job. |
| 2358 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. |
| 2359 | */ |
| 2360 | set_iommu_table_base(&pe->pdev->dev, tbl); |
| 2361 | iommu_add_device(&pe->pdev->dev); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2362 | } else if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2363 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
Benjamin Herrenschmidt | 74251fe | 2013-07-01 17:54:09 +1000 | [diff] [blame] | 2364 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2365 | return; |
| 2366 | fail: |
| 2367 | /* XXX Failure: Try to fallback to 64-bit only ? */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2368 | if (tce_mem) |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 2369 | __free_pages(tce_mem, get_order(tce32_segsz * segs)); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2370 | if (tbl) { |
| 2371 | pnv_pci_unlink_table_and_group(tbl, &pe->table_group); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2372 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 0eaf4de | 2015-06-05 16:35:09 +1000 | [diff] [blame] | 2373 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2374 | } |
| 2375 | |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2376 | static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group, |
| 2377 | int num, struct iommu_table *tbl) |
| 2378 | { |
| 2379 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2380 | table_group); |
| 2381 | struct pnv_phb *phb = pe->phb; |
| 2382 | int64_t rc; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2383 | const unsigned long size = tbl->it_indirect_levels ? |
| 2384 | tbl->it_level_size : tbl->it_size; |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2385 | const __u64 start_addr = tbl->it_offset << tbl->it_page_shift; |
| 2386 | const __u64 win_size = tbl->it_size << tbl->it_page_shift; |
| 2387 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2388 | pe_info(pe, "Setting up window#%d %llx..%llx pg=%x\n", num, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2389 | start_addr, start_addr + win_size - 1, |
| 2390 | IOMMU_PAGE_SIZE(tbl)); |
| 2391 | |
| 2392 | /* |
| 2393 | * Map TCE table through TVT. The TVE index is the PE number |
| 2394 | * shifted by 1 bit for 32-bits DMA space. |
| 2395 | */ |
| 2396 | rc = opal_pci_map_pe_dma_window(phb->opal_id, |
| 2397 | pe->pe_number, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2398 | (pe->pe_number << 1) + num, |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2399 | tbl->it_indirect_levels + 1, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2400 | __pa(tbl->it_base), |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2401 | size << 3, |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2402 | IOMMU_PAGE_SIZE(tbl)); |
| 2403 | if (rc) { |
| 2404 | pe_err(pe, "Failed to configure TCE table, err %ld\n", rc); |
| 2405 | return rc; |
| 2406 | } |
| 2407 | |
| 2408 | pnv_pci_link_table_and_group(phb->hose->node, num, |
| 2409 | tbl, &pe->table_group); |
Michael Ellerman | ed7d9a1 | 2016-09-15 17:03:06 +1000 | [diff] [blame] | 2410 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
Alexey Kardashevskiy | 43cb60a | 2015-06-05 16:35:18 +1000 | [diff] [blame] | 2411 | |
| 2412 | return 0; |
| 2413 | } |
| 2414 | |
Frederic Barrat | 2552910 | 2017-08-04 11:55:14 +0200 | [diff] [blame] | 2415 | void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2416 | { |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2417 | uint16_t window_id = (pe->pe_number << 1 ) + 1; |
| 2418 | int64_t rc; |
| 2419 | |
| 2420 | pe_info(pe, "%sabling 64-bit DMA bypass\n", enable ? "En" : "Dis"); |
| 2421 | if (enable) { |
| 2422 | phys_addr_t top = memblock_end_of_DRAM(); |
| 2423 | |
| 2424 | top = roundup_pow_of_two(top); |
| 2425 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, |
| 2426 | pe->pe_number, |
| 2427 | window_id, |
| 2428 | pe->tce_bypass_base, |
| 2429 | top); |
| 2430 | } else { |
| 2431 | rc = opal_pci_map_pe_dma_window_real(pe->phb->opal_id, |
| 2432 | pe->pe_number, |
| 2433 | window_id, |
| 2434 | pe->tce_bypass_base, |
| 2435 | 0); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2436 | } |
| 2437 | if (rc) |
| 2438 | pe_err(pe, "OPAL error %lld configuring bypass window\n", rc); |
| 2439 | else |
| 2440 | pe->tce_bypass_enabled = enable; |
| 2441 | } |
| 2442 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2443 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
| 2444 | __u32 page_shift, __u64 window_size, __u32 levels, |
| 2445 | struct iommu_table *tbl); |
| 2446 | |
| 2447 | static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group, |
| 2448 | int num, __u32 page_shift, __u64 window_size, __u32 levels, |
| 2449 | struct iommu_table **ptbl) |
| 2450 | { |
| 2451 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2452 | table_group); |
| 2453 | int nid = pe->phb->hose->node; |
| 2454 | __u64 bus_offset = num ? pe->tce_bypass_base : table_group->tce32_start; |
| 2455 | long ret; |
| 2456 | struct iommu_table *tbl; |
| 2457 | |
| 2458 | tbl = pnv_pci_table_alloc(nid); |
| 2459 | if (!tbl) |
| 2460 | return -ENOMEM; |
| 2461 | |
Alexey Kardashevskiy | 11edf11 | 2017-03-22 15:21:49 +1100 | [diff] [blame] | 2462 | tbl->it_ops = &pnv_ioda2_iommu_ops; |
| 2463 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2464 | ret = pnv_pci_ioda2_table_alloc_pages(nid, |
| 2465 | bus_offset, page_shift, window_size, |
| 2466 | levels, tbl); |
| 2467 | if (ret) { |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2468 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2469 | return ret; |
| 2470 | } |
| 2471 | |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2472 | *ptbl = tbl; |
| 2473 | |
| 2474 | return 0; |
| 2475 | } |
| 2476 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2477 | static long pnv_pci_ioda2_setup_default_config(struct pnv_ioda_pe *pe) |
| 2478 | { |
| 2479 | struct iommu_table *tbl = NULL; |
| 2480 | long rc; |
| 2481 | |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2482 | /* |
Nishanth Aravamudan | fa14486 | 2015-09-04 11:22:52 -0700 | [diff] [blame] | 2483 | * crashkernel= specifies the kdump kernel's maximum memory at |
| 2484 | * some offset and there is no guaranteed the result is a power |
| 2485 | * of 2, which will cause errors later. |
| 2486 | */ |
| 2487 | const u64 max_memory = __rounddown_pow_of_two(memory_hotplug_max()); |
| 2488 | |
| 2489 | /* |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2490 | * In memory constrained environments, e.g. kdump kernel, the |
| 2491 | * DMA window can be larger than available memory, which will |
| 2492 | * cause errors later. |
| 2493 | */ |
Nishanth Aravamudan | fa14486 | 2015-09-04 11:22:52 -0700 | [diff] [blame] | 2494 | const u64 window_size = min((u64)pe->table_group.tce32_size, max_memory); |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2495 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2496 | rc = pnv_pci_ioda2_create_table(&pe->table_group, 0, |
| 2497 | IOMMU_PAGE_SHIFT_4K, |
Nishanth Aravamudan | bb00545 | 2015-09-02 08:39:28 -0700 | [diff] [blame] | 2498 | window_size, |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2499 | POWERNV_IOMMU_DEFAULT_LEVELS, &tbl); |
| 2500 | if (rc) { |
| 2501 | pe_err(pe, "Failed to create 32-bit TCE table, err %ld", |
| 2502 | rc); |
| 2503 | return rc; |
| 2504 | } |
| 2505 | |
| 2506 | iommu_init_table(tbl, pe->phb->hose->node); |
| 2507 | |
| 2508 | rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl); |
| 2509 | if (rc) { |
| 2510 | pe_err(pe, "Failed to configure 32-bit TCE table, err %ld\n", |
| 2511 | rc); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2512 | iommu_tce_table_put(tbl); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2513 | return rc; |
| 2514 | } |
| 2515 | |
| 2516 | if (!pnv_iommu_bypass_disabled) |
| 2517 | pnv_pci_ioda2_set_bypass(pe, true); |
| 2518 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2519 | /* |
| 2520 | * Setting table base here only for carrying iommu_group |
| 2521 | * further down to let iommu_add_device() do the job. |
| 2522 | * pnv_pci_ioda_dma_dev_setup will override it later anyway. |
| 2523 | */ |
| 2524 | if (pe->flags & PNV_IODA_PE_DEV) |
| 2525 | set_iommu_table_base(&pe->pdev->dev, tbl); |
| 2526 | |
| 2527 | return 0; |
| 2528 | } |
| 2529 | |
Alexey Kardashevskiy | b592643 | 2015-06-15 17:49:59 +1000 | [diff] [blame] | 2530 | #if defined(CONFIG_IOMMU_API) || defined(CONFIG_PCI_IOV) |
| 2531 | static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group, |
| 2532 | int num) |
| 2533 | { |
| 2534 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2535 | table_group); |
| 2536 | struct pnv_phb *phb = pe->phb; |
| 2537 | long ret; |
| 2538 | |
| 2539 | pe_info(pe, "Removing DMA window #%d\n", num); |
| 2540 | |
| 2541 | ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, |
| 2542 | (pe->pe_number << 1) + num, |
| 2543 | 0/* levels */, 0/* table address */, |
| 2544 | 0/* table size */, 0/* page size */); |
| 2545 | if (ret) |
| 2546 | pe_warn(pe, "Unmapping failed, ret = %ld\n", ret); |
| 2547 | else |
Michael Ellerman | ed7d9a1 | 2016-09-15 17:03:06 +1000 | [diff] [blame] | 2548 | pnv_pci_ioda2_tce_invalidate_pe(pe); |
Alexey Kardashevskiy | b592643 | 2015-06-15 17:49:59 +1000 | [diff] [blame] | 2549 | |
| 2550 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); |
| 2551 | |
| 2552 | return ret; |
| 2553 | } |
| 2554 | #endif |
| 2555 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2556 | #ifdef CONFIG_IOMMU_API |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2557 | static unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift, |
| 2558 | __u64 window_size, __u32 levels) |
| 2559 | { |
| 2560 | unsigned long bytes = 0; |
| 2561 | const unsigned window_shift = ilog2(window_size); |
| 2562 | unsigned entries_shift = window_shift - page_shift; |
| 2563 | unsigned table_shift = entries_shift + 3; |
| 2564 | unsigned long tce_table_size = max(0x1000UL, 1UL << table_shift); |
| 2565 | unsigned long direct_table_size; |
| 2566 | |
| 2567 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS) || |
| 2568 | (window_size > memory_hotplug_max()) || |
| 2569 | !is_power_of_2(window_size)) |
| 2570 | return 0; |
| 2571 | |
| 2572 | /* Calculate a direct table size from window_size and levels */ |
| 2573 | entries_shift = (entries_shift + levels - 1) / levels; |
| 2574 | table_shift = entries_shift + 3; |
| 2575 | table_shift = max_t(unsigned, table_shift, PAGE_SHIFT); |
| 2576 | direct_table_size = 1UL << table_shift; |
| 2577 | |
| 2578 | for ( ; levels; --levels) { |
| 2579 | bytes += _ALIGN_UP(tce_table_size, direct_table_size); |
| 2580 | |
| 2581 | tce_table_size /= direct_table_size; |
| 2582 | tce_table_size <<= 3; |
Alexey Kardashevskiy | e49a6a2 | 2017-04-13 17:05:27 +1000 | [diff] [blame] | 2583 | tce_table_size = max_t(unsigned long, |
| 2584 | tce_table_size, direct_table_size); |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2585 | } |
| 2586 | |
| 2587 | return bytes; |
| 2588 | } |
| 2589 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2590 | static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group) |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2591 | { |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2592 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2593 | table_group); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2594 | /* Store @tbl as pnv_pci_ioda2_unset_window() resets it */ |
| 2595 | struct iommu_table *tbl = pe->table_group.tables[0]; |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2596 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2597 | pnv_pci_ioda2_set_bypass(pe, false); |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2598 | pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2599 | if (pe->pbus) |
| 2600 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 2601 | iommu_tce_table_put(tbl); |
Benjamin Herrenschmidt | cd15b04 | 2014-02-11 11:32:38 +1100 | [diff] [blame] | 2602 | } |
| 2603 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2604 | static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group) |
| 2605 | { |
| 2606 | struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe, |
| 2607 | table_group); |
| 2608 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2609 | pnv_pci_ioda2_setup_default_config(pe); |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2610 | if (pe->pbus) |
| 2611 | pnv_ioda_setup_bus_dma(pe, pe->pbus, false); |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2612 | } |
| 2613 | |
| 2614 | static struct iommu_table_group_ops pnv_pci_ioda2_ops = { |
Alexey Kardashevskiy | 0054719 | 2015-06-05 16:35:22 +1000 | [diff] [blame] | 2615 | .get_table_size = pnv_pci_ioda2_get_table_size, |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2616 | .create_table = pnv_pci_ioda2_create_table, |
| 2617 | .set_window = pnv_pci_ioda2_set_window, |
| 2618 | .unset_window = pnv_pci_ioda2_unset_window, |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2619 | .take_ownership = pnv_ioda2_take_ownership, |
| 2620 | .release_ownership = pnv_ioda2_release_ownership, |
| 2621 | }; |
Alexey Kardashevskiy | b5cb9ab | 2016-04-29 18:55:24 +1000 | [diff] [blame] | 2622 | |
| 2623 | static int gpe_table_group_to_npe_cb(struct device *dev, void *opaque) |
| 2624 | { |
| 2625 | struct pci_controller *hose; |
| 2626 | struct pnv_phb *phb; |
| 2627 | struct pnv_ioda_pe **ptmppe = opaque; |
| 2628 | struct pci_dev *pdev = container_of(dev, struct pci_dev, dev); |
| 2629 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 2630 | |
| 2631 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 2632 | return 0; |
| 2633 | |
| 2634 | hose = pci_bus_to_host(pdev->bus); |
| 2635 | phb = hose->private_data; |
| 2636 | if (phb->type != PNV_PHB_NPU) |
| 2637 | return 0; |
| 2638 | |
| 2639 | *ptmppe = &phb->ioda.pe_array[pdn->pe_number]; |
| 2640 | |
| 2641 | return 1; |
| 2642 | } |
| 2643 | |
| 2644 | /* |
| 2645 | * This returns PE of associated NPU. |
| 2646 | * This assumes that NPU is in the same IOMMU group with GPU and there is |
| 2647 | * no other PEs. |
| 2648 | */ |
| 2649 | static struct pnv_ioda_pe *gpe_table_group_to_npe( |
| 2650 | struct iommu_table_group *table_group) |
| 2651 | { |
| 2652 | struct pnv_ioda_pe *npe = NULL; |
| 2653 | int ret = iommu_group_for_each_dev(table_group->group, &npe, |
| 2654 | gpe_table_group_to_npe_cb); |
| 2655 | |
| 2656 | BUG_ON(!ret || !npe); |
| 2657 | |
| 2658 | return npe; |
| 2659 | } |
| 2660 | |
| 2661 | static long pnv_pci_ioda2_npu_set_window(struct iommu_table_group *table_group, |
| 2662 | int num, struct iommu_table *tbl) |
| 2663 | { |
| 2664 | long ret = pnv_pci_ioda2_set_window(table_group, num, tbl); |
| 2665 | |
| 2666 | if (ret) |
| 2667 | return ret; |
| 2668 | |
| 2669 | ret = pnv_npu_set_window(gpe_table_group_to_npe(table_group), num, tbl); |
| 2670 | if (ret) |
| 2671 | pnv_pci_ioda2_unset_window(table_group, num); |
| 2672 | |
| 2673 | return ret; |
| 2674 | } |
| 2675 | |
| 2676 | static long pnv_pci_ioda2_npu_unset_window( |
| 2677 | struct iommu_table_group *table_group, |
| 2678 | int num) |
| 2679 | { |
| 2680 | long ret = pnv_pci_ioda2_unset_window(table_group, num); |
| 2681 | |
| 2682 | if (ret) |
| 2683 | return ret; |
| 2684 | |
| 2685 | return pnv_npu_unset_window(gpe_table_group_to_npe(table_group), num); |
| 2686 | } |
| 2687 | |
| 2688 | static void pnv_ioda2_npu_take_ownership(struct iommu_table_group *table_group) |
| 2689 | { |
| 2690 | /* |
| 2691 | * Detach NPU first as pnv_ioda2_take_ownership() will destroy |
| 2692 | * the iommu_table if 32bit DMA is enabled. |
| 2693 | */ |
| 2694 | pnv_npu_take_ownership(gpe_table_group_to_npe(table_group)); |
| 2695 | pnv_ioda2_take_ownership(table_group); |
| 2696 | } |
| 2697 | |
| 2698 | static struct iommu_table_group_ops pnv_pci_ioda2_npu_ops = { |
| 2699 | .get_table_size = pnv_pci_ioda2_get_table_size, |
| 2700 | .create_table = pnv_pci_ioda2_create_table, |
| 2701 | .set_window = pnv_pci_ioda2_npu_set_window, |
| 2702 | .unset_window = pnv_pci_ioda2_npu_unset_window, |
| 2703 | .take_ownership = pnv_ioda2_npu_take_ownership, |
| 2704 | .release_ownership = pnv_ioda2_release_ownership, |
| 2705 | }; |
| 2706 | |
| 2707 | static void pnv_pci_ioda_setup_iommu_api(void) |
| 2708 | { |
| 2709 | struct pci_controller *hose, *tmp; |
| 2710 | struct pnv_phb *phb; |
| 2711 | struct pnv_ioda_pe *pe, *gpe; |
| 2712 | |
| 2713 | /* |
| 2714 | * Now we have all PHBs discovered, time to add NPU devices to |
| 2715 | * the corresponding IOMMU groups. |
| 2716 | */ |
| 2717 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
| 2718 | phb = hose->private_data; |
| 2719 | |
| 2720 | if (phb->type != PNV_PHB_NPU) |
| 2721 | continue; |
| 2722 | |
| 2723 | list_for_each_entry(pe, &phb->ioda.pe_list, list) { |
| 2724 | gpe = pnv_pci_npu_setup_iommu(pe); |
| 2725 | if (gpe) |
| 2726 | gpe->table_group.ops = &pnv_pci_ioda2_npu_ops; |
| 2727 | } |
| 2728 | } |
| 2729 | } |
| 2730 | #else /* !CONFIG_IOMMU_API */ |
| 2731 | static void pnv_pci_ioda_setup_iommu_api(void) { }; |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2732 | #endif |
| 2733 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2734 | static __be64 *pnv_pci_ioda2_table_do_alloc_pages(int nid, unsigned shift, |
| 2735 | unsigned levels, unsigned long limit, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2736 | unsigned long *current_offset, unsigned long *total_allocated) |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2737 | { |
| 2738 | struct page *tce_mem = NULL; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2739 | __be64 *addr, *tmp; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2740 | unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2741 | unsigned long allocated = 1UL << (order + PAGE_SHIFT); |
| 2742 | unsigned entries = 1UL << (shift - 3); |
| 2743 | long i; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2744 | |
| 2745 | tce_mem = alloc_pages_node(nid, GFP_KERNEL, order); |
| 2746 | if (!tce_mem) { |
| 2747 | pr_err("Failed to allocate a TCE memory, order=%d\n", order); |
| 2748 | return NULL; |
| 2749 | } |
| 2750 | addr = page_address(tce_mem); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2751 | memset(addr, 0, allocated); |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2752 | *total_allocated += allocated; |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2753 | |
| 2754 | --levels; |
| 2755 | if (!levels) { |
| 2756 | *current_offset += allocated; |
| 2757 | return addr; |
| 2758 | } |
| 2759 | |
| 2760 | for (i = 0; i < entries; ++i) { |
| 2761 | tmp = pnv_pci_ioda2_table_do_alloc_pages(nid, shift, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2762 | levels, limit, current_offset, total_allocated); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2763 | if (!tmp) |
| 2764 | break; |
| 2765 | |
| 2766 | addr[i] = cpu_to_be64(__pa(tmp) | |
| 2767 | TCE_PCI_READ | TCE_PCI_WRITE); |
| 2768 | |
| 2769 | if (*current_offset >= limit) |
| 2770 | break; |
| 2771 | } |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2772 | |
| 2773 | return addr; |
| 2774 | } |
| 2775 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2776 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
| 2777 | unsigned long size, unsigned level); |
| 2778 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2779 | static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset, |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2780 | __u32 page_shift, __u64 window_size, __u32 levels, |
| 2781 | struct iommu_table *tbl) |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2782 | { |
| 2783 | void *addr; |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2784 | unsigned long offset = 0, level_shift, total_allocated = 0; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2785 | const unsigned window_shift = ilog2(window_size); |
| 2786 | unsigned entries_shift = window_shift - page_shift; |
| 2787 | unsigned table_shift = max_t(unsigned, entries_shift + 3, PAGE_SHIFT); |
| 2788 | const unsigned long tce_table_size = 1UL << table_shift; |
| 2789 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2790 | if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS)) |
| 2791 | return -EINVAL; |
| 2792 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2793 | if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size)) |
| 2794 | return -EINVAL; |
| 2795 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2796 | /* Adjust direct table size from window_size and levels */ |
| 2797 | entries_shift = (entries_shift + levels - 1) / levels; |
| 2798 | level_shift = entries_shift + 3; |
| 2799 | level_shift = max_t(unsigned, level_shift, PAGE_SHIFT); |
| 2800 | |
Alexey Kardashevskiy | 8deb580 | 2018-06-01 18:06:16 +1000 | [diff] [blame] | 2801 | if ((level_shift - 3) * levels + page_shift >= 55) |
Alexey Kardashevskiy | 7aafac1 | 2017-02-22 15:43:59 +1100 | [diff] [blame] | 2802 | return -EINVAL; |
| 2803 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2804 | /* Allocate TCE table */ |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2805 | addr = pnv_pci_ioda2_table_do_alloc_pages(nid, level_shift, |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2806 | levels, tce_table_size, &offset, &total_allocated); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2807 | |
| 2808 | /* addr==NULL means that the first level allocation failed */ |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2809 | if (!addr) |
| 2810 | return -ENOMEM; |
| 2811 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2812 | /* |
| 2813 | * First level was allocated but some lower level failed as |
| 2814 | * we did not allocate as much as we wanted, |
| 2815 | * release partially allocated table. |
| 2816 | */ |
| 2817 | if (offset < tce_table_size) { |
| 2818 | pnv_pci_ioda2_table_do_free_pages(addr, |
| 2819 | 1ULL << (level_shift - 3), levels - 1); |
| 2820 | return -ENOMEM; |
| 2821 | } |
| 2822 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2823 | /* Setup linux iommu table */ |
| 2824 | pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, bus_offset, |
| 2825 | page_shift); |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2826 | tbl->it_level_size = 1ULL << (level_shift - 3); |
| 2827 | tbl->it_indirect_levels = levels - 1; |
Alexey Kardashevskiy | 3ba3a73 | 2015-07-20 20:45:51 +1000 | [diff] [blame] | 2828 | tbl->it_allocated_size = total_allocated; |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2829 | |
| 2830 | pr_devel("Created TCE table: ws=%08llx ts=%lx @%08llx\n", |
| 2831 | window_size, tce_table_size, bus_offset); |
| 2832 | |
| 2833 | return 0; |
| 2834 | } |
| 2835 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2836 | static void pnv_pci_ioda2_table_do_free_pages(__be64 *addr, |
| 2837 | unsigned long size, unsigned level) |
| 2838 | { |
| 2839 | const unsigned long addr_ul = (unsigned long) addr & |
| 2840 | ~(TCE_PCI_READ | TCE_PCI_WRITE); |
| 2841 | |
| 2842 | if (level) { |
| 2843 | long i; |
| 2844 | u64 *tmp = (u64 *) addr_ul; |
| 2845 | |
| 2846 | for (i = 0; i < size; ++i) { |
| 2847 | unsigned long hpa = be64_to_cpu(tmp[i]); |
| 2848 | |
| 2849 | if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE))) |
| 2850 | continue; |
| 2851 | |
| 2852 | pnv_pci_ioda2_table_do_free_pages(__va(hpa), size, |
| 2853 | level - 1); |
| 2854 | } |
| 2855 | } |
| 2856 | |
| 2857 | free_pages(addr_ul, get_order(size << 3)); |
| 2858 | } |
| 2859 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2860 | static void pnv_pci_ioda2_table_free_pages(struct iommu_table *tbl) |
| 2861 | { |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2862 | const unsigned long size = tbl->it_indirect_levels ? |
| 2863 | tbl->it_level_size : tbl->it_size; |
| 2864 | |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2865 | if (!tbl->it_size) |
| 2866 | return; |
| 2867 | |
Alexey Kardashevskiy | bbb845c | 2015-06-05 16:35:19 +1000 | [diff] [blame] | 2868 | pnv_pci_ioda2_table_do_free_pages((__be64 *)tbl->it_base, size, |
| 2869 | tbl->it_indirect_levels); |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2870 | } |
| 2871 | |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2872 | static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb, |
| 2873 | struct pnv_ioda_pe *pe) |
| 2874 | { |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2875 | int64_t rc; |
| 2876 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 2877 | if (!pnv_pci_ioda_pe_dma_weight(pe)) |
| 2878 | return; |
| 2879 | |
Alexey Kardashevskiy | f87a886 | 2015-06-05 16:35:10 +1000 | [diff] [blame] | 2880 | /* TVE #1 is selected by PCI address bit 59 */ |
| 2881 | pe->tce_bypass_base = 1ull << 59; |
| 2882 | |
Alexey Kardashevskiy | b348aa6 | 2015-06-05 16:35:08 +1000 | [diff] [blame] | 2883 | iommu_register_group(&pe->table_group, phb->hose->global_number, |
| 2884 | pe->pe_number); |
Alexey Kardashevskiy | c577382 | 2015-06-05 16:34:55 +1000 | [diff] [blame] | 2885 | |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2886 | /* The PE will reserve all possible 32-bits space */ |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2887 | pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n", |
Alexey Kardashevskiy | aca6913 | 2015-06-05 16:35:17 +1000 | [diff] [blame] | 2888 | phb->ioda.m32_pci_base); |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2889 | |
Alexey Kardashevskiy | e5aad1e | 2015-06-05 16:35:16 +1000 | [diff] [blame] | 2890 | /* Setup linux iommu table */ |
Alexey Kardashevskiy | 4793d65 | 2015-06-05 16:35:20 +1000 | [diff] [blame] | 2891 | pe->table_group.tce32_start = 0; |
| 2892 | pe->table_group.tce32_size = phb->ioda.m32_pci_base; |
| 2893 | pe->table_group.max_dynamic_windows_supported = |
| 2894 | IOMMU_TABLE_GROUP_MAX_TABLES; |
| 2895 | pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS; |
| 2896 | pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M; |
Alexey Kardashevskiy | e5aad1e | 2015-06-05 16:35:16 +1000 | [diff] [blame] | 2897 | #ifdef CONFIG_IOMMU_API |
| 2898 | pe->table_group.ops = &pnv_pci_ioda2_ops; |
| 2899 | #endif |
| 2900 | |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2901 | rc = pnv_pci_ioda2_setup_default_config(pe); |
Gavin Shan | 801846d | 2016-05-03 15:41:34 +1000 | [diff] [blame] | 2902 | if (rc) |
Alexey Kardashevskiy | 46d3e1e | 2015-06-05 16:35:23 +1000 | [diff] [blame] | 2903 | return; |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2904 | |
Alexey Kardashevskiy | 20f13b9 | 2017-02-21 13:40:20 +1100 | [diff] [blame] | 2905 | if (pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL)) |
Alexey Kardashevskiy | db08e1d | 2017-02-21 13:41:31 +1100 | [diff] [blame] | 2906 | pnv_ioda_setup_bus_dma(pe, pe->pbus, true); |
Gavin Shan | 373f565 | 2013-04-25 19:21:01 +0000 | [diff] [blame] | 2907 | } |
| 2908 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2909 | #ifdef CONFIG_PCI_MSI |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 2910 | int64_t pnv_opal_pci_msi_eoi(struct irq_chip *chip, unsigned int hw_irq) |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2911 | { |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2912 | struct pnv_phb *phb = container_of(chip, struct pnv_phb, |
| 2913 | ioda.irq_chip); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2914 | |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 2915 | return opal_pci_msi_eoi(phb->opal_id, hw_irq); |
| 2916 | } |
| 2917 | |
| 2918 | static void pnv_ioda2_msi_eoi(struct irq_data *d) |
| 2919 | { |
| 2920 | int64_t rc; |
| 2921 | unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d); |
| 2922 | struct irq_chip *chip = irq_data_get_irq_chip(d); |
| 2923 | |
| 2924 | rc = pnv_opal_pci_msi_eoi(chip, hw_irq); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2925 | WARN_ON_ONCE(rc); |
| 2926 | |
| 2927 | icp_native_eoi(d); |
| 2928 | } |
| 2929 | |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 2930 | |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 2931 | void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq) |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 2932 | { |
| 2933 | struct irq_data *idata; |
| 2934 | struct irq_chip *ichip; |
| 2935 | |
Benjamin Herrenschmidt | fb11133 | 2016-07-08 16:37:09 +1000 | [diff] [blame] | 2936 | /* The MSI EOI OPAL call is only needed on PHB3 */ |
| 2937 | if (phb->model != PNV_PHB_MODEL_PHB3) |
Ian Munsie | fd9a1c2 | 2014-10-08 19:54:55 +1100 | [diff] [blame] | 2938 | return; |
| 2939 | |
| 2940 | if (!phb->ioda.irq_chip_init) { |
| 2941 | /* |
| 2942 | * First time we setup an MSI IRQ, we need to setup the |
| 2943 | * corresponding IRQ chip to route correctly. |
| 2944 | */ |
| 2945 | idata = irq_get_irq_data(virq); |
| 2946 | ichip = irq_data_get_irq_chip(idata); |
| 2947 | phb->ioda.irq_chip_init = 1; |
| 2948 | phb->ioda.irq_chip = *ichip; |
| 2949 | phb->ioda.irq_chip.irq_eoi = pnv_ioda2_msi_eoi; |
| 2950 | } |
| 2951 | irq_set_chip(virq, &phb->ioda.irq_chip); |
| 2952 | } |
| 2953 | |
Suresh Warrier | 4ee11c1 | 2016-08-19 15:35:49 +1000 | [diff] [blame] | 2954 | /* |
| 2955 | * Returns true iff chip is something that we could call |
| 2956 | * pnv_opal_pci_msi_eoi for. |
| 2957 | */ |
| 2958 | bool is_pnv_opal_msi(struct irq_chip *chip) |
| 2959 | { |
| 2960 | return chip->irq_eoi == pnv_ioda2_msi_eoi; |
| 2961 | } |
| 2962 | EXPORT_SYMBOL_GPL(is_pnv_opal_msi); |
| 2963 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2964 | static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev, |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 2965 | unsigned int hwirq, unsigned int virq, |
| 2966 | unsigned int is_64, struct msi_msg *msg) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2967 | { |
| 2968 | struct pnv_ioda_pe *pe = pnv_ioda_get_pe(dev); |
| 2969 | unsigned int xive_num = hwirq - phb->msi_base; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 2970 | __be32 data; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2971 | int rc; |
| 2972 | |
| 2973 | /* No PE assigned ? bail out ... no MSI for you ! */ |
| 2974 | if (pe == NULL) |
| 2975 | return -ENXIO; |
| 2976 | |
| 2977 | /* Check if we have an MVE */ |
| 2978 | if (pe->mve_number < 0) |
| 2979 | return -ENXIO; |
| 2980 | |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 2981 | /* Force 32-bit MSI on some broken devices */ |
Benjamin Herrenschmidt | 3607438 | 2014-10-07 16:12:36 +1100 | [diff] [blame] | 2982 | if (dev->no_64bit_msi) |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 2983 | is_64 = 0; |
| 2984 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2985 | /* Assign XIVE to PE */ |
| 2986 | rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num); |
| 2987 | if (rc) { |
| 2988 | pr_warn("%s: OPAL error %d setting XIVE %d PE\n", |
| 2989 | pci_name(dev), rc, xive_num); |
| 2990 | return -EIO; |
| 2991 | } |
| 2992 | |
| 2993 | if (is_64) { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 2994 | __be64 addr64; |
| 2995 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 2996 | rc = opal_get_msi_64(phb->opal_id, pe->mve_number, xive_num, 1, |
| 2997 | &addr64, &data); |
| 2998 | if (rc) { |
| 2999 | pr_warn("%s: OPAL error %d getting 64-bit MSI data\n", |
| 3000 | pci_name(dev), rc); |
| 3001 | return -EIO; |
| 3002 | } |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3003 | msg->address_hi = be64_to_cpu(addr64) >> 32; |
| 3004 | msg->address_lo = be64_to_cpu(addr64) & 0xfffffffful; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3005 | } else { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3006 | __be32 addr32; |
| 3007 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3008 | rc = opal_get_msi_32(phb->opal_id, pe->mve_number, xive_num, 1, |
| 3009 | &addr32, &data); |
| 3010 | if (rc) { |
| 3011 | pr_warn("%s: OPAL error %d getting 32-bit MSI data\n", |
| 3012 | pci_name(dev), rc); |
| 3013 | return -EIO; |
| 3014 | } |
| 3015 | msg->address_hi = 0; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3016 | msg->address_lo = be32_to_cpu(addr32); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3017 | } |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3018 | msg->data = be32_to_cpu(data); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3019 | |
Ian Munsie | f456834 | 2016-07-14 07:17:00 +1000 | [diff] [blame] | 3020 | pnv_set_msi_irq_chip(phb, virq); |
Gavin Shan | 137436c | 2013-04-25 19:20:59 +0000 | [diff] [blame] | 3021 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3022 | pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d)," |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3023 | " address=%x_%08x data=%x PE# %x\n", |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3024 | pci_name(dev), is_64 ? "64" : "32", hwirq, xive_num, |
| 3025 | msg->address_hi, msg->address_lo, data, pe->pe_number); |
| 3026 | |
| 3027 | return 0; |
| 3028 | } |
| 3029 | |
| 3030 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) |
| 3031 | { |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3032 | unsigned int count; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3033 | const __be32 *prop = of_get_property(phb->hose->dn, |
| 3034 | "ibm,opal-msi-ranges", NULL); |
| 3035 | if (!prop) { |
| 3036 | /* BML Fallback */ |
| 3037 | prop = of_get_property(phb->hose->dn, "msi-ranges", NULL); |
| 3038 | } |
| 3039 | if (!prop) |
| 3040 | return; |
| 3041 | |
| 3042 | phb->msi_base = be32_to_cpup(prop); |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3043 | count = be32_to_cpup(prop + 1); |
| 3044 | if (msi_bitmap_alloc(&phb->msi_bmp, count, phb->hose->dn)) { |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3045 | pr_err("PCI %d: Failed to allocate MSI bitmap !\n", |
| 3046 | phb->hose->global_number); |
| 3047 | return; |
| 3048 | } |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3049 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3050 | phb->msi_setup = pnv_pci_ioda_msi_setup; |
| 3051 | phb->msi32_support = 1; |
| 3052 | pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n", |
Gavin Shan | fb1b55d | 2013-03-05 21:12:37 +0000 | [diff] [blame] | 3053 | count, phb->msi_base); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3054 | } |
| 3055 | #else |
| 3056 | static void pnv_pci_init_ioda_msis(struct pnv_phb *phb) { } |
| 3057 | #endif /* CONFIG_PCI_MSI */ |
| 3058 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3059 | #ifdef CONFIG_PCI_IOV |
| 3060 | static void pnv_pci_ioda_fixup_iov_resources(struct pci_dev *pdev) |
| 3061 | { |
Wei Yang | f2dd0af | 2015-10-22 09:22:17 +0800 | [diff] [blame] | 3062 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3063 | struct pnv_phb *phb = hose->private_data; |
| 3064 | const resource_size_t gate = phb->ioda.m64_segsize >> 2; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3065 | struct resource *res; |
| 3066 | int i; |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3067 | resource_size_t size, total_vf_bar_sz; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3068 | struct pci_dn *pdn; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3069 | int mul, total_vfs; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3070 | |
| 3071 | if (!pdev->is_physfn || pdev->is_added) |
| 3072 | return; |
| 3073 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3074 | pdn = pci_get_pdn(pdev); |
| 3075 | pdn->vfs_expanded = 0; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3076 | pdn->m64_single_mode = false; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3077 | |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3078 | total_vfs = pci_sriov_get_totalvfs(pdev); |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3079 | mul = phb->ioda.total_pe_num; |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3080 | total_vf_bar_sz = 0; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3081 | |
| 3082 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3083 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3084 | if (!res->flags || res->parent) |
| 3085 | continue; |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 3086 | if (!pnv_pci_is_m64_flags(res->flags)) { |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3087 | dev_warn(&pdev->dev, "Don't support SR-IOV with" |
| 3088 | " non M64 VF BAR%d: %pR. \n", |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3089 | i, res); |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3090 | goto truncate_iov; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3091 | } |
| 3092 | |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3093 | total_vf_bar_sz += pci_iov_resource_size(pdev, |
| 3094 | i + PCI_IOV_RESOURCES); |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3095 | |
Wei Yang | f2dd0af | 2015-10-22 09:22:17 +0800 | [diff] [blame] | 3096 | /* |
| 3097 | * If bigger than quarter of M64 segment size, just round up |
| 3098 | * power of two. |
| 3099 | * |
| 3100 | * Generally, one M64 BAR maps one IOV BAR. To avoid conflict |
| 3101 | * with other devices, IOV BAR size is expanded to be |
| 3102 | * (total_pe * VF_BAR_size). When VF_BAR_size is half of M64 |
| 3103 | * segment size , the expanded size would equal to half of the |
| 3104 | * whole M64 space size, which will exhaust the M64 Space and |
| 3105 | * limit the system flexibility. This is a design decision to |
| 3106 | * set the boundary to quarter of the M64 segment size. |
| 3107 | */ |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3108 | if (total_vf_bar_sz > gate) { |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3109 | mul = roundup_pow_of_two(total_vfs); |
Wei Yang | dfcc8d4 | 2015-10-22 09:22:18 +0800 | [diff] [blame] | 3110 | dev_info(&pdev->dev, |
| 3111 | "VF BAR Total IOV size %llx > %llx, roundup to %d VFs\n", |
| 3112 | total_vf_bar_sz, gate, mul); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3113 | pdn->m64_single_mode = true; |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3114 | break; |
| 3115 | } |
| 3116 | } |
| 3117 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3118 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3119 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3120 | if (!res->flags || res->parent) |
| 3121 | continue; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3122 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3123 | size = pci_iov_resource_size(pdev, i + PCI_IOV_RESOURCES); |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3124 | /* |
| 3125 | * On PHB3, the minimum size alignment of M64 BAR in single |
| 3126 | * mode is 32MB. |
| 3127 | */ |
| 3128 | if (pdn->m64_single_mode && (size < SZ_32M)) |
| 3129 | goto truncate_iov; |
| 3130 | dev_dbg(&pdev->dev, " Fixing VF BAR%d: %pR to\n", i, res); |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3131 | res->end = res->start + size * mul - 1; |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3132 | dev_dbg(&pdev->dev, " %pR\n", res); |
| 3133 | dev_info(&pdev->dev, "VF BAR%d: %pR (expanded to %d VFs for PE alignment)", |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3134 | i, res, mul); |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3135 | } |
Wei Yang | 5b88ec2 | 2015-03-25 16:23:58 +0800 | [diff] [blame] | 3136 | pdn->vfs_expanded = mul; |
Wei Yang | b033185 | 2015-10-22 09:22:14 +0800 | [diff] [blame] | 3137 | |
| 3138 | return; |
| 3139 | |
| 3140 | truncate_iov: |
| 3141 | /* To save MMIO space, IOV BAR is truncated. */ |
| 3142 | for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { |
| 3143 | res = &pdev->resource[i + PCI_IOV_RESOURCES]; |
| 3144 | res->flags = 0; |
| 3145 | res->end = res->start - 1; |
| 3146 | } |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 3147 | } |
| 3148 | #endif /* CONFIG_PCI_IOV */ |
| 3149 | |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3150 | static void pnv_ioda_setup_pe_res(struct pnv_ioda_pe *pe, |
| 3151 | struct resource *res) |
| 3152 | { |
| 3153 | struct pnv_phb *phb = pe->phb; |
| 3154 | struct pci_bus_region region; |
| 3155 | int index; |
| 3156 | int64_t rc; |
| 3157 | |
Frederic Barrat | 887084d | 2023-01-20 10:32:15 +0100 | [diff] [blame] | 3158 | if (!res || !res->flags || res->start > res->end || |
| 3159 | res->flags & IORESOURCE_UNSET) |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3160 | return; |
| 3161 | |
| 3162 | if (res->flags & IORESOURCE_IO) { |
| 3163 | region.start = res->start - phb->ioda.io_pci_base; |
| 3164 | region.end = res->end - phb->ioda.io_pci_base; |
| 3165 | index = region.start / phb->ioda.io_segsize; |
| 3166 | |
| 3167 | while (index < phb->ioda.total_pe_num && |
| 3168 | region.start <= region.end) { |
| 3169 | phb->ioda.io_segmap[index] = pe->pe_number; |
| 3170 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3171 | pe->pe_number, OPAL_IO_WINDOW_TYPE, 0, index); |
| 3172 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3173 | pr_err("%s: Error %lld mapping IO segment#%d to PE#%x\n", |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3174 | __func__, rc, index, pe->pe_number); |
| 3175 | break; |
| 3176 | } |
| 3177 | |
| 3178 | region.start += phb->ioda.io_segsize; |
| 3179 | index++; |
| 3180 | } |
| 3181 | } else if ((res->flags & IORESOURCE_MEM) && |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3182 | !pnv_pci_is_m64(phb, res)) { |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3183 | region.start = res->start - |
| 3184 | phb->hose->mem_offset[0] - |
| 3185 | phb->ioda.m32_pci_base; |
| 3186 | region.end = res->end - |
| 3187 | phb->hose->mem_offset[0] - |
| 3188 | phb->ioda.m32_pci_base; |
| 3189 | index = region.start / phb->ioda.m32_segsize; |
| 3190 | |
| 3191 | while (index < phb->ioda.total_pe_num && |
| 3192 | region.start <= region.end) { |
| 3193 | phb->ioda.m32_segmap[index] = pe->pe_number; |
| 3194 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3195 | pe->pe_number, OPAL_M32_WINDOW_TYPE, 0, index); |
| 3196 | if (rc != OPAL_SUCCESS) { |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3197 | pr_err("%s: Error %lld mapping M32 segment#%d to PE#%x", |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3198 | __func__, rc, index, pe->pe_number); |
| 3199 | break; |
| 3200 | } |
| 3201 | |
| 3202 | region.start += phb->ioda.m32_segsize; |
| 3203 | index++; |
| 3204 | } |
| 3205 | } |
| 3206 | } |
| 3207 | |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3208 | /* |
| 3209 | * This function is supposed to be called on basis of PE from top |
| 3210 | * to bottom style. So the the I/O or MMIO segment assigned to |
Masahiro Yamada | 0367105 | 2017-02-27 14:29:28 -0800 | [diff] [blame] | 3211 | * parent PE could be overridden by its child PEs if necessary. |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3212 | */ |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3213 | static void pnv_ioda_setup_pe_seg(struct pnv_ioda_pe *pe) |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3214 | { |
Gavin Shan | 69d733e | 2016-05-03 15:41:28 +1000 | [diff] [blame] | 3215 | struct pci_dev *pdev; |
Gavin Shan | 23e7942 | 2016-05-03 15:41:27 +1000 | [diff] [blame] | 3216 | int i; |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3217 | |
| 3218 | /* |
| 3219 | * NOTE: We only care PCI bus based PE for now. For PCI |
| 3220 | * device based PE, for example SRIOV sensitive VF should |
| 3221 | * be figured out later. |
| 3222 | */ |
| 3223 | BUG_ON(!(pe->flags & (PNV_IODA_PE_BUS | PNV_IODA_PE_BUS_ALL))); |
| 3224 | |
Gavin Shan | 69d733e | 2016-05-03 15:41:28 +1000 | [diff] [blame] | 3225 | list_for_each_entry(pdev, &pe->pbus->devices, bus_list) { |
| 3226 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) |
| 3227 | pnv_ioda_setup_pe_res(pe, &pdev->resource[i]); |
| 3228 | |
| 3229 | /* |
| 3230 | * If the PE contains all subordinate PCI buses, the |
| 3231 | * windows of the child bridges should be mapped to |
| 3232 | * the PE as well. |
| 3233 | */ |
| 3234 | if (!(pe->flags & PNV_IODA_PE_BUS_ALL) || !pci_is_bridge(pdev)) |
| 3235 | continue; |
| 3236 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) |
| 3237 | pnv_ioda_setup_pe_res(pe, |
| 3238 | &pdev->resource[PCI_BRIDGE_RESOURCES + i]); |
| 3239 | } |
Gavin Shan | 11685be | 2012-08-20 03:49:16 +0000 | [diff] [blame] | 3240 | } |
| 3241 | |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3242 | #ifdef CONFIG_DEBUG_FS |
| 3243 | static int pnv_pci_diag_data_set(void *data, u64 val) |
| 3244 | { |
| 3245 | struct pci_controller *hose; |
| 3246 | struct pnv_phb *phb; |
| 3247 | s64 ret; |
| 3248 | |
| 3249 | if (val != 1ULL) |
| 3250 | return -EINVAL; |
| 3251 | |
| 3252 | hose = (struct pci_controller *)data; |
| 3253 | if (!hose || !hose->private_data) |
| 3254 | return -ENODEV; |
| 3255 | |
| 3256 | phb = hose->private_data; |
| 3257 | |
| 3258 | /* Retrieve the diag data from firmware */ |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3259 | ret = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag_data, |
| 3260 | phb->diag_data_size); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3261 | if (ret != OPAL_SUCCESS) |
| 3262 | return -EIO; |
| 3263 | |
| 3264 | /* Print the diag data to the kernel log */ |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3265 | pnv_pci_dump_phb_diag_data(phb->hose, phb->diag_data); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3266 | return 0; |
| 3267 | } |
| 3268 | |
| 3269 | DEFINE_SIMPLE_ATTRIBUTE(pnv_pci_diag_data_fops, NULL, |
| 3270 | pnv_pci_diag_data_set, "%llu\n"); |
| 3271 | |
| 3272 | #endif /* CONFIG_DEBUG_FS */ |
| 3273 | |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3274 | static void pnv_pci_ioda_create_dbgfs(void) |
| 3275 | { |
| 3276 | #ifdef CONFIG_DEBUG_FS |
| 3277 | struct pci_controller *hose, *tmp; |
| 3278 | struct pnv_phb *phb; |
| 3279 | char name[16]; |
| 3280 | |
| 3281 | list_for_each_entry_safe(hose, tmp, &hose_list, list_node) { |
| 3282 | phb = hose->private_data; |
| 3283 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3284 | /* Notify initialization of PHB done */ |
| 3285 | phb->initialized = 1; |
| 3286 | |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3287 | sprintf(name, "PCI%04x", hose->global_number); |
| 3288 | phb->dbgfs = debugfs_create_dir(name, powerpc_debugfs_root); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3289 | if (!phb->dbgfs) { |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3290 | pr_warning("%s: Error on creating debugfs on PHB#%x\n", |
| 3291 | __func__, hose->global_number); |
Russell Currey | 98b665d | 2016-07-28 15:05:03 +1000 | [diff] [blame] | 3292 | continue; |
| 3293 | } |
| 3294 | |
| 3295 | debugfs_create_file("dump_diag_regs", 0200, phb->dbgfs, hose, |
| 3296 | &pnv_pci_diag_data_fops); |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3297 | } |
| 3298 | #endif /* CONFIG_DEBUG_FS */ |
| 3299 | } |
| 3300 | |
Benjamin Herrenschmidt | 1eb08e7 | 2018-08-17 17:30:39 +1000 | [diff] [blame] | 3301 | static void pnv_pci_enable_bridge(struct pci_bus *bus) |
| 3302 | { |
| 3303 | struct pci_dev *dev = bus->self; |
| 3304 | struct pci_bus *child; |
| 3305 | |
| 3306 | /* Empty bus ? bail */ |
| 3307 | if (list_empty(&bus->devices)) |
| 3308 | return; |
| 3309 | |
| 3310 | /* |
| 3311 | * If there's a bridge associated with that bus enable it. This works |
| 3312 | * around races in the generic code if the enabling is done during |
| 3313 | * parallel probing. This can be removed once those races have been |
| 3314 | * fixed. |
| 3315 | */ |
| 3316 | if (dev) { |
| 3317 | int rc = pci_enable_device(dev); |
| 3318 | if (rc) |
| 3319 | pci_err(dev, "Error enabling bridge (%d)\n", rc); |
| 3320 | pci_set_master(dev); |
| 3321 | } |
| 3322 | |
| 3323 | /* Perform the same to child busses */ |
| 3324 | list_for_each_entry(child, &bus->children, node) |
| 3325 | pnv_pci_enable_bridge(child); |
| 3326 | } |
| 3327 | |
| 3328 | static void pnv_pci_enable_bridges(void) |
| 3329 | { |
| 3330 | struct pci_controller *hose; |
| 3331 | |
| 3332 | list_for_each_entry(hose, &hose_list, list_node) |
| 3333 | pnv_pci_enable_bridge(hose->bus); |
| 3334 | } |
| 3335 | |
Greg Kroah-Hartman | cad5cef | 2012-12-21 14:04:10 -0800 | [diff] [blame] | 3336 | static void pnv_pci_ioda_fixup(void) |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 3337 | { |
| 3338 | pnv_pci_ioda_setup_PEs(); |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3339 | pnv_pci_ioda_setup_iommu_api(); |
Gavin Shan | 37c367f | 2013-06-20 18:13:25 +0800 | [diff] [blame] | 3340 | pnv_pci_ioda_create_dbgfs(); |
| 3341 | |
Benjamin Herrenschmidt | 1eb08e7 | 2018-08-17 17:30:39 +1000 | [diff] [blame] | 3342 | pnv_pci_enable_bridges(); |
| 3343 | |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3344 | #ifdef CONFIG_EEH |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3345 | eeh_init(); |
Mike Qiu | dadcd6d | 2014-06-26 02:58:47 -0400 | [diff] [blame] | 3346 | eeh_addr_cache_build(); |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3347 | #endif |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 3348 | } |
| 3349 | |
Gavin Shan | 271fd03 | 2012-09-11 16:59:47 -0600 | [diff] [blame] | 3350 | /* |
| 3351 | * Returns the alignment for I/O or memory windows for P2P |
| 3352 | * bridges. That actually depends on how PEs are segmented. |
| 3353 | * For now, we return I/O or M32 segment size for PE sensitive |
| 3354 | * P2P bridges. Otherwise, the default values (4KiB for I/O, |
| 3355 | * 1MiB for memory) will be returned. |
| 3356 | * |
| 3357 | * The current PCI bus might be put into one PE, which was |
| 3358 | * create against the parent PCI bridge. For that case, we |
| 3359 | * needn't enlarge the alignment so that we can save some |
| 3360 | * resources. |
| 3361 | */ |
| 3362 | static resource_size_t pnv_pci_window_alignment(struct pci_bus *bus, |
| 3363 | unsigned long type) |
| 3364 | { |
| 3365 | struct pci_dev *bridge; |
| 3366 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3367 | struct pnv_phb *phb = hose->private_data; |
| 3368 | int num_pci_bridges = 0; |
| 3369 | |
| 3370 | bridge = bus->self; |
| 3371 | while (bridge) { |
| 3372 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) { |
| 3373 | num_pci_bridges++; |
| 3374 | if (num_pci_bridges >= 2) |
| 3375 | return 1; |
| 3376 | } |
| 3377 | |
| 3378 | bridge = bridge->bus->self; |
| 3379 | } |
| 3380 | |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3381 | /* |
| 3382 | * We fall back to M32 if M64 isn't supported. We enforce the M64 |
| 3383 | * alignment for any 64-bit resource, PCIe doesn't care and |
| 3384 | * bridges only do 64-bit prefetchable anyway. |
| 3385 | */ |
Russell Currey | b79331a | 2016-09-14 16:37:17 +1000 | [diff] [blame] | 3386 | if (phb->ioda.m64_segsize && pnv_pci_is_m64_flags(type)) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3387 | return phb->ioda.m64_segsize; |
Gavin Shan | 271fd03 | 2012-09-11 16:59:47 -0600 | [diff] [blame] | 3388 | if (type & IORESOURCE_MEM) |
| 3389 | return phb->ioda.m32_segsize; |
| 3390 | |
| 3391 | return phb->ioda.io_segsize; |
| 3392 | } |
| 3393 | |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3394 | /* |
| 3395 | * We are updating root port or the upstream port of the |
| 3396 | * bridge behind the root port with PHB's windows in order |
| 3397 | * to accommodate the changes on required resources during |
| 3398 | * PCI (slot) hotplug, which is connected to either root |
| 3399 | * port or the downstream ports of PCIe switch behind the |
| 3400 | * root port. |
| 3401 | */ |
| 3402 | static void pnv_pci_fixup_bridge_resources(struct pci_bus *bus, |
| 3403 | unsigned long type) |
| 3404 | { |
| 3405 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3406 | struct pnv_phb *phb = hose->private_data; |
| 3407 | struct pci_dev *bridge = bus->self; |
| 3408 | struct resource *r, *w; |
| 3409 | bool msi_region = false; |
| 3410 | int i; |
| 3411 | |
| 3412 | /* Check if we need apply fixup to the bridge's windows */ |
| 3413 | if (!pci_is_root_bus(bridge->bus) && |
| 3414 | !pci_is_root_bus(bridge->bus->self->bus)) |
| 3415 | return; |
| 3416 | |
| 3417 | /* Fixup the resources */ |
| 3418 | for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { |
| 3419 | r = &bridge->resource[PCI_BRIDGE_RESOURCES + i]; |
| 3420 | if (!r->flags || !r->parent) |
| 3421 | continue; |
| 3422 | |
| 3423 | w = NULL; |
| 3424 | if (r->flags & type & IORESOURCE_IO) |
| 3425 | w = &hose->io_resource; |
Benjamin Herrenschmidt | 5958d19 | 2016-07-08 15:55:43 +1000 | [diff] [blame] | 3426 | else if (pnv_pci_is_m64(phb, r) && |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3427 | (type & IORESOURCE_PREFETCH) && |
| 3428 | phb->ioda.m64_segsize) |
| 3429 | w = &hose->mem_resources[1]; |
| 3430 | else if (r->flags & type & IORESOURCE_MEM) { |
| 3431 | w = &hose->mem_resources[0]; |
| 3432 | msi_region = true; |
| 3433 | } |
| 3434 | |
| 3435 | r->start = w->start; |
| 3436 | r->end = w->end; |
| 3437 | |
| 3438 | /* The 64KB 32-bits MSI region shouldn't be included in |
| 3439 | * the 32-bits bridge window. Otherwise, we can see strange |
| 3440 | * issues. One of them is EEH error observed on Garrison. |
| 3441 | * |
| 3442 | * Exclude top 1MB region which is the minimal alignment of |
| 3443 | * 32-bits bridge window. |
| 3444 | */ |
| 3445 | if (msi_region) { |
| 3446 | r->end += 0x10000; |
| 3447 | r->end -= 0x100000; |
| 3448 | } |
| 3449 | } |
| 3450 | } |
| 3451 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3452 | static void pnv_pci_setup_bridge(struct pci_bus *bus, unsigned long type) |
| 3453 | { |
| 3454 | struct pci_controller *hose = pci_bus_to_host(bus); |
| 3455 | struct pnv_phb *phb = hose->private_data; |
| 3456 | struct pci_dev *bridge = bus->self; |
| 3457 | struct pnv_ioda_pe *pe; |
| 3458 | bool all = (pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE); |
| 3459 | |
Gavin Shan | 40e2a47 | 2016-05-20 16:41:33 +1000 | [diff] [blame] | 3460 | /* Extend bridge's windows if necessary */ |
| 3461 | pnv_pci_fixup_bridge_resources(bus, type); |
| 3462 | |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 3463 | /* The PE for root bus should be realized before any one else */ |
| 3464 | if (!phb->ioda.root_pe_populated) { |
| 3465 | pe = pnv_ioda_setup_bus_PE(phb->hose->bus, false); |
| 3466 | if (pe) { |
| 3467 | phb->ioda.root_pe_idx = pe->pe_number; |
| 3468 | phb->ioda.root_pe_populated = true; |
| 3469 | } |
| 3470 | } |
| 3471 | |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3472 | /* Don't assign PE to PCI bus, which doesn't have subordinate devices */ |
| 3473 | if (list_empty(&bus->devices)) |
| 3474 | return; |
| 3475 | |
| 3476 | /* Reserve PEs according to used M64 resources */ |
| 3477 | if (phb->reserve_m64_pe) |
| 3478 | phb->reserve_m64_pe(bus, NULL, all); |
| 3479 | |
| 3480 | /* |
| 3481 | * Assign PE. We might run here because of partial hotplug. |
| 3482 | * For the case, we just pick up the existing PE and should |
| 3483 | * not allocate resources again. |
| 3484 | */ |
| 3485 | pe = pnv_ioda_setup_bus_PE(bus, all); |
| 3486 | if (!pe) |
| 3487 | return; |
| 3488 | |
| 3489 | pnv_ioda_setup_pe_seg(pe); |
| 3490 | switch (phb->type) { |
| 3491 | case PNV_PHB_IODA1: |
| 3492 | pnv_pci_ioda1_setup_dma_pe(phb, pe); |
| 3493 | break; |
| 3494 | case PNV_PHB_IODA2: |
| 3495 | pnv_pci_ioda2_setup_dma_pe(phb, pe); |
| 3496 | break; |
| 3497 | default: |
Russell Currey | 1f52f17 | 2016-11-16 14:02:15 +1100 | [diff] [blame] | 3498 | pr_warn("%s: No DMA for PHB#%x (type %d)\n", |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3499 | __func__, phb->hose->global_number, phb->type); |
| 3500 | } |
| 3501 | } |
| 3502 | |
Yongji Xie | 3827463 | 2017-04-10 19:58:13 +0800 | [diff] [blame] | 3503 | static resource_size_t pnv_pci_default_alignment(void) |
| 3504 | { |
| 3505 | return PAGE_SIZE; |
| 3506 | } |
| 3507 | |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3508 | #ifdef CONFIG_PCI_IOV |
| 3509 | static resource_size_t pnv_pci_iov_resource_alignment(struct pci_dev *pdev, |
| 3510 | int resno) |
| 3511 | { |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3512 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3513 | struct pnv_phb *phb = hose->private_data; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3514 | struct pci_dn *pdn = pci_get_pdn(pdev); |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3515 | resource_size_t align; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3516 | |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3517 | /* |
| 3518 | * On PowerNV platform, IOV BAR is mapped by M64 BAR to enable the |
| 3519 | * SR-IOV. While from hardware perspective, the range mapped by M64 |
| 3520 | * BAR should be size aligned. |
| 3521 | * |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3522 | * When IOV BAR is mapped with M64 BAR in Single PE mode, the extra |
| 3523 | * powernv-specific hardware restriction is gone. But if just use the |
| 3524 | * VF BAR size as the alignment, PF BAR / VF BAR may be allocated with |
| 3525 | * in one segment of M64 #15, which introduces the PE conflict between |
| 3526 | * PF and VF. Based on this, the minimum alignment of an IOV BAR is |
| 3527 | * m64_segsize. |
| 3528 | * |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3529 | * This function returns the total IOV BAR size if M64 BAR is in |
| 3530 | * Shared PE mode or just VF BAR size if not. |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3531 | * If the M64 BAR is in Single PE mode, return the VF BAR size or |
| 3532 | * M64 segment size if IOV BAR size is less. |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3533 | */ |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3534 | align = pci_iov_resource_size(pdev, resno); |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3535 | if (!pdn->vfs_expanded) |
| 3536 | return align; |
Wei Yang | ee8222f | 2015-10-22 09:22:16 +0800 | [diff] [blame] | 3537 | if (pdn->m64_single_mode) |
| 3538 | return max(align, (resource_size_t)phb->ioda.m64_segsize); |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3539 | |
Wei Yang | 7fbe7a9 | 2015-10-22 09:22:15 +0800 | [diff] [blame] | 3540 | return pdn->vfs_expanded * align; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 3541 | } |
| 3542 | #endif /* CONFIG_PCI_IOV */ |
| 3543 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3544 | /* Prevent enabling devices for which we couldn't properly |
| 3545 | * assign a PE |
| 3546 | */ |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3547 | bool pnv_pci_enable_device_hook(struct pci_dev *dev) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3548 | { |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3549 | struct pci_controller *hose = pci_bus_to_host(dev->bus); |
| 3550 | struct pnv_phb *phb = hose->private_data; |
| 3551 | struct pci_dn *pdn; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3552 | |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3553 | /* The function is probably called while the PEs have |
| 3554 | * not be created yet. For example, resource reassignment |
| 3555 | * during PCI probe period. We just skip the check if |
| 3556 | * PEs isn't ready. |
| 3557 | */ |
| 3558 | if (!phb->initialized) |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3559 | return true; |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3560 | |
Benjamin Herrenschmidt | b72c1f6 | 2013-05-21 22:58:21 +0000 | [diff] [blame] | 3561 | pdn = pci_get_pdn(dev); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3562 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3563 | return false; |
Gavin Shan | db1266c | 2012-08-20 03:49:18 +0000 | [diff] [blame] | 3564 | |
Daniel Axtens | c88c2a1 | 2015-03-31 16:00:41 +1100 | [diff] [blame] | 3565 | return true; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3566 | } |
| 3567 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3568 | static long pnv_pci_ioda1_unset_window(struct iommu_table_group *table_group, |
| 3569 | int num) |
| 3570 | { |
| 3571 | struct pnv_ioda_pe *pe = container_of(table_group, |
| 3572 | struct pnv_ioda_pe, table_group); |
| 3573 | struct pnv_phb *phb = pe->phb; |
| 3574 | unsigned int idx; |
| 3575 | long rc; |
| 3576 | |
| 3577 | pe_info(pe, "Removing DMA window #%d\n", num); |
| 3578 | for (idx = 0; idx < phb->ioda.dma32_count; idx++) { |
| 3579 | if (phb->ioda.dma32_segmap[idx] != pe->pe_number) |
| 3580 | continue; |
| 3581 | |
| 3582 | rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number, |
| 3583 | idx, 0, 0ul, 0ul, 0ul); |
| 3584 | if (rc != OPAL_SUCCESS) { |
| 3585 | pe_warn(pe, "Failure %ld unmapping DMA32 segment#%d\n", |
| 3586 | rc, idx); |
| 3587 | return rc; |
| 3588 | } |
| 3589 | |
| 3590 | phb->ioda.dma32_segmap[idx] = IODA_INVALID_PE; |
| 3591 | } |
| 3592 | |
| 3593 | pnv_pci_unlink_table_and_group(table_group->tables[num], table_group); |
| 3594 | return OPAL_SUCCESS; |
| 3595 | } |
| 3596 | |
| 3597 | static void pnv_pci_ioda1_release_pe_dma(struct pnv_ioda_pe *pe) |
| 3598 | { |
| 3599 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 3600 | struct iommu_table *tbl = pe->table_group.tables[0]; |
| 3601 | int64_t rc; |
| 3602 | |
| 3603 | if (!weight) |
| 3604 | return; |
| 3605 | |
| 3606 | rc = pnv_pci_ioda1_unset_window(&pe->table_group, 0); |
| 3607 | if (rc != OPAL_SUCCESS) |
| 3608 | return; |
| 3609 | |
Benjamin Herrenschmidt | a34ab7c | 2016-07-08 16:37:12 +1000 | [diff] [blame] | 3610 | pnv_pci_p7ioc_tce_invalidate(tbl, tbl->it_offset, tbl->it_size, false); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3611 | if (pe->table_group.group) { |
| 3612 | iommu_group_put(pe->table_group.group); |
| 3613 | WARN_ON(pe->table_group.group); |
| 3614 | } |
| 3615 | |
| 3616 | free_pages(tbl->it_base, get_order(tbl->it_size << 3)); |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 3617 | iommu_tce_table_put(tbl); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3618 | } |
| 3619 | |
| 3620 | static void pnv_pci_ioda2_release_pe_dma(struct pnv_ioda_pe *pe) |
| 3621 | { |
| 3622 | struct iommu_table *tbl = pe->table_group.tables[0]; |
| 3623 | unsigned int weight = pnv_pci_ioda_pe_dma_weight(pe); |
| 3624 | #ifdef CONFIG_IOMMU_API |
| 3625 | int64_t rc; |
| 3626 | #endif |
| 3627 | |
| 3628 | if (!weight) |
| 3629 | return; |
| 3630 | |
| 3631 | #ifdef CONFIG_IOMMU_API |
| 3632 | rc = pnv_pci_ioda2_unset_window(&pe->table_group, 0); |
| 3633 | if (rc) |
| 3634 | pe_warn(pe, "OPAL error %ld release DMA window\n", rc); |
| 3635 | #endif |
| 3636 | |
| 3637 | pnv_pci_ioda2_set_bypass(pe, false); |
| 3638 | if (pe->table_group.group) { |
| 3639 | iommu_group_put(pe->table_group.group); |
| 3640 | WARN_ON(pe->table_group.group); |
| 3641 | } |
| 3642 | |
Alexey Kardashevskiy | e5afdf9 | 2017-03-22 15:21:50 +1100 | [diff] [blame] | 3643 | iommu_tce_table_put(tbl); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3644 | } |
| 3645 | |
| 3646 | static void pnv_ioda_free_pe_seg(struct pnv_ioda_pe *pe, |
| 3647 | unsigned short win, |
| 3648 | unsigned int *map) |
| 3649 | { |
| 3650 | struct pnv_phb *phb = pe->phb; |
| 3651 | int idx; |
| 3652 | int64_t rc; |
| 3653 | |
| 3654 | for (idx = 0; idx < phb->ioda.total_pe_num; idx++) { |
| 3655 | if (map[idx] != pe->pe_number) |
| 3656 | continue; |
| 3657 | |
| 3658 | if (win == OPAL_M64_WINDOW_TYPE) |
| 3659 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3660 | phb->ioda.reserved_pe_idx, win, |
| 3661 | idx / PNV_IODA1_M64_SEGS, |
| 3662 | idx % PNV_IODA1_M64_SEGS); |
| 3663 | else |
| 3664 | rc = opal_pci_map_pe_mmio_window(phb->opal_id, |
| 3665 | phb->ioda.reserved_pe_idx, win, 0, idx); |
| 3666 | |
| 3667 | if (rc != OPAL_SUCCESS) |
| 3668 | pe_warn(pe, "Error %ld unmapping (%d) segment#%d\n", |
| 3669 | rc, win, idx); |
| 3670 | |
| 3671 | map[idx] = IODA_INVALID_PE; |
| 3672 | } |
| 3673 | } |
| 3674 | |
| 3675 | static void pnv_ioda_release_pe_seg(struct pnv_ioda_pe *pe) |
| 3676 | { |
| 3677 | struct pnv_phb *phb = pe->phb; |
| 3678 | |
| 3679 | if (phb->type == PNV_PHB_IODA1) { |
| 3680 | pnv_ioda_free_pe_seg(pe, OPAL_IO_WINDOW_TYPE, |
| 3681 | phb->ioda.io_segmap); |
| 3682 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, |
| 3683 | phb->ioda.m32_segmap); |
| 3684 | pnv_ioda_free_pe_seg(pe, OPAL_M64_WINDOW_TYPE, |
| 3685 | phb->ioda.m64_segmap); |
| 3686 | } else if (phb->type == PNV_PHB_IODA2) { |
| 3687 | pnv_ioda_free_pe_seg(pe, OPAL_M32_WINDOW_TYPE, |
| 3688 | phb->ioda.m32_segmap); |
| 3689 | } |
| 3690 | } |
| 3691 | |
| 3692 | static void pnv_ioda_release_pe(struct pnv_ioda_pe *pe) |
| 3693 | { |
| 3694 | struct pnv_phb *phb = pe->phb; |
| 3695 | struct pnv_ioda_pe *slave, *tmp; |
| 3696 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3697 | list_del(&pe->list); |
| 3698 | switch (phb->type) { |
| 3699 | case PNV_PHB_IODA1: |
| 3700 | pnv_pci_ioda1_release_pe_dma(pe); |
| 3701 | break; |
| 3702 | case PNV_PHB_IODA2: |
| 3703 | pnv_pci_ioda2_release_pe_dma(pe); |
| 3704 | break; |
| 3705 | default: |
| 3706 | WARN_ON(1); |
| 3707 | } |
| 3708 | |
| 3709 | pnv_ioda_release_pe_seg(pe); |
| 3710 | pnv_ioda_deconfigure_pe(pe->phb, pe); |
Gavin Shan | b314427 | 2016-09-06 14:16:44 +1000 | [diff] [blame] | 3711 | |
| 3712 | /* Release slave PEs in the compound PE */ |
| 3713 | if (pe->flags & PNV_IODA_PE_MASTER) { |
| 3714 | list_for_each_entry_safe(slave, tmp, &pe->slaves, list) { |
| 3715 | list_del(&slave->list); |
| 3716 | pnv_ioda_free_pe(slave); |
| 3717 | } |
| 3718 | } |
| 3719 | |
Gavin Shan | 6eaed16 | 2016-09-13 16:40:24 +1000 | [diff] [blame] | 3720 | /* |
| 3721 | * The PE for root bus can be removed because of hotplug in EEH |
| 3722 | * recovery for fenced PHB error. We need to mark the PE dead so |
| 3723 | * that it can be populated again in PCI hot add path. The PE |
| 3724 | * shouldn't be destroyed as it's the global reserved resource. |
| 3725 | */ |
| 3726 | if (phb->ioda.root_pe_populated && |
| 3727 | phb->ioda.root_pe_idx == pe->pe_number) |
| 3728 | phb->ioda.root_pe_populated = false; |
| 3729 | else |
| 3730 | pnv_ioda_free_pe(pe); |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3731 | } |
| 3732 | |
| 3733 | static void pnv_pci_release_device(struct pci_dev *pdev) |
| 3734 | { |
| 3735 | struct pci_controller *hose = pci_bus_to_host(pdev->bus); |
| 3736 | struct pnv_phb *phb = hose->private_data; |
| 3737 | struct pci_dn *pdn = pci_get_pdn(pdev); |
| 3738 | struct pnv_ioda_pe *pe; |
| 3739 | |
| 3740 | if (pdev->is_virtfn) |
| 3741 | return; |
| 3742 | |
| 3743 | if (!pdn || pdn->pe_number == IODA_INVALID_PE) |
| 3744 | return; |
| 3745 | |
Gavin Shan | 29bf282 | 2016-09-06 16:34:01 +1000 | [diff] [blame] | 3746 | /* |
| 3747 | * PCI hotplug can happen as part of EEH error recovery. The @pdn |
| 3748 | * isn't removed and added afterwards in this scenario. We should |
| 3749 | * set the PE number in @pdn to an invalid one. Otherwise, the PE's |
| 3750 | * device count is decreased on removing devices while failing to |
| 3751 | * be increased on adding devices. It leads to unbalanced PE's device |
| 3752 | * count and eventually make normal PCI hotplug path broken. |
| 3753 | */ |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3754 | pe = &phb->ioda.pe_array[pdn->pe_number]; |
Gavin Shan | 29bf282 | 2016-09-06 16:34:01 +1000 | [diff] [blame] | 3755 | pdn->pe_number = IODA_INVALID_PE; |
| 3756 | |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3757 | WARN_ON(--pe->device_count < 0); |
| 3758 | if (pe->device_count == 0) |
| 3759 | pnv_ioda_release_pe(pe); |
| 3760 | } |
| 3761 | |
Michael Neuling | 7a8e6bb | 2015-05-27 16:06:59 +1000 | [diff] [blame] | 3762 | static void pnv_pci_ioda_shutdown(struct pci_controller *hose) |
Benjamin Herrenschmidt | 73ed148 | 2013-05-10 16:59:18 +1000 | [diff] [blame] | 3763 | { |
Michael Neuling | 7a8e6bb | 2015-05-27 16:06:59 +1000 | [diff] [blame] | 3764 | struct pnv_phb *phb = hose->private_data; |
| 3765 | |
Gavin Shan | d1a85ee | 2014-09-30 12:39:05 +1000 | [diff] [blame] | 3766 | opal_pci_reset(phb->opal_id, OPAL_RESET_PCI_IODA_TABLE, |
Benjamin Herrenschmidt | 73ed148 | 2013-05-10 16:59:18 +1000 | [diff] [blame] | 3767 | OPAL_ASSERT_RESET); |
| 3768 | } |
| 3769 | |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3770 | static const struct pci_controller_ops pnv_pci_ioda_controller_ops = { |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3771 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
| 3772 | .dma_bus_setup = pnv_pci_dma_bus_setup, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3773 | #ifdef CONFIG_PCI_MSI |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3774 | .setup_msi_irqs = pnv_setup_msi_irqs, |
| 3775 | .teardown_msi_irqs = pnv_teardown_msi_irqs, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3776 | #endif |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3777 | .enable_device_hook = pnv_pci_enable_device_hook, |
Gavin Shan | c5f7700 | 2016-05-20 16:41:35 +1000 | [diff] [blame] | 3778 | .release_device = pnv_pci_release_device, |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3779 | .window_alignment = pnv_pci_window_alignment, |
Gavin Shan | ccd1c19 | 2016-05-20 16:41:31 +1000 | [diff] [blame] | 3780 | .setup_bridge = pnv_pci_setup_bridge, |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3781 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3782 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, |
| 3783 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, |
| 3784 | .shutdown = pnv_pci_ioda_shutdown, |
Daniel Axtens | 92ae035 | 2015-04-28 15:12:05 +1000 | [diff] [blame] | 3785 | }; |
| 3786 | |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 3787 | static int pnv_npu_dma_set_mask(struct pci_dev *npdev, u64 dma_mask) |
| 3788 | { |
| 3789 | dev_err_once(&npdev->dev, |
| 3790 | "%s operation unsupported for NVLink devices\n", |
| 3791 | __func__); |
| 3792 | return -EPERM; |
| 3793 | } |
| 3794 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3795 | static const struct pci_controller_ops pnv_npu_ioda_controller_ops = { |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3796 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3797 | #ifdef CONFIG_PCI_MSI |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3798 | .setup_msi_irqs = pnv_setup_msi_irqs, |
| 3799 | .teardown_msi_irqs = pnv_teardown_msi_irqs, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3800 | #endif |
Gavin Shan | cb4224c | 2016-05-03 15:41:21 +1000 | [diff] [blame] | 3801 | .enable_device_hook = pnv_pci_enable_device_hook, |
| 3802 | .window_alignment = pnv_pci_window_alignment, |
| 3803 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3804 | .dma_set_mask = pnv_npu_dma_set_mask, |
| 3805 | .shutdown = pnv_pci_ioda_shutdown, |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3806 | }; |
| 3807 | |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3808 | #ifdef CONFIG_CXL_BASE |
| 3809 | const struct pci_controller_ops pnv_cxl_cx4_ioda_controller_ops = { |
| 3810 | .dma_dev_setup = pnv_pci_dma_dev_setup, |
| 3811 | .dma_bus_setup = pnv_pci_dma_bus_setup, |
Ian Munsie | a2f67d5 | 2016-07-14 07:17:10 +1000 | [diff] [blame] | 3812 | #ifdef CONFIG_PCI_MSI |
| 3813 | .setup_msi_irqs = pnv_cxl_cx4_setup_msi_irqs, |
| 3814 | .teardown_msi_irqs = pnv_cxl_cx4_teardown_msi_irqs, |
| 3815 | #endif |
Ian Munsie | 4361b03 | 2016-07-14 07:17:06 +1000 | [diff] [blame] | 3816 | .enable_device_hook = pnv_cxl_enable_device_hook, |
| 3817 | .disable_device = pnv_cxl_disable_device, |
| 3818 | .release_device = pnv_pci_release_device, |
| 3819 | .window_alignment = pnv_pci_window_alignment, |
| 3820 | .setup_bridge = pnv_pci_setup_bridge, |
| 3821 | .reset_secondary_bus = pnv_pci_reset_secondary_bus, |
| 3822 | .dma_set_mask = pnv_pci_ioda_dma_set_mask, |
| 3823 | .dma_get_required_mask = pnv_pci_ioda_dma_get_required_mask, |
| 3824 | .shutdown = pnv_pci_ioda_shutdown, |
| 3825 | }; |
| 3826 | #endif |
| 3827 | |
Anton Blanchard | e51df2c | 2014-08-20 08:55:18 +1000 | [diff] [blame] | 3828 | static void __init pnv_pci_init_ioda_phb(struct device_node *np, |
| 3829 | u64 hub_id, int ioda_type) |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3830 | { |
| 3831 | struct pci_controller *hose; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3832 | struct pnv_phb *phb; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3833 | unsigned long size, m64map_off, m32map_off, pemap_off; |
| 3834 | unsigned long iomap_off = 0, dma32map_off = 0; |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 3835 | struct resource r; |
Alistair Popple | c681b93 | 2013-09-23 12:04:57 +1000 | [diff] [blame] | 3836 | const __be64 *prop64; |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3837 | const __be32 *prop32; |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3838 | int len; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3839 | unsigned int segno; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3840 | u64 phb_id; |
| 3841 | void *aux; |
| 3842 | long rc; |
| 3843 | |
Benjamin Herrenschmidt | 08a45b3 | 2016-07-08 16:37:17 +1000 | [diff] [blame] | 3844 | if (!of_device_is_available(np)) |
| 3845 | return; |
| 3846 | |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3847 | pr_info("Initializing %s PHB (%pOF)\n", pnv_phb_names[ioda_type], np); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3848 | |
| 3849 | prop64 = of_get_property(np, "ibm,opal-phbid", NULL); |
| 3850 | if (!prop64) { |
| 3851 | pr_err(" Missing \"ibm,opal-phbid\" property !\n"); |
| 3852 | return; |
| 3853 | } |
| 3854 | phb_id = be64_to_cpup(prop64); |
| 3855 | pr_debug(" PHB-ID : 0x%016llx\n", phb_id); |
| 3856 | |
Michael Ellerman | e39f223f | 2014-11-18 16:47:35 +1100 | [diff] [blame] | 3857 | phb = memblock_virt_alloc(sizeof(struct pnv_phb), 0); |
Gavin Shan | 58d714e | 2013-07-31 16:47:00 +0800 | [diff] [blame] | 3858 | |
| 3859 | /* Allocate PCI controller */ |
Gavin Shan | 58d714e | 2013-07-31 16:47:00 +0800 | [diff] [blame] | 3860 | phb->hose = hose = pcibios_alloc_controller(np); |
| 3861 | if (!phb->hose) { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3862 | pr_err(" Can't allocate PCI controller for %pOF\n", |
| 3863 | np); |
Michael Ellerman | e39f223f | 2014-11-18 16:47:35 +1100 | [diff] [blame] | 3864 | memblock_free(__pa(phb), sizeof(struct pnv_phb)); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3865 | return; |
| 3866 | } |
| 3867 | |
| 3868 | spin_lock_init(&phb->lock); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3869 | prop32 = of_get_property(np, "bus-range", &len); |
| 3870 | if (prop32 && len == 8) { |
Benjamin Herrenschmidt | 3a1a466 | 2013-09-23 12:05:01 +1000 | [diff] [blame] | 3871 | hose->first_busno = be32_to_cpu(prop32[0]); |
| 3872 | hose->last_busno = be32_to_cpu(prop32[1]); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3873 | } else { |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 3874 | pr_warn(" Broken <bus-range> on %pOF\n", np); |
Gavin Shan | f1b7cc3 | 2013-07-31 16:47:01 +0800 | [diff] [blame] | 3875 | hose->first_busno = 0; |
| 3876 | hose->last_busno = 0xff; |
| 3877 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3878 | hose->private_data = phb; |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 3879 | phb->hub_id = hub_id; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3880 | phb->opal_id = phb_id; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3881 | phb->type = ioda_type; |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 3882 | mutex_init(&phb->ioda.pe_alloc_mutex); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3883 | |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 3884 | /* Detect specific models for error handling */ |
| 3885 | if (of_device_is_compatible(np, "ibm,p7ioc-pciex")) |
| 3886 | phb->model = PNV_PHB_MODEL_P7IOC; |
Benjamin Herrenschmidt | f3d40c2 | 2013-05-04 14:24:32 +0000 | [diff] [blame] | 3887 | else if (of_device_is_compatible(np, "ibm,power8-pciex")) |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3888 | phb->model = PNV_PHB_MODEL_PHB3; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 3889 | else if (of_device_is_compatible(np, "ibm,power8-npu-pciex")) |
| 3890 | phb->model = PNV_PHB_MODEL_NPU; |
Alistair Popple | 616badd | 2017-01-10 15:41:44 +1100 | [diff] [blame] | 3891 | else if (of_device_is_compatible(np, "ibm,power9-npu-pciex")) |
| 3892 | phb->model = PNV_PHB_MODEL_NPU2; |
Benjamin Herrenschmidt | cee72d5 | 2011-11-29 18:22:53 +0000 | [diff] [blame] | 3893 | else |
| 3894 | phb->model = PNV_PHB_MODEL_UNKNOWN; |
| 3895 | |
Russell Currey | 5cb1f8f | 2017-06-14 14:19:59 +1000 | [diff] [blame] | 3896 | /* Initialize diagnostic data buffer */ |
| 3897 | prop32 = of_get_property(np, "ibm,phb-diag-data-size", NULL); |
| 3898 | if (prop32) |
| 3899 | phb->diag_data_size = be32_to_cpup(prop32); |
| 3900 | else |
| 3901 | phb->diag_data_size = PNV_PCI_DIAG_BUF_SIZE; |
| 3902 | |
| 3903 | phb->diag_data = memblock_virt_alloc(phb->diag_data_size, 0); |
| 3904 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3905 | /* Parse 32-bit and IO ranges (if any) */ |
Gavin Shan | 2f1ec02 | 2013-07-31 16:47:02 +0800 | [diff] [blame] | 3906 | pci_process_bridge_OF_ranges(hose, np, !hose->global_number); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3907 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3908 | /* Get registers */ |
Benjamin Herrenschmidt | fd141d1a | 2016-07-08 16:37:14 +1000 | [diff] [blame] | 3909 | if (!of_address_to_resource(np, 0, &r)) { |
| 3910 | phb->regs_phys = r.start; |
| 3911 | phb->regs = ioremap(r.start, resource_size(&r)); |
| 3912 | if (phb->regs == NULL) |
| 3913 | pr_err(" Failed to map registers !\n"); |
| 3914 | } |
Gavin Shan | 577c8c8 | 2016-05-20 16:41:28 +1000 | [diff] [blame] | 3915 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3916 | /* Initialize more IODA stuff */ |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3917 | phb->ioda.total_pe_num = 1; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3918 | prop32 = of_get_property(np, "ibm,opal-num-pes", NULL); |
Gavin Shan | 36954dc | 2013-11-04 16:32:47 +0800 | [diff] [blame] | 3919 | if (prop32) |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3920 | phb->ioda.total_pe_num = be32_to_cpup(prop32); |
Gavin Shan | 36954dc | 2013-11-04 16:32:47 +0800 | [diff] [blame] | 3921 | prop32 = of_get_property(np, "ibm,opal-reserved-pe", NULL); |
| 3922 | if (prop32) |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3923 | phb->ioda.reserved_pe_idx = be32_to_cpup(prop32); |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3924 | |
Gavin Shan | c127562 | 2016-05-20 16:41:29 +1000 | [diff] [blame] | 3925 | /* Invalidate RID to PE# mapping */ |
| 3926 | for (segno = 0; segno < ARRAY_SIZE(phb->ioda.pe_rmap); segno++) |
| 3927 | phb->ioda.pe_rmap[segno] = IODA_INVALID_PE; |
| 3928 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 3929 | /* Parse 64-bit MMIO range */ |
| 3930 | pnv_ioda_parse_m64_window(phb); |
| 3931 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3932 | phb->ioda.m32_size = resource_size(&hose->mem_resources[0]); |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 3933 | /* FW Has already off top 64k of M32 space (MSI space) */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3934 | phb->ioda.m32_size += 0x10000; |
| 3935 | |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3936 | phb->ioda.m32_segsize = phb->ioda.m32_size / phb->ioda.total_pe_num; |
Benjamin Herrenschmidt | 3fd47f0 | 2013-05-06 13:40:40 +1000 | [diff] [blame] | 3937 | phb->ioda.m32_pci_base = hose->mem_resources[0].start - hose->mem_offset[0]; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3938 | phb->ioda.io_size = hose->pci_io_size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3939 | phb->ioda.io_segsize = phb->ioda.io_size / phb->ioda.total_pe_num; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3940 | phb->ioda.io_pci_base = 0; /* XXX calculate this ? */ |
| 3941 | |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3942 | /* Calculate how many 32-bit TCE segments we have */ |
| 3943 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
| 3944 | PNV_IODA1_DMA32_SEGSIZE; |
| 3945 | |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3946 | /* Allocate aux data & arrays. We don't have IO ports on PHB3 */ |
Alexey Kardashevskiy | 92a8675 | 2016-05-12 15:47:09 +1000 | [diff] [blame] | 3947 | size = _ALIGN_UP(max_t(unsigned, phb->ioda.total_pe_num, 8) / 8, |
| 3948 | sizeof(unsigned long)); |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 3949 | m64map_off = size; |
| 3950 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m64_segmap[0]); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3951 | m32map_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3952 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.m32_segmap[0]); |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3953 | if (phb->type == PNV_PHB_IODA1) { |
| 3954 | iomap_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3955 | size += phb->ioda.total_pe_num * sizeof(phb->ioda.io_segmap[0]); |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3956 | dma32map_off = size; |
| 3957 | size += phb->ioda.dma32_count * |
| 3958 | sizeof(phb->ioda.dma32_segmap[0]); |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3959 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3960 | pemap_off = size; |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 3961 | size += phb->ioda.total_pe_num * sizeof(struct pnv_ioda_pe); |
Michael Ellerman | e39f223f | 2014-11-18 16:47:35 +1100 | [diff] [blame] | 3962 | aux = memblock_virt_alloc(size, 0); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3963 | phb->ioda.pe_alloc = aux; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 3964 | phb->ioda.m64_segmap = aux + m64map_off; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3965 | phb->ioda.m32_segmap = aux + m32map_off; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 3966 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) { |
| 3967 | phb->ioda.m64_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3968 | phb->ioda.m32_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 93289d8 | 2016-05-03 15:41:29 +1000 | [diff] [blame] | 3969 | } |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3970 | if (phb->type == PNV_PHB_IODA1) { |
Gavin Shan | c35d2a8 | 2013-07-31 16:47:04 +0800 | [diff] [blame] | 3971 | phb->ioda.io_segmap = aux + iomap_off; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3972 | for (segno = 0; segno < phb->ioda.total_pe_num; segno++) |
| 3973 | phb->ioda.io_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 3974 | |
| 3975 | phb->ioda.dma32_segmap = aux + dma32map_off; |
| 3976 | for (segno = 0; segno < phb->ioda.dma32_count; segno++) |
| 3977 | phb->ioda.dma32_segmap[segno] = IODA_INVALID_PE; |
Gavin Shan | 3fa23ff | 2016-05-03 15:41:26 +1000 | [diff] [blame] | 3978 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3979 | phb->ioda.pe_array = aux + pemap_off; |
Gavin Shan | 63803c3 | 2016-05-20 16:41:32 +1000 | [diff] [blame] | 3980 | |
| 3981 | /* |
| 3982 | * Choose PE number for root bus, which shouldn't have |
| 3983 | * M64 resources consumed by its child devices. To pick |
| 3984 | * the PE number adjacent to the reserved one if possible. |
| 3985 | */ |
| 3986 | pnv_ioda_reserve_pe(phb, phb->ioda.reserved_pe_idx); |
| 3987 | if (phb->ioda.reserved_pe_idx == 0) { |
| 3988 | phb->ioda.root_pe_idx = 1; |
| 3989 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); |
| 3990 | } else if (phb->ioda.reserved_pe_idx == (phb->ioda.total_pe_num - 1)) { |
| 3991 | phb->ioda.root_pe_idx = phb->ioda.reserved_pe_idx - 1; |
| 3992 | pnv_ioda_reserve_pe(phb, phb->ioda.root_pe_idx); |
| 3993 | } else { |
| 3994 | phb->ioda.root_pe_idx = IODA_INVALID_PE; |
| 3995 | } |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3996 | |
| 3997 | INIT_LIST_HEAD(&phb->ioda.pe_list); |
Wei Yang | 781a868 | 2015-03-25 16:23:57 +0800 | [diff] [blame] | 3998 | mutex_init(&phb->ioda.pe_list_mutex); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 3999 | |
| 4000 | /* Calculate how many 32-bit TCE segments we have */ |
Gavin Shan | 2b923ed | 2016-05-05 12:04:16 +1000 | [diff] [blame] | 4001 | phb->ioda.dma32_count = phb->ioda.m32_pci_base / |
Gavin Shan | acce971 | 2016-05-03 15:41:33 +1000 | [diff] [blame] | 4002 | PNV_IODA1_DMA32_SEGSIZE; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4003 | |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4004 | #if 0 /* We should really do that ... */ |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4005 | rc = opal_pci_set_phb_mem_window(opal->phb_id, |
| 4006 | window_type, |
| 4007 | window_num, |
| 4008 | starting_real_address, |
| 4009 | starting_pci_address, |
| 4010 | segment_size); |
| 4011 | #endif |
| 4012 | |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4013 | pr_info(" %03d (%03d) PE's M32: 0x%x [segment=0x%x]\n", |
Gavin Shan | 92b8f13 | 2016-05-03 15:41:24 +1000 | [diff] [blame] | 4014 | phb->ioda.total_pe_num, phb->ioda.reserved_pe_idx, |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4015 | phb->ioda.m32_size, phb->ioda.m32_segsize); |
| 4016 | if (phb->ioda.m64_size) |
| 4017 | pr_info(" M64: 0x%lx [segment=0x%lx]\n", |
| 4018 | phb->ioda.m64_size, phb->ioda.m64_segsize); |
| 4019 | if (phb->ioda.io_size) |
| 4020 | pr_info(" IO: 0x%x [segment=0x%x]\n", |
| 4021 | phb->ioda.io_size, phb->ioda.io_segsize); |
| 4022 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4023 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4024 | phb->hose->ops = &pnv_pci_ops; |
Gavin Shan | 49dec92 | 2014-07-21 14:42:33 +1000 | [diff] [blame] | 4025 | phb->get_pe_state = pnv_ioda_get_pe_state; |
| 4026 | phb->freeze_pe = pnv_ioda_freeze_pe; |
| 4027 | phb->unfreeze_pe = pnv_ioda_unfreeze_pe; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4028 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4029 | /* Setup MSI support */ |
| 4030 | pnv_pci_init_ioda_msis(phb); |
| 4031 | |
Gavin Shan | c40a421 | 2012-08-20 03:49:20 +0000 | [diff] [blame] | 4032 | /* |
| 4033 | * We pass the PCI probe flag PCI_REASSIGN_ALL_RSRC here |
| 4034 | * to let the PCI core do resource assignment. It's supposed |
| 4035 | * that the PCI core will do correct I/O and MMIO alignment |
| 4036 | * for the P2P bridge bars so that each PCI bus (excluding |
| 4037 | * the child P2P bridges) can form individual PE. |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4038 | */ |
Gavin Shan | fb446ad | 2012-08-20 03:49:14 +0000 | [diff] [blame] | 4039 | ppc_md.pcibios_fixup = pnv_pci_ioda_fixup; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4040 | |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 4041 | if (phb->type == PNV_PHB_NPU) { |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4042 | hose->controller_ops = pnv_npu_ioda_controller_ops; |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 4043 | } else { |
| 4044 | phb->dma_dev_setup = pnv_pci_ioda_dma_dev_setup; |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4045 | hose->controller_ops = pnv_pci_ioda_controller_ops; |
Alexey Kardashevskiy | f9f8345 | 2016-04-29 18:55:20 +1000 | [diff] [blame] | 4046 | } |
Michael Ellerman | ad30cb9 | 2015-04-14 09:29:23 +1000 | [diff] [blame] | 4047 | |
Yongji Xie | 3827463 | 2017-04-10 19:58:13 +0800 | [diff] [blame] | 4048 | ppc_md.pcibios_default_alignment = pnv_pci_default_alignment; |
| 4049 | |
Wei Yang | 6e628c7 | 2015-03-25 16:23:55 +0800 | [diff] [blame] | 4050 | #ifdef CONFIG_PCI_IOV |
| 4051 | ppc_md.pcibios_fixup_sriov = pnv_pci_ioda_fixup_iov_resources; |
Wei Yang | 5350ab3 | 2015-03-25 16:23:56 +0800 | [diff] [blame] | 4052 | ppc_md.pcibios_iov_resource_alignment = pnv_pci_iov_resource_alignment; |
Michael Ellerman | ad30cb9 | 2015-04-14 09:29:23 +1000 | [diff] [blame] | 4053 | #endif |
| 4054 | |
Gavin Shan | c40a421 | 2012-08-20 03:49:20 +0000 | [diff] [blame] | 4055 | pci_add_flags(PCI_REASSIGN_ALL_RSRC); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4056 | |
| 4057 | /* Reset IODA tables to a clean state */ |
Gavin Shan | d1a85ee | 2014-09-30 12:39:05 +1000 | [diff] [blame] | 4058 | rc = opal_pci_reset(phb_id, OPAL_RESET_PCI_IODA_TABLE, OPAL_ASSERT_RESET); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4059 | if (rc) |
Benjamin Herrenschmidt | f11fe55 | 2011-11-29 18:22:50 +0000 | [diff] [blame] | 4060 | pr_warning(" OPAL Error %ld performing IODA table reset !\n", rc); |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4061 | |
Andrew Donnellan | 6060e9e | 2016-09-16 20:39:44 +1000 | [diff] [blame] | 4062 | /* |
| 4063 | * If we're running in kdump kernel, the previous kernel never |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4064 | * shutdown PCI devices correctly. We already got IODA table |
| 4065 | * cleaned out. So we have to issue PHB reset to stop all PCI |
Andrew Donnellan | 6060e9e | 2016-09-16 20:39:44 +1000 | [diff] [blame] | 4066 | * transactions from previous kernel. |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4067 | */ |
| 4068 | if (is_kdump_kernel()) { |
| 4069 | pr_info(" Issue PHB reset ...\n"); |
Gavin Shan | cadf364 | 2015-02-16 14:45:47 +1100 | [diff] [blame] | 4070 | pnv_eeh_phb_reset(hose, EEH_RESET_FUNDAMENTAL); |
| 4071 | pnv_eeh_phb_reset(hose, EEH_RESET_DEACTIVATE); |
Gavin Shan | 361f2a2 | 2014-04-24 18:00:25 +1000 | [diff] [blame] | 4072 | } |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4073 | |
Gavin Shan | 9e9e893 | 2014-11-12 13:36:05 +1100 | [diff] [blame] | 4074 | /* Remove M64 resource if we can't configure it successfully */ |
| 4075 | if (!phb->init_m64 || phb->init_m64(phb)) |
Guo Chao | 262af55 | 2014-07-21 14:42:30 +1000 | [diff] [blame] | 4076 | hose->mem_resources[1].flags = 0; |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4077 | } |
| 4078 | |
Bjorn Helgaas | 6797500 | 2013-07-02 12:20:03 -0600 | [diff] [blame] | 4079 | void __init pnv_pci_init_ioda2_phb(struct device_node *np) |
Gavin Shan | aa0c033 | 2013-04-25 19:20:57 +0000 | [diff] [blame] | 4080 | { |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 4081 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_IODA2); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4082 | } |
| 4083 | |
Alistair Popple | 5d2aa71 | 2015-12-17 13:43:13 +1100 | [diff] [blame] | 4084 | void __init pnv_pci_init_npu_phb(struct device_node *np) |
| 4085 | { |
| 4086 | pnv_pci_init_ioda_phb(np, 0, PNV_PHB_NPU); |
| 4087 | } |
| 4088 | |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4089 | void __init pnv_pci_init_ioda_hub(struct device_node *np) |
| 4090 | { |
| 4091 | struct device_node *phbn; |
Alistair Popple | c681b93 | 2013-09-23 12:04:57 +1000 | [diff] [blame] | 4092 | const __be64 *prop64; |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4093 | u64 hub_id; |
| 4094 | |
Rob Herring | b7c670d | 2017-08-21 10:16:47 -0500 | [diff] [blame] | 4095 | pr_info("Probing IODA IO-Hub %pOF\n", np); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4096 | |
| 4097 | prop64 = of_get_property(np, "ibm,opal-hubid", NULL); |
| 4098 | if (!prop64) { |
| 4099 | pr_err(" Missing \"ibm,opal-hubid\" property !\n"); |
| 4100 | return; |
| 4101 | } |
| 4102 | hub_id = be64_to_cpup(prop64); |
| 4103 | pr_devel(" HUB-ID : 0x%016llx\n", hub_id); |
| 4104 | |
| 4105 | /* Count child PHBs */ |
| 4106 | for_each_child_of_node(np, phbn) { |
| 4107 | /* Look for IODA1 PHBs */ |
| 4108 | if (of_device_is_compatible(phbn, "ibm,ioda-phb")) |
Gavin Shan | e9cc17d | 2013-06-20 13:21:14 +0800 | [diff] [blame] | 4109 | pnv_pci_init_ioda_phb(phbn, hub_id, PNV_PHB_IODA1); |
Benjamin Herrenschmidt | 184cd4a | 2011-11-15 17:29:08 +0000 | [diff] [blame] | 4110 | } |
| 4111 | } |