Mikael Starvik | 51533b6 | 2005-07-27 11:44:44 -0700 | [diff] [blame] | 1 | /* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version |
| 2 | from ../../inst/intr_vect/rtl/guinness/ivmask.config.r |
| 3 | version . */ |
| 4 | |
| 5 | #ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R |
| 6 | #define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R |
| 7 | #define MEMARB_INTR_VECT 0x31 |
| 8 | #define GEN_IO_INTR_VECT 0x32 |
| 9 | #define IOP0_INTR_VECT 0x33 |
| 10 | #define IOP1_INTR_VECT 0x34 |
| 11 | #define IOP2_INTR_VECT 0x35 |
| 12 | #define IOP3_INTR_VECT 0x36 |
| 13 | #define DMA0_INTR_VECT 0x37 |
| 14 | #define DMA1_INTR_VECT 0x38 |
| 15 | #define DMA2_INTR_VECT 0x39 |
| 16 | #define DMA3_INTR_VECT 0x3a |
| 17 | #define DMA4_INTR_VECT 0x3b |
| 18 | #define DMA5_INTR_VECT 0x3c |
| 19 | #define DMA6_INTR_VECT 0x3d |
| 20 | #define DMA7_INTR_VECT 0x3e |
| 21 | #define DMA8_INTR_VECT 0x3f |
| 22 | #define DMA9_INTR_VECT 0x40 |
| 23 | #define ATA_INTR_VECT 0x41 |
| 24 | #define SSER0_INTR_VECT 0x42 |
| 25 | #define SSER1_INTR_VECT 0x43 |
| 26 | #define SER0_INTR_VECT 0x44 |
| 27 | #define SER1_INTR_VECT 0x45 |
| 28 | #define SER2_INTR_VECT 0x46 |
| 29 | #define SER3_INTR_VECT 0x47 |
| 30 | #define P21_INTR_VECT 0x48 |
| 31 | #define ETH0_INTR_VECT 0x49 |
| 32 | #define ETH1_INTR_VECT 0x4a |
| 33 | #define TIMER_INTR_VECT 0x4b |
| 34 | #define BIF_ARB_INTR_VECT 0x4c |
| 35 | #define BIF_DMA_INTR_VECT 0x4d |
| 36 | #define EXT_INTR_VECT 0x4e |
| 37 | #define IPI_INTR_VECT 0x4f |
| 38 | |
| 39 | #endif |