Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Russell King |
| 3 | * Rewritten from the dovefb driver, and Armada510 manuals. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | #include <linux/clk.h> |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 10 | #include <linux/component.h> |
| 11 | #include <linux/of_device.h> |
| 12 | #include <linux/platform_device.h> |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 13 | #include <drm/drmP.h> |
| 14 | #include <drm/drm_crtc_helper.h> |
Daniel Vetter | 3cb9ae4 | 2014-10-29 10:03:57 +0100 | [diff] [blame] | 15 | #include <drm/drm_plane_helper.h> |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 16 | #include "armada_crtc.h" |
| 17 | #include "armada_drm.h" |
| 18 | #include "armada_fb.h" |
| 19 | #include "armada_gem.h" |
| 20 | #include "armada_hw.h" |
Russell King | c8a220c | 2016-05-17 13:51:08 +0100 | [diff] [blame] | 21 | #include "armada_trace.h" |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 22 | |
| 23 | struct armada_frame_work { |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 24 | struct armada_plane_work work; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 25 | struct drm_pending_vblank_event *event; |
| 26 | struct armada_regs regs[4]; |
| 27 | struct drm_framebuffer *old_fb; |
| 28 | }; |
| 29 | |
| 30 | enum csc_mode { |
| 31 | CSC_AUTO = 0, |
| 32 | CSC_YUV_CCIR601 = 1, |
| 33 | CSC_YUV_CCIR709 = 2, |
| 34 | CSC_RGB_COMPUTER = 1, |
| 35 | CSC_RGB_STUDIO = 2, |
| 36 | }; |
| 37 | |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 38 | static const uint32_t armada_primary_formats[] = { |
| 39 | DRM_FORMAT_UYVY, |
| 40 | DRM_FORMAT_YUYV, |
| 41 | DRM_FORMAT_VYUY, |
| 42 | DRM_FORMAT_YVYU, |
| 43 | DRM_FORMAT_ARGB8888, |
| 44 | DRM_FORMAT_ABGR8888, |
| 45 | DRM_FORMAT_XRGB8888, |
| 46 | DRM_FORMAT_XBGR8888, |
| 47 | DRM_FORMAT_RGB888, |
| 48 | DRM_FORMAT_BGR888, |
| 49 | DRM_FORMAT_ARGB1555, |
| 50 | DRM_FORMAT_ABGR1555, |
| 51 | DRM_FORMAT_RGB565, |
| 52 | DRM_FORMAT_BGR565, |
| 53 | }; |
| 54 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 55 | /* |
| 56 | * A note about interlacing. Let's consider HDMI 1920x1080i. |
| 57 | * The timing parameters we have from X are: |
| 58 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot |
| 59 | * 1920 2448 2492 2640 1080 1084 1094 1125 |
| 60 | * Which get translated to: |
| 61 | * Hact HsyA HsyI Htot Vact VsyA VsyI Vtot |
| 62 | * 1920 2448 2492 2640 540 542 547 562 |
| 63 | * |
| 64 | * This is how it is defined by CEA-861-D - line and pixel numbers are |
| 65 | * referenced to the rising edge of VSYNC and HSYNC. Total clocks per |
| 66 | * line: 2640. The odd frame, the first active line is at line 21, and |
| 67 | * the even frame, the first active line is 584. |
| 68 | * |
| 69 | * LN: 560 561 562 563 567 568 569 |
| 70 | * DE: ~~~|____________________________//__________________________ |
| 71 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ |
| 72 | * VSYNC: _________________________|~~~~~~//~~~~~~~~~~~~~~~|__________ |
| 73 | * 22 blanking lines. VSYNC at 1320 (referenced to the HSYNC rising edge). |
| 74 | * |
| 75 | * LN: 1123 1124 1125 1 5 6 7 |
| 76 | * DE: ~~~|____________________________//__________________________ |
| 77 | * HSYNC: ____|~|_____|~|_____|~|_____|~|_//__|~|_____|~|_____|~|_____ |
| 78 | * VSYNC: ____________________|~~~~~~~~~~~//~~~~~~~~~~|_______________ |
| 79 | * 23 blanking lines |
| 80 | * |
| 81 | * The Armada LCD Controller line and pixel numbers are, like X timings, |
| 82 | * referenced to the top left of the active frame. |
| 83 | * |
| 84 | * So, translating these to our LCD controller: |
| 85 | * Odd frame, 563 total lines, VSYNC at line 543-548, pixel 1128. |
| 86 | * Even frame, 562 total lines, VSYNC at line 542-547, pixel 2448. |
| 87 | * Note: Vsync front porch remains constant! |
| 88 | * |
| 89 | * if (odd_frame) { |
| 90 | * vtotal = mode->crtc_vtotal + 1; |
| 91 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay + 1; |
| 92 | * vhorizpos = mode->crtc_hsync_start - mode->crtc_htotal / 2 |
| 93 | * } else { |
| 94 | * vtotal = mode->crtc_vtotal; |
| 95 | * vbackporch = mode->crtc_vsync_start - mode->crtc_vdisplay; |
| 96 | * vhorizpos = mode->crtc_hsync_start; |
| 97 | * } |
| 98 | * vfrontporch = mode->crtc_vtotal - mode->crtc_vsync_end; |
| 99 | * |
| 100 | * So, we need to reprogram these registers on each vsync event: |
| 101 | * LCD_SPU_V_PORCH, LCD_SPU_ADV_REG, LCD_SPUT_V_H_TOTAL |
| 102 | * |
| 103 | * Note: we do not use the frame done interrupts because these appear |
| 104 | * to happen too early, and lead to jitter on the display (presumably |
| 105 | * they occur at the end of the last active line, before the vsync back |
| 106 | * porch, which we're reprogramming.) |
| 107 | */ |
| 108 | |
| 109 | void |
| 110 | armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) |
| 111 | { |
| 112 | while (regs->offset != ~0) { |
| 113 | void __iomem *reg = dcrtc->base + regs->offset; |
| 114 | uint32_t val; |
| 115 | |
| 116 | val = regs->mask; |
| 117 | if (val != 0) |
| 118 | val &= readl_relaxed(reg); |
| 119 | writel_relaxed(val | regs->val, reg); |
| 120 | ++regs; |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | #define dpms_blanked(dpms) ((dpms) != DRM_MODE_DPMS_ON) |
| 125 | |
| 126 | static void armada_drm_crtc_update(struct armada_crtc *dcrtc) |
| 127 | { |
| 128 | uint32_t dumb_ctrl; |
| 129 | |
| 130 | dumb_ctrl = dcrtc->cfg_dumb_ctrl; |
| 131 | |
| 132 | if (!dpms_blanked(dcrtc->dpms)) |
| 133 | dumb_ctrl |= CFG_DUMB_ENA; |
| 134 | |
| 135 | /* |
| 136 | * When the dumb interface isn't in DUMB24_RGB888_0 mode, it might |
| 137 | * be using SPI or GPIO. If we set this to DUMB_BLANK, we will |
| 138 | * force LCD_D[23:0] to output blank color, overriding the GPIO or |
| 139 | * SPI usage. So leave it as-is unless in DUMB24_RGB888_0 mode. |
| 140 | */ |
| 141 | if (dpms_blanked(dcrtc->dpms) && |
| 142 | (dumb_ctrl & DUMB_MASK) == DUMB24_RGB888_0) { |
| 143 | dumb_ctrl &= ~DUMB_MASK; |
| 144 | dumb_ctrl |= DUMB_BLANK; |
| 145 | } |
| 146 | |
| 147 | /* |
| 148 | * The documentation doesn't indicate what the normal state of |
| 149 | * the sync signals are. Sebastian Hesselbart kindly probed |
| 150 | * these signals on his board to determine their state. |
| 151 | * |
| 152 | * The non-inverted state of the sync signals is active high. |
| 153 | * Setting these bits makes the appropriate signal active low. |
| 154 | */ |
| 155 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) |
| 156 | dumb_ctrl |= CFG_INV_CSYNC; |
| 157 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) |
| 158 | dumb_ctrl |= CFG_INV_HSYNC; |
| 159 | if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) |
| 160 | dumb_ctrl |= CFG_INV_VSYNC; |
| 161 | |
| 162 | if (dcrtc->dumb_ctrl != dumb_ctrl) { |
| 163 | dcrtc->dumb_ctrl = dumb_ctrl; |
| 164 | writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); |
| 165 | } |
| 166 | } |
| 167 | |
Russell King | f0b2487 | 2016-08-16 22:09:11 +0100 | [diff] [blame] | 168 | void armada_drm_plane_calc_addrs(u32 *addrs, struct drm_framebuffer *fb, |
| 169 | int x, int y) |
| 170 | { |
| 171 | u32 addr = drm_fb_obj(fb)->dev_addr; |
Ville Syrjälä | bcb0b46 | 2016-12-14 23:30:22 +0200 | [diff] [blame] | 172 | int num_planes = fb->format->num_planes; |
Russell King | f0b2487 | 2016-08-16 22:09:11 +0100 | [diff] [blame] | 173 | int i; |
| 174 | |
| 175 | if (num_planes > 3) |
| 176 | num_planes = 3; |
| 177 | |
| 178 | for (i = 0; i < num_planes; i++) |
| 179 | addrs[i] = addr + fb->offsets[i] + y * fb->pitches[i] + |
Ville Syrjälä | 353c859 | 2016-12-14 23:30:57 +0200 | [diff] [blame^] | 180 | x * fb->format->cpp[i]; |
Russell King | f0b2487 | 2016-08-16 22:09:11 +0100 | [diff] [blame] | 181 | for (; i < 3; i++) |
| 182 | addrs[i] = 0; |
| 183 | } |
| 184 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 185 | static unsigned armada_drm_crtc_calc_fb(struct drm_framebuffer *fb, |
| 186 | int x, int y, struct armada_regs *regs, bool interlaced) |
| 187 | { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 188 | unsigned pitch = fb->pitches[0]; |
Russell King | f0b2487 | 2016-08-16 22:09:11 +0100 | [diff] [blame] | 189 | u32 addrs[3], addr_odd, addr_even; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 190 | unsigned i = 0; |
| 191 | |
| 192 | DRM_DEBUG_DRIVER("pitch %u x %d y %d bpp %d\n", |
| 193 | pitch, x, y, fb->bits_per_pixel); |
| 194 | |
Russell King | f0b2487 | 2016-08-16 22:09:11 +0100 | [diff] [blame] | 195 | armada_drm_plane_calc_addrs(addrs, fb, x, y); |
| 196 | |
| 197 | addr_odd = addr_even = addrs[0]; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 198 | |
| 199 | if (interlaced) { |
| 200 | addr_even += pitch; |
| 201 | pitch *= 2; |
| 202 | } |
| 203 | |
| 204 | /* write offset, base, and pitch */ |
| 205 | armada_reg_queue_set(regs, i, addr_odd, LCD_CFG_GRA_START_ADDR0); |
| 206 | armada_reg_queue_set(regs, i, addr_even, LCD_CFG_GRA_START_ADDR1); |
| 207 | armada_reg_queue_mod(regs, i, pitch, 0xffff, LCD_CFG_GRA_PITCH); |
| 208 | |
| 209 | return i; |
| 210 | } |
| 211 | |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 212 | static void armada_drm_plane_work_run(struct armada_crtc *dcrtc, |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 213 | struct drm_plane *plane) |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 214 | { |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 215 | struct armada_plane *dplane = drm_to_armada_plane(plane); |
| 216 | struct armada_plane_work *work = xchg(&dplane->work, NULL); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 217 | |
| 218 | /* Handle any pending frame work. */ |
| 219 | if (work) { |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 220 | work->fn(dcrtc, dplane, work); |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 221 | drm_crtc_vblank_put(&dcrtc->crtc); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 222 | } |
Russell King | 7cb410c | 2015-08-07 13:34:26 +0100 | [diff] [blame] | 223 | |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 224 | wake_up(&dplane->frame_wait); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | int armada_drm_plane_work_queue(struct armada_crtc *dcrtc, |
| 228 | struct armada_plane *plane, struct armada_plane_work *work) |
| 229 | { |
| 230 | int ret; |
| 231 | |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 232 | ret = drm_crtc_vblank_get(&dcrtc->crtc); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 233 | if (ret) { |
| 234 | DRM_ERROR("failed to acquire vblank counter\n"); |
| 235 | return ret; |
| 236 | } |
| 237 | |
| 238 | ret = cmpxchg(&plane->work, NULL, work) ? -EBUSY : 0; |
| 239 | if (ret) |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 240 | drm_crtc_vblank_put(&dcrtc->crtc); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 241 | |
| 242 | return ret; |
| 243 | } |
| 244 | |
| 245 | int armada_drm_plane_work_wait(struct armada_plane *plane, long timeout) |
| 246 | { |
| 247 | return wait_event_timeout(plane->frame_wait, !plane->work, timeout); |
| 248 | } |
| 249 | |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 250 | struct armada_plane_work *armada_drm_plane_work_cancel( |
| 251 | struct armada_crtc *dcrtc, struct armada_plane *plane) |
Russell King | 7c8f7e1 | 2015-06-29 17:52:16 +0100 | [diff] [blame] | 252 | { |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 253 | struct armada_plane_work *work = xchg(&plane->work, NULL); |
Russell King | 7c8f7e1 | 2015-06-29 17:52:16 +0100 | [diff] [blame] | 254 | |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 255 | if (work) |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 256 | drm_crtc_vblank_put(&dcrtc->crtc); |
Russell King | 7c8f7e1 | 2015-06-29 17:52:16 +0100 | [diff] [blame] | 257 | |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 258 | return work; |
Russell King | 7c8f7e1 | 2015-06-29 17:52:16 +0100 | [diff] [blame] | 259 | } |
| 260 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 261 | static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, |
| 262 | struct armada_frame_work *work) |
| 263 | { |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 264 | struct armada_plane *plane = drm_to_armada_plane(dcrtc->crtc.primary); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 265 | |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 266 | return armada_drm_plane_work_queue(dcrtc, plane, &work->work); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 267 | } |
| 268 | |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 269 | static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc, |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 270 | struct armada_plane *plane, struct armada_plane_work *work) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 271 | { |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 272 | struct armada_frame_work *fwork = container_of(work, struct armada_frame_work, work); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 273 | struct drm_device *dev = dcrtc->crtc.dev; |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 274 | unsigned long flags; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 275 | |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 276 | spin_lock_irqsave(&dcrtc->irq_lock, flags); |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 277 | armada_drm_crtc_update_regs(dcrtc, fwork->regs); |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 278 | spin_unlock_irqrestore(&dcrtc->irq_lock, flags); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 279 | |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 280 | if (fwork->event) { |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 281 | spin_lock_irqsave(&dev->event_lock, flags); |
Gustavo Padovan | dd54b80 | 2016-06-06 11:41:33 -0300 | [diff] [blame] | 282 | drm_crtc_send_vblank_event(&dcrtc->crtc, fwork->event); |
Russell King | 709ffd8 | 2015-07-15 18:09:38 +0100 | [diff] [blame] | 283 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 284 | } |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 285 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 286 | /* Finally, queue the process-half of the cleanup. */ |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 287 | __armada_drm_queue_unref_work(dcrtc->crtc.dev, fwork->old_fb); |
| 288 | kfree(fwork); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 289 | } |
| 290 | |
| 291 | static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, |
| 292 | struct drm_framebuffer *fb, bool force) |
| 293 | { |
| 294 | struct armada_frame_work *work; |
| 295 | |
| 296 | if (!fb) |
| 297 | return; |
| 298 | |
| 299 | if (force) { |
| 300 | /* Display is disabled, so just drop the old fb */ |
| 301 | drm_framebuffer_unreference(fb); |
| 302 | return; |
| 303 | } |
| 304 | |
| 305 | work = kmalloc(sizeof(*work), GFP_KERNEL); |
| 306 | if (work) { |
| 307 | int i = 0; |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 308 | work->work.fn = armada_drm_crtc_complete_frame_work; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 309 | work->event = NULL; |
| 310 | work->old_fb = fb; |
| 311 | armada_reg_queue_end(work->regs, i); |
| 312 | |
| 313 | if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) |
| 314 | return; |
| 315 | |
| 316 | kfree(work); |
| 317 | } |
| 318 | |
| 319 | /* |
| 320 | * Oops - just drop the reference immediately and hope for |
| 321 | * the best. The worst that will happen is the buffer gets |
| 322 | * reused before it has finished being displayed. |
| 323 | */ |
| 324 | drm_framebuffer_unreference(fb); |
| 325 | } |
| 326 | |
| 327 | static void armada_drm_vblank_off(struct armada_crtc *dcrtc) |
| 328 | { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 329 | /* |
| 330 | * Tell the DRM core that vblank IRQs aren't going to happen for |
| 331 | * a while. This cleans up any pending vblank events for us. |
| 332 | */ |
Russell King | 178e561 | 2014-10-11 23:57:04 +0100 | [diff] [blame] | 333 | drm_crtc_vblank_off(&dcrtc->crtc); |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 334 | armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | void armada_drm_crtc_gamma_set(struct drm_crtc *crtc, u16 r, u16 g, u16 b, |
| 338 | int idx) |
| 339 | { |
| 340 | } |
| 341 | |
| 342 | void armada_drm_crtc_gamma_get(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
| 343 | int idx) |
| 344 | { |
| 345 | } |
| 346 | |
| 347 | /* The mode_config.mutex will be held for this call */ |
| 348 | static void armada_drm_crtc_dpms(struct drm_crtc *crtc, int dpms) |
| 349 | { |
| 350 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 351 | |
Russell King | ea908ba | 2016-10-04 22:19:57 +0100 | [diff] [blame] | 352 | if (dpms_blanked(dcrtc->dpms) != dpms_blanked(dpms)) { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 353 | if (dpms_blanked(dpms)) |
| 354 | armada_drm_vblank_off(dcrtc); |
Russell King | ea908ba | 2016-10-04 22:19:57 +0100 | [diff] [blame] | 355 | else if (!IS_ERR(dcrtc->clk)) |
| 356 | WARN_ON(clk_prepare_enable(dcrtc->clk)); |
| 357 | dcrtc->dpms = dpms; |
| 358 | armada_drm_crtc_update(dcrtc); |
| 359 | if (!dpms_blanked(dpms)) |
Russell King | 178e561 | 2014-10-11 23:57:04 +0100 | [diff] [blame] | 360 | drm_crtc_vblank_on(&dcrtc->crtc); |
Russell King | ea908ba | 2016-10-04 22:19:57 +0100 | [diff] [blame] | 361 | else if (!IS_ERR(dcrtc->clk)) |
| 362 | clk_disable_unprepare(dcrtc->clk); |
| 363 | } else if (dcrtc->dpms != dpms) { |
| 364 | dcrtc->dpms = dpms; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 365 | } |
| 366 | } |
| 367 | |
| 368 | /* |
| 369 | * Prepare for a mode set. Turn off overlay to ensure that we don't end |
| 370 | * up with the overlay size being bigger than the active screen size. |
| 371 | * We rely upon X refreshing this state after the mode set has completed. |
| 372 | * |
| 373 | * The mode_config.mutex will be held for this call |
| 374 | */ |
| 375 | static void armada_drm_crtc_prepare(struct drm_crtc *crtc) |
| 376 | { |
| 377 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 378 | struct drm_plane *plane; |
| 379 | |
| 380 | /* |
| 381 | * If we have an overlay plane associated with this CRTC, disable |
| 382 | * it before the modeset to avoid its coordinates being outside |
Russell King | f8e1406 | 2015-06-29 17:52:42 +0100 | [diff] [blame] | 383 | * the new mode parameters. |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 384 | */ |
| 385 | plane = dcrtc->plane; |
Russell King | f8e1406 | 2015-06-29 17:52:42 +0100 | [diff] [blame] | 386 | if (plane) |
| 387 | drm_plane_force_disable(plane); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | /* The mode_config.mutex will be held for this call */ |
| 391 | static void armada_drm_crtc_commit(struct drm_crtc *crtc) |
| 392 | { |
| 393 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 394 | |
| 395 | if (dcrtc->dpms != DRM_MODE_DPMS_ON) { |
| 396 | dcrtc->dpms = DRM_MODE_DPMS_ON; |
| 397 | armada_drm_crtc_update(dcrtc); |
| 398 | } |
| 399 | } |
| 400 | |
| 401 | /* The mode_config.mutex will be held for this call */ |
| 402 | static bool armada_drm_crtc_mode_fixup(struct drm_crtc *crtc, |
| 403 | const struct drm_display_mode *mode, struct drm_display_mode *adj) |
| 404 | { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 405 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 406 | int ret; |
| 407 | |
| 408 | /* We can't do interlaced modes if we don't have the SPU_ADV_REG */ |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 409 | if (!dcrtc->variant->has_spu_adv_reg && |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 410 | adj->flags & DRM_MODE_FLAG_INTERLACE) |
| 411 | return false; |
| 412 | |
| 413 | /* Check whether the display mode is possible */ |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 414 | ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 415 | if (ret) |
| 416 | return false; |
| 417 | |
| 418 | return true; |
| 419 | } |
| 420 | |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 421 | static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 422 | { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 423 | void __iomem *base = dcrtc->base; |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 424 | struct drm_plane *ovl_plane; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 425 | |
| 426 | if (stat & DMA_FF_UNDERFLOW) |
| 427 | DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); |
| 428 | if (stat & GRA_FF_UNDERFLOW) |
| 429 | DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); |
| 430 | |
| 431 | if (stat & VSYNC_IRQ) |
Gustavo Padovan | 0ac28c5 | 2016-07-04 21:04:48 -0300 | [diff] [blame] | 432 | drm_crtc_handle_vblank(&dcrtc->crtc); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 433 | |
| 434 | spin_lock(&dcrtc->irq_lock); |
Russell King | 4a8506d | 2015-08-07 09:33:05 +0100 | [diff] [blame] | 435 | ovl_plane = dcrtc->plane; |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 436 | if (ovl_plane) |
| 437 | armada_drm_plane_work_run(dcrtc, ovl_plane); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 438 | |
| 439 | if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { |
| 440 | int i = stat & GRA_FRAME_IRQ0 ? 0 : 1; |
| 441 | uint32_t val; |
| 442 | |
| 443 | writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); |
| 444 | writel_relaxed(dcrtc->v[i].spu_v_h_total, |
| 445 | base + LCD_SPUT_V_H_TOTAL); |
| 446 | |
| 447 | val = readl_relaxed(base + LCD_SPU_ADV_REG); |
| 448 | val &= ~(ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | ADV_VSYNCOFFEN); |
| 449 | val |= dcrtc->v[i].spu_adv_reg; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 450 | writel_relaxed(val, base + LCD_SPU_ADV_REG); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 451 | } |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 452 | |
| 453 | if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { |
| 454 | writel_relaxed(dcrtc->cursor_hw_pos, |
| 455 | base + LCD_SPU_HWC_OVSA_HPXL_VLN); |
| 456 | writel_relaxed(dcrtc->cursor_hw_sz, |
| 457 | base + LCD_SPU_HWC_HPXL_VLN); |
| 458 | armada_updatel(CFG_HWC_ENA, |
| 459 | CFG_HWC_ENA | CFG_HWC_1BITMOD | CFG_HWC_1BITENA, |
| 460 | base + LCD_SPU_DMA_CTRL0); |
| 461 | dcrtc->cursor_update = false; |
| 462 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 463 | } |
| 464 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 465 | spin_unlock(&dcrtc->irq_lock); |
| 466 | |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 467 | if (stat & GRA_FRAME_IRQ) |
| 468 | armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 469 | } |
| 470 | |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 471 | static irqreturn_t armada_drm_irq(int irq, void *arg) |
| 472 | { |
| 473 | struct armada_crtc *dcrtc = arg; |
| 474 | u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); |
| 475 | |
| 476 | /* |
| 477 | * This is rediculous - rather than writing bits to clear, we |
| 478 | * have to set the actual status register value. This is racy. |
| 479 | */ |
| 480 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); |
| 481 | |
Russell King | c8a220c | 2016-05-17 13:51:08 +0100 | [diff] [blame] | 482 | trace_armada_drm_irq(&dcrtc->crtc, stat); |
| 483 | |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 484 | /* Mask out those interrupts we haven't enabled */ |
| 485 | v = stat & dcrtc->irq_ena; |
| 486 | |
| 487 | if (v & (VSYNC_IRQ|GRA_FRAME_IRQ|DUMB_FRAMEDONE)) { |
| 488 | armada_drm_crtc_irq(dcrtc, stat); |
| 489 | return IRQ_HANDLED; |
| 490 | } |
| 491 | return IRQ_NONE; |
| 492 | } |
| 493 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 494 | /* These are locked by dev->vbl_lock */ |
| 495 | void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) |
| 496 | { |
| 497 | if (dcrtc->irq_ena & mask) { |
| 498 | dcrtc->irq_ena &= ~mask; |
| 499 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 500 | } |
| 501 | } |
| 502 | |
| 503 | void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) |
| 504 | { |
| 505 | if ((dcrtc->irq_ena & mask) != mask) { |
| 506 | dcrtc->irq_ena |= mask; |
| 507 | writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 508 | if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) |
| 509 | writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); |
| 510 | } |
| 511 | } |
| 512 | |
| 513 | static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) |
| 514 | { |
| 515 | struct drm_display_mode *adj = &dcrtc->crtc.mode; |
| 516 | uint32_t val = 0; |
| 517 | |
| 518 | if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) |
| 519 | val |= CFG_CSC_YUV_CCIR709; |
| 520 | if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) |
| 521 | val |= CFG_CSC_RGB_STUDIO; |
| 522 | |
| 523 | /* |
| 524 | * In auto mode, set the colorimetry, based upon the HDMI spec. |
| 525 | * 1280x720p, 1920x1080p and 1920x1080i use ITU709, others use |
| 526 | * ITU601. It may be more appropriate to set this depending on |
| 527 | * the source - but what if the graphic frame is YUV and the |
| 528 | * video frame is RGB? |
| 529 | */ |
| 530 | if ((adj->hdisplay == 1280 && adj->vdisplay == 720 && |
| 531 | !(adj->flags & DRM_MODE_FLAG_INTERLACE)) || |
| 532 | (adj->hdisplay == 1920 && adj->vdisplay == 1080)) { |
| 533 | if (dcrtc->csc_yuv_mode == CSC_AUTO) |
| 534 | val |= CFG_CSC_YUV_CCIR709; |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * We assume we're connected to a TV-like device, so the YUV->RGB |
| 539 | * conversion should produce a limited range. We should set this |
| 540 | * depending on the connectors attached to this CRTC, and what |
| 541 | * kind of device they report being connected. |
| 542 | */ |
| 543 | if (dcrtc->csc_rgb_mode == CSC_AUTO) |
| 544 | val |= CFG_CSC_RGB_STUDIO; |
| 545 | |
| 546 | return val; |
| 547 | } |
| 548 | |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 549 | static void armada_drm_primary_set(struct drm_crtc *crtc, |
| 550 | struct drm_plane *plane, int x, int y) |
| 551 | { |
| 552 | struct armada_plane_state *state = &drm_to_armada_plane(plane)->state; |
| 553 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
Russell King | 2925db0 | 2016-08-16 22:09:10 +0100 | [diff] [blame] | 554 | struct armada_regs regs[8]; |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 555 | bool interlaced = dcrtc->interlaced; |
| 556 | unsigned i; |
Russell King | 2925db0 | 2016-08-16 22:09:10 +0100 | [diff] [blame] | 557 | u32 ctrl0; |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 558 | |
| 559 | i = armada_drm_crtc_calc_fb(plane->fb, x, y, regs, interlaced); |
| 560 | |
Russell King | 2925db0 | 2016-08-16 22:09:10 +0100 | [diff] [blame] | 561 | armada_reg_queue_set(regs, i, state->dst_yx, LCD_SPU_GRA_OVSA_HPXL_VLN); |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 562 | armada_reg_queue_set(regs, i, state->src_hw, LCD_SPU_GRA_HPXL_VLN); |
| 563 | armada_reg_queue_set(regs, i, state->dst_hw, LCD_SPU_GZM_HPXL_VLN); |
| 564 | |
| 565 | ctrl0 = state->ctrl0; |
| 566 | if (interlaced) |
| 567 | ctrl0 |= CFG_GRA_FTOGGLE; |
| 568 | |
| 569 | armada_reg_queue_mod(regs, i, ctrl0, CFG_GRAFORMAT | |
| 570 | CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV | |
| 571 | CFG_SWAPYU | CFG_YUV2RGB) | |
| 572 | CFG_PALETTE_ENA | CFG_GRA_FTOGGLE, |
| 573 | LCD_SPU_DMA_CTRL0); |
| 574 | armada_reg_queue_end(regs, i); |
| 575 | armada_drm_crtc_update_regs(dcrtc, regs); |
| 576 | } |
| 577 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 578 | /* The mode_config.mutex will be held for this call */ |
| 579 | static int armada_drm_crtc_mode_set(struct drm_crtc *crtc, |
| 580 | struct drm_display_mode *mode, struct drm_display_mode *adj, |
| 581 | int x, int y, struct drm_framebuffer *old_fb) |
| 582 | { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 583 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 584 | struct armada_regs regs[17]; |
| 585 | uint32_t lm, rm, tm, bm, val, sclk; |
| 586 | unsigned long flags; |
| 587 | unsigned i; |
| 588 | bool interlaced; |
| 589 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 590 | drm_framebuffer_reference(crtc->primary->fb); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 591 | |
| 592 | interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE); |
| 593 | |
Russell King | 8be523d | 2016-08-16 22:09:08 +0100 | [diff] [blame] | 594 | val = CFG_GRA_ENA | CFG_GRA_HSMOOTH; |
| 595 | val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); |
| 596 | val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 597 | |
Russell King | 8be523d | 2016-08-16 22:09:08 +0100 | [diff] [blame] | 598 | if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) |
| 599 | val |= CFG_PALETTE_ENA; |
| 600 | |
| 601 | drm_to_armada_plane(crtc->primary)->state.ctrl0 = val; |
| 602 | drm_to_armada_plane(crtc->primary)->state.src_hw = |
| 603 | drm_to_armada_plane(crtc->primary)->state.dst_hw = |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 604 | adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; |
Russell King | 8be523d | 2016-08-16 22:09:08 +0100 | [diff] [blame] | 605 | drm_to_armada_plane(crtc->primary)->state.dst_yx = 0; |
| 606 | |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 607 | i = 0; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 608 | rm = adj->crtc_hsync_start - adj->crtc_hdisplay; |
| 609 | lm = adj->crtc_htotal - adj->crtc_hsync_end; |
| 610 | bm = adj->crtc_vsync_start - adj->crtc_vdisplay; |
| 611 | tm = adj->crtc_vtotal - adj->crtc_vsync_end; |
| 612 | |
| 613 | DRM_DEBUG_DRIVER("H: %d %d %d %d lm %d rm %d\n", |
| 614 | adj->crtc_hdisplay, |
| 615 | adj->crtc_hsync_start, |
| 616 | adj->crtc_hsync_end, |
| 617 | adj->crtc_htotal, lm, rm); |
| 618 | DRM_DEBUG_DRIVER("V: %d %d %d %d tm %d bm %d\n", |
| 619 | adj->crtc_vdisplay, |
| 620 | adj->crtc_vsync_start, |
| 621 | adj->crtc_vsync_end, |
| 622 | adj->crtc_vtotal, tm, bm); |
| 623 | |
| 624 | /* Wait for pending flips to complete */ |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 625 | armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), |
| 626 | MAX_SCHEDULE_TIMEOUT); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 627 | |
Russell King | 178e561 | 2014-10-11 23:57:04 +0100 | [diff] [blame] | 628 | drm_crtc_vblank_off(crtc); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 629 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 630 | val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; |
| 631 | if (val != dcrtc->dumb_ctrl) { |
| 632 | dcrtc->dumb_ctrl = val; |
| 633 | writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); |
| 634 | } |
| 635 | |
Russell King | e0ac5e9 | 2015-06-29 18:01:38 +0100 | [diff] [blame] | 636 | /* |
| 637 | * If we are blanked, we would have disabled the clock. Re-enable |
| 638 | * it so that compute_clock() does the right thing. |
| 639 | */ |
| 640 | if (!IS_ERR(dcrtc->clk) && dpms_blanked(dcrtc->dpms)) |
| 641 | WARN_ON(clk_prepare_enable(dcrtc->clk)); |
| 642 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 643 | /* Now compute the divider for real */ |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 644 | dcrtc->variant->compute_clock(dcrtc, adj, &sclk); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 645 | |
| 646 | /* Ensure graphic fifo is enabled */ |
| 647 | armada_reg_queue_mod(regs, i, 0, CFG_PDWN64x66, LCD_SPU_SRAM_PARA1); |
| 648 | armada_reg_queue_set(regs, i, sclk, LCD_CFG_SCLK_DIV); |
| 649 | |
| 650 | if (interlaced ^ dcrtc->interlaced) { |
| 651 | if (adj->flags & DRM_MODE_FLAG_INTERLACE) |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 652 | drm_crtc_vblank_get(&dcrtc->crtc); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 653 | else |
Gustavo Padovan | accbaf6 | 2016-06-06 11:41:40 -0300 | [diff] [blame] | 654 | drm_crtc_vblank_put(&dcrtc->crtc); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 655 | dcrtc->interlaced = interlaced; |
| 656 | } |
| 657 | |
| 658 | spin_lock_irqsave(&dcrtc->irq_lock, flags); |
| 659 | |
| 660 | /* Even interlaced/progressive frame */ |
| 661 | dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | |
| 662 | adj->crtc_htotal; |
| 663 | dcrtc->v[1].spu_v_porch = tm << 16 | bm; |
| 664 | val = adj->crtc_hsync_start; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 665 | dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 666 | dcrtc->variant->spu_adv_reg; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 667 | |
| 668 | if (interlaced) { |
| 669 | /* Odd interlaced frame */ |
| 670 | dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + |
| 671 | (1 << 16); |
| 672 | dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; |
| 673 | val = adj->crtc_hsync_start - adj->crtc_htotal / 2; |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 674 | dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 675 | dcrtc->variant->spu_adv_reg; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 676 | } else { |
| 677 | dcrtc->v[0] = dcrtc->v[1]; |
| 678 | } |
| 679 | |
| 680 | val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay; |
| 681 | |
| 682 | armada_reg_queue_set(regs, i, val, LCD_SPU_V_H_ACTIVE); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 683 | armada_reg_queue_set(regs, i, (lm << 16) | rm, LCD_SPU_H_PORCH); |
| 684 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); |
| 685 | armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, |
| 686 | LCD_SPUT_V_H_TOTAL); |
| 687 | |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 688 | if (dcrtc->variant->has_spu_adv_reg) { |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 689 | armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, |
| 690 | ADV_VSYNC_L_OFF | ADV_VSYNC_H_OFF | |
| 691 | ADV_VSYNCOFFEN, LCD_SPU_ADV_REG); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 692 | } |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 693 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 694 | val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0; |
| 695 | armada_reg_queue_mod(regs, i, val, CFG_VSYNC_INV, LCD_SPU_DMA_CTRL1); |
| 696 | |
| 697 | val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); |
| 698 | armada_reg_queue_set(regs, i, val, LCD_SPU_IOPAD_CONTROL); |
| 699 | armada_reg_queue_end(regs, i); |
| 700 | |
| 701 | armada_drm_crtc_update_regs(dcrtc, regs); |
Russell King | 37af35c | 2016-08-16 22:09:09 +0100 | [diff] [blame] | 702 | |
| 703 | armada_drm_primary_set(crtc, crtc->primary, x, y); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 704 | spin_unlock_irqrestore(&dcrtc->irq_lock, flags); |
| 705 | |
| 706 | armada_drm_crtc_update(dcrtc); |
| 707 | |
Russell King | 178e561 | 2014-10-11 23:57:04 +0100 | [diff] [blame] | 708 | drm_crtc_vblank_on(crtc); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 709 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); |
| 710 | |
| 711 | return 0; |
| 712 | } |
| 713 | |
| 714 | /* The mode_config.mutex will be held for this call */ |
| 715 | static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
| 716 | struct drm_framebuffer *old_fb) |
| 717 | { |
| 718 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 719 | struct armada_regs regs[4]; |
| 720 | unsigned i; |
| 721 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 722 | i = armada_drm_crtc_calc_fb(crtc->primary->fb, crtc->x, crtc->y, regs, |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 723 | dcrtc->interlaced); |
| 724 | armada_reg_queue_end(regs, i); |
| 725 | |
| 726 | /* Wait for pending flips to complete */ |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 727 | armada_drm_plane_work_wait(drm_to_armada_plane(dcrtc->crtc.primary), |
| 728 | MAX_SCHEDULE_TIMEOUT); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 729 | |
| 730 | /* Take a reference to the new fb as we're using it */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 731 | drm_framebuffer_reference(crtc->primary->fb); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 732 | |
| 733 | /* Update the base in the CRTC */ |
| 734 | armada_drm_crtc_update_regs(dcrtc, regs); |
| 735 | |
| 736 | /* Drop our previously held reference */ |
| 737 | armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); |
| 738 | |
| 739 | return 0; |
| 740 | } |
| 741 | |
Russell King | 5832680 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 742 | void armada_drm_crtc_plane_disable(struct armada_crtc *dcrtc, |
| 743 | struct drm_plane *plane) |
| 744 | { |
Russell King | 9099ea1 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 745 | u32 sram_para1, dma_ctrl0_mask; |
Russell King | 5832680 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 746 | |
| 747 | /* |
| 748 | * Drop our reference on any framebuffer attached to this plane. |
| 749 | * We don't need to NULL this out as drm_plane_force_disable(), |
| 750 | * and __setplane_internal() will do so for an overlay plane, and |
| 751 | * __drm_helper_disable_unused_functions() will do so for the |
| 752 | * primary plane. |
| 753 | */ |
| 754 | if (plane->fb) |
| 755 | drm_framebuffer_unreference(plane->fb); |
| 756 | |
| 757 | /* Power down the Y/U/V FIFOs */ |
| 758 | sram_para1 = CFG_PDWN16x66 | CFG_PDWN32x66; |
| 759 | |
| 760 | /* Power down most RAMs and FIFOs if this is the primary plane */ |
Russell King | 9099ea1 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 761 | if (plane->type == DRM_PLANE_TYPE_PRIMARY) { |
Russell King | 5832680 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 762 | sram_para1 |= CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | |
| 763 | CFG_PDWN32x32 | CFG_PDWN64x66; |
Russell King | 9099ea1 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 764 | dma_ctrl0_mask = CFG_GRA_ENA; |
| 765 | } else { |
| 766 | dma_ctrl0_mask = CFG_DMA_ENA; |
| 767 | } |
| 768 | |
| 769 | spin_lock_irq(&dcrtc->irq_lock); |
| 770 | armada_updatel(0, dma_ctrl0_mask, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 771 | spin_unlock_irq(&dcrtc->irq_lock); |
Russell King | 5832680 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 772 | |
| 773 | armada_updatel(sram_para1, 0, dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 774 | } |
| 775 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 776 | /* The mode_config.mutex will be held for this call */ |
| 777 | static void armada_drm_crtc_disable(struct drm_crtc *crtc) |
| 778 | { |
| 779 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 780 | |
| 781 | armada_drm_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
Russell King | 5832680 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 782 | armada_drm_crtc_plane_disable(dcrtc, crtc->primary); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 783 | } |
| 784 | |
| 785 | static const struct drm_crtc_helper_funcs armada_crtc_helper_funcs = { |
| 786 | .dpms = armada_drm_crtc_dpms, |
| 787 | .prepare = armada_drm_crtc_prepare, |
| 788 | .commit = armada_drm_crtc_commit, |
| 789 | .mode_fixup = armada_drm_crtc_mode_fixup, |
| 790 | .mode_set = armada_drm_crtc_mode_set, |
| 791 | .mode_set_base = armada_drm_crtc_mode_set_base, |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 792 | .disable = armada_drm_crtc_disable, |
| 793 | }; |
| 794 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 795 | static void armada_load_cursor_argb(void __iomem *base, uint32_t *pix, |
| 796 | unsigned stride, unsigned width, unsigned height) |
| 797 | { |
| 798 | uint32_t addr; |
| 799 | unsigned y; |
| 800 | |
| 801 | addr = SRAM_HWC32_RAM1; |
| 802 | for (y = 0; y < height; y++) { |
| 803 | uint32_t *p = &pix[y * stride]; |
| 804 | unsigned x; |
| 805 | |
| 806 | for (x = 0; x < width; x++, p++) { |
| 807 | uint32_t val = *p; |
| 808 | |
| 809 | val = (val & 0xff00ff00) | |
| 810 | (val & 0x000000ff) << 16 | |
| 811 | (val & 0x00ff0000) >> 16; |
| 812 | |
| 813 | writel_relaxed(val, |
| 814 | base + LCD_SPU_SRAM_WRDAT); |
| 815 | writel_relaxed(addr | SRAM_WRITE, |
| 816 | base + LCD_SPU_SRAM_CTRL); |
Russell King | c39b069 | 2014-04-07 12:00:17 +0100 | [diff] [blame] | 817 | readl_relaxed(base + LCD_SPU_HWC_OVSA_HPXL_VLN); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 818 | addr += 1; |
| 819 | if ((addr & 0x00ff) == 0) |
| 820 | addr += 0xf00; |
| 821 | if ((addr & 0x30ff) == 0) |
| 822 | addr = SRAM_HWC32_RAM2; |
| 823 | } |
| 824 | } |
| 825 | } |
| 826 | |
| 827 | static void armada_drm_crtc_cursor_tran(void __iomem *base) |
| 828 | { |
| 829 | unsigned addr; |
| 830 | |
| 831 | for (addr = 0; addr < 256; addr++) { |
| 832 | /* write the default value */ |
| 833 | writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT); |
| 834 | writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN, |
| 835 | base + LCD_SPU_SRAM_CTRL); |
| 836 | } |
| 837 | } |
| 838 | |
| 839 | static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) |
| 840 | { |
| 841 | uint32_t xoff, xscr, w = dcrtc->cursor_w, s; |
| 842 | uint32_t yoff, yscr, h = dcrtc->cursor_h; |
| 843 | uint32_t para1; |
| 844 | |
| 845 | /* |
| 846 | * Calculate the visible width and height of the cursor, |
| 847 | * screen position, and the position in the cursor bitmap. |
| 848 | */ |
| 849 | if (dcrtc->cursor_x < 0) { |
| 850 | xoff = -dcrtc->cursor_x; |
| 851 | xscr = 0; |
| 852 | w -= min(xoff, w); |
| 853 | } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { |
| 854 | xoff = 0; |
| 855 | xscr = dcrtc->cursor_x; |
| 856 | w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); |
| 857 | } else { |
| 858 | xoff = 0; |
| 859 | xscr = dcrtc->cursor_x; |
| 860 | } |
| 861 | |
| 862 | if (dcrtc->cursor_y < 0) { |
| 863 | yoff = -dcrtc->cursor_y; |
| 864 | yscr = 0; |
| 865 | h -= min(yoff, h); |
| 866 | } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { |
| 867 | yoff = 0; |
| 868 | yscr = dcrtc->cursor_y; |
| 869 | h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); |
| 870 | } else { |
| 871 | yoff = 0; |
| 872 | yscr = dcrtc->cursor_y; |
| 873 | } |
| 874 | |
| 875 | /* On interlaced modes, the vertical cursor size must be halved */ |
| 876 | s = dcrtc->cursor_w; |
| 877 | if (dcrtc->interlaced) { |
| 878 | s *= 2; |
| 879 | yscr /= 2; |
| 880 | h /= 2; |
| 881 | } |
| 882 | |
| 883 | if (!dcrtc->cursor_obj || !h || !w) { |
| 884 | spin_lock_irq(&dcrtc->irq_lock); |
| 885 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 886 | dcrtc->cursor_update = false; |
| 887 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 888 | spin_unlock_irq(&dcrtc->irq_lock); |
| 889 | return 0; |
| 890 | } |
| 891 | |
| 892 | para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 893 | armada_updatel(CFG_CSB_256x32, CFG_CSB_256x32 | CFG_PDWN256x32, |
| 894 | dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 895 | |
| 896 | /* |
| 897 | * Initialize the transparency if the SRAM was powered down. |
| 898 | * We must also reload the cursor data as well. |
| 899 | */ |
| 900 | if (!(para1 & CFG_CSB_256x32)) { |
| 901 | armada_drm_crtc_cursor_tran(dcrtc->base); |
| 902 | reload = true; |
| 903 | } |
| 904 | |
| 905 | if (dcrtc->cursor_hw_sz != (h << 16 | w)) { |
| 906 | spin_lock_irq(&dcrtc->irq_lock); |
| 907 | armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 908 | dcrtc->cursor_update = false; |
| 909 | armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 910 | spin_unlock_irq(&dcrtc->irq_lock); |
| 911 | reload = true; |
| 912 | } |
| 913 | if (reload) { |
| 914 | struct armada_gem_object *obj = dcrtc->cursor_obj; |
| 915 | uint32_t *pix; |
| 916 | /* Set the top-left corner of the cursor image */ |
| 917 | pix = obj->addr; |
| 918 | pix += yoff * s + xoff; |
| 919 | armada_load_cursor_argb(dcrtc->base, pix, s, w, h); |
| 920 | } |
| 921 | |
| 922 | /* Reload the cursor position, size and enable in the IRQ handler */ |
| 923 | spin_lock_irq(&dcrtc->irq_lock); |
| 924 | dcrtc->cursor_hw_pos = yscr << 16 | xscr; |
| 925 | dcrtc->cursor_hw_sz = h << 16 | w; |
| 926 | dcrtc->cursor_update = true; |
| 927 | armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); |
| 928 | spin_unlock_irq(&dcrtc->irq_lock); |
| 929 | |
| 930 | return 0; |
| 931 | } |
| 932 | |
| 933 | static void cursor_update(void *data) |
| 934 | { |
| 935 | armada_drm_crtc_cursor_update(data, true); |
| 936 | } |
| 937 | |
| 938 | static int armada_drm_crtc_cursor_set(struct drm_crtc *crtc, |
| 939 | struct drm_file *file, uint32_t handle, uint32_t w, uint32_t h) |
| 940 | { |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 941 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 942 | struct armada_gem_object *obj = NULL; |
| 943 | int ret; |
| 944 | |
| 945 | /* If no cursor support, replicate drm's return value */ |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 946 | if (!dcrtc->variant->has_spu_adv_reg) |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 947 | return -ENXIO; |
| 948 | |
| 949 | if (handle && w > 0 && h > 0) { |
| 950 | /* maximum size is 64x32 or 32x64 */ |
| 951 | if (w > 64 || h > 64 || (w > 32 && h > 32)) |
| 952 | return -ENOMEM; |
| 953 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 954 | obj = armada_gem_object_lookup(file, handle); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 955 | if (!obj) |
| 956 | return -ENOENT; |
| 957 | |
| 958 | /* Must be a kernel-mapped object */ |
| 959 | if (!obj->addr) { |
| 960 | drm_gem_object_unreference_unlocked(&obj->obj); |
| 961 | return -EINVAL; |
| 962 | } |
| 963 | |
| 964 | if (obj->obj.size < w * h * 4) { |
| 965 | DRM_ERROR("buffer is too small\n"); |
| 966 | drm_gem_object_unreference_unlocked(&obj->obj); |
| 967 | return -ENOMEM; |
| 968 | } |
| 969 | } |
| 970 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 971 | if (dcrtc->cursor_obj) { |
| 972 | dcrtc->cursor_obj->update = NULL; |
| 973 | dcrtc->cursor_obj->update_data = NULL; |
Daniel Vetter | 4bd3fd4 | 2015-11-23 10:32:45 +0100 | [diff] [blame] | 974 | drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 975 | } |
| 976 | dcrtc->cursor_obj = obj; |
| 977 | dcrtc->cursor_w = w; |
| 978 | dcrtc->cursor_h = h; |
| 979 | ret = armada_drm_crtc_cursor_update(dcrtc, true); |
| 980 | if (obj) { |
| 981 | obj->update_data = dcrtc; |
| 982 | obj->update = cursor_update; |
| 983 | } |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 984 | |
| 985 | return ret; |
| 986 | } |
| 987 | |
| 988 | static int armada_drm_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
| 989 | { |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 990 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 991 | int ret; |
| 992 | |
| 993 | /* If no cursor support, replicate drm's return value */ |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 994 | if (!dcrtc->variant->has_spu_adv_reg) |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 995 | return -EFAULT; |
| 996 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 997 | dcrtc->cursor_x = x; |
| 998 | dcrtc->cursor_y = y; |
| 999 | ret = armada_drm_crtc_cursor_update(dcrtc, false); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 1000 | |
| 1001 | return ret; |
| 1002 | } |
| 1003 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1004 | static void armada_drm_crtc_destroy(struct drm_crtc *crtc) |
| 1005 | { |
| 1006 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 1007 | struct armada_private *priv = crtc->dev->dev_private; |
| 1008 | |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 1009 | if (dcrtc->cursor_obj) |
Daniel Vetter | 7a6f713 | 2015-11-23 10:32:34 +0100 | [diff] [blame] | 1010 | drm_gem_object_unreference_unlocked(&dcrtc->cursor_obj->obj); |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 1011 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1012 | priv->dcrtc[dcrtc->num] = NULL; |
| 1013 | drm_crtc_cleanup(&dcrtc->crtc); |
| 1014 | |
| 1015 | if (!IS_ERR(dcrtc->clk)) |
| 1016 | clk_disable_unprepare(dcrtc->clk); |
| 1017 | |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 1018 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 1019 | |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1020 | of_node_put(dcrtc->crtc.port); |
| 1021 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1022 | kfree(dcrtc); |
| 1023 | } |
| 1024 | |
| 1025 | /* |
| 1026 | * The mode_config lock is held here, to prevent races between this |
| 1027 | * and a mode_set. |
| 1028 | */ |
| 1029 | static int armada_drm_crtc_page_flip(struct drm_crtc *crtc, |
Dave Airlie | 5e4e3ba | 2013-10-22 09:38:18 +0100 | [diff] [blame] | 1030 | struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, uint32_t page_flip_flags) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1031 | { |
| 1032 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 1033 | struct armada_frame_work *work; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1034 | unsigned i; |
| 1035 | int ret; |
| 1036 | |
| 1037 | /* We don't support changing the pixel format */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1038 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1039 | return -EINVAL; |
| 1040 | |
| 1041 | work = kmalloc(sizeof(*work), GFP_KERNEL); |
| 1042 | if (!work) |
| 1043 | return -ENOMEM; |
| 1044 | |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 1045 | work->work.fn = armada_drm_crtc_complete_frame_work; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1046 | work->event = event; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1047 | work->old_fb = dcrtc->crtc.primary->fb; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1048 | |
| 1049 | i = armada_drm_crtc_calc_fb(fb, crtc->x, crtc->y, work->regs, |
| 1050 | dcrtc->interlaced); |
| 1051 | armada_reg_queue_end(work->regs, i); |
| 1052 | |
| 1053 | /* |
Russell King | c548830 | 2014-10-11 23:53:35 +0100 | [diff] [blame] | 1054 | * Ensure that we hold a reference on the new framebuffer. |
| 1055 | * This has to match the behaviour in mode_set. |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1056 | */ |
Russell King | c548830 | 2014-10-11 23:53:35 +0100 | [diff] [blame] | 1057 | drm_framebuffer_reference(fb); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1058 | |
| 1059 | ret = armada_drm_crtc_queue_frame_work(dcrtc, work); |
| 1060 | if (ret) { |
Russell King | c548830 | 2014-10-11 23:53:35 +0100 | [diff] [blame] | 1061 | /* Undo our reference above */ |
| 1062 | drm_framebuffer_unreference(fb); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1063 | kfree(work); |
| 1064 | return ret; |
| 1065 | } |
| 1066 | |
| 1067 | /* |
| 1068 | * Don't take a reference on the new framebuffer; |
| 1069 | * drm_mode_page_flip_ioctl() has already grabbed a reference and |
| 1070 | * will _not_ drop that reference on successful return from this |
| 1071 | * function. Simply mark this new framebuffer as the current one. |
| 1072 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1073 | dcrtc->crtc.primary->fb = fb; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1074 | |
| 1075 | /* |
| 1076 | * Finally, if the display is blanked, we won't receive an |
| 1077 | * interrupt, so complete it now. |
| 1078 | */ |
Russell King | 4b5dda8 | 2015-08-06 16:37:18 +0100 | [diff] [blame] | 1079 | if (dpms_blanked(dcrtc->dpms)) |
Russell King | ec6fb15 | 2016-07-25 15:16:11 +0100 | [diff] [blame] | 1080 | armada_drm_plane_work_run(dcrtc, dcrtc->crtc.primary); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1081 | |
| 1082 | return 0; |
| 1083 | } |
| 1084 | |
| 1085 | static int |
| 1086 | armada_drm_crtc_set_property(struct drm_crtc *crtc, |
| 1087 | struct drm_property *property, uint64_t val) |
| 1088 | { |
| 1089 | struct armada_private *priv = crtc->dev->dev_private; |
| 1090 | struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); |
| 1091 | bool update_csc = false; |
| 1092 | |
| 1093 | if (property == priv->csc_yuv_prop) { |
| 1094 | dcrtc->csc_yuv_mode = val; |
| 1095 | update_csc = true; |
| 1096 | } else if (property == priv->csc_rgb_prop) { |
| 1097 | dcrtc->csc_rgb_mode = val; |
| 1098 | update_csc = true; |
| 1099 | } |
| 1100 | |
| 1101 | if (update_csc) { |
| 1102 | uint32_t val; |
| 1103 | |
| 1104 | val = dcrtc->spu_iopad_ctrl | |
| 1105 | armada_drm_crtc_calculate_csc(dcrtc); |
| 1106 | writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); |
| 1107 | } |
| 1108 | |
| 1109 | return 0; |
| 1110 | } |
| 1111 | |
Ville Syrjälä | a02fb90 | 2015-12-15 12:20:59 +0100 | [diff] [blame] | 1112 | static const struct drm_crtc_funcs armada_crtc_funcs = { |
Russell King | 662af0d | 2013-05-19 10:55:17 +0100 | [diff] [blame] | 1113 | .cursor_set = armada_drm_crtc_cursor_set, |
| 1114 | .cursor_move = armada_drm_crtc_cursor_move, |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1115 | .destroy = armada_drm_crtc_destroy, |
| 1116 | .set_config = drm_crtc_helper_set_config, |
| 1117 | .page_flip = armada_drm_crtc_page_flip, |
| 1118 | .set_property = armada_drm_crtc_set_property, |
| 1119 | }; |
| 1120 | |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1121 | static const struct drm_plane_funcs armada_primary_plane_funcs = { |
| 1122 | .update_plane = drm_primary_helper_update, |
| 1123 | .disable_plane = drm_primary_helper_disable, |
| 1124 | .destroy = drm_primary_helper_destroy, |
| 1125 | }; |
| 1126 | |
Russell King | 5740d27 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 1127 | int armada_drm_plane_init(struct armada_plane *plane) |
| 1128 | { |
| 1129 | init_waitqueue_head(&plane->frame_wait); |
| 1130 | |
| 1131 | return 0; |
| 1132 | } |
| 1133 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1134 | static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { |
| 1135 | { CSC_AUTO, "Auto" }, |
| 1136 | { CSC_YUV_CCIR601, "CCIR601" }, |
| 1137 | { CSC_YUV_CCIR709, "CCIR709" }, |
| 1138 | }; |
| 1139 | |
| 1140 | static struct drm_prop_enum_list armada_drm_csc_rgb_enum_list[] = { |
| 1141 | { CSC_AUTO, "Auto" }, |
| 1142 | { CSC_RGB_COMPUTER, "Computer system" }, |
| 1143 | { CSC_RGB_STUDIO, "Studio" }, |
| 1144 | }; |
| 1145 | |
| 1146 | static int armada_drm_crtc_create_properties(struct drm_device *dev) |
| 1147 | { |
| 1148 | struct armada_private *priv = dev->dev_private; |
| 1149 | |
| 1150 | if (priv->csc_yuv_prop) |
| 1151 | return 0; |
| 1152 | |
| 1153 | priv->csc_yuv_prop = drm_property_create_enum(dev, 0, |
| 1154 | "CSC_YUV", armada_drm_csc_yuv_enum_list, |
| 1155 | ARRAY_SIZE(armada_drm_csc_yuv_enum_list)); |
| 1156 | priv->csc_rgb_prop = drm_property_create_enum(dev, 0, |
| 1157 | "CSC_RGB", armada_drm_csc_rgb_enum_list, |
| 1158 | ARRAY_SIZE(armada_drm_csc_rgb_enum_list)); |
| 1159 | |
| 1160 | if (!priv->csc_yuv_prop || !priv->csc_rgb_prop) |
| 1161 | return -ENOMEM; |
| 1162 | |
| 1163 | return 0; |
| 1164 | } |
| 1165 | |
Russell King | 0fb2970 | 2015-06-06 21:46:53 +0100 | [diff] [blame] | 1166 | static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev, |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1167 | struct resource *res, int irq, const struct armada_variant *variant, |
| 1168 | struct device_node *port) |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1169 | { |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1170 | struct armada_private *priv = drm->dev_private; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1171 | struct armada_crtc *dcrtc; |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1172 | struct armada_plane *primary; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1173 | void __iomem *base; |
| 1174 | int ret; |
| 1175 | |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1176 | ret = armada_drm_crtc_create_properties(drm); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1177 | if (ret) |
| 1178 | return ret; |
| 1179 | |
Linus Torvalds | a7d7a14 | 2014-08-07 17:36:12 -0700 | [diff] [blame] | 1180 | base = devm_ioremap_resource(dev, res); |
Jingoo Han | c9d53c0 | 2014-06-11 14:00:05 +0900 | [diff] [blame] | 1181 | if (IS_ERR(base)) |
| 1182 | return PTR_ERR(base); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1183 | |
| 1184 | dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); |
| 1185 | if (!dcrtc) { |
| 1186 | DRM_ERROR("failed to allocate Armada crtc\n"); |
| 1187 | return -ENOMEM; |
| 1188 | } |
| 1189 | |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1190 | if (dev != drm->dev) |
| 1191 | dev_set_drvdata(dev, dcrtc); |
| 1192 | |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 1193 | dcrtc->variant = variant; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1194 | dcrtc->base = base; |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1195 | dcrtc->num = drm->mode_config.num_crtc; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1196 | dcrtc->clk = ERR_PTR(-EINVAL); |
| 1197 | dcrtc->csc_yuv_mode = CSC_AUTO; |
| 1198 | dcrtc->csc_rgb_mode = CSC_AUTO; |
| 1199 | dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; |
| 1200 | dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; |
| 1201 | spin_lock_init(&dcrtc->irq_lock); |
| 1202 | dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1203 | |
| 1204 | /* Initialize some registers which we don't otherwise set */ |
| 1205 | writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); |
| 1206 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); |
| 1207 | writel_relaxed(dcrtc->spu_iopad_ctrl, |
| 1208 | dcrtc->base + LCD_SPU_IOPAD_CONTROL); |
| 1209 | writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); |
| 1210 | writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 | |
| 1211 | CFG_PDWN32x32 | CFG_PDWN16x66 | CFG_PDWN32x66 | |
| 1212 | CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); |
| 1213 | writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 1214 | writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); |
| 1215 | writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1216 | |
Russell King | e5d9ddf | 2014-04-26 15:19:38 +0100 | [diff] [blame] | 1217 | ret = devm_request_irq(dev, irq, armada_drm_irq, 0, "armada_drm_crtc", |
| 1218 | dcrtc); |
| 1219 | if (ret < 0) { |
| 1220 | kfree(dcrtc); |
| 1221 | return ret; |
| 1222 | } |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1223 | |
Russell King | 42e62ba | 2014-04-22 15:24:03 +0100 | [diff] [blame] | 1224 | if (dcrtc->variant->init) { |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1225 | ret = dcrtc->variant->init(dcrtc, dev); |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1226 | if (ret) { |
| 1227 | kfree(dcrtc); |
| 1228 | return ret; |
| 1229 | } |
| 1230 | } |
| 1231 | |
| 1232 | /* Ensure AXI pipeline is enabled */ |
| 1233 | armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); |
| 1234 | |
| 1235 | priv->dcrtc[dcrtc->num] = dcrtc; |
| 1236 | |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1237 | dcrtc->crtc.port = port; |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1238 | |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1239 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1240 | if (!primary) |
| 1241 | return -ENOMEM; |
| 1242 | |
Russell King | 5740d27 | 2015-07-15 18:11:25 +0100 | [diff] [blame] | 1243 | ret = armada_drm_plane_init(primary); |
| 1244 | if (ret) { |
| 1245 | kfree(primary); |
| 1246 | return ret; |
| 1247 | } |
| 1248 | |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1249 | ret = drm_universal_plane_init(drm, &primary->base, 0, |
| 1250 | &armada_primary_plane_funcs, |
| 1251 | armada_primary_formats, |
| 1252 | ARRAY_SIZE(armada_primary_formats), |
Ville Syrjälä | b0b3b79 | 2015-12-09 16:19:55 +0200 | [diff] [blame] | 1253 | DRM_PLANE_TYPE_PRIMARY, NULL); |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1254 | if (ret) { |
| 1255 | kfree(primary); |
| 1256 | return ret; |
| 1257 | } |
| 1258 | |
| 1259 | ret = drm_crtc_init_with_planes(drm, &dcrtc->crtc, &primary->base, NULL, |
Ville Syrjälä | f988287 | 2015-12-09 16:19:31 +0200 | [diff] [blame] | 1260 | &armada_crtc_funcs, NULL); |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1261 | if (ret) |
| 1262 | goto err_crtc_init; |
| 1263 | |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1264 | drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); |
| 1265 | |
| 1266 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, |
| 1267 | dcrtc->csc_yuv_mode); |
| 1268 | drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, |
| 1269 | dcrtc->csc_rgb_mode); |
| 1270 | |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1271 | return armada_overlay_plane_create(drm, 1 << dcrtc->num); |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1272 | |
| 1273 | err_crtc_init: |
Russell King | de32301 | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1274 | primary->base.funcs->destroy(&primary->base); |
Russell King | 1c914ce | 2015-07-15 18:11:24 +0100 | [diff] [blame] | 1275 | return ret; |
Russell King | 96f60e3 | 2012-08-15 13:59:49 +0100 | [diff] [blame] | 1276 | } |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1277 | |
| 1278 | static int |
| 1279 | armada_lcd_bind(struct device *dev, struct device *master, void *data) |
| 1280 | { |
| 1281 | struct platform_device *pdev = to_platform_device(dev); |
| 1282 | struct drm_device *drm = data; |
| 1283 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1284 | int irq = platform_get_irq(pdev, 0); |
| 1285 | const struct armada_variant *variant; |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1286 | struct device_node *port = NULL; |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1287 | |
| 1288 | if (irq < 0) |
| 1289 | return irq; |
| 1290 | |
| 1291 | if (!dev->of_node) { |
| 1292 | const struct platform_device_id *id; |
| 1293 | |
| 1294 | id = platform_get_device_id(pdev); |
| 1295 | if (!id) |
| 1296 | return -ENXIO; |
| 1297 | |
| 1298 | variant = (const struct armada_variant *)id->driver_data; |
| 1299 | } else { |
| 1300 | const struct of_device_id *match; |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1301 | struct device_node *np, *parent = dev->of_node; |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1302 | |
| 1303 | match = of_match_device(dev->driver->of_match_table, dev); |
| 1304 | if (!match) |
| 1305 | return -ENXIO; |
| 1306 | |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1307 | np = of_get_child_by_name(parent, "ports"); |
| 1308 | if (np) |
| 1309 | parent = np; |
| 1310 | port = of_get_child_by_name(parent, "port"); |
| 1311 | of_node_put(np); |
| 1312 | if (!port) { |
| 1313 | dev_err(dev, "no port node found in %s\n", |
| 1314 | parent->full_name); |
| 1315 | return -ENXIO; |
| 1316 | } |
| 1317 | |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1318 | variant = match->data; |
| 1319 | } |
| 1320 | |
Russell King | 9611cb9 | 2014-06-15 11:21:23 +0100 | [diff] [blame] | 1321 | return armada_drm_crtc_create(drm, dev, res, irq, variant, port); |
Russell King | d8c9608 | 2014-04-22 11:10:15 +0100 | [diff] [blame] | 1322 | } |
| 1323 | |
| 1324 | static void |
| 1325 | armada_lcd_unbind(struct device *dev, struct device *master, void *data) |
| 1326 | { |
| 1327 | struct armada_crtc *dcrtc = dev_get_drvdata(dev); |
| 1328 | |
| 1329 | armada_drm_crtc_destroy(&dcrtc->crtc); |
| 1330 | } |
| 1331 | |
| 1332 | static const struct component_ops armada_lcd_ops = { |
| 1333 | .bind = armada_lcd_bind, |
| 1334 | .unbind = armada_lcd_unbind, |
| 1335 | }; |
| 1336 | |
| 1337 | static int armada_lcd_probe(struct platform_device *pdev) |
| 1338 | { |
| 1339 | return component_add(&pdev->dev, &armada_lcd_ops); |
| 1340 | } |
| 1341 | |
| 1342 | static int armada_lcd_remove(struct platform_device *pdev) |
| 1343 | { |
| 1344 | component_del(&pdev->dev, &armada_lcd_ops); |
| 1345 | return 0; |
| 1346 | } |
| 1347 | |
| 1348 | static struct of_device_id armada_lcd_of_match[] = { |
| 1349 | { |
| 1350 | .compatible = "marvell,dove-lcd", |
| 1351 | .data = &armada510_ops, |
| 1352 | }, |
| 1353 | {} |
| 1354 | }; |
| 1355 | MODULE_DEVICE_TABLE(of, armada_lcd_of_match); |
| 1356 | |
| 1357 | static const struct platform_device_id armada_lcd_platform_ids[] = { |
| 1358 | { |
| 1359 | .name = "armada-lcd", |
| 1360 | .driver_data = (unsigned long)&armada510_ops, |
| 1361 | }, { |
| 1362 | .name = "armada-510-lcd", |
| 1363 | .driver_data = (unsigned long)&armada510_ops, |
| 1364 | }, |
| 1365 | { }, |
| 1366 | }; |
| 1367 | MODULE_DEVICE_TABLE(platform, armada_lcd_platform_ids); |
| 1368 | |
| 1369 | struct platform_driver armada_lcd_platform_driver = { |
| 1370 | .probe = armada_lcd_probe, |
| 1371 | .remove = armada_lcd_remove, |
| 1372 | .driver = { |
| 1373 | .name = "armada-lcd", |
| 1374 | .owner = THIS_MODULE, |
| 1375 | .of_match_table = armada_lcd_of_match, |
| 1376 | }, |
| 1377 | .id_table = armada_lcd_platform_ids, |
| 1378 | }; |