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Heiko Stübnerd3e51162013-06-10 22:16:22 +02001/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
Paul Gortmaker2f436202016-08-23 17:19:42 -040026#include <linux/init.h>
Heiko Stübnerd3e51162013-06-10 22:16:22 +020027#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
Heiko Stübner7e865ab2013-07-23 13:34:20 +020039#include <linux/clk.h>
Heiko Stübner751a99a2014-05-05 13:58:20 +020040#include <linux/regmap.h>
Heiko Stübner14dee862014-05-05 13:59:09 +020041#include <linux/mfd/syscon.h>
Heiko Stübnerd3e51162013-06-10 22:16:22 +020042#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
Heiko Stübnera2829262013-10-16 01:07:20 +020061enum rockchip_pinctrl_type {
Andy Yanb9c6dca2017-03-17 18:18:36 +010062 RV1108,
Heiko Stübnera2829262013-10-16 01:07:20 +020063 RK2928,
64 RK3066B,
David Wud23c66d2017-07-21 14:27:15 +080065 RK3128,
Heiko Stübnera2829262013-10-16 01:07:20 +020066 RK3188,
Heiko Stübner66d750e2014-07-20 01:49:17 +020067 RK3288,
Heiko Stübnerdaecdc62015-06-12 23:51:01 +020068 RK3368,
David Wub6c23272016-02-01 10:58:21 +080069 RK3399,
Heiko Stübnera2829262013-10-16 01:07:20 +020070};
71
Heiko Stübnerfc72c922014-06-16 01:36:05 +020072/**
73 * Encode variants of iomux registers into a type variable
74 */
75#define IOMUX_GPIO_ONLY BIT(0)
Heiko Stübner03716e12014-06-16 01:36:57 +020076#define IOMUX_WIDTH_4BIT BIT(1)
Heiko Stübner95ec8ae2014-06-16 01:37:23 +020077#define IOMUX_SOURCE_PMU BIT(2)
Heiko Stübner62f49222014-06-16 01:37:49 +020078#define IOMUX_UNROUTED BIT(3)
david.wu8b6c6f92017-02-10 18:23:47 +080079#define IOMUX_WIDTH_3BIT BIT(4)
Heiko Stübnerfc72c922014-06-16 01:36:05 +020080
81/**
82 * @type: iomux variant using IOMUX_* constants
Heiko Stübner6bc0d1212014-06-16 01:36:33 +020083 * @offset: if initialized to -1 it will be autocalculated, by specifying
84 * an initial offset value the relevant source offset can be reset
85 * to a new value for autocalculating the following iomux registers.
Heiko Stübnerfc72c922014-06-16 01:36:05 +020086 */
87struct rockchip_iomux {
88 int type;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +020089 int offset;
Heiko Stübner65fca612013-10-16 01:07:49 +020090};
91
Heiko Stübnerd3e51162013-06-10 22:16:22 +020092/**
David Wub6c23272016-02-01 10:58:21 +080093 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
94 */
95enum rockchip_pin_drv_type {
96 DRV_TYPE_IO_DEFAULT = 0,
97 DRV_TYPE_IO_1V8_OR_3V0,
98 DRV_TYPE_IO_1V8_ONLY,
99 DRV_TYPE_IO_1V8_3V0_AUTO,
100 DRV_TYPE_IO_3V3_ONLY,
101 DRV_TYPE_MAX
102};
103
104/**
David Wu3ba67672016-05-11 11:39:28 +0800105 * enum type index corresponding to rockchip_pull_list arrays index.
106 */
107enum rockchip_pin_pull_type {
108 PULL_TYPE_IO_DEFAULT = 0,
109 PULL_TYPE_IO_1V8_ONLY,
110 PULL_TYPE_MAX
111};
112
113/**
David Wub6c23272016-02-01 10:58:21 +0800114 * @drv_type: drive strength variant using rockchip_perpin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
120 */
121struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
123 int offset;
124};
125
126/**
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200127 * @reg_base: register base of the gpio bank
Heiko Stübner6ca52742013-10-16 01:08:42 +0200128 * @reg_pull: optional separate register for additional pull settings
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
Doug Anderson5ae0c7a2015-01-26 08:24:03 -0800131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200136 * @iomux: array describing the 4 iomux sources of the bank
David Wub6c23272016-02-01 10:58:21 +0800137 * @drv: array describing the 4 drive strength sources of the bank
David Wu3ba67672016-05-11 11:39:28 +0800138 * @pull_type: array describing the 4 pull type sources of the bank
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200139 * @valid: are all necessary informations present
140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank
143 * @gpio_chip: gpiolib chip
144 * @grange: gpio range
145 * @slock: spinlock for the gpio bank
David Wubd35b9b2017-05-26 15:20:20 +0800146 * @route_mask: bits describing the routing pins of per bank
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200147 */
148struct rockchip_pin_bank {
149 void __iomem *reg_base;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200150 struct regmap *regmap_pull;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200151 struct clk *clk;
152 int irq;
Doug Anderson5ae0c7a2015-01-26 08:24:03 -0800153 u32 saved_masks;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200154 u32 pin_base;
155 u8 nr_pins;
156 char *name;
157 u8 bank_num;
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200158 struct rockchip_iomux iomux[4];
David Wub6c23272016-02-01 10:58:21 +0800159 struct rockchip_drv drv[4];
David Wu3ba67672016-05-11 11:39:28 +0800160 enum rockchip_pin_pull_type pull_type[4];
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200161 bool valid;
162 struct device_node *of_node;
163 struct rockchip_pinctrl *drvdata;
164 struct irq_domain *domain;
165 struct gpio_chip gpio_chip;
166 struct pinctrl_gpio_range grange;
John Keeping70b7aa72017-03-23 10:59:29 +0000167 raw_spinlock_t slock;
Heiko Stübner5a927502013-10-16 01:09:08 +0200168 u32 toggle_edge_mode;
David Wuc04c3fa2017-07-21 14:27:14 +0800169 u32 recalced_mask;
David Wubd35b9b2017-05-26 15:20:20 +0800170 u32 route_mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200171};
172
173#define PIN_BANK(id, pins, label) \
174 { \
175 .bank_num = id, \
176 .nr_pins = pins, \
177 .name = label, \
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200178 .iomux = { \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
183 }, \
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200184 }
185
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200186#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
187 { \
188 .bank_num = id, \
189 .nr_pins = pins, \
190 .name = label, \
191 .iomux = { \
Heiko Stübner6bc0d1212014-06-16 01:36:33 +0200192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
Heiko Stübnerfc72c922014-06-16 01:36:05 +0200196 }, \
197 }
198
David Wub6c23272016-02-01 10:58:21 +0800199#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
200 { \
201 .bank_num = id, \
202 .nr_pins = pins, \
203 .name = label, \
204 .iomux = { \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
209 }, \
210 .drv = { \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
215 }, \
216 }
217
David Wu3ba67672016-05-11 11:39:28 +0800218#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
219 drv2, drv3, pull0, pull1, \
220 pull2, pull3) \
221 { \
222 .bank_num = id, \
223 .nr_pins = pins, \
224 .name = label, \
225 .iomux = { \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
230 }, \
231 .drv = { \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
236 }, \
237 .pull_type[0] = pull0, \
238 .pull_type[1] = pull1, \
239 .pull_type[2] = pull2, \
240 .pull_type[3] = pull3, \
241 }
242
David Wub6c23272016-02-01 10:58:21 +0800243#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
244 iom2, iom3, drv0, drv1, drv2, \
245 drv3, offset0, offset1, \
246 offset2, offset3) \
247 { \
248 .bank_num = id, \
249 .nr_pins = pins, \
250 .name = label, \
251 .iomux = { \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
256 }, \
257 .drv = { \
258 { .drv_type = drv0, .offset = offset0 }, \
259 { .drv_type = drv1, .offset = offset1 }, \
260 { .drv_type = drv2, .offset = offset2 }, \
261 { .drv_type = drv3, .offset = offset3 }, \
262 }, \
263 }
264
David Wu3ba67672016-05-11 11:39:28 +0800265#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
266 label, iom0, iom1, iom2, \
267 iom3, drv0, drv1, drv2, \
268 drv3, offset0, offset1, \
269 offset2, offset3, pull0, \
270 pull1, pull2, pull3) \
271 { \
272 .bank_num = id, \
273 .nr_pins = pins, \
274 .name = label, \
275 .iomux = { \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
280 }, \
281 .drv = { \
282 { .drv_type = drv0, .offset = offset0 }, \
283 { .drv_type = drv1, .offset = offset1 }, \
284 { .drv_type = drv2, .offset = offset2 }, \
285 { .drv_type = drv3, .offset = offset3 }, \
286 }, \
287 .pull_type[0] = pull0, \
288 .pull_type[1] = pull1, \
289 .pull_type[2] = pull2, \
290 .pull_type[3] = pull3, \
291 }
292
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200293/**
David Wubd35b9b2017-05-26 15:20:20 +0800294 * struct rockchip_mux_recalced_data: represent a pin iomux data.
David Wuc04c3fa2017-07-21 14:27:14 +0800295 * @num: bank number.
296 * @pin: pin number.
297 * @bit: index at register.
298 * @reg: register offset.
299 * @mask: mask bit
300 */
301struct rockchip_mux_recalced_data {
302 u8 num;
303 u8 pin;
David Wu12b8f012017-08-23 16:00:07 +0800304 u32 reg;
David Wuc04c3fa2017-07-21 14:27:14 +0800305 u8 bit;
306 u8 mask;
307};
308
309/**
310 * struct rockchip_mux_recalced_data: represent a pin iomux data.
David Wubd35b9b2017-05-26 15:20:20 +0800311 * @bank_num: bank number.
312 * @pin: index at register or used to calc index.
313 * @func: the min pin.
314 * @route_offset: the max pin.
315 * @route_val: the register offset.
316 */
317struct rockchip_mux_route_data {
318 u8 bank_num;
319 u8 pin;
320 u8 func;
321 u32 route_offset;
322 u32 route_val;
323};
324
325/**
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200326 */
327struct rockchip_pin_ctrl {
328 struct rockchip_pin_bank *pin_banks;
329 u32 nr_banks;
330 u32 nr_pins;
331 char *label;
Heiko Stübnera2829262013-10-16 01:07:20 +0200332 enum rockchip_pinctrl_type type;
Heiko Stübner95ec8ae2014-06-16 01:37:23 +0200333 int grf_mux_offset;
334 int pmu_mux_offset;
David Wub6c23272016-02-01 10:58:21 +0800335 int grf_drv_offset;
336 int pmu_drv_offset;
David Wuc04c3fa2017-07-21 14:27:14 +0800337 struct rockchip_mux_recalced_data *iomux_recalced;
338 u32 niomux_recalced;
David Wubd35b9b2017-05-26 15:20:20 +0800339 struct rockchip_mux_route_data *iomux_routes;
340 u32 niomux_routes;
David Wub6c23272016-02-01 10:58:21 +0800341
Heiko Stübner751a99a2014-05-05 13:58:20 +0200342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
343 int pin_num, struct regmap **regmap,
344 int *reg, u8 *bit);
Heiko Stübneref17f692015-06-12 23:50:11 +0200345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
346 int pin_num, struct regmap **regmap,
347 int *reg, u8 *bit);
david.wue3b357d2017-03-02 15:11:23 +0800348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
350 int *reg, u8 *bit);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200351};
352
353struct rockchip_pin_config {
354 unsigned int func;
355 unsigned long *configs;
356 unsigned int nconfigs;
357};
358
359/**
360 * struct rockchip_pin_group: represent group of pins of a pinmux function.
361 * @name: name of the pin group, used to lookup the group.
362 * @pins: the pins included in this group.
363 * @npins: number of pins included in this group.
364 * @func: the mux function number to be programmed when selected.
365 * @configs: the config values to be set for each pin
366 * @nconfigs: number of configs for each pin
367 */
368struct rockchip_pin_group {
369 const char *name;
370 unsigned int npins;
371 unsigned int *pins;
372 struct rockchip_pin_config *data;
373};
374
375/**
376 * struct rockchip_pmx_func: represent a pin function.
377 * @name: name of the pin function, used to lookup the function.
378 * @groups: one or more names of pin groups that provide this function.
379 * @num_groups: number of groups included in @groups.
380 */
381struct rockchip_pmx_func {
382 const char *name;
383 const char **groups;
384 u8 ngroups;
385};
386
387struct rockchip_pinctrl {
Heiko Stübner751a99a2014-05-05 13:58:20 +0200388 struct regmap *regmap_base;
Heiko Stübnerbfc7a422014-05-05 13:58:00 +0200389 int reg_size;
Heiko Stübner751a99a2014-05-05 13:58:20 +0200390 struct regmap *regmap_pull;
Heiko Stübner14dee862014-05-05 13:59:09 +0200391 struct regmap *regmap_pmu;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200392 struct device *dev;
393 struct rockchip_pin_ctrl *ctrl;
394 struct pinctrl_desc pctl;
395 struct pinctrl_dev *pctl_dev;
396 struct rockchip_pin_group *groups;
397 unsigned int ngroups;
398 struct rockchip_pmx_func *functions;
399 unsigned int nfunctions;
400};
401
Heiko Stübner751a99a2014-05-05 13:58:20 +0200402static struct regmap_config rockchip_regmap_config = {
403 .reg_bits = 32,
404 .val_bits = 32,
405 .reg_stride = 4,
406};
407
Arnd Bergmann56411f32016-06-13 17:18:34 +0200408static inline const struct rockchip_pin_group *pinctrl_name_to_group(
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200409 const struct rockchip_pinctrl *info,
410 const char *name)
411{
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200412 int i;
413
414 for (i = 0; i < info->ngroups; i++) {
Axel Lin1cb95392013-08-21 10:28:50 +0800415 if (!strcmp(info->groups[i].name, name))
416 return &info->groups[i];
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200417 }
418
Axel Lin1cb95392013-08-21 10:28:50 +0800419 return NULL;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200420}
421
422/*
423 * given a pin number that is local to a pin controller, find out the pin bank
424 * and the register base of the pin bank.
425 */
426static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
427 unsigned pin)
428{
429 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
430
Axel Lin51578b92013-08-23 15:49:00 +0800431 while (pin >= (b->pin_base + b->nr_pins))
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200432 b++;
433
434 return b;
435}
436
437static struct rockchip_pin_bank *bank_num_to_bank(
438 struct rockchip_pinctrl *info,
439 unsigned num)
440{
441 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
442 int i;
443
Axel Lin1cb95392013-08-21 10:28:50 +0800444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200445 if (b->bank_num == num)
Axel Lin1cb95392013-08-21 10:28:50 +0800446 return b;
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200447 }
448
Axel Lin1cb95392013-08-21 10:28:50 +0800449 return ERR_PTR(-EINVAL);
Heiko Stübnerd3e51162013-06-10 22:16:22 +0200450}
451
452/*
453 * Pinctrl_ops handling
454 */
455
456static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
457{
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459
460 return info->ngroups;
461}
462
463static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
464 unsigned selector)
465{
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467
468 return info->groups[selector].name;
469}
470
471static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
472 unsigned selector, const unsigned **pins,
473 unsigned *npins)
474{
475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
476
477 if (selector >= info->ngroups)
478 return -EINVAL;
479
480 *pins = info->groups[selector].pins;
481 *npins = info->groups[selector].npins;
482
483 return 0;
484}
485
486static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np,
488 struct pinctrl_map **map, unsigned *num_maps)
489{
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
491 const struct rockchip_pin_group *grp;
492 struct pinctrl_map *new_map;
493 struct device_node *parent;
494 int map_num = 1;
495 int i;
496
497 /*
498 * first find the group of this node and check if we need to create
499 * config maps for pins
500 */
501 grp = pinctrl_name_to_group(info, np->name);
502 if (!grp) {
503 dev_err(info->dev, "unable to find group for node %s\n",
504 np->name);
505 return -EINVAL;
506 }
507
508 map_num += grp->npins;
509 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
510 GFP_KERNEL);
511 if (!new_map)
512 return -ENOMEM;
513
514 *map = new_map;
515 *num_maps = map_num;
516
517 /* create mux map */
518 parent = of_get_parent(np);
519 if (!parent) {
520 devm_kfree(pctldev->dev, new_map);
521 return -EINVAL;
522 }
523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
524 new_map[0].data.mux.function = parent->name;
525 new_map[0].data.mux.group = np->name;
526 of_node_put(parent);
527
528 /* create config map */
529 new_map++;
530 for (i = 0; i < grp->npins; i++) {
531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
532 new_map[i].data.configs.group_or_pin =
533 pin_get_name(pctldev, grp->pins[i]);
534 new_map[i].data.configs.configs = grp->data[i].configs;
535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
536 }
537
538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
539 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
540
541 return 0;
542}
543
544static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
545 struct pinctrl_map *map, unsigned num_maps)
546{
547}
548
549static const struct pinctrl_ops rockchip_pctrl_ops = {
550 .get_groups_count = rockchip_get_groups_count,
551 .get_group_name = rockchip_get_group_name,
552 .get_group_pins = rockchip_get_group_pins,
553 .dt_node_to_map = rockchip_dt_node_to_map,
554 .dt_free_map = rockchip_dt_free_map,
555};
556
557/*
558 * Hardware access
559 */
560
David Wu12b8f012017-08-23 16:00:07 +0800561static struct rockchip_mux_recalced_data rv1108_mux_recalced_data[] = {
562 {
563 .num = 1,
564 .pin = 0,
565 .reg = 0x418,
566 .bit = 0,
567 .mask = 0x3
568 }, {
569 .num = 1,
570 .pin = 1,
571 .reg = 0x418,
572 .bit = 2,
573 .mask = 0x3
574 }, {
575 .num = 1,
576 .pin = 2,
577 .reg = 0x418,
578 .bit = 4,
579 .mask = 0x3
580 }, {
581 .num = 1,
582 .pin = 3,
583 .reg = 0x418,
584 .bit = 6,
585 .mask = 0x3
586 }, {
587 .num = 1,
588 .pin = 4,
589 .reg = 0x418,
590 .bit = 8,
591 .mask = 0x3
592 }, {
593 .num = 1,
594 .pin = 5,
595 .reg = 0x418,
596 .bit = 10,
597 .mask = 0x3
598 }, {
599 .num = 1,
600 .pin = 6,
601 .reg = 0x418,
602 .bit = 12,
603 .mask = 0x3
604 }, {
605 .num = 1,
606 .pin = 7,
607 .reg = 0x418,
608 .bit = 14,
609 .mask = 0x3
610 }, {
611 .num = 1,
612 .pin = 8,
613 .reg = 0x41c,
614 .bit = 0,
615 .mask = 0x3
616 }, {
617 .num = 1,
618 .pin = 9,
619 .reg = 0x41c,
620 .bit = 2,
621 .mask = 0x3
622 },
623};
624
David Wud23c66d2017-07-21 14:27:15 +0800625static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
626 {
627 .num = 2,
628 .pin = 20,
629 .reg = 0xe8,
630 .bit = 0,
631 .mask = 0x7
632 }, {
633 .num = 2,
634 .pin = 21,
635 .reg = 0xe8,
636 .bit = 4,
637 .mask = 0x7
638 }, {
639 .num = 2,
640 .pin = 22,
641 .reg = 0xe8,
642 .bit = 8,
643 .mask = 0x7
644 }, {
645 .num = 2,
646 .pin = 23,
647 .reg = 0xe8,
648 .bit = 12,
649 .mask = 0x7
650 }, {
651 .num = 2,
652 .pin = 24,
653 .reg = 0xd4,
654 .bit = 12,
655 .mask = 0x7
656 },
657};
658
David Wuc04c3fa2017-07-21 14:27:14 +0800659static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
david.wu3818e4a2017-02-10 18:23:49 +0800660 {
661 .num = 2,
662 .pin = 12,
663 .reg = 0x24,
664 .bit = 8,
665 .mask = 0x3
666 }, {
667 .num = 2,
668 .pin = 15,
669 .reg = 0x28,
670 .bit = 0,
671 .mask = 0x7
672 }, {
673 .num = 2,
674 .pin = 23,
675 .reg = 0x30,
676 .bit = 14,
677 .mask = 0x3
678 },
679};
680
David Wuc04c3fa2017-07-21 14:27:14 +0800681static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
682 int *reg, u8 *bit, int *mask)
david.wu3818e4a2017-02-10 18:23:49 +0800683{
David Wuc04c3fa2017-07-21 14:27:14 +0800684 struct rockchip_pinctrl *info = bank->drvdata;
685 struct rockchip_pin_ctrl *ctrl = info->ctrl;
686 struct rockchip_mux_recalced_data *data;
david.wu3818e4a2017-02-10 18:23:49 +0800687 int i;
688
David Wuc04c3fa2017-07-21 14:27:14 +0800689 for (i = 0; i < ctrl->niomux_recalced; i++) {
690 data = &ctrl->iomux_recalced[i];
691 if (data->num == bank->bank_num &&
692 data->pin == pin)
david.wu3818e4a2017-02-10 18:23:49 +0800693 break;
David Wuc04c3fa2017-07-21 14:27:14 +0800694 }
david.wu3818e4a2017-02-10 18:23:49 +0800695
David Wuc04c3fa2017-07-21 14:27:14 +0800696 if (i >= ctrl->niomux_recalced)
david.wu3818e4a2017-02-10 18:23:49 +0800697 return;
698
699 *reg = data->reg;
700 *mask = data->mask;
701 *bit = data->bit;
702}
703
David Wud23c66d2017-07-21 14:27:15 +0800704static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
705 {
706 /* spi-0 */
707 .bank_num = 1,
708 .pin = 10,
709 .func = 1,
710 .route_offset = 0x144,
711 .route_val = BIT(16 + 3) | BIT(16 + 4),
712 }, {
713 /* spi-1 */
714 .bank_num = 1,
715 .pin = 27,
716 .func = 3,
717 .route_offset = 0x144,
718 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
719 }, {
720 /* spi-2 */
721 .bank_num = 0,
722 .pin = 13,
723 .func = 2,
724 .route_offset = 0x144,
725 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
726 }, {
727 /* i2s-0 */
728 .bank_num = 1,
729 .pin = 5,
730 .func = 1,
731 .route_offset = 0x144,
732 .route_val = BIT(16 + 5),
733 }, {
734 /* i2s-1 */
735 .bank_num = 0,
736 .pin = 14,
737 .func = 1,
738 .route_offset = 0x144,
739 .route_val = BIT(16 + 5) | BIT(5),
740 }, {
741 /* emmc-0 */
742 .bank_num = 1,
743 .pin = 22,
744 .func = 2,
745 .route_offset = 0x144,
746 .route_val = BIT(16 + 6),
747 }, {
748 /* emmc-1 */
749 .bank_num = 2,
750 .pin = 4,
751 .func = 2,
752 .route_offset = 0x144,
753 .route_val = BIT(16 + 6) | BIT(6),
754 },
755};
756
David Wud4970ee2017-05-26 15:20:21 +0800757static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
758 {
759 /* pwm0-0 */
760 .bank_num = 0,
761 .pin = 26,
762 .func = 1,
763 .route_offset = 0x50,
764 .route_val = BIT(16),
765 }, {
766 /* pwm0-1 */
767 .bank_num = 3,
768 .pin = 21,
769 .func = 1,
770 .route_offset = 0x50,
771 .route_val = BIT(16) | BIT(0),
772 }, {
773 /* pwm1-0 */
774 .bank_num = 0,
775 .pin = 27,
776 .func = 1,
777 .route_offset = 0x50,
778 .route_val = BIT(16 + 1),
779 }, {
780 /* pwm1-1 */
781 .bank_num = 0,
782 .pin = 30,
783 .func = 2,
784 .route_offset = 0x50,
785 .route_val = BIT(16 + 1) | BIT(1),
786 }, {
787 /* pwm2-0 */
788 .bank_num = 0,
789 .pin = 28,
790 .func = 1,
791 .route_offset = 0x50,
792 .route_val = BIT(16 + 2),
793 }, {
794 /* pwm2-1 */
795 .bank_num = 1,
796 .pin = 12,
797 .func = 2,
798 .route_offset = 0x50,
799 .route_val = BIT(16 + 2) | BIT(2),
800 }, {
801 /* pwm3-0 */
802 .bank_num = 3,
803 .pin = 26,
804 .func = 1,
805 .route_offset = 0x50,
806 .route_val = BIT(16 + 3),
807 }, {
808 /* pwm3-1 */
809 .bank_num = 1,
810 .pin = 11,
811 .func = 2,
812 .route_offset = 0x50,
813 .route_val = BIT(16 + 3) | BIT(3),
814 }, {
815 /* sdio-0_d0 */
816 .bank_num = 1,
817 .pin = 1,
818 .func = 1,
819 .route_offset = 0x50,
820 .route_val = BIT(16 + 4),
821 }, {
822 /* sdio-1_d0 */
823 .bank_num = 3,
824 .pin = 2,
825 .func = 1,
826 .route_offset = 0x50,
827 .route_val = BIT(16 + 4) | BIT(4),
828 }, {
829 /* spi-0_rx */
830 .bank_num = 0,
831 .pin = 13,
832 .func = 2,
833 .route_offset = 0x50,
834 .route_val = BIT(16 + 5),
835 }, {
836 /* spi-1_rx */
837 .bank_num = 2,
838 .pin = 0,
839 .func = 2,
840 .route_offset = 0x50,
841 .route_val = BIT(16 + 5) | BIT(5),
842 }, {
843 /* emmc-0_cmd */
844 .bank_num = 1,
845 .pin = 22,
846 .func = 2,
847 .route_offset = 0x50,
848 .route_val = BIT(16 + 7),
849 }, {
850 /* emmc-1_cmd */
851 .bank_num = 2,
852 .pin = 4,
853 .func = 2,
854 .route_offset = 0x50,
855 .route_val = BIT(16 + 7) | BIT(7),
856 }, {
857 /* uart2-0_rx */
858 .bank_num = 1,
859 .pin = 19,
860 .func = 2,
861 .route_offset = 0x50,
862 .route_val = BIT(16 + 8),
863 }, {
864 /* uart2-1_rx */
865 .bank_num = 1,
866 .pin = 10,
867 .func = 2,
868 .route_offset = 0x50,
869 .route_val = BIT(16 + 8) | BIT(8),
870 }, {
871 /* uart1-0_rx */
872 .bank_num = 1,
873 .pin = 10,
874 .func = 1,
875 .route_offset = 0x50,
876 .route_val = BIT(16 + 11),
877 }, {
878 /* uart1-1_rx */
879 .bank_num = 3,
880 .pin = 13,
881 .func = 1,
882 .route_offset = 0x50,
883 .route_val = BIT(16 + 11) | BIT(11),
884 },
885};
886
David Wucedc9642017-05-26 15:20:22 +0800887static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
888 {
889 /* uart2dbg_rxm0 */
890 .bank_num = 1,
891 .pin = 1,
892 .func = 2,
893 .route_offset = 0x50,
894 .route_val = BIT(16) | BIT(16 + 1),
895 }, {
896 /* uart2dbg_rxm1 */
897 .bank_num = 2,
898 .pin = 1,
899 .func = 1,
900 .route_offset = 0x50,
901 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
902 }, {
903 /* gmac-m1-optimized_rxd0 */
904 .bank_num = 1,
905 .pin = 11,
906 .func = 2,
907 .route_offset = 0x50,
908 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
909 }, {
910 /* pdm_sdi0m0 */
911 .bank_num = 2,
912 .pin = 19,
913 .func = 2,
914 .route_offset = 0x50,
915 .route_val = BIT(16 + 3),
916 }, {
917 /* pdm_sdi0m1 */
918 .bank_num = 1,
919 .pin = 23,
920 .func = 3,
921 .route_offset = 0x50,
922 .route_val = BIT(16 + 3) | BIT(3),
923 }, {
924 /* spi_rxdm2 */
925 .bank_num = 3,
926 .pin = 2,
927 .func = 4,
928 .route_offset = 0x50,
929 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
930 }, {
931 /* i2s2_sdim0 */
932 .bank_num = 1,
933 .pin = 24,
934 .func = 1,
935 .route_offset = 0x50,
936 .route_val = BIT(16 + 6),
937 }, {
938 /* i2s2_sdim1 */
939 .bank_num = 3,
940 .pin = 2,
941 .func = 6,
942 .route_offset = 0x50,
943 .route_val = BIT(16 + 6) | BIT(6),
944 }, {
945 /* card_iom1 */
946 .bank_num = 2,
947 .pin = 22,
948 .func = 3,
949 .route_offset = 0x50,
950 .route_val = BIT(16 + 7) | BIT(7),
951 }, {
952 /* tsp_d5m1 */
953 .bank_num = 2,
954 .pin = 16,
955 .func = 3,
956 .route_offset = 0x50,
957 .route_val = BIT(16 + 8) | BIT(8),
958 }, {
959 /* cif_data5m1 */
960 .bank_num = 2,
961 .pin = 16,
962 .func = 4,
963 .route_offset = 0x50,
964 .route_val = BIT(16 + 9) | BIT(9),
965 },
966};
967
David Wuaccc1ce2017-05-26 15:20:23 +0800968static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
969 {
970 /* uart2dbga_rx */
971 .bank_num = 4,
972 .pin = 8,
973 .func = 2,
974 .route_offset = 0xe21c,
975 .route_val = BIT(16 + 10) | BIT(16 + 11),
976 }, {
977 /* uart2dbgb_rx */
978 .bank_num = 4,
979 .pin = 16,
980 .func = 2,
981 .route_offset = 0xe21c,
982 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
983 }, {
984 /* uart2dbgc_rx */
985 .bank_num = 4,
986 .pin = 19,
987 .func = 1,
988 .route_offset = 0xe21c,
989 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
990 }, {
991 /* pcie_clkreqn */
992 .bank_num = 2,
993 .pin = 26,
994 .func = 2,
995 .route_offset = 0xe21c,
996 .route_val = BIT(16 + 14),
997 }, {
998 /* pcie_clkreqnb */
999 .bank_num = 4,
1000 .pin = 24,
1001 .func = 1,
1002 .route_offset = 0xe21c,
1003 .route_val = BIT(16 + 14) | BIT(14),
1004 },
1005};
1006
David Wubd35b9b2017-05-26 15:20:20 +08001007static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
1008 int mux, u32 *reg, u32 *value)
1009{
1010 struct rockchip_pinctrl *info = bank->drvdata;
1011 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1012 struct rockchip_mux_route_data *data;
1013 int i;
1014
1015 for (i = 0; i < ctrl->niomux_routes; i++) {
1016 data = &ctrl->iomux_routes[i];
1017 if ((data->bank_num == bank->bank_num) &&
1018 (data->pin == pin) && (data->func == mux))
1019 break;
1020 }
1021
1022 if (i >= ctrl->niomux_routes)
1023 return false;
1024
1025 *reg = data->route_offset;
1026 *value = data->route_val;
1027
1028 return true;
1029}
1030
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001031static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
1032{
1033 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001034 int iomux_num = (pin / 8);
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001035 struct regmap *regmap;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001036 unsigned int val;
david.wuea262ad2017-02-10 18:23:48 +08001037 int reg, ret, mask, mux_type;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001038 u8 bit;
1039
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001040 if (iomux_num > 3)
1041 return -EINVAL;
1042
Heiko Stübner62f49222014-06-16 01:37:49 +02001043 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1044 dev_err(info->dev, "pin %d is unrouted\n", pin);
1045 return -EINVAL;
1046 }
1047
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001048 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001049 return RK_FUNC_GPIO;
1050
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001051 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1052 ? info->regmap_pmu : info->regmap_base;
1053
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001054 /* get basic quadrupel of mux registers and the correct reg inside */
david.wuea262ad2017-02-10 18:23:48 +08001055 mux_type = bank->iomux[iomux_num].type;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001056 reg = bank->iomux[iomux_num].offset;
david.wuea262ad2017-02-10 18:23:48 +08001057 if (mux_type & IOMUX_WIDTH_4BIT) {
Heiko Stübner03716e12014-06-16 01:36:57 +02001058 if ((pin % 8) >= 4)
1059 reg += 0x4;
1060 bit = (pin % 4) * 4;
david.wu8b6c6f92017-02-10 18:23:47 +08001061 mask = 0xf;
david.wuea262ad2017-02-10 18:23:48 +08001062 } else if (mux_type & IOMUX_WIDTH_3BIT) {
david.wu8b6c6f92017-02-10 18:23:47 +08001063 if ((pin % 8) >= 5)
1064 reg += 0x4;
1065 bit = (pin % 8 % 5) * 3;
1066 mask = 0x7;
Heiko Stübner03716e12014-06-16 01:36:57 +02001067 } else {
1068 bit = (pin % 8) * 2;
david.wu8b6c6f92017-02-10 18:23:47 +08001069 mask = 0x3;
Heiko Stübner03716e12014-06-16 01:36:57 +02001070 }
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001071
David Wuc04c3fa2017-07-21 14:27:14 +08001072 if (bank->recalced_mask & BIT(pin))
1073 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
david.wuea262ad2017-02-10 18:23:48 +08001074
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001075 ret = regmap_read(regmap, reg, &val);
Heiko Stübner751a99a2014-05-05 13:58:20 +02001076 if (ret)
1077 return ret;
1078
Heiko Stübner03716e12014-06-16 01:36:57 +02001079 return ((val >> bit) & mask);
Heiko Stübnera076e2e2014-04-23 14:28:59 +02001080}
1081
John Keeping05709c32017-03-23 10:59:30 +00001082static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1083 int pin, int mux)
1084{
1085 struct rockchip_pinctrl *info = bank->drvdata;
1086 int iomux_num = (pin / 8);
1087
1088 if (iomux_num > 3)
1089 return -EINVAL;
1090
1091 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1092 dev_err(info->dev, "pin %d is unrouted\n", pin);
1093 return -EINVAL;
1094 }
1095
1096 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1097 if (mux != RK_FUNC_GPIO) {
1098 dev_err(info->dev,
1099 "pin %d only supports a gpio mux\n", pin);
1100 return -ENOTSUPP;
1101 }
1102 }
1103
1104 return 0;
1105}
1106
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001107/*
1108 * Set a new mux function for a pin.
1109 *
1110 * The register is divided into the upper and lower 16 bit. When changing
1111 * a value, the previous register value is not read and changed. Instead
1112 * it seems the changed bits are marked in the upper 16 bit, while the
1113 * changed value gets set in the same offset in the lower 16 bit.
1114 * All pin settings seem to be 2 bit wide in both the upper and lower
1115 * parts.
1116 * @bank: pin bank to change
1117 * @pin: pin to change
1118 * @mux: new mux function to set
1119 */
Heiko Stübner14797182014-03-26 00:57:00 +01001120static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001121{
1122 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001123 int iomux_num = (pin / 8);
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001124 struct regmap *regmap;
david.wuea262ad2017-02-10 18:23:48 +08001125 int reg, ret, mask, mux_type;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001126 u8 bit;
David Wubd35b9b2017-05-26 15:20:20 +08001127 u32 data, rmask, route_reg, route_val;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001128
John Keeping05709c32017-03-23 10:59:30 +00001129 ret = rockchip_verify_mux(bank, pin, mux);
1130 if (ret < 0)
1131 return ret;
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001132
John Keeping05709c32017-03-23 10:59:30 +00001133 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1134 return 0;
Heiko Stübnerc4a532de2014-03-26 00:57:52 +01001135
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001136 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1137 bank->bank_num, pin, mux);
1138
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02001139 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1140 ? info->regmap_pmu : info->regmap_base;
1141
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001142 /* get basic quadrupel of mux registers and the correct reg inside */
david.wuea262ad2017-02-10 18:23:48 +08001143 mux_type = bank->iomux[iomux_num].type;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02001144 reg = bank->iomux[iomux_num].offset;
david.wuea262ad2017-02-10 18:23:48 +08001145 if (mux_type & IOMUX_WIDTH_4BIT) {
Heiko Stübner03716e12014-06-16 01:36:57 +02001146 if ((pin % 8) >= 4)
1147 reg += 0x4;
1148 bit = (pin % 4) * 4;
david.wu8b6c6f92017-02-10 18:23:47 +08001149 mask = 0xf;
david.wuea262ad2017-02-10 18:23:48 +08001150 } else if (mux_type & IOMUX_WIDTH_3BIT) {
david.wu8b6c6f92017-02-10 18:23:47 +08001151 if ((pin % 8) >= 5)
1152 reg += 0x4;
1153 bit = (pin % 8 % 5) * 3;
1154 mask = 0x7;
Heiko Stübner03716e12014-06-16 01:36:57 +02001155 } else {
1156 bit = (pin % 8) * 2;
david.wu8b6c6f92017-02-10 18:23:47 +08001157 mask = 0x3;
Heiko Stübner03716e12014-06-16 01:36:57 +02001158 }
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001159
David Wuc04c3fa2017-07-21 14:27:14 +08001160 if (bank->recalced_mask & BIT(pin))
1161 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
david.wuea262ad2017-02-10 18:23:48 +08001162
David Wubd35b9b2017-05-26 15:20:20 +08001163 if (bank->route_mask & BIT(pin)) {
1164 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1165 &route_val)) {
1166 ret = regmap_write(regmap, route_reg, route_val);
1167 if (ret)
1168 return ret;
1169 }
1170 }
1171
Heiko Stübner03716e12014-06-16 01:36:57 +02001172 data = (mask << (bit + 16));
Sonny Rao99e872d2014-07-31 22:58:00 -07001173 rmask = data | (data >> 16);
Heiko Stübner03716e12014-06-16 01:36:57 +02001174 data |= (mux & mask) << bit;
Sonny Rao99e872d2014-07-31 22:58:00 -07001175 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001176
Heiko Stübner751a99a2014-05-05 13:58:20 +02001177 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001178}
1179
Andy Yanb9c6dca2017-03-17 18:18:36 +01001180#define RV1108_PULL_PMU_OFFSET 0x10
1181#define RV1108_PULL_OFFSET 0x110
1182#define RV1108_PULL_PINS_PER_REG 8
1183#define RV1108_PULL_BITS_PER_PIN 2
1184#define RV1108_PULL_BANK_STRIDE 16
Andy Yan688daf22016-11-15 18:02:43 +08001185
Andy Yanb9c6dca2017-03-17 18:18:36 +01001186static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
Andy Yan688daf22016-11-15 18:02:43 +08001187 int pin_num, struct regmap **regmap,
1188 int *reg, u8 *bit)
1189{
1190 struct rockchip_pinctrl *info = bank->drvdata;
1191
1192 /* The first 24 pins of the first bank are located in PMU */
1193 if (bank->bank_num == 0) {
1194 *regmap = info->regmap_pmu;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001195 *reg = RV1108_PULL_PMU_OFFSET;
Andy Yan688daf22016-11-15 18:02:43 +08001196 } else {
Andy Yanb9c6dca2017-03-17 18:18:36 +01001197 *reg = RV1108_PULL_OFFSET;
Andy Yan688daf22016-11-15 18:02:43 +08001198 *regmap = info->regmap_base;
1199 /* correct the offset, as we're starting with the 2nd bank */
1200 *reg -= 0x10;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001201 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
Andy Yan688daf22016-11-15 18:02:43 +08001202 }
1203
Andy Yanb9c6dca2017-03-17 18:18:36 +01001204 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1205 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1206 *bit *= RV1108_PULL_BITS_PER_PIN;
Andy Yan688daf22016-11-15 18:02:43 +08001207}
1208
Andy Yanb9c6dca2017-03-17 18:18:36 +01001209#define RV1108_DRV_PMU_OFFSET 0x20
1210#define RV1108_DRV_GRF_OFFSET 0x210
1211#define RV1108_DRV_BITS_PER_PIN 2
1212#define RV1108_DRV_PINS_PER_REG 8
1213#define RV1108_DRV_BANK_STRIDE 16
Andy Yan688daf22016-11-15 18:02:43 +08001214
Andy Yanb9c6dca2017-03-17 18:18:36 +01001215static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
Andy Yan688daf22016-11-15 18:02:43 +08001216 int pin_num, struct regmap **regmap,
1217 int *reg, u8 *bit)
1218{
1219 struct rockchip_pinctrl *info = bank->drvdata;
1220
1221 /* The first 24 pins of the first bank are located in PMU */
1222 if (bank->bank_num == 0) {
1223 *regmap = info->regmap_pmu;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001224 *reg = RV1108_DRV_PMU_OFFSET;
Andy Yan688daf22016-11-15 18:02:43 +08001225 } else {
1226 *regmap = info->regmap_base;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001227 *reg = RV1108_DRV_GRF_OFFSET;
Andy Yan688daf22016-11-15 18:02:43 +08001228
1229 /* correct the offset, as we're starting with the 2nd bank */
1230 *reg -= 0x10;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001231 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
Andy Yan688daf22016-11-15 18:02:43 +08001232 }
1233
Andy Yanb9c6dca2017-03-17 18:18:36 +01001234 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1235 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1236 *bit *= RV1108_DRV_BITS_PER_PIN;
Andy Yan688daf22016-11-15 18:02:43 +08001237}
1238
Andy Yan5caff7e2017-07-31 18:10:22 +08001239#define RV1108_SCHMITT_PMU_OFFSET 0x30
1240#define RV1108_SCHMITT_GRF_OFFSET 0x388
1241#define RV1108_SCHMITT_BANK_STRIDE 8
1242#define RV1108_SCHMITT_PINS_PER_GRF_REG 16
1243#define RV1108_SCHMITT_PINS_PER_PMU_REG 8
1244
1245static int rv1108_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1246 int pin_num,
1247 struct regmap **regmap,
1248 int *reg, u8 *bit)
1249{
1250 struct rockchip_pinctrl *info = bank->drvdata;
1251 int pins_per_reg;
1252
1253 if (bank->bank_num == 0) {
1254 *regmap = info->regmap_pmu;
1255 *reg = RV1108_SCHMITT_PMU_OFFSET;
1256 pins_per_reg = RV1108_SCHMITT_PINS_PER_PMU_REG;
1257 } else {
1258 *regmap = info->regmap_base;
1259 *reg = RV1108_SCHMITT_GRF_OFFSET;
1260 pins_per_reg = RV1108_SCHMITT_PINS_PER_GRF_REG;
1261 *reg += (bank->bank_num - 1) * RV1108_SCHMITT_BANK_STRIDE;
1262 }
1263 *reg += ((pin_num / pins_per_reg) * 4);
1264 *bit = pin_num % pins_per_reg;
1265
1266 return 0;
1267}
1268
Heiko Stübnera2829262013-10-16 01:07:20 +02001269#define RK2928_PULL_OFFSET 0x118
1270#define RK2928_PULL_PINS_PER_REG 16
1271#define RK2928_PULL_BANK_STRIDE 8
1272
1273static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
Heiko Stübner751a99a2014-05-05 13:58:20 +02001274 int pin_num, struct regmap **regmap,
1275 int *reg, u8 *bit)
Heiko Stübnera2829262013-10-16 01:07:20 +02001276{
1277 struct rockchip_pinctrl *info = bank->drvdata;
1278
Heiko Stübner751a99a2014-05-05 13:58:20 +02001279 *regmap = info->regmap_base;
1280 *reg = RK2928_PULL_OFFSET;
Heiko Stübnera2829262013-10-16 01:07:20 +02001281 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1282 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1283
1284 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1285};
1286
David Wud23c66d2017-07-21 14:27:15 +08001287#define RK3128_PULL_OFFSET 0x118
1288
1289static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1290 int pin_num, struct regmap **regmap,
1291 int *reg, u8 *bit)
1292{
1293 struct rockchip_pinctrl *info = bank->drvdata;
1294
1295 *regmap = info->regmap_base;
1296 *reg = RK3128_PULL_OFFSET;
1297 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1298 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1299
1300 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1301}
1302
Heiko Stübnerbfc7a422014-05-05 13:58:00 +02001303#define RK3188_PULL_OFFSET 0x164
Heiko Stübner6ca52742013-10-16 01:08:42 +02001304#define RK3188_PULL_BITS_PER_PIN 2
1305#define RK3188_PULL_PINS_PER_REG 8
1306#define RK3188_PULL_BANK_STRIDE 16
Heiko Stübner14dee862014-05-05 13:59:09 +02001307#define RK3188_PULL_PMU_OFFSET 0x64
Heiko Stübner6ca52742013-10-16 01:08:42 +02001308
1309static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
Heiko Stübner751a99a2014-05-05 13:58:20 +02001310 int pin_num, struct regmap **regmap,
1311 int *reg, u8 *bit)
Heiko Stübner6ca52742013-10-16 01:08:42 +02001312{
1313 struct rockchip_pinctrl *info = bank->drvdata;
1314
1315 /* The first 12 pins of the first bank are located elsewhere */
Heiko Stübnerfc72c922014-06-16 01:36:05 +02001316 if (bank->bank_num == 0 && pin_num < 12) {
Heiko Stübner14dee862014-05-05 13:59:09 +02001317 *regmap = info->regmap_pmu ? info->regmap_pmu
1318 : bank->regmap_pull;
1319 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001320 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
Heiko Stübner6ca52742013-10-16 01:08:42 +02001321 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1322 *bit *= RK3188_PULL_BITS_PER_PIN;
1323 } else {
Heiko Stübner751a99a2014-05-05 13:58:20 +02001324 *regmap = info->regmap_pull ? info->regmap_pull
1325 : info->regmap_base;
1326 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1327
Heiko Stübnerbfc7a422014-05-05 13:58:00 +02001328 /* correct the offset, as it is the 2nd pull register */
1329 *reg -= 4;
Heiko Stübner6ca52742013-10-16 01:08:42 +02001330 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1331 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1332
1333 /*
1334 * The bits in these registers have an inverse ordering
1335 * with the lowest pin being in bits 15:14 and the highest
1336 * pin in bits 1:0
1337 */
1338 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1339 *bit *= RK3188_PULL_BITS_PER_PIN;
1340 }
1341}
1342
Heiko Stübner304f0772014-06-16 01:38:14 +02001343#define RK3288_PULL_OFFSET 0x140
1344static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1345 int pin_num, struct regmap **regmap,
1346 int *reg, u8 *bit)
1347{
1348 struct rockchip_pinctrl *info = bank->drvdata;
1349
1350 /* The first 24 pins of the first bank are located in PMU */
1351 if (bank->bank_num == 0) {
1352 *regmap = info->regmap_pmu;
1353 *reg = RK3188_PULL_PMU_OFFSET;
1354
1355 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1356 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1357 *bit *= RK3188_PULL_BITS_PER_PIN;
1358 } else {
1359 *regmap = info->regmap_base;
1360 *reg = RK3288_PULL_OFFSET;
1361
1362 /* correct the offset, as we're starting with the 2nd bank */
1363 *reg -= 0x10;
1364 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1365 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1366
1367 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1368 *bit *= RK3188_PULL_BITS_PER_PIN;
1369 }
1370}
1371
Heiko Stübnerb547c802014-07-20 01:50:11 +02001372#define RK3288_DRV_PMU_OFFSET 0x70
1373#define RK3288_DRV_GRF_OFFSET 0x1c0
1374#define RK3288_DRV_BITS_PER_PIN 2
1375#define RK3288_DRV_PINS_PER_REG 8
1376#define RK3288_DRV_BANK_STRIDE 16
Heiko Stübnerb547c802014-07-20 01:50:11 +02001377
1378static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1379 int pin_num, struct regmap **regmap,
1380 int *reg, u8 *bit)
1381{
1382 struct rockchip_pinctrl *info = bank->drvdata;
1383
1384 /* The first 24 pins of the first bank are located in PMU */
1385 if (bank->bank_num == 0) {
1386 *regmap = info->regmap_pmu;
1387 *reg = RK3288_DRV_PMU_OFFSET;
1388
1389 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1390 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1391 *bit *= RK3288_DRV_BITS_PER_PIN;
1392 } else {
1393 *regmap = info->regmap_base;
1394 *reg = RK3288_DRV_GRF_OFFSET;
1395
1396 /* correct the offset, as we're starting with the 2nd bank */
1397 *reg -= 0x10;
1398 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1399 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1400
1401 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1402 *bit *= RK3288_DRV_BITS_PER_PIN;
1403 }
1404}
1405
Jeffy Chenfea0fe62015-12-09 17:04:06 +08001406#define RK3228_PULL_OFFSET 0x100
1407
1408static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1409 int pin_num, struct regmap **regmap,
1410 int *reg, u8 *bit)
1411{
1412 struct rockchip_pinctrl *info = bank->drvdata;
1413
1414 *regmap = info->regmap_base;
1415 *reg = RK3228_PULL_OFFSET;
1416 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1417 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1418
1419 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1420 *bit *= RK3188_PULL_BITS_PER_PIN;
1421}
1422
1423#define RK3228_DRV_GRF_OFFSET 0x200
1424
1425static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1426 int pin_num, struct regmap **regmap,
1427 int *reg, u8 *bit)
1428{
1429 struct rockchip_pinctrl *info = bank->drvdata;
1430
1431 *regmap = info->regmap_base;
1432 *reg = RK3228_DRV_GRF_OFFSET;
1433 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1434 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1435
1436 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1437 *bit *= RK3288_DRV_BITS_PER_PIN;
1438}
1439
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02001440#define RK3368_PULL_GRF_OFFSET 0x100
1441#define RK3368_PULL_PMU_OFFSET 0x10
1442
1443static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1444 int pin_num, struct regmap **regmap,
1445 int *reg, u8 *bit)
1446{
1447 struct rockchip_pinctrl *info = bank->drvdata;
1448
1449 /* The first 32 pins of the first bank are located in PMU */
1450 if (bank->bank_num == 0) {
1451 *regmap = info->regmap_pmu;
1452 *reg = RK3368_PULL_PMU_OFFSET;
1453
1454 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1455 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1456 *bit *= RK3188_PULL_BITS_PER_PIN;
1457 } else {
1458 *regmap = info->regmap_base;
1459 *reg = RK3368_PULL_GRF_OFFSET;
1460
1461 /* correct the offset, as we're starting with the 2nd bank */
1462 *reg -= 0x10;
1463 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1464 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1465
1466 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1467 *bit *= RK3188_PULL_BITS_PER_PIN;
1468 }
1469}
1470
1471#define RK3368_DRV_PMU_OFFSET 0x20
1472#define RK3368_DRV_GRF_OFFSET 0x200
1473
1474static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1475 int pin_num, struct regmap **regmap,
1476 int *reg, u8 *bit)
1477{
1478 struct rockchip_pinctrl *info = bank->drvdata;
1479
1480 /* The first 32 pins of the first bank are located in PMU */
1481 if (bank->bank_num == 0) {
1482 *regmap = info->regmap_pmu;
1483 *reg = RK3368_DRV_PMU_OFFSET;
1484
1485 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1486 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1487 *bit *= RK3288_DRV_BITS_PER_PIN;
1488 } else {
1489 *regmap = info->regmap_base;
1490 *reg = RK3368_DRV_GRF_OFFSET;
1491
1492 /* correct the offset, as we're starting with the 2nd bank */
1493 *reg -= 0x10;
1494 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1495 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1496
1497 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1498 *bit *= RK3288_DRV_BITS_PER_PIN;
1499 }
1500}
1501
David Wub6c23272016-02-01 10:58:21 +08001502#define RK3399_PULL_GRF_OFFSET 0xe040
1503#define RK3399_PULL_PMU_OFFSET 0x40
1504#define RK3399_DRV_3BITS_PER_PIN 3
1505
1506static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1507 int pin_num, struct regmap **regmap,
1508 int *reg, u8 *bit)
1509{
1510 struct rockchip_pinctrl *info = bank->drvdata;
1511
1512 /* The bank0:16 and bank1:32 pins are located in PMU */
1513 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1514 *regmap = info->regmap_pmu;
1515 *reg = RK3399_PULL_PMU_OFFSET;
1516
1517 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1518
1519 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1520 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1521 *bit *= RK3188_PULL_BITS_PER_PIN;
1522 } else {
1523 *regmap = info->regmap_base;
1524 *reg = RK3399_PULL_GRF_OFFSET;
1525
1526 /* correct the offset, as we're starting with the 3rd bank */
1527 *reg -= 0x20;
1528 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1529 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1530
1531 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1532 *bit *= RK3188_PULL_BITS_PER_PIN;
1533 }
1534}
1535
1536static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1537 int pin_num, struct regmap **regmap,
1538 int *reg, u8 *bit)
1539{
1540 struct rockchip_pinctrl *info = bank->drvdata;
1541 int drv_num = (pin_num / 8);
1542
1543 /* The bank0:16 and bank1:32 pins are located in PMU */
1544 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1545 *regmap = info->regmap_pmu;
1546 else
1547 *regmap = info->regmap_base;
1548
1549 *reg = bank->drv[drv_num].offset;
1550 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1551 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1552 *bit = (pin_num % 8) * 3;
1553 else
1554 *bit = (pin_num % 8) * 2;
1555}
1556
1557static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1558 { 2, 4, 8, 12, -1, -1, -1, -1 },
1559 { 3, 6, 9, 12, -1, -1, -1, -1 },
1560 { 5, 10, 15, 20, -1, -1, -1, -1 },
1561 { 4, 6, 8, 10, 12, 14, 16, 18 },
1562 { 4, 7, 10, 13, 16, 19, 22, 26 }
1563};
Heiko Stübneref17f692015-06-12 23:50:11 +02001564
1565static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1566 int pin_num)
Heiko Stübnerb547c802014-07-20 01:50:11 +02001567{
Heiko Stübneref17f692015-06-12 23:50:11 +02001568 struct rockchip_pinctrl *info = bank->drvdata;
1569 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001570 struct regmap *regmap;
1571 int reg, ret;
David Wub6c23272016-02-01 10:58:21 +08001572 u32 data, temp, rmask_bits;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001573 u8 bit;
David Wub6c23272016-02-01 10:58:21 +08001574 int drv_type = bank->drv[pin_num / 8].drv_type;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001575
Heiko Stübneref17f692015-06-12 23:50:11 +02001576 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001577
David Wub6c23272016-02-01 10:58:21 +08001578 switch (drv_type) {
1579 case DRV_TYPE_IO_1V8_3V0_AUTO:
1580 case DRV_TYPE_IO_3V3_ONLY:
1581 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1582 switch (bit) {
1583 case 0 ... 12:
1584 /* regular case, nothing to do */
1585 break;
1586 case 15:
1587 /*
1588 * drive-strength offset is special, as it is
1589 * spread over 2 registers
1590 */
1591 ret = regmap_read(regmap, reg, &data);
1592 if (ret)
1593 return ret;
1594
1595 ret = regmap_read(regmap, reg + 0x4, &temp);
1596 if (ret)
1597 return ret;
1598
1599 /*
1600 * the bit data[15] contains bit 0 of the value
1601 * while temp[1:0] contains bits 2 and 1
1602 */
1603 data >>= 15;
1604 temp &= 0x3;
1605 temp <<= 1;
1606 data |= temp;
1607
1608 return rockchip_perpin_drv_list[drv_type][data];
1609 case 18 ... 21:
1610 /* setting fully enclosed in the second register */
1611 reg += 4;
1612 bit -= 16;
1613 break;
1614 default:
1615 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1616 bit, drv_type);
1617 return -EINVAL;
1618 }
1619
1620 break;
1621 case DRV_TYPE_IO_DEFAULT:
1622 case DRV_TYPE_IO_1V8_OR_3V0:
1623 case DRV_TYPE_IO_1V8_ONLY:
1624 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1625 break;
1626 default:
1627 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1628 drv_type);
1629 return -EINVAL;
1630 }
1631
Heiko Stübnerb547c802014-07-20 01:50:11 +02001632 ret = regmap_read(regmap, reg, &data);
1633 if (ret)
1634 return ret;
1635
1636 data >>= bit;
David Wub6c23272016-02-01 10:58:21 +08001637 data &= (1 << rmask_bits) - 1;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001638
David Wub6c23272016-02-01 10:58:21 +08001639 return rockchip_perpin_drv_list[drv_type][data];
Heiko Stübnerb547c802014-07-20 01:50:11 +02001640}
1641
Heiko Stübneref17f692015-06-12 23:50:11 +02001642static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1643 int pin_num, int strength)
Heiko Stübnerb547c802014-07-20 01:50:11 +02001644{
1645 struct rockchip_pinctrl *info = bank->drvdata;
Heiko Stübneref17f692015-06-12 23:50:11 +02001646 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001647 struct regmap *regmap;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001648 int reg, ret, i;
David Wub6c23272016-02-01 10:58:21 +08001649 u32 data, rmask, rmask_bits, temp;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001650 u8 bit;
David Wub6c23272016-02-01 10:58:21 +08001651 int drv_type = bank->drv[pin_num / 8].drv_type;
1652
1653 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1654 bank->bank_num, pin_num, strength);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001655
Heiko Stübneref17f692015-06-12 23:50:11 +02001656 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001657
1658 ret = -EINVAL;
David Wub6c23272016-02-01 10:58:21 +08001659 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1660 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
Heiko Stübnerb547c802014-07-20 01:50:11 +02001661 ret = i;
1662 break;
David Wub6c23272016-02-01 10:58:21 +08001663 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1664 ret = rockchip_perpin_drv_list[drv_type][i];
1665 break;
Heiko Stübnerb547c802014-07-20 01:50:11 +02001666 }
1667 }
1668
1669 if (ret < 0) {
1670 dev_err(info->dev, "unsupported driver strength %d\n",
1671 strength);
1672 return ret;
1673 }
1674
David Wub6c23272016-02-01 10:58:21 +08001675 switch (drv_type) {
1676 case DRV_TYPE_IO_1V8_3V0_AUTO:
1677 case DRV_TYPE_IO_3V3_ONLY:
1678 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1679 switch (bit) {
1680 case 0 ... 12:
1681 /* regular case, nothing to do */
1682 break;
1683 case 15:
1684 /*
1685 * drive-strength offset is special, as it is spread
1686 * over 2 registers, the bit data[15] contains bit 0
1687 * of the value while temp[1:0] contains bits 2 and 1
1688 */
1689 data = (ret & 0x1) << 15;
1690 temp = (ret >> 0x1) & 0x3;
1691
1692 rmask = BIT(15) | BIT(31);
1693 data |= BIT(31);
1694 ret = regmap_update_bits(regmap, reg, rmask, data);
John Keepingf07bedc2017-03-23 10:59:28 +00001695 if (ret)
David Wub6c23272016-02-01 10:58:21 +08001696 return ret;
David Wub6c23272016-02-01 10:58:21 +08001697
1698 rmask = 0x3 | (0x3 << 16);
1699 temp |= (0x3 << 16);
1700 reg += 0x4;
1701 ret = regmap_update_bits(regmap, reg, rmask, temp);
1702
David Wub6c23272016-02-01 10:58:21 +08001703 return ret;
1704 case 18 ... 21:
1705 /* setting fully enclosed in the second register */
1706 reg += 4;
1707 bit -= 16;
1708 break;
1709 default:
David Wub6c23272016-02-01 10:58:21 +08001710 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1711 bit, drv_type);
1712 return -EINVAL;
1713 }
1714 break;
1715 case DRV_TYPE_IO_DEFAULT:
1716 case DRV_TYPE_IO_1V8_OR_3V0:
1717 case DRV_TYPE_IO_1V8_ONLY:
1718 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1719 break;
1720 default:
David Wub6c23272016-02-01 10:58:21 +08001721 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1722 drv_type);
1723 return -EINVAL;
1724 }
1725
Heiko Stübnerb547c802014-07-20 01:50:11 +02001726 /* enable the write to the equivalent lower bits */
David Wub6c23272016-02-01 10:58:21 +08001727 data = ((1 << rmask_bits) - 1) << (bit + 16);
Sonny Rao99e872d2014-07-31 22:58:00 -07001728 rmask = data | (data >> 16);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001729 data |= (ret << bit);
1730
Sonny Rao99e872d2014-07-31 22:58:00 -07001731 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübnerb547c802014-07-20 01:50:11 +02001732
1733 return ret;
1734}
1735
David Wu3ba67672016-05-11 11:39:28 +08001736static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1737 {
1738 PIN_CONFIG_BIAS_DISABLE,
1739 PIN_CONFIG_BIAS_PULL_UP,
1740 PIN_CONFIG_BIAS_PULL_DOWN,
1741 PIN_CONFIG_BIAS_BUS_HOLD
1742 },
1743 {
1744 PIN_CONFIG_BIAS_DISABLE,
1745 PIN_CONFIG_BIAS_PULL_DOWN,
1746 PIN_CONFIG_BIAS_DISABLE,
1747 PIN_CONFIG_BIAS_PULL_UP
1748 },
1749};
1750
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001751static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1752{
1753 struct rockchip_pinctrl *info = bank->drvdata;
1754 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001755 struct regmap *regmap;
David Wu3ba67672016-05-11 11:39:28 +08001756 int reg, ret, pull_type;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001757 u8 bit;
Heiko Stübner6ca52742013-10-16 01:08:42 +02001758 u32 data;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001759
1760 /* rk3066b does support any pulls */
Heiko Stübnera2829262013-10-16 01:07:20 +02001761 if (ctrl->type == RK3066B)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001762 return PIN_CONFIG_BIAS_DISABLE;
1763
Heiko Stübner751a99a2014-05-05 13:58:20 +02001764 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1765
1766 ret = regmap_read(regmap, reg, &data);
1767 if (ret)
1768 return ret;
Heiko Stübner6ca52742013-10-16 01:08:42 +02001769
Heiko Stübnera2829262013-10-16 01:07:20 +02001770 switch (ctrl->type) {
1771 case RK2928:
David Wud23c66d2017-07-21 14:27:15 +08001772 case RK3128:
Heiko Stübner751a99a2014-05-05 13:58:20 +02001773 return !(data & BIT(bit))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001774 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1775 : PIN_CONFIG_BIAS_DISABLE;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001776 case RV1108:
Heiko Stübnera2829262013-10-16 01:07:20 +02001777 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +02001778 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02001779 case RK3368:
David Wub6c23272016-02-01 10:58:21 +08001780 case RK3399:
David Wu3ba67672016-05-11 11:39:28 +08001781 pull_type = bank->pull_type[pin_num / 8];
Heiko Stübner751a99a2014-05-05 13:58:20 +02001782 data >>= bit;
Heiko Stübner6ca52742013-10-16 01:08:42 +02001783 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1784
David Wu3ba67672016-05-11 11:39:28 +08001785 return rockchip_pull_list[pull_type][data];
Heiko Stübnera2829262013-10-16 01:07:20 +02001786 default:
1787 dev_err(info->dev, "unsupported pinctrl type\n");
1788 return -EINVAL;
1789 };
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001790}
1791
1792static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1793 int pin_num, int pull)
1794{
1795 struct rockchip_pinctrl *info = bank->drvdata;
1796 struct rockchip_pin_ctrl *ctrl = info->ctrl;
Heiko Stübner751a99a2014-05-05 13:58:20 +02001797 struct regmap *regmap;
David Wu3ba67672016-05-11 11:39:28 +08001798 int reg, ret, i, pull_type;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001799 u8 bit;
Sonny Rao99e872d2014-07-31 22:58:00 -07001800 u32 data, rmask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001801
1802 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1803 bank->bank_num, pin_num, pull);
1804
1805 /* rk3066b does support any pulls */
Heiko Stübnera2829262013-10-16 01:07:20 +02001806 if (ctrl->type == RK3066B)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001807 return pull ? -EINVAL : 0;
1808
Heiko Stübner751a99a2014-05-05 13:58:20 +02001809 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
Heiko Stübner6ca52742013-10-16 01:08:42 +02001810
Heiko Stübnera2829262013-10-16 01:07:20 +02001811 switch (ctrl->type) {
1812 case RK2928:
David Wud23c66d2017-07-21 14:27:15 +08001813 case RK3128:
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001814 data = BIT(bit + 16);
1815 if (pull == PIN_CONFIG_BIAS_DISABLE)
1816 data |= BIT(bit);
Heiko Stübner751a99a2014-05-05 13:58:20 +02001817 ret = regmap_write(regmap, reg, data);
Heiko Stübnera2829262013-10-16 01:07:20 +02001818 break;
Andy Yanb9c6dca2017-03-17 18:18:36 +01001819 case RV1108:
Heiko Stübnera2829262013-10-16 01:07:20 +02001820 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +02001821 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02001822 case RK3368:
David Wub6c23272016-02-01 10:58:21 +08001823 case RK3399:
David Wu3ba67672016-05-11 11:39:28 +08001824 pull_type = bank->pull_type[pin_num / 8];
1825 ret = -EINVAL;
1826 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1827 i++) {
1828 if (rockchip_pull_list[pull_type][i] == pull) {
1829 ret = i;
1830 break;
1831 }
1832 }
1833
1834 if (ret < 0) {
1835 dev_err(info->dev, "unsupported pull setting %d\n",
1836 pull);
1837 return ret;
1838 }
1839
Heiko Stübner6ca52742013-10-16 01:08:42 +02001840 /* enable the write to the equivalent lower bits */
1841 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
Sonny Rao99e872d2014-07-31 22:58:00 -07001842 rmask = data | (data >> 16);
David Wu3ba67672016-05-11 11:39:28 +08001843 data |= (ret << bit);
Heiko Stübner6ca52742013-10-16 01:08:42 +02001844
Sonny Rao99e872d2014-07-31 22:58:00 -07001845 ret = regmap_update_bits(regmap, reg, rmask, data);
Heiko Stübner6ca52742013-10-16 01:08:42 +02001846 break;
Heiko Stübnera2829262013-10-16 01:07:20 +02001847 default:
1848 dev_err(info->dev, "unsupported pinctrl type\n");
1849 return -EINVAL;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001850 }
1851
Heiko Stübner751a99a2014-05-05 13:58:20 +02001852 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001853}
1854
david.wu728d3f52017-03-02 15:11:24 +08001855#define RK3328_SCHMITT_BITS_PER_PIN 1
1856#define RK3328_SCHMITT_PINS_PER_REG 16
1857#define RK3328_SCHMITT_BANK_STRIDE 8
1858#define RK3328_SCHMITT_GRF_OFFSET 0x380
1859
1860static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1861 int pin_num,
1862 struct regmap **regmap,
1863 int *reg, u8 *bit)
1864{
1865 struct rockchip_pinctrl *info = bank->drvdata;
1866
1867 *regmap = info->regmap_base;
1868 *reg = RK3328_SCHMITT_GRF_OFFSET;
1869
1870 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1871 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1872 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1873
1874 return 0;
1875}
1876
david.wue3b357d2017-03-02 15:11:23 +08001877static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1878{
1879 struct rockchip_pinctrl *info = bank->drvdata;
1880 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1881 struct regmap *regmap;
1882 int reg, ret;
1883 u8 bit;
1884 u32 data;
1885
1886 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1887 if (ret)
1888 return ret;
1889
1890 ret = regmap_read(regmap, reg, &data);
1891 if (ret)
1892 return ret;
1893
1894 data >>= bit;
1895 return data & 0x1;
1896}
1897
1898static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1899 int pin_num, int enable)
1900{
1901 struct rockchip_pinctrl *info = bank->drvdata;
1902 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1903 struct regmap *regmap;
1904 int reg, ret;
david.wue3b357d2017-03-02 15:11:23 +08001905 u8 bit;
1906 u32 data, rmask;
1907
1908 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1909 bank->bank_num, pin_num, enable);
1910
1911 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1912 if (ret)
1913 return ret;
1914
david.wue3b357d2017-03-02 15:11:23 +08001915 /* enable the write to the equivalent lower bits */
1916 data = BIT(bit + 16) | (enable << bit);
1917 rmask = BIT(bit + 16) | BIT(bit);
1918
John Keepingf07bedc2017-03-23 10:59:28 +00001919 return regmap_update_bits(regmap, reg, rmask, data);
david.wue3b357d2017-03-02 15:11:23 +08001920}
1921
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001922/*
1923 * Pinmux_ops handling
1924 */
1925
1926static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1927{
1928 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1929
1930 return info->nfunctions;
1931}
1932
1933static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1934 unsigned selector)
1935{
1936 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1937
1938 return info->functions[selector].name;
1939}
1940
1941static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1942 unsigned selector, const char * const **groups,
1943 unsigned * const num_groups)
1944{
1945 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1946
1947 *groups = info->functions[selector].groups;
1948 *num_groups = info->functions[selector].ngroups;
1949
1950 return 0;
1951}
1952
Linus Walleij03e9f0c2014-09-03 13:02:56 +02001953static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1954 unsigned group)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001955{
1956 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1957 const unsigned int *pins = info->groups[group].pins;
1958 const struct rockchip_pin_config *data = info->groups[group].data;
1959 struct rockchip_pin_bank *bank;
Heiko Stübner14797182014-03-26 00:57:00 +01001960 int cnt, ret = 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001961
1962 dev_dbg(info->dev, "enable function %s group %s\n",
1963 info->functions[selector].name, info->groups[group].name);
1964
1965 /*
1966 * for each pin in the pin group selected, program the correspoding pin
1967 * pin function number in the config register.
1968 */
1969 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1970 bank = pin_to_bank(info, pins[cnt]);
Heiko Stübner14797182014-03-26 00:57:00 +01001971 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1972 data[cnt].func);
1973 if (ret)
1974 break;
1975 }
1976
1977 if (ret) {
1978 /* revert the already done pin settings */
1979 for (cnt--; cnt >= 0; cnt--)
1980 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1981
1982 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001983 }
1984
1985 return 0;
1986}
1987
Caesar Wang6ba20a02016-03-15 15:55:45 +08001988static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1989{
1990 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1991 u32 data;
1992
1993 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1994
1995 return !(data & BIT(offset));
1996}
1997
Heiko Stübnerd3e51162013-06-10 22:16:22 +02001998/*
1999 * The calls to gpio_direction_output() and gpio_direction_input()
2000 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
2001 * function called from the gpiolib interface).
2002 */
Doug Andersone5c2c9d2014-10-21 10:47:33 -07002003static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
2004 int pin, bool input)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002005{
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002006 struct rockchip_pin_bank *bank;
Doug Andersone5c2c9d2014-10-21 10:47:33 -07002007 int ret;
Doug Andersonfab262f2014-10-21 10:47:35 -07002008 unsigned long flags;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002009 u32 data;
2010
Linus Walleij03bf81f2015-12-08 09:39:13 +01002011 bank = gpiochip_get_data(chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002012
Heiko Stübner14797182014-03-26 00:57:00 +01002013 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
2014 if (ret < 0)
2015 return ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002016
Lin Huang07a06ae2015-08-11 18:12:04 +08002017 clk_enable(bank->clk);
John Keeping70b7aa72017-03-23 10:59:29 +00002018 raw_spin_lock_irqsave(&bank->slock, flags);
Doug Andersonfab262f2014-10-21 10:47:35 -07002019
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002020 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2021 /* set bit to 1 for output, 0 for input */
2022 if (!input)
2023 data |= BIT(pin);
2024 else
2025 data &= ~BIT(pin);
2026 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2027
John Keeping70b7aa72017-03-23 10:59:29 +00002028 raw_spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +08002029 clk_disable(bank->clk);
Doug Andersonfab262f2014-10-21 10:47:35 -07002030
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002031 return 0;
2032}
2033
Doug Andersone5c2c9d2014-10-21 10:47:33 -07002034static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
2035 struct pinctrl_gpio_range *range,
2036 unsigned offset, bool input)
2037{
2038 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2039 struct gpio_chip *chip;
2040 int pin;
2041
2042 chip = range->gc;
2043 pin = offset - chip->base;
2044 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
2045 offset, range->name, pin, input ? "input" : "output");
2046
2047 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
2048 input);
2049}
2050
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002051static const struct pinmux_ops rockchip_pmx_ops = {
2052 .get_functions_count = rockchip_pmx_get_funcs_count,
2053 .get_function_name = rockchip_pmx_get_func_name,
2054 .get_function_groups = rockchip_pmx_get_groups,
Linus Walleij03e9f0c2014-09-03 13:02:56 +02002055 .set_mux = rockchip_pmx_set,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002056 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
2057};
2058
2059/*
2060 * Pinconf_ops handling
2061 */
2062
Heiko Stübner44b6d932013-06-16 17:41:16 +02002063static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
2064 enum pin_config_param pull)
2065{
Heiko Stübnera2829262013-10-16 01:07:20 +02002066 switch (ctrl->type) {
2067 case RK2928:
David Wud23c66d2017-07-21 14:27:15 +08002068 case RK3128:
Heiko Stübnera2829262013-10-16 01:07:20 +02002069 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
2070 pull == PIN_CONFIG_BIAS_DISABLE);
2071 case RK3066B:
Heiko Stübner44b6d932013-06-16 17:41:16 +02002072 return pull ? false : true;
Andy Yanb9c6dca2017-03-17 18:18:36 +01002073 case RV1108:
Heiko Stübnera2829262013-10-16 01:07:20 +02002074 case RK3188:
Heiko Stübner66d750e2014-07-20 01:49:17 +02002075 case RK3288:
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02002076 case RK3368:
David Wub6c23272016-02-01 10:58:21 +08002077 case RK3399:
Heiko Stübnera2829262013-10-16 01:07:20 +02002078 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
Heiko Stübner44b6d932013-06-16 17:41:16 +02002079 }
2080
Heiko Stübnera2829262013-10-16 01:07:20 +02002081 return false;
Heiko Stübner44b6d932013-06-16 17:41:16 +02002082}
2083
Doug Andersone5c2c9d2014-10-21 10:47:33 -07002084static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
Heiko Stübnera076e2e2014-04-23 14:28:59 +02002085static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
2086
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002087/* set the pin config settings for a specified pin */
2088static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
Sherman Yin03b054e2013-08-27 11:32:12 -07002089 unsigned long *configs, unsigned num_configs)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002090{
2091 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2092 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
Sherman Yin03b054e2013-08-27 11:32:12 -07002093 enum pin_config_param param;
Mika Westerberg58957d22017-01-23 15:34:32 +03002094 u32 arg;
Sherman Yin03b054e2013-08-27 11:32:12 -07002095 int i;
2096 int rc;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002097
Sherman Yin03b054e2013-08-27 11:32:12 -07002098 for (i = 0; i < num_configs; i++) {
2099 param = pinconf_to_config_param(configs[i]);
2100 arg = pinconf_to_config_argument(configs[i]);
2101
2102 switch (param) {
2103 case PIN_CONFIG_BIAS_DISABLE:
2104 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2105 param);
2106 if (rc)
2107 return rc;
2108 break;
2109 case PIN_CONFIG_BIAS_PULL_UP:
2110 case PIN_CONFIG_BIAS_PULL_DOWN:
2111 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
Heiko Stübner6ca52742013-10-16 01:08:42 +02002112 case PIN_CONFIG_BIAS_BUS_HOLD:
Sherman Yin03b054e2013-08-27 11:32:12 -07002113 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2114 return -ENOTSUPP;
2115
2116 if (!arg)
2117 return -EINVAL;
2118
2119 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2120 param);
2121 if (rc)
2122 return rc;
2123 break;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02002124 case PIN_CONFIG_OUTPUT:
Doug Andersone5c2c9d2014-10-21 10:47:33 -07002125 rockchip_gpio_set(&bank->gpio_chip,
2126 pin - bank->pin_base, arg);
2127 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2128 pin - bank->pin_base, false);
Heiko Stübnera076e2e2014-04-23 14:28:59 +02002129 if (rc)
2130 return rc;
2131 break;
Heiko Stübnerb547c802014-07-20 01:50:11 +02002132 case PIN_CONFIG_DRIVE_STRENGTH:
2133 /* rk3288 is the first with per-pin drive-strength */
Heiko Stübneref17f692015-06-12 23:50:11 +02002134 if (!info->ctrl->drv_calc_reg)
Heiko Stübnerb547c802014-07-20 01:50:11 +02002135 return -ENOTSUPP;
2136
Heiko Stübneref17f692015-06-12 23:50:11 +02002137 rc = rockchip_set_drive_perpin(bank,
2138 pin - bank->pin_base, arg);
Heiko Stübnerb547c802014-07-20 01:50:11 +02002139 if (rc < 0)
2140 return rc;
2141 break;
david.wue3b357d2017-03-02 15:11:23 +08002142 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2143 if (!info->ctrl->schmitt_calc_reg)
2144 return -ENOTSUPP;
2145
2146 rc = rockchip_set_schmitt(bank,
2147 pin - bank->pin_base, arg);
2148 if (rc < 0)
2149 return rc;
2150 break;
Sherman Yin03b054e2013-08-27 11:32:12 -07002151 default:
Heiko Stübner44b6d932013-06-16 17:41:16 +02002152 return -ENOTSUPP;
Sherman Yin03b054e2013-08-27 11:32:12 -07002153 break;
2154 }
2155 } /* for each config */
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002156
2157 return 0;
2158}
2159
2160/* get the pin config settings for a specified pin */
2161static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2162 unsigned long *config)
2163{
2164 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2165 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2166 enum pin_config_param param = pinconf_to_config_param(*config);
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02002167 u16 arg;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02002168 int rc;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002169
2170 switch (param) {
2171 case PIN_CONFIG_BIAS_DISABLE:
Heiko Stübner44b6d932013-06-16 17:41:16 +02002172 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002173 return -EINVAL;
2174
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02002175 arg = 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002176 break;
Heiko Stübner44b6d932013-06-16 17:41:16 +02002177 case PIN_CONFIG_BIAS_PULL_UP:
2178 case PIN_CONFIG_BIAS_PULL_DOWN:
2179 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
Heiko Stübner6ca52742013-10-16 01:08:42 +02002180 case PIN_CONFIG_BIAS_BUS_HOLD:
Heiko Stübner44b6d932013-06-16 17:41:16 +02002181 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2182 return -ENOTSUPP;
2183
2184 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2185 return -EINVAL;
2186
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02002187 arg = 1;
Heiko Stübner44b6d932013-06-16 17:41:16 +02002188 break;
Heiko Stübnera076e2e2014-04-23 14:28:59 +02002189 case PIN_CONFIG_OUTPUT:
2190 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2191 if (rc != RK_FUNC_GPIO)
2192 return -EINVAL;
2193
2194 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2195 if (rc < 0)
2196 return rc;
2197
2198 arg = rc ? 1 : 0;
2199 break;
Heiko Stübnerb547c802014-07-20 01:50:11 +02002200 case PIN_CONFIG_DRIVE_STRENGTH:
2201 /* rk3288 is the first with per-pin drive-strength */
Heiko Stübneref17f692015-06-12 23:50:11 +02002202 if (!info->ctrl->drv_calc_reg)
Heiko Stübnerb547c802014-07-20 01:50:11 +02002203 return -ENOTSUPP;
2204
Heiko Stübneref17f692015-06-12 23:50:11 +02002205 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
Heiko Stübnerb547c802014-07-20 01:50:11 +02002206 if (rc < 0)
2207 return rc;
2208
2209 arg = rc;
2210 break;
david.wue3b357d2017-03-02 15:11:23 +08002211 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2212 if (!info->ctrl->schmitt_calc_reg)
2213 return -ENOTSUPP;
2214
2215 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2216 if (rc < 0)
2217 return rc;
2218
2219 arg = rc;
2220 break;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002221 default:
2222 return -ENOTSUPP;
2223 break;
2224 }
2225
Heiko Stübnerdab3eba2014-04-23 14:27:51 +02002226 *config = pinconf_to_config_packed(param, arg);
2227
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002228 return 0;
2229}
2230
2231static const struct pinconf_ops rockchip_pinconf_ops = {
2232 .pin_config_get = rockchip_pinconf_get,
2233 .pin_config_set = rockchip_pinconf_set,
Heiko Stübnered62f2f2014-07-20 01:48:45 +02002234 .is_generic = true,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002235};
2236
Heiko Stübner65fca612013-10-16 01:07:49 +02002237static const struct of_device_id rockchip_bank_match[] = {
2238 { .compatible = "rockchip,gpio-bank" },
Heiko Stübner6ca52742013-10-16 01:08:42 +02002239 { .compatible = "rockchip,rk3188-gpio-bank0" },
Heiko Stübner65fca612013-10-16 01:07:49 +02002240 {},
2241};
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002242
2243static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2244 struct device_node *np)
2245{
2246 struct device_node *child;
2247
2248 for_each_child_of_node(np, child) {
Heiko Stübner65fca612013-10-16 01:07:49 +02002249 if (of_match_node(rockchip_bank_match, child))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002250 continue;
2251
2252 info->nfunctions++;
2253 info->ngroups += of_get_child_count(child);
2254 }
2255}
2256
2257static int rockchip_pinctrl_parse_groups(struct device_node *np,
2258 struct rockchip_pin_group *grp,
2259 struct rockchip_pinctrl *info,
2260 u32 index)
2261{
2262 struct rockchip_pin_bank *bank;
2263 int size;
2264 const __be32 *list;
2265 int num;
2266 int i, j;
2267 int ret;
2268
2269 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2270
2271 /* Initialise group */
2272 grp->name = np->name;
2273
2274 /*
2275 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2276 * do sanity check and calculate pins number
2277 */
2278 list = of_get_property(np, "rockchip,pins", &size);
2279 /* we do not check return since it's safe node passed down */
2280 size /= sizeof(*list);
2281 if (!size || size % 4) {
2282 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2283 return -EINVAL;
2284 }
2285
2286 grp->npins = size / 4;
2287
2288 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2289 GFP_KERNEL);
2290 grp->data = devm_kzalloc(info->dev, grp->npins *
2291 sizeof(struct rockchip_pin_config),
2292 GFP_KERNEL);
2293 if (!grp->pins || !grp->data)
2294 return -ENOMEM;
2295
2296 for (i = 0, j = 0; i < size; i += 4, j++) {
2297 const __be32 *phandle;
2298 struct device_node *np_config;
2299
2300 num = be32_to_cpu(*list++);
2301 bank = bank_num_to_bank(info, num);
2302 if (IS_ERR(bank))
2303 return PTR_ERR(bank);
2304
2305 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2306 grp->data[j].func = be32_to_cpu(*list++);
2307
2308 phandle = list++;
2309 if (!phandle)
2310 return -EINVAL;
2311
2312 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
Soren Brinkmanndd4d01f2015-01-09 07:43:46 -08002313 ret = pinconf_generic_parse_dt_config(np_config, NULL,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002314 &grp->data[j].configs, &grp->data[j].nconfigs);
2315 if (ret)
2316 return ret;
2317 }
2318
2319 return 0;
2320}
2321
2322static int rockchip_pinctrl_parse_functions(struct device_node *np,
2323 struct rockchip_pinctrl *info,
2324 u32 index)
2325{
2326 struct device_node *child;
2327 struct rockchip_pmx_func *func;
2328 struct rockchip_pin_group *grp;
2329 int ret;
2330 static u32 grp_index;
2331 u32 i = 0;
2332
2333 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2334
2335 func = &info->functions[index];
2336
2337 /* Initialise function */
2338 func->name = np->name;
2339 func->ngroups = of_get_child_count(np);
2340 if (func->ngroups <= 0)
2341 return 0;
2342
2343 func->groups = devm_kzalloc(info->dev,
2344 func->ngroups * sizeof(char *), GFP_KERNEL);
2345 if (!func->groups)
2346 return -ENOMEM;
2347
2348 for_each_child_of_node(np, child) {
2349 func->groups[i] = child->name;
2350 grp = &info->groups[grp_index++];
2351 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
Julia Lawallf7a81b72015-12-21 17:39:47 +01002352 if (ret) {
2353 of_node_put(child);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002354 return ret;
Julia Lawallf7a81b72015-12-21 17:39:47 +01002355 }
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002356 }
2357
2358 return 0;
2359}
2360
2361static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2362 struct rockchip_pinctrl *info)
2363{
2364 struct device *dev = &pdev->dev;
2365 struct device_node *np = dev->of_node;
2366 struct device_node *child;
2367 int ret;
2368 int i;
2369
2370 rockchip_pinctrl_child_count(info, np);
2371
2372 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2373 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2374
2375 info->functions = devm_kzalloc(dev, info->nfunctions *
2376 sizeof(struct rockchip_pmx_func),
2377 GFP_KERNEL);
2378 if (!info->functions) {
2379 dev_err(dev, "failed to allocate memory for function list\n");
2380 return -EINVAL;
2381 }
2382
2383 info->groups = devm_kzalloc(dev, info->ngroups *
2384 sizeof(struct rockchip_pin_group),
2385 GFP_KERNEL);
2386 if (!info->groups) {
2387 dev_err(dev, "failed allocate memory for ping group list\n");
2388 return -EINVAL;
2389 }
2390
2391 i = 0;
2392
2393 for_each_child_of_node(np, child) {
Heiko Stübner65fca612013-10-16 01:07:49 +02002394 if (of_match_node(rockchip_bank_match, child))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002395 continue;
Heiko Stübner65fca612013-10-16 01:07:49 +02002396
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002397 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2398 if (ret) {
2399 dev_err(&pdev->dev, "failed to parse function\n");
Julia Lawallf7a81b72015-12-21 17:39:47 +01002400 of_node_put(child);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002401 return ret;
2402 }
2403 }
2404
2405 return 0;
2406}
2407
2408static int rockchip_pinctrl_register(struct platform_device *pdev,
2409 struct rockchip_pinctrl *info)
2410{
2411 struct pinctrl_desc *ctrldesc = &info->pctl;
2412 struct pinctrl_pin_desc *pindesc, *pdesc;
2413 struct rockchip_pin_bank *pin_bank;
2414 int pin, bank, ret;
2415 int k;
2416
2417 ctrldesc->name = "rockchip-pinctrl";
2418 ctrldesc->owner = THIS_MODULE;
2419 ctrldesc->pctlops = &rockchip_pctrl_ops;
2420 ctrldesc->pmxops = &rockchip_pmx_ops;
2421 ctrldesc->confops = &rockchip_pinconf_ops;
2422
2423 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2424 info->ctrl->nr_pins, GFP_KERNEL);
2425 if (!pindesc) {
2426 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2427 return -ENOMEM;
2428 }
2429 ctrldesc->pins = pindesc;
2430 ctrldesc->npins = info->ctrl->nr_pins;
2431
2432 pdesc = pindesc;
2433 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2434 pin_bank = &info->ctrl->pin_banks[bank];
2435 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2436 pdesc->number = k;
2437 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2438 pin_bank->name, pin);
2439 pdesc++;
2440 }
2441 }
2442
Doug Anderson0fb7dcb2014-10-21 10:47:34 -07002443 ret = rockchip_pinctrl_parse_dt(pdev, info);
2444 if (ret)
2445 return ret;
2446
Laxman Dewangan0085a2b2016-02-24 14:44:07 +05302447 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
Masahiro Yamada323de9e2015-06-09 13:01:16 +09002448 if (IS_ERR(info->pctl_dev)) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002449 dev_err(&pdev->dev, "could not register pinctrl driver\n");
Masahiro Yamada323de9e2015-06-09 13:01:16 +09002450 return PTR_ERR(info->pctl_dev);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002451 }
2452
2453 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2454 pin_bank = &info->ctrl->pin_banks[bank];
2455 pin_bank->grange.name = pin_bank->name;
2456 pin_bank->grange.id = bank;
2457 pin_bank->grange.pin_base = pin_bank->pin_base;
2458 pin_bank->grange.base = pin_bank->gpio_chip.base;
2459 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2460 pin_bank->grange.gc = &pin_bank->gpio_chip;
2461 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2462 }
2463
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002464 return 0;
2465}
2466
2467/*
2468 * GPIO handling
2469 */
2470
2471static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2472{
Linus Walleij03bf81f2015-12-08 09:39:13 +01002473 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002474 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2475 unsigned long flags;
2476 u32 data;
2477
Lin Huang07a06ae2015-08-11 18:12:04 +08002478 clk_enable(bank->clk);
John Keeping70b7aa72017-03-23 10:59:29 +00002479 raw_spin_lock_irqsave(&bank->slock, flags);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002480
2481 data = readl(reg);
2482 data &= ~BIT(offset);
2483 if (value)
2484 data |= BIT(offset);
2485 writel(data, reg);
2486
John Keeping70b7aa72017-03-23 10:59:29 +00002487 raw_spin_unlock_irqrestore(&bank->slock, flags);
Lin Huang07a06ae2015-08-11 18:12:04 +08002488 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002489}
2490
2491/*
2492 * Returns the level of the pin for input direction and setting of the DR
2493 * register for output gpios.
2494 */
2495static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2496{
Linus Walleij03bf81f2015-12-08 09:39:13 +01002497 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002498 u32 data;
2499
Lin Huang07a06ae2015-08-11 18:12:04 +08002500 clk_enable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002501 data = readl(bank->reg_base + GPIO_EXT_PORT);
Lin Huang07a06ae2015-08-11 18:12:04 +08002502 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002503 data >>= offset;
2504 data &= 1;
2505 return data;
2506}
2507
2508/*
2509 * gpiolib gpio_direction_input callback function. The setting of the pin
2510 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2511 * interface.
2512 */
2513static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2514{
2515 return pinctrl_gpio_direction_input(gc->base + offset);
2516}
2517
2518/*
2519 * gpiolib gpio_direction_output callback function. The setting of the pin
2520 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2521 * interface.
2522 */
2523static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2524 unsigned offset, int value)
2525{
2526 rockchip_gpio_set(gc, offset, value);
2527 return pinctrl_gpio_direction_output(gc->base + offset);
2528}
2529
2530/*
2531 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2532 * and a virtual IRQ, if not already present.
2533 */
2534static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2535{
Linus Walleij03bf81f2015-12-08 09:39:13 +01002536 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002537 unsigned int virq;
2538
2539 if (!bank->domain)
2540 return -ENXIO;
2541
2542 virq = irq_create_mapping(bank->domain, offset);
2543
2544 return (virq) ? : -ENXIO;
2545}
2546
2547static const struct gpio_chip rockchip_gpiolib_chip = {
Jonas Gorski98c85d52015-10-11 17:34:19 +02002548 .request = gpiochip_generic_request,
2549 .free = gpiochip_generic_free,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002550 .set = rockchip_gpio_set,
2551 .get = rockchip_gpio_get,
Caesar Wang6ba20a02016-03-15 15:55:45 +08002552 .get_direction = rockchip_gpio_get_direction,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002553 .direction_input = rockchip_gpio_direction_input,
2554 .direction_output = rockchip_gpio_direction_output,
2555 .to_irq = rockchip_gpio_to_irq,
2556 .owner = THIS_MODULE,
2557};
2558
2559/*
2560 * Interrupt handling
2561 */
2562
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +02002563static void rockchip_irq_demux(struct irq_desc *desc)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002564{
Jiang Liu5663bb22015-06-04 12:13:16 +08002565 struct irq_chip *chip = irq_desc_get_chip(desc);
2566 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002567 u32 pend;
2568
2569 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2570
2571 chained_irq_enter(chip, desc);
2572
2573 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2574
2575 while (pend) {
Thomas Gleixner415f7482015-07-13 01:52:00 +02002576 unsigned int irq, virq;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002577
2578 irq = __ffs(pend);
2579 pend &= ~BIT(irq);
2580 virq = irq_linear_revmap(bank->domain, irq);
2581
2582 if (!virq) {
2583 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2584 continue;
2585 }
2586
2587 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2588
Heiko Stübner5a927502013-10-16 01:09:08 +02002589 /*
2590 * Triggering IRQ on both rising and falling edge
2591 * needs manual intervention.
2592 */
2593 if (bank->toggle_edge_mode & BIT(irq)) {
Doug Anderson53b1bfc2014-12-22 10:47:29 -08002594 u32 data, data_old, polarity;
2595 unsigned long flags;
Heiko Stübner5a927502013-10-16 01:09:08 +02002596
Doug Anderson53b1bfc2014-12-22 10:47:29 -08002597 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2598 do {
John Keeping70b7aa72017-03-23 10:59:29 +00002599 raw_spin_lock_irqsave(&bank->slock, flags);
Doug Anderson53b1bfc2014-12-22 10:47:29 -08002600
2601 polarity = readl_relaxed(bank->reg_base +
2602 GPIO_INT_POLARITY);
2603 if (data & BIT(irq))
2604 polarity &= ~BIT(irq);
2605 else
2606 polarity |= BIT(irq);
2607 writel(polarity,
2608 bank->reg_base + GPIO_INT_POLARITY);
2609
John Keeping70b7aa72017-03-23 10:59:29 +00002610 raw_spin_unlock_irqrestore(&bank->slock, flags);
Doug Anderson53b1bfc2014-12-22 10:47:29 -08002611
2612 data_old = data;
2613 data = readl_relaxed(bank->reg_base +
2614 GPIO_EXT_PORT);
2615 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
Heiko Stübner5a927502013-10-16 01:09:08 +02002616 }
2617
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002618 generic_handle_irq(virq);
2619 }
2620
2621 chained_irq_exit(chip, desc);
2622}
2623
2624static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2625{
2626 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2627 struct rockchip_pin_bank *bank = gc->private;
2628 u32 mask = BIT(d->hwirq);
2629 u32 polarity;
2630 u32 level;
2631 u32 data;
Doug Andersonfab262f2014-10-21 10:47:35 -07002632 unsigned long flags;
Heiko Stübner14797182014-03-26 00:57:00 +01002633 int ret;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002634
Heiko Stübner5a927502013-10-16 01:09:08 +02002635 /* make sure the pin is configured as gpio input */
Brian Norris1d80df92017-06-23 13:59:11 -07002636 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
Heiko Stübner14797182014-03-26 00:57:00 +01002637 if (ret < 0)
2638 return ret;
2639
Brian Norris1d80df92017-06-23 13:59:11 -07002640 clk_enable(bank->clk);
John Keeping70b7aa72017-03-23 10:59:29 +00002641 raw_spin_lock_irqsave(&bank->slock, flags);
Doug Andersonfab262f2014-10-21 10:47:35 -07002642
Heiko Stübner5a927502013-10-16 01:09:08 +02002643 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2644 data &= ~mask;
2645 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2646
John Keeping70b7aa72017-03-23 10:59:29 +00002647 raw_spin_unlock_irqrestore(&bank->slock, flags);
Doug Andersonfab262f2014-10-21 10:47:35 -07002648
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002649 if (type & IRQ_TYPE_EDGE_BOTH)
Thomas Gleixner2dbf1bc2015-06-23 15:52:50 +02002650 irq_set_handler_locked(d, handle_edge_irq);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002651 else
Thomas Gleixner2dbf1bc2015-06-23 15:52:50 +02002652 irq_set_handler_locked(d, handle_level_irq);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002653
John Keeping70b7aa72017-03-23 10:59:29 +00002654 raw_spin_lock_irqsave(&bank->slock, flags);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002655 irq_gc_lock(gc);
2656
2657 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2658 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2659
2660 switch (type) {
Heiko Stübner5a927502013-10-16 01:09:08 +02002661 case IRQ_TYPE_EDGE_BOTH:
2662 bank->toggle_edge_mode |= mask;
2663 level |= mask;
2664
2665 /*
2666 * Determine gpio state. If 1 next interrupt should be falling
2667 * otherwise rising.
2668 */
2669 data = readl(bank->reg_base + GPIO_EXT_PORT);
2670 if (data & mask)
2671 polarity &= ~mask;
2672 else
2673 polarity |= mask;
2674 break;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002675 case IRQ_TYPE_EDGE_RISING:
Heiko Stübner5a927502013-10-16 01:09:08 +02002676 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002677 level |= mask;
2678 polarity |= mask;
2679 break;
2680 case IRQ_TYPE_EDGE_FALLING:
Heiko Stübner5a927502013-10-16 01:09:08 +02002681 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002682 level |= mask;
2683 polarity &= ~mask;
2684 break;
2685 case IRQ_TYPE_LEVEL_HIGH:
Heiko Stübner5a927502013-10-16 01:09:08 +02002686 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002687 level &= ~mask;
2688 polarity |= mask;
2689 break;
2690 case IRQ_TYPE_LEVEL_LOW:
Heiko Stübner5a927502013-10-16 01:09:08 +02002691 bank->toggle_edge_mode &= ~mask;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002692 level &= ~mask;
2693 polarity &= ~mask;
2694 break;
2695 default:
Axel Lin7cc5f972013-06-23 08:48:34 +08002696 irq_gc_unlock(gc);
John Keeping70b7aa72017-03-23 10:59:29 +00002697 raw_spin_unlock_irqrestore(&bank->slock, flags);
Brian Norris1d80df92017-06-23 13:59:11 -07002698 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002699 return -EINVAL;
2700 }
2701
2702 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2703 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2704
2705 irq_gc_unlock(gc);
John Keeping70b7aa72017-03-23 10:59:29 +00002706 raw_spin_unlock_irqrestore(&bank->slock, flags);
Brian Norris1d80df92017-06-23 13:59:11 -07002707 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002708
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002709 return 0;
2710}
2711
Doug Anderson68bda472014-11-19 14:51:32 -08002712static void rockchip_irq_suspend(struct irq_data *d)
2713{
2714 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2715 struct rockchip_pin_bank *bank = gc->private;
2716
Lin Huang07a06ae2015-08-11 18:12:04 +08002717 clk_enable(bank->clk);
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08002718 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2719 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
Lin Huang07a06ae2015-08-11 18:12:04 +08002720 clk_disable(bank->clk);
Doug Anderson68bda472014-11-19 14:51:32 -08002721}
2722
2723static void rockchip_irq_resume(struct irq_data *d)
2724{
2725 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2726 struct rockchip_pin_bank *bank = gc->private;
2727
Lin Huang07a06ae2015-08-11 18:12:04 +08002728 clk_enable(bank->clk);
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08002729 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
Lin Huang07a06ae2015-08-11 18:12:04 +08002730 clk_disable(bank->clk);
2731}
2732
Jeffy Chend4682892017-03-02 13:56:52 +08002733static void rockchip_irq_enable(struct irq_data *d)
Lin Huang07a06ae2015-08-11 18:12:04 +08002734{
2735 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2736 struct rockchip_pin_bank *bank = gc->private;
2737
2738 clk_enable(bank->clk);
2739 irq_gc_mask_clr_bit(d);
2740}
2741
Jeffy Chend4682892017-03-02 13:56:52 +08002742static void rockchip_irq_disable(struct irq_data *d)
Lin Huang07a06ae2015-08-11 18:12:04 +08002743{
2744 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2745 struct rockchip_pin_bank *bank = gc->private;
2746
2747 irq_gc_mask_set_bit(d);
2748 clk_disable(bank->clk);
Doug Andersonf2dd0282014-11-19 14:51:33 -08002749}
2750
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002751static int rockchip_interrupts_register(struct platform_device *pdev,
2752 struct rockchip_pinctrl *info)
2753{
2754 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2755 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2756 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2757 struct irq_chip_generic *gc;
2758 int ret;
Lin Huang07a06ae2015-08-11 18:12:04 +08002759 int i, j;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002760
2761 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2762 if (!bank->valid) {
2763 dev_warn(&pdev->dev, "bank %s is not valid\n",
2764 bank->name);
2765 continue;
2766 }
2767
Lin Huang07a06ae2015-08-11 18:12:04 +08002768 ret = clk_enable(bank->clk);
2769 if (ret) {
2770 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2771 bank->name);
2772 continue;
2773 }
2774
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002775 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2776 &irq_generic_chip_ops, NULL);
2777 if (!bank->domain) {
2778 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2779 bank->name);
Lin Huang07a06ae2015-08-11 18:12:04 +08002780 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002781 continue;
2782 }
2783
2784 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2785 "rockchip_gpio_irq", handle_level_irq,
2786 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2787 if (ret) {
2788 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2789 bank->name);
2790 irq_domain_remove(bank->domain);
Lin Huang07a06ae2015-08-11 18:12:04 +08002791 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002792 continue;
2793 }
2794
Doug Anderson5ae0c7a2015-01-26 08:24:03 -08002795 /*
2796 * Linux assumes that all interrupts start out disabled/masked.
2797 * Our driver only uses the concept of masked and always keeps
2798 * things enabled, so for us that's all masked and all enabled.
2799 */
2800 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2801 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2802
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002803 gc = irq_get_domain_generic_chip(bank->domain, 0);
2804 gc->reg_base = bank->reg_base;
2805 gc->private = bank;
Doug Andersonf2dd0282014-11-19 14:51:33 -08002806 gc->chip_types[0].regs.mask = GPIO_INTMASK;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002807 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2808 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
Jeffy Chend4682892017-03-02 13:56:52 +08002809 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2810 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2811 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2812 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002813 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
Doug Anderson68bda472014-11-19 14:51:32 -08002814 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2815 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002816 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
Doug Anderson876d7162014-10-21 10:47:32 -07002817 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002818
Thomas Gleixner03051bc2015-06-21 21:11:06 +02002819 irq_set_chained_handler_and_data(bank->irq,
2820 rockchip_irq_demux, bank);
Lin Huang07a06ae2015-08-11 18:12:04 +08002821
2822 /* map the gpio irqs here, when the clock is still running */
2823 for (j = 0 ; j < 32 ; j++)
2824 irq_create_mapping(bank->domain, j);
2825
2826 clk_disable(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002827 }
2828
2829 return 0;
2830}
2831
2832static int rockchip_gpiolib_register(struct platform_device *pdev,
2833 struct rockchip_pinctrl *info)
2834{
2835 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2836 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2837 struct gpio_chip *gc;
2838 int ret;
2839 int i;
2840
2841 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2842 if (!bank->valid) {
2843 dev_warn(&pdev->dev, "bank %s is not valid\n",
2844 bank->name);
2845 continue;
2846 }
2847
2848 bank->gpio_chip = rockchip_gpiolib_chip;
2849
2850 gc = &bank->gpio_chip;
2851 gc->base = bank->pin_base;
2852 gc->ngpio = bank->nr_pins;
Linus Walleij58383c72015-11-04 09:56:26 +01002853 gc->parent = &pdev->dev;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002854 gc->of_node = bank->of_node;
2855 gc->label = bank->name;
2856
Linus Walleij03bf81f2015-12-08 09:39:13 +01002857 ret = gpiochip_add_data(gc, bank);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002858 if (ret) {
2859 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2860 gc->label, ret);
2861 goto fail;
2862 }
2863 }
2864
2865 rockchip_interrupts_register(pdev, info);
2866
2867 return 0;
2868
2869fail:
2870 for (--i, --bank; i >= 0; --i, --bank) {
2871 if (!bank->valid)
2872 continue;
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02002873 gpiochip_remove(&bank->gpio_chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002874 }
2875 return ret;
2876}
2877
2878static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2879 struct rockchip_pinctrl *info)
2880{
2881 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2882 struct rockchip_pin_bank *bank = ctrl->pin_banks;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002883 int i;
2884
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02002885 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002886 if (!bank->valid)
2887 continue;
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02002888 gpiochip_remove(&bank->gpio_chip);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002889 }
2890
abdoulaye bertheb4e7c552014-07-12 22:30:13 +02002891 return 0;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002892}
2893
2894static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
Heiko Stübner622f3232014-05-05 13:58:46 +02002895 struct rockchip_pinctrl *info)
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002896{
2897 struct resource res;
Heiko Stübner751a99a2014-05-05 13:58:20 +02002898 void __iomem *base;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002899
2900 if (of_address_to_resource(bank->of_node, 0, &res)) {
Heiko Stübner622f3232014-05-05 13:58:46 +02002901 dev_err(info->dev, "cannot find IO resource for bank\n");
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002902 return -ENOENT;
2903 }
2904
Heiko Stübner622f3232014-05-05 13:58:46 +02002905 bank->reg_base = devm_ioremap_resource(info->dev, &res);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002906 if (IS_ERR(bank->reg_base))
2907 return PTR_ERR(bank->reg_base);
2908
Heiko Stübner6ca52742013-10-16 01:08:42 +02002909 /*
2910 * special case, where parts of the pull setting-registers are
2911 * part of the PMU register space
2912 */
2913 if (of_device_is_compatible(bank->of_node,
2914 "rockchip,rk3188-gpio-bank0")) {
Heiko Stübnera658efa2014-05-05 13:59:30 +02002915 struct device_node *node;
Heiko Stübnerbfc7a422014-05-05 13:58:00 +02002916
Heiko Stübnera658efa2014-05-05 13:59:30 +02002917 node = of_parse_phandle(bank->of_node->parent,
2918 "rockchip,pmu", 0);
2919 if (!node) {
2920 if (of_address_to_resource(bank->of_node, 1, &res)) {
2921 dev_err(info->dev, "cannot find IO resource for bank\n");
2922 return -ENOENT;
2923 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02002924
Heiko Stübnera658efa2014-05-05 13:59:30 +02002925 base = devm_ioremap_resource(info->dev, &res);
2926 if (IS_ERR(base))
2927 return PTR_ERR(base);
2928 rockchip_regmap_config.max_register =
2929 resource_size(&res) - 4;
2930 rockchip_regmap_config.name =
2931 "rockchip,rk3188-gpio-bank0-pull";
2932 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2933 base,
2934 &rockchip_regmap_config);
2935 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02002936 }
Heiko Stübner65fca612013-10-16 01:07:49 +02002937
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002938 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2939
2940 bank->clk = of_clk_get(bank->of_node, 0);
2941 if (IS_ERR(bank->clk))
2942 return PTR_ERR(bank->clk);
2943
Lin Huang07a06ae2015-08-11 18:12:04 +08002944 return clk_prepare(bank->clk);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002945}
2946
2947static const struct of_device_id rockchip_pinctrl_dt_match[];
2948
2949/* retrieve the soc specific data */
2950static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2951 struct rockchip_pinctrl *d,
2952 struct platform_device *pdev)
2953{
2954 const struct of_device_id *match;
2955 struct device_node *node = pdev->dev.of_node;
2956 struct device_node *np;
2957 struct rockchip_pin_ctrl *ctrl;
2958 struct rockchip_pin_bank *bank;
David Wub6c23272016-02-01 10:58:21 +08002959 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002960
2961 match = of_match_node(rockchip_pinctrl_dt_match, node);
2962 ctrl = (struct rockchip_pin_ctrl *)match->data;
2963
2964 for_each_child_of_node(node, np) {
2965 if (!of_find_property(np, "gpio-controller", NULL))
2966 continue;
2967
2968 bank = ctrl->pin_banks;
2969 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2970 if (!strcmp(bank->name, np->name)) {
2971 bank->of_node = np;
2972
Heiko Stübner622f3232014-05-05 13:58:46 +02002973 if (!rockchip_get_bank_data(bank, d))
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002974 bank->valid = true;
2975
2976 break;
2977 }
2978 }
2979 }
2980
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02002981 grf_offs = ctrl->grf_mux_offset;
2982 pmu_offs = ctrl->pmu_mux_offset;
David Wub6c23272016-02-01 10:58:21 +08002983 drv_pmu_offs = ctrl->pmu_drv_offset;
2984 drv_grf_offs = ctrl->grf_drv_offset;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002985 bank = ctrl->pin_banks;
2986 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02002987 int bank_pins = 0;
2988
John Keeping70b7aa72017-03-23 10:59:29 +00002989 raw_spin_lock_init(&bank->slock);
Heiko Stübnerd3e51162013-06-10 22:16:22 +02002990 bank->drvdata = d;
2991 bank->pin_base = ctrl->nr_pins;
2992 ctrl->nr_pins += bank->nr_pins;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02002993
David Wub6c23272016-02-01 10:58:21 +08002994 /* calculate iomux and drv offsets */
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02002995 for (j = 0; j < 4; j++) {
2996 struct rockchip_iomux *iom = &bank->iomux[j];
David Wub6c23272016-02-01 10:58:21 +08002997 struct rockchip_drv *drv = &bank->drv[j];
Heiko Stübner03716e12014-06-16 01:36:57 +02002998 int inc;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02002999
3000 if (bank_pins >= bank->nr_pins)
3001 break;
3002
David Wub6c23272016-02-01 10:58:21 +08003003 /* preset iomux offset value, set new start value */
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003004 if (iom->offset >= 0) {
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003005 if (iom->type & IOMUX_SOURCE_PMU)
3006 pmu_offs = iom->offset;
3007 else
3008 grf_offs = iom->offset;
David Wub6c23272016-02-01 10:58:21 +08003009 } else { /* set current iomux offset */
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003010 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3011 pmu_offs : grf_offs;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003012 }
3013
David Wub6c23272016-02-01 10:58:21 +08003014 /* preset drv offset value, set new start value */
3015 if (drv->offset >= 0) {
3016 if (iom->type & IOMUX_SOURCE_PMU)
3017 drv_pmu_offs = drv->offset;
3018 else
3019 drv_grf_offs = drv->offset;
3020 } else { /* set current drv offset */
3021 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
3022 drv_pmu_offs : drv_grf_offs;
3023 }
3024
3025 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
3026 i, j, iom->offset, drv->offset);
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003027
3028 /*
3029 * Increase offset according to iomux width.
Heiko Stübner03716e12014-06-16 01:36:57 +02003030 * 4bit iomux'es are spread over two registers.
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003031 */
david.wu8b6c6f92017-02-10 18:23:47 +08003032 inc = (iom->type & (IOMUX_WIDTH_4BIT |
3033 IOMUX_WIDTH_3BIT)) ? 8 : 4;
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003034 if (iom->type & IOMUX_SOURCE_PMU)
3035 pmu_offs += inc;
3036 else
3037 grf_offs += inc;
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003038
David Wub6c23272016-02-01 10:58:21 +08003039 /*
3040 * Increase offset according to drv width.
3041 * 3bit drive-strenth'es are spread over two registers.
3042 */
3043 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
3044 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
3045 inc = 8;
3046 else
3047 inc = 4;
3048
3049 if (iom->type & IOMUX_SOURCE_PMU)
3050 drv_pmu_offs += inc;
3051 else
3052 drv_grf_offs += inc;
3053
Heiko Stübner6bc0d1212014-06-16 01:36:33 +02003054 bank_pins += 8;
3055 }
David Wubd35b9b2017-05-26 15:20:20 +08003056
David Wuc04c3fa2017-07-21 14:27:14 +08003057 /* calculate the per-bank recalced_mask */
3058 for (j = 0; j < ctrl->niomux_recalced; j++) {
3059 int pin = 0;
3060
3061 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
3062 pin = ctrl->iomux_recalced[j].pin;
3063 bank->recalced_mask |= BIT(pin);
3064 }
3065 }
3066
David Wubd35b9b2017-05-26 15:20:20 +08003067 /* calculate the per-bank route_mask */
3068 for (j = 0; j < ctrl->niomux_routes; j++) {
3069 int pin = 0;
3070
3071 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
3072 pin = ctrl->iomux_routes[j].pin;
3073 bank->route_mask |= BIT(pin);
3074 }
3075 }
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003076 }
3077
3078 return ctrl;
3079}
3080
Chris Zhong8dca9332014-10-29 19:52:00 +08003081#define RK3288_GRF_GPIO6C_IOMUX 0x64
3082#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
3083
3084static u32 rk3288_grf_gpio6c_iomux;
3085
Chris Zhong9198f502014-10-29 19:51:59 +08003086static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
3087{
3088 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
Chris Zhong8dca9332014-10-29 19:52:00 +08003089 int ret = pinctrl_force_sleep(info->pctl_dev);
Chris Zhong9198f502014-10-29 19:51:59 +08003090
Chris Zhong8dca9332014-10-29 19:52:00 +08003091 if (ret)
3092 return ret;
3093
3094 /*
3095 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3096 * the setting here, and restore it at resume.
3097 */
3098 if (info->ctrl->type == RK3288) {
3099 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3100 &rk3288_grf_gpio6c_iomux);
3101 if (ret) {
3102 pinctrl_force_default(info->pctl_dev);
3103 return ret;
3104 }
3105 }
3106
3107 return 0;
Chris Zhong9198f502014-10-29 19:51:59 +08003108}
3109
3110static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3111{
3112 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
Chris Zhong8dca9332014-10-29 19:52:00 +08003113 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3114 rk3288_grf_gpio6c_iomux |
3115 GPIO6C6_SEL_WRITE_ENABLE);
3116
3117 if (ret)
3118 return ret;
Chris Zhong9198f502014-10-29 19:51:59 +08003119
3120 return pinctrl_force_default(info->pctl_dev);
3121}
3122
3123static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3124 rockchip_pinctrl_resume);
3125
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003126static int rockchip_pinctrl_probe(struct platform_device *pdev)
3127{
3128 struct rockchip_pinctrl *info;
3129 struct device *dev = &pdev->dev;
3130 struct rockchip_pin_ctrl *ctrl;
Heiko Stübner14dee862014-05-05 13:59:09 +02003131 struct device_node *np = pdev->dev.of_node, *node;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003132 struct resource *res;
Heiko Stübner751a99a2014-05-05 13:58:20 +02003133 void __iomem *base;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003134 int ret;
3135
3136 if (!dev->of_node) {
3137 dev_err(dev, "device tree node not found\n");
3138 return -ENODEV;
3139 }
3140
3141 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3142 if (!info)
3143 return -ENOMEM;
3144
Heiko Stübner622f3232014-05-05 13:58:46 +02003145 info->dev = dev;
3146
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003147 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3148 if (!ctrl) {
3149 dev_err(dev, "driver data not available\n");
3150 return -EINVAL;
3151 }
3152 info->ctrl = ctrl;
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003153
Heiko Stübner1e747e52014-05-05 13:59:51 +02003154 node = of_parse_phandle(np, "rockchip,grf", 0);
3155 if (node) {
3156 info->regmap_base = syscon_node_to_regmap(node);
3157 if (IS_ERR(info->regmap_base))
3158 return PTR_ERR(info->regmap_base);
3159 } else {
3160 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Heiko Stübner751a99a2014-05-05 13:58:20 +02003161 base = devm_ioremap_resource(&pdev->dev, res);
3162 if (IS_ERR(base))
3163 return PTR_ERR(base);
3164
3165 rockchip_regmap_config.max_register = resource_size(res) - 4;
Heiko Stübner1e747e52014-05-05 13:59:51 +02003166 rockchip_regmap_config.name = "rockchip,pinctrl";
3167 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3168 &rockchip_regmap_config);
3169
3170 /* to check for the old dt-bindings */
3171 info->reg_size = resource_size(res);
3172
3173 /* Honor the old binding, with pull registers as 2nd resource */
3174 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3175 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3176 base = devm_ioremap_resource(&pdev->dev, res);
3177 if (IS_ERR(base))
3178 return PTR_ERR(base);
3179
3180 rockchip_regmap_config.max_register =
3181 resource_size(res) - 4;
3182 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3183 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3184 base,
3185 &rockchip_regmap_config);
3186 }
Heiko Stübner6ca52742013-10-16 01:08:42 +02003187 }
3188
Heiko Stübner14dee862014-05-05 13:59:09 +02003189 /* try to find the optional reference to the pmu syscon */
3190 node = of_parse_phandle(np, "rockchip,pmu", 0);
3191 if (node) {
3192 info->regmap_pmu = syscon_node_to_regmap(node);
3193 if (IS_ERR(info->regmap_pmu))
3194 return PTR_ERR(info->regmap_pmu);
3195 }
3196
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003197 ret = rockchip_gpiolib_register(pdev, info);
3198 if (ret)
3199 return ret;
3200
3201 ret = rockchip_pinctrl_register(pdev, info);
3202 if (ret) {
3203 rockchip_gpiolib_unregister(pdev, info);
3204 return ret;
3205 }
3206
3207 platform_set_drvdata(pdev, info);
3208
3209 return 0;
3210}
3211
Andy Yanb9c6dca2017-03-17 18:18:36 +01003212static struct rockchip_pin_bank rv1108_pin_banks[] = {
Andy Yan688daf22016-11-15 18:02:43 +08003213 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3214 IOMUX_SOURCE_PMU,
3215 IOMUX_SOURCE_PMU,
3216 IOMUX_SOURCE_PMU),
3217 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3218 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3219 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3220};
3221
Andy Yanb9c6dca2017-03-17 18:18:36 +01003222static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3223 .pin_banks = rv1108_pin_banks,
3224 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3225 .label = "RV1108-GPIO",
3226 .type = RV1108,
Andy Yan688daf22016-11-15 18:02:43 +08003227 .grf_mux_offset = 0x10,
3228 .pmu_mux_offset = 0x0,
David Wu12b8f012017-08-23 16:00:07 +08003229 .iomux_recalced = rv1108_mux_recalced_data,
3230 .niomux_recalced = ARRAY_SIZE(rv1108_mux_recalced_data),
Andy Yanb9c6dca2017-03-17 18:18:36 +01003231 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3232 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
Andy Yan5caff7e2017-07-31 18:10:22 +08003233 .schmitt_calc_reg = rv1108_calc_schmitt_reg_and_bit,
Andy Yan688daf22016-11-15 18:02:43 +08003234};
3235
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003236static struct rockchip_pin_bank rk2928_pin_banks[] = {
3237 PIN_BANK(0, 32, "gpio0"),
3238 PIN_BANK(1, 32, "gpio1"),
3239 PIN_BANK(2, 32, "gpio2"),
3240 PIN_BANK(3, 32, "gpio3"),
3241};
3242
3243static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3244 .pin_banks = rk2928_pin_banks,
3245 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3246 .label = "RK2928-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02003247 .type = RK2928,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003248 .grf_mux_offset = 0xa8,
Heiko Stübnera2829262013-10-16 01:07:20 +02003249 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003250};
3251
Xing Zhengc5ce7672015-08-28 13:46:47 +08003252static struct rockchip_pin_bank rk3036_pin_banks[] = {
3253 PIN_BANK(0, 32, "gpio0"),
3254 PIN_BANK(1, 32, "gpio1"),
3255 PIN_BANK(2, 32, "gpio2"),
3256};
3257
3258static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3259 .pin_banks = rk3036_pin_banks,
3260 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3261 .label = "RK3036-GPIO",
3262 .type = RK2928,
3263 .grf_mux_offset = 0xa8,
3264 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3265};
3266
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003267static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3268 PIN_BANK(0, 32, "gpio0"),
3269 PIN_BANK(1, 32, "gpio1"),
3270 PIN_BANK(2, 32, "gpio2"),
3271 PIN_BANK(3, 32, "gpio3"),
3272 PIN_BANK(4, 32, "gpio4"),
3273 PIN_BANK(6, 16, "gpio6"),
3274};
3275
3276static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3277 .pin_banks = rk3066a_pin_banks,
3278 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3279 .label = "RK3066a-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02003280 .type = RK2928,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003281 .grf_mux_offset = 0xa8,
Heiko Stübnera2829262013-10-16 01:07:20 +02003282 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003283};
3284
3285static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3286 PIN_BANK(0, 32, "gpio0"),
3287 PIN_BANK(1, 32, "gpio1"),
3288 PIN_BANK(2, 32, "gpio2"),
3289 PIN_BANK(3, 32, "gpio3"),
3290};
3291
3292static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3293 .pin_banks = rk3066b_pin_banks,
3294 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3295 .label = "RK3066b-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02003296 .type = RK3066B,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003297 .grf_mux_offset = 0x60,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003298};
3299
David Wud23c66d2017-07-21 14:27:15 +08003300static struct rockchip_pin_bank rk3128_pin_banks[] = {
3301 PIN_BANK(0, 32, "gpio0"),
3302 PIN_BANK(1, 32, "gpio1"),
3303 PIN_BANK(2, 32, "gpio2"),
3304 PIN_BANK(3, 32, "gpio3"),
3305};
3306
3307static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3308 .pin_banks = rk3128_pin_banks,
3309 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3310 .label = "RK3128-GPIO",
3311 .type = RK3128,
3312 .grf_mux_offset = 0xa8,
3313 .iomux_recalced = rk3128_mux_recalced_data,
3314 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3315 .iomux_routes = rk3128_mux_route_data,
3316 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3317 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3318};
3319
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003320static struct rockchip_pin_bank rk3188_pin_banks[] = {
Heiko Stübnerfc72c922014-06-16 01:36:05 +02003321 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003322 PIN_BANK(1, 32, "gpio1"),
3323 PIN_BANK(2, 32, "gpio2"),
3324 PIN_BANK(3, 32, "gpio3"),
3325};
3326
3327static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3328 .pin_banks = rk3188_pin_banks,
3329 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3330 .label = "RK3188-GPIO",
Heiko Stübnera2829262013-10-16 01:07:20 +02003331 .type = RK3188,
Heiko Stübner95ec8ae2014-06-16 01:37:23 +02003332 .grf_mux_offset = 0x60,
Heiko Stübner6ca52742013-10-16 01:08:42 +02003333 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003334};
3335
Jeffy Chenfea0fe62015-12-09 17:04:06 +08003336static struct rockchip_pin_bank rk3228_pin_banks[] = {
3337 PIN_BANK(0, 32, "gpio0"),
3338 PIN_BANK(1, 32, "gpio1"),
3339 PIN_BANK(2, 32, "gpio2"),
3340 PIN_BANK(3, 32, "gpio3"),
3341};
3342
3343static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3344 .pin_banks = rk3228_pin_banks,
3345 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3346 .label = "RK3228-GPIO",
3347 .type = RK3288,
3348 .grf_mux_offset = 0x0,
David Wud4970ee2017-05-26 15:20:21 +08003349 .iomux_routes = rk3228_mux_route_data,
3350 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
Jeffy Chenfea0fe62015-12-09 17:04:06 +08003351 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3352 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3353};
3354
Heiko Stübner304f0772014-06-16 01:38:14 +02003355static struct rockchip_pin_bank rk3288_pin_banks[] = {
3356 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3357 IOMUX_SOURCE_PMU,
3358 IOMUX_SOURCE_PMU,
3359 IOMUX_UNROUTED
3360 ),
3361 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3362 IOMUX_UNROUTED,
3363 IOMUX_UNROUTED,
3364 0
3365 ),
3366 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3367 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3368 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3369 IOMUX_WIDTH_4BIT,
3370 0,
3371 0
3372 ),
3373 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3374 0,
3375 0,
3376 IOMUX_UNROUTED
3377 ),
3378 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3379 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3380 0,
3381 IOMUX_WIDTH_4BIT,
3382 IOMUX_UNROUTED
3383 ),
3384 PIN_BANK(8, 16, "gpio8"),
3385};
3386
3387static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3388 .pin_banks = rk3288_pin_banks,
3389 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3390 .label = "RK3288-GPIO",
Heiko Stübner66d750e2014-07-20 01:49:17 +02003391 .type = RK3288,
Heiko Stübner304f0772014-06-16 01:38:14 +02003392 .grf_mux_offset = 0x0,
3393 .pmu_mux_offset = 0x84,
3394 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
Heiko Stübneref17f692015-06-12 23:50:11 +02003395 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
Heiko Stübner304f0772014-06-16 01:38:14 +02003396};
3397
david.wu3818e4a2017-02-10 18:23:49 +08003398static struct rockchip_pin_bank rk3328_pin_banks[] = {
3399 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3400 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3401 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
David Wuc04c3fa2017-07-21 14:27:14 +08003402 IOMUX_WIDTH_3BIT,
3403 IOMUX_WIDTH_3BIT,
david.wu3818e4a2017-02-10 18:23:49 +08003404 0),
3405 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3406 IOMUX_WIDTH_3BIT,
David Wuc04c3fa2017-07-21 14:27:14 +08003407 IOMUX_WIDTH_3BIT,
david.wu3818e4a2017-02-10 18:23:49 +08003408 0,
3409 0),
3410};
3411
3412static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3413 .pin_banks = rk3328_pin_banks,
3414 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3415 .label = "RK3328-GPIO",
3416 .type = RK3288,
3417 .grf_mux_offset = 0x0,
David Wuc04c3fa2017-07-21 14:27:14 +08003418 .iomux_recalced = rk3328_mux_recalced_data,
3419 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
David Wucedc9642017-05-26 15:20:22 +08003420 .iomux_routes = rk3328_mux_route_data,
3421 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
david.wu3818e4a2017-02-10 18:23:49 +08003422 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3423 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
david.wu728d3f52017-03-02 15:11:24 +08003424 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
david.wu3818e4a2017-02-10 18:23:49 +08003425};
3426
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02003427static struct rockchip_pin_bank rk3368_pin_banks[] = {
3428 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3429 IOMUX_SOURCE_PMU,
3430 IOMUX_SOURCE_PMU,
3431 IOMUX_SOURCE_PMU
3432 ),
3433 PIN_BANK(1, 32, "gpio1"),
3434 PIN_BANK(2, 32, "gpio2"),
3435 PIN_BANK(3, 32, "gpio3"),
3436};
3437
3438static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3439 .pin_banks = rk3368_pin_banks,
3440 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3441 .label = "RK3368-GPIO",
3442 .type = RK3368,
3443 .grf_mux_offset = 0x0,
3444 .pmu_mux_offset = 0x0,
3445 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3446 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3447};
3448
David Wub6c23272016-02-01 10:58:21 +08003449static struct rockchip_pin_bank rk3399_pin_banks[] = {
David Wu3ba67672016-05-11 11:39:28 +08003450 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3451 IOMUX_SOURCE_PMU,
3452 IOMUX_SOURCE_PMU,
3453 IOMUX_SOURCE_PMU,
3454 IOMUX_SOURCE_PMU,
3455 DRV_TYPE_IO_1V8_ONLY,
3456 DRV_TYPE_IO_1V8_ONLY,
3457 DRV_TYPE_IO_DEFAULT,
3458 DRV_TYPE_IO_DEFAULT,
3459 0x0,
3460 0x8,
3461 -1,
3462 -1,
3463 PULL_TYPE_IO_1V8_ONLY,
3464 PULL_TYPE_IO_1V8_ONLY,
3465 PULL_TYPE_IO_DEFAULT,
3466 PULL_TYPE_IO_DEFAULT
3467 ),
David Wub6c23272016-02-01 10:58:21 +08003468 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3469 IOMUX_SOURCE_PMU,
3470 IOMUX_SOURCE_PMU,
3471 IOMUX_SOURCE_PMU,
3472 DRV_TYPE_IO_1V8_OR_3V0,
3473 DRV_TYPE_IO_1V8_OR_3V0,
3474 DRV_TYPE_IO_1V8_OR_3V0,
3475 DRV_TYPE_IO_1V8_OR_3V0,
3476 0x20,
3477 0x28,
3478 0x30,
3479 0x38
3480 ),
David Wu3ba67672016-05-11 11:39:28 +08003481 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3482 DRV_TYPE_IO_1V8_OR_3V0,
3483 DRV_TYPE_IO_1V8_ONLY,
3484 DRV_TYPE_IO_1V8_ONLY,
3485 PULL_TYPE_IO_DEFAULT,
3486 PULL_TYPE_IO_DEFAULT,
3487 PULL_TYPE_IO_1V8_ONLY,
3488 PULL_TYPE_IO_1V8_ONLY
3489 ),
David Wub6c23272016-02-01 10:58:21 +08003490 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3491 DRV_TYPE_IO_3V3_ONLY,
3492 DRV_TYPE_IO_3V3_ONLY,
3493 DRV_TYPE_IO_1V8_OR_3V0
3494 ),
3495 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3496 DRV_TYPE_IO_1V8_3V0_AUTO,
3497 DRV_TYPE_IO_1V8_OR_3V0,
3498 DRV_TYPE_IO_1V8_OR_3V0
3499 ),
3500};
3501
3502static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3503 .pin_banks = rk3399_pin_banks,
3504 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3505 .label = "RK3399-GPIO",
3506 .type = RK3399,
3507 .grf_mux_offset = 0xe000,
3508 .pmu_mux_offset = 0x0,
3509 .grf_drv_offset = 0xe100,
3510 .pmu_drv_offset = 0x80,
David Wuaccc1ce2017-05-26 15:20:23 +08003511 .iomux_routes = rk3399_mux_route_data,
3512 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
David Wub6c23272016-02-01 10:58:21 +08003513 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3514 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3515};
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02003516
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003517static const struct of_device_id rockchip_pinctrl_dt_match[] = {
Andy Yanb9c6dca2017-03-17 18:18:36 +01003518 { .compatible = "rockchip,rv1108-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003519 .data = &rv1108_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003520 { .compatible = "rockchip,rk2928-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003521 .data = &rk2928_pin_ctrl },
Xing Zhengc5ce7672015-08-28 13:46:47 +08003522 { .compatible = "rockchip,rk3036-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003523 .data = &rk3036_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003524 { .compatible = "rockchip,rk3066a-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003525 .data = &rk3066a_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003526 { .compatible = "rockchip,rk3066b-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003527 .data = &rk3066b_pin_ctrl },
David Wud23c66d2017-07-21 14:27:15 +08003528 { .compatible = "rockchip,rk3128-pinctrl",
3529 .data = (void *)&rk3128_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003530 { .compatible = "rockchip,rk3188-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003531 .data = &rk3188_pin_ctrl },
Jeffy Chenfea0fe62015-12-09 17:04:06 +08003532 { .compatible = "rockchip,rk3228-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003533 .data = &rk3228_pin_ctrl },
Heiko Stübner304f0772014-06-16 01:38:14 +02003534 { .compatible = "rockchip,rk3288-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003535 .data = &rk3288_pin_ctrl },
david.wu3818e4a2017-02-10 18:23:49 +08003536 { .compatible = "rockchip,rk3328-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003537 .data = &rk3328_pin_ctrl },
Heiko Stübnerdaecdc62015-06-12 23:51:01 +02003538 { .compatible = "rockchip,rk3368-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003539 .data = &rk3368_pin_ctrl },
David Wub6c23272016-02-01 10:58:21 +08003540 { .compatible = "rockchip,rk3399-pinctrl",
Masahiro Yamadacdbbd262017-04-28 21:50:35 +09003541 .data = &rk3399_pin_ctrl },
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003542 {},
3543};
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003544
3545static struct platform_driver rockchip_pinctrl_driver = {
3546 .probe = rockchip_pinctrl_probe,
3547 .driver = {
3548 .name = "rockchip-pinctrl",
Chris Zhong9198f502014-10-29 19:51:59 +08003549 .pm = &rockchip_pinctrl_dev_pm_ops,
Axel Lin0be9e702013-08-23 14:27:53 +08003550 .of_match_table = rockchip_pinctrl_dt_match,
Heiko Stübnerd3e51162013-06-10 22:16:22 +02003551 },
3552};
3553
3554static int __init rockchip_pinctrl_drv_register(void)
3555{
3556 return platform_driver_register(&rockchip_pinctrl_driver);
3557}
3558postcore_initcall(rockchip_pinctrl_drv_register);