blob: 0fd6ba985b164b7752c26544e5d4b6d9684c88be [file] [log] [blame]
Ruud Derwig2924cd12014-12-03 15:52:41 +01001/*
2 * Copyright (C) 2013, 2014 Synopsys, Inc. (www.synopsys.com)
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * Device tree for AXC003 CPU card: HS38x UP configuration (VDK version)
11 */
12
Vineet Gupta2e8cd932016-01-19 16:00:42 +053013/include/ "skeleton_hs.dtsi"
14
Ruud Derwig2924cd12014-12-03 15:52:41 +010015/ {
16 compatible = "snps,arc";
Ruud Derwig2924cd12014-12-03 15:52:41 +010017 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpu_card {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
24
25 ranges = <0x00000000 0xf0000000 0x10000000>;
26
Vineet Guptab3d6aba2016-01-01 18:48:40 +053027 core_clk: core_clk {
28 #clock-cells = <0>;
29 compatible = "fixed-clock";
30 clock-frequency = <50000000>;
31 };
32
Vineet Gupta9ba76482016-01-28 09:57:12 +053033 core_intc: archs-intc@cpu {
Ruud Derwig2924cd12014-12-03 15:52:41 +010034 compatible = "snps,archs-intc";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 };
38
39 debug_uart: dw-apb-uart@0x5000 {
40 compatible = "snps,dw-apb-uart";
41 reg = <0x5000 0x100>;
42 clock-frequency = <2403200>;
Vineet Gupta9ba76482016-01-28 09:57:12 +053043 interrupt-parent = <&core_intc>;
Ruud Derwig2924cd12014-12-03 15:52:41 +010044 interrupts = <19>;
45 baud = <115200>;
46 reg-shift = <2>;
47 reg-io-width = <4>;
48 };
49
50 };
51
52 mb_intc: dw-apb-ictl@0xe0012000 {
53 #interrupt-cells = <1>;
54 compatible = "snps,dw-apb-ictl";
55 reg = < 0xe0012000 0x200 >;
56 interrupt-controller;
Vineet Gupta9ba76482016-01-28 09:57:12 +053057 interrupt-parent = <&core_intc>;
Ruud Derwig2924cd12014-12-03 15:52:41 +010058 interrupts = < 18 >;
59 };
60
61 memory {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 ranges = <0x00000000 0x80000000 0x40000000>;
65 device_type = "memory";
Vineet Guptaf759ee52015-01-23 18:10:26 +053066 reg = <0x80000000 0x20000000>; /* 512MiB */
Ruud Derwig2924cd12014-12-03 15:52:41 +010067 };
68};