Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1 | #include <linux/init.h> |
| 2 | #include <linux/kernel.h> |
| 3 | #include <linux/gpio.h> |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 4 | #include <cpu/sh7722.h> |
| 5 | |
Laurent Pinchart | c332380 | 2012-12-15 23:51:55 +0100 | [diff] [blame] | 6 | #include "sh_pfc.h" |
| 7 | |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 8 | enum { |
| 9 | PINMUX_RESERVED = 0, |
| 10 | |
| 11 | PINMUX_DATA_BEGIN, |
| 12 | PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, |
| 13 | PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA, |
| 14 | PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, |
| 15 | PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA, |
| 16 | PTC7_DATA, PTC5_DATA, PTC4_DATA, PTC3_DATA, PTC2_DATA, PTC0_DATA, |
| 17 | PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, |
| 18 | PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA, |
| 19 | PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, PTE1_DATA, PTE0_DATA, |
| 20 | PTF6_DATA, PTF5_DATA, PTF4_DATA, |
| 21 | PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA, |
| 22 | PTG4_DATA, PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA, |
| 23 | PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, |
| 24 | PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA, |
| 25 | PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ1_DATA, PTJ0_DATA, |
| 26 | PTK6_DATA, PTK5_DATA, PTK4_DATA, |
| 27 | PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA, |
| 28 | PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, |
| 29 | PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA, |
| 30 | PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, |
| 31 | PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA, |
| 32 | PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, |
| 33 | PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA, |
| 34 | PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, |
| 35 | PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA, |
| 36 | PTR4_DATA, PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA, |
| 37 | PTS4_DATA, PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA, |
| 38 | PTT4_DATA, PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA, |
| 39 | PTU4_DATA, PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA, |
| 40 | PTV4_DATA, PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA, |
| 41 | PTW6_DATA, PTW5_DATA, PTW4_DATA, |
| 42 | PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA, |
| 43 | PTX6_DATA, PTX5_DATA, PTX4_DATA, |
| 44 | PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA, |
| 45 | PTY6_DATA, PTY5_DATA, PTY4_DATA, |
| 46 | PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA, |
| 47 | PTZ5_DATA, PTZ4_DATA, PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA, |
| 48 | PINMUX_DATA_END, |
| 49 | |
| 50 | PINMUX_INPUT_BEGIN, |
| 51 | PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN, |
| 52 | PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN, |
| 53 | PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN, |
| 54 | PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN, |
| 55 | PTC7_IN, PTC5_IN, PTC4_IN, PTC3_IN, PTC2_IN, PTC0_IN, |
| 56 | PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN, PTD3_IN, PTD2_IN, PTD1_IN, |
| 57 | PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN, PTE1_IN, PTE0_IN, |
| 58 | PTF6_IN, PTF5_IN, PTF4_IN, PTF3_IN, PTF2_IN, PTF1_IN, |
| 59 | PTH6_IN, PTH5_IN, PTH1_IN, PTH0_IN, |
| 60 | PTJ1_IN, PTJ0_IN, |
| 61 | PTK6_IN, PTK5_IN, PTK4_IN, PTK3_IN, PTK2_IN, PTK0_IN, |
| 62 | PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN, |
| 63 | PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN, |
| 64 | PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN, |
| 65 | PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN, |
| 66 | PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN, |
| 67 | PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN, |
| 68 | PTQ5_IN, PTQ4_IN, PTQ3_IN, PTQ2_IN, PTQ0_IN, |
| 69 | PTR2_IN, |
| 70 | PTS4_IN, PTS2_IN, PTS1_IN, |
| 71 | PTT4_IN, PTT3_IN, PTT2_IN, PTT1_IN, |
| 72 | PTU4_IN, PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN, |
| 73 | PTV4_IN, PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN, |
| 74 | PTW6_IN, PTW4_IN, PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN, |
| 75 | PTX6_IN, PTX5_IN, PTX4_IN, PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN, |
| 76 | PTY5_IN, PTY4_IN, PTY3_IN, PTY2_IN, PTY0_IN, |
| 77 | PTZ5_IN, PTZ4_IN, PTZ3_IN, PTZ2_IN, PTZ1_IN, |
| 78 | PINMUX_INPUT_END, |
| 79 | |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 80 | PINMUX_OUTPUT_BEGIN, |
| 81 | PTA7_OUT, PTA5_OUT, |
| 82 | PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT, |
| 83 | PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT, |
| 84 | PTC4_OUT, PTC3_OUT, PTC2_OUT, PTC0_OUT, |
| 85 | PTD6_OUT, PTD5_OUT, PTD4_OUT, |
| 86 | PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT, |
| 87 | PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT, PTE1_OUT, PTE0_OUT, |
| 88 | PTF6_OUT, PTF5_OUT, PTF4_OUT, PTF3_OUT, PTF2_OUT, PTF0_OUT, |
| 89 | PTG4_OUT, PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT, |
| 90 | PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT, |
| 91 | PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT, |
| 92 | PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ1_OUT, PTJ0_OUT, |
| 93 | PTK6_OUT, PTK5_OUT, PTK4_OUT, PTK3_OUT, PTK1_OUT, PTK0_OUT, |
| 94 | PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT, |
| 95 | PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT, |
| 96 | PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT, |
| 97 | PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT, |
| 98 | PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT, |
| 99 | PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT, |
| 100 | PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT, |
| 101 | PTR4_OUT, PTR3_OUT, PTR1_OUT, PTR0_OUT, |
| 102 | PTS3_OUT, PTS2_OUT, PTS0_OUT, |
| 103 | PTT4_OUT, PTT3_OUT, PTT2_OUT, PTT0_OUT, |
| 104 | PTU4_OUT, PTU3_OUT, PTU2_OUT, PTU0_OUT, |
| 105 | PTV4_OUT, PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT, |
| 106 | PTW5_OUT, PTW4_OUT, PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT, |
| 107 | PTX6_OUT, PTX5_OUT, PTX4_OUT, PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT, |
| 108 | PTY5_OUT, PTY4_OUT, PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT, |
| 109 | PINMUX_OUTPUT_END, |
| 110 | |
| 111 | PINMUX_MARK_BEGIN, |
| 112 | SCIF0_TXD_MARK, SCIF0_RXD_MARK, |
| 113 | SCIF0_RTS_MARK, SCIF0_CTS_MARK, SCIF0_SCK_MARK, |
| 114 | SCIF1_TXD_MARK, SCIF1_RXD_MARK, |
| 115 | SCIF1_RTS_MARK, SCIF1_CTS_MARK, SCIF1_SCK_MARK, |
| 116 | SCIF2_TXD_MARK, SCIF2_RXD_MARK, |
| 117 | SCIF2_RTS_MARK, SCIF2_CTS_MARK, SCIF2_SCK_MARK, |
| 118 | SIOTXD_MARK, SIORXD_MARK, |
| 119 | SIOD_MARK, SIOSTRB0_MARK, SIOSTRB1_MARK, |
| 120 | SIOSCK_MARK, SIOMCK_MARK, |
| 121 | VIO_D15_MARK, VIO_D14_MARK, VIO_D13_MARK, VIO_D12_MARK, |
| 122 | VIO_D11_MARK, VIO_D10_MARK, VIO_D9_MARK, VIO_D8_MARK, |
| 123 | VIO_D7_MARK, VIO_D6_MARK, VIO_D5_MARK, VIO_D4_MARK, |
| 124 | VIO_D3_MARK, VIO_D2_MARK, VIO_D1_MARK, VIO_D0_MARK, |
| 125 | VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK, VIO_FLD_MARK, |
| 126 | VIO_CKO_MARK, VIO_STEX_MARK, VIO_STEM_MARK, VIO_VD2_MARK, |
| 127 | VIO_HD2_MARK, VIO_CLK2_MARK, |
| 128 | LCDD23_MARK, LCDD22_MARK, LCDD21_MARK, LCDD20_MARK, |
| 129 | LCDD19_MARK, LCDD18_MARK, LCDD17_MARK, LCDD16_MARK, |
| 130 | LCDD15_MARK, LCDD14_MARK, LCDD13_MARK, LCDD12_MARK, |
| 131 | LCDD11_MARK, LCDD10_MARK, LCDD9_MARK, LCDD8_MARK, |
| 132 | LCDD7_MARK, LCDD6_MARK, LCDD5_MARK, LCDD4_MARK, |
| 133 | LCDD3_MARK, LCDD2_MARK, LCDD1_MARK, LCDD0_MARK, |
| 134 | LCDLCLK_MARK, LCDDON_MARK, LCDVCPWC_MARK, LCDVEPWC_MARK, |
| 135 | LCDVSYN_MARK, LCDDCK_MARK, LCDHSYN_MARK, LCDDISP_MARK, |
| 136 | LCDRS_MARK, LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, |
| 137 | LCDDON2_MARK, LCDVCPWC2_MARK, LCDVEPWC2_MARK, LCDVSYN2_MARK, |
| 138 | LCDCS2_MARK, |
| 139 | IOIS16_MARK, A25_MARK, A24_MARK, A23_MARK, A22_MARK, |
| 140 | BS_MARK, CS6B_CE1B_MARK, WAIT_MARK, CS6A_CE2B_MARK, |
| 141 | HPD63_MARK, HPD62_MARK, HPD61_MARK, HPD60_MARK, |
| 142 | HPD59_MARK, HPD58_MARK, HPD57_MARK, HPD56_MARK, |
| 143 | HPD55_MARK, HPD54_MARK, HPD53_MARK, HPD52_MARK, |
| 144 | HPD51_MARK, HPD50_MARK, HPD49_MARK, HPD48_MARK, |
| 145 | HPDQM7_MARK, HPDQM6_MARK, HPDQM5_MARK, HPDQM4_MARK, |
| 146 | IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, |
| 147 | IRQ4_MARK, IRQ5_MARK, IRQ6_MARK, IRQ7_MARK, |
| 148 | SDHICD_MARK, SDHIWP_MARK, SDHID3_MARK, SDHID2_MARK, |
| 149 | SDHID1_MARK, SDHID0_MARK, SDHICMD_MARK, SDHICLK_MARK, |
| 150 | SIUAOLR_MARK, SIUAOBT_MARK, SIUAISLD_MARK, SIUAILR_MARK, |
| 151 | SIUAIBT_MARK, SIUAOSLD_MARK, SIUMCKA_MARK, SIUFCKA_MARK, |
| 152 | SIUBOLR_MARK, SIUBOBT_MARK, SIUBISLD_MARK, SIUBILR_MARK, |
| 153 | SIUBIBT_MARK, SIUBOSLD_MARK, SIUMCKB_MARK, SIUFCKB_MARK, |
| 154 | AUDSYNC_MARK, AUDATA3_MARK, AUDATA2_MARK, AUDATA1_MARK, AUDATA0_MARK, |
| 155 | DACK_MARK, DREQ0_MARK, |
| 156 | DV_CLKI_MARK, DV_CLK_MARK, DV_HSYNC_MARK, DV_VSYNC_MARK, |
| 157 | DV_D15_MARK, DV_D14_MARK, DV_D13_MARK, DV_D12_MARK, |
| 158 | DV_D11_MARK, DV_D10_MARK, DV_D9_MARK, DV_D8_MARK, |
| 159 | DV_D7_MARK, DV_D6_MARK, DV_D5_MARK, DV_D4_MARK, |
| 160 | DV_D3_MARK, DV_D2_MARK, DV_D1_MARK, DV_D0_MARK, |
| 161 | STATUS0_MARK, PDSTATUS_MARK, |
| 162 | SIOF0_MCK_MARK, SIOF0_SCK_MARK, |
| 163 | SIOF0_SYNC_MARK, SIOF0_SS1_MARK, SIOF0_SS2_MARK, |
| 164 | SIOF0_TXD_MARK, SIOF0_RXD_MARK, |
| 165 | SIOF1_MCK_MARK, SIOF1_SCK_MARK, |
| 166 | SIOF1_SYNC_MARK, SIOF1_SS1_MARK, SIOF1_SS2_MARK, |
| 167 | SIOF1_TXD_MARK, SIOF1_RXD_MARK, |
| 168 | SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK, |
| 169 | TS_SDAT_MARK, TS_SCK_MARK, TS_SDEN_MARK, TS_SPSYNC_MARK, |
| 170 | IRDA_IN_MARK, IRDA_OUT_MARK, |
| 171 | TPUTO_MARK, |
| 172 | FCE_MARK, NAF7_MARK, NAF6_MARK, NAF5_MARK, NAF4_MARK, |
| 173 | NAF3_MARK, NAF2_MARK, NAF1_MARK, NAF0_MARK, FCDE_MARK, |
| 174 | FOE_MARK, FSC_MARK, FWE_MARK, FRB_MARK, |
| 175 | KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK, KEYIN4_MARK, |
| 176 | KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, |
| 177 | KEYOUT4_IN6_MARK, KEYOUT5_IN5_MARK, |
| 178 | PINMUX_MARK_END, |
| 179 | |
| 180 | PINMUX_FUNCTION_BEGIN, |
| 181 | VIO_D7_SCIF1_SCK, VIO_D6_SCIF1_RXD, VIO_D5_SCIF1_TXD, VIO_D4, |
| 182 | VIO_D3, VIO_D2, VIO_D1, VIO_D0_LCDLCLK, |
| 183 | HPD55, HPD54, HPD53, HPD52, HPD51, HPD50, HPD49, HPD48, |
| 184 | IOIS16, HPDQM7, HPDQM6, HPDQM5, HPDQM4, |
| 185 | SDHICD, SDHIWP, SDHID3, IRQ2_SDHID2, SDHID1, SDHID0, SDHICMD, SDHICLK, |
| 186 | A25, A24, A23, A22, IRQ5, IRQ4_BS, |
| 187 | PTF6, SIOSCK_SIUBOBT, SIOSTRB1_SIUBOLR, |
| 188 | SIOSTRB0_SIUBIBT, SIOD_SIUBILR, SIORXD_SIUBISLD, SIOTXD_SIUBOSLD, |
| 189 | AUDSYNC, AUDATA3, AUDATA2, AUDATA1, AUDATA0, |
| 190 | LCDVCPWC_LCDVCPWC2, LCDVSYN2_DACK, LCDVSYN, LCDDISP_LCDRS, |
| 191 | LCDHSYN_LCDCS, LCDDON_LCDDON2, LCDD17_DV_HSYNC, LCDD16_DV_VSYNC, |
| 192 | STATUS0, PDSTATUS, IRQ1, IRQ0, |
| 193 | SIUAILR_SIOF1_SS2, SIUAIBT_SIOF1_SS1, SIUAOLR_SIOF1_SYNC, |
| 194 | SIUAOBT_SIOF1_SCK, SIUAISLD_SIOF1_RXD, SIUAOSLD_SIOF1_TXD, PTK0, |
| 195 | LCDD15_DV_D15, LCDD14_DV_D14, LCDD13_DV_D13, LCDD12_DV_D12, |
| 196 | LCDD11_DV_D11, LCDD10_DV_D10, LCDD9_DV_D9, LCDD8_DV_D8, |
| 197 | LCDD7_DV_D7, LCDD6_DV_D6, LCDD5_DV_D5, LCDD4_DV_D4, |
| 198 | LCDD3_DV_D3, LCDD2_DV_D2, LCDD1_DV_D1, LCDD0_DV_D0, |
| 199 | HPD63, HPD62, HPD61, HPD60, HPD59, HPD58, HPD57, HPD56, |
| 200 | SIOF0_SS2_SIM_RST, SIOF0_SS1_TS_SPSYNC, SIOF0_SYNC_TS_SDEN, |
| 201 | SIOF0_SCK_TS_SCK, PTQ2, PTQ1, PTQ0, |
| 202 | LCDRD, CS6B_CE1B_LCDCS2, WAIT, LCDDCK_LCDWR, LCDVEPWC_LCDVEPWC2, |
| 203 | SCIF0_CTS_SIUAISPD, SCIF0_RTS_SIUAOSPD, |
| 204 | SCIF0_SCK_TPUTO, SCIF0_RXD, SCIF0_TXD, |
| 205 | FOE_VIO_VD2, FWE, FSC, DREQ0, FCDE, |
| 206 | NAF2_VIO_D10, NAF1_VIO_D9, NAF0_VIO_D8, |
| 207 | FRB_VIO_CLK2, FCE_VIO_HD2, |
| 208 | NAF7_VIO_D15, NAF6_VIO_D14, NAF5_VIO_D13, NAF4_VIO_D12, NAF3_VIO_D11, |
| 209 | VIO_FLD_SCIF2_CTS, VIO_CKO_SCIF2_RTS, VIO_STEX_SCIF2_SCK, |
| 210 | VIO_STEM_SCIF2_TXD, VIO_HD_SCIF2_RXD, |
| 211 | VIO_VD_SCIF1_CTS, VIO_CLK_SCIF1_RTS, |
| 212 | CS6A_CE2B, LCDD23, LCDD22, LCDD21, LCDD20, |
| 213 | LCDD19_DV_CLKI, LCDD18_DV_CLK, |
| 214 | KEYOUT5_IN5, KEYOUT4_IN6, KEYOUT3, KEYOUT2, KEYOUT1, KEYOUT0, |
| 215 | KEYIN4_IRQ7, KEYIN3, KEYIN2, KEYIN1, KEYIN0_IRQ6, |
| 216 | |
| 217 | PSA15_KEYIN0, PSA15_IRQ6, PSA14_KEYIN4, PSA14_IRQ7, |
| 218 | PSA9_IRQ4, PSA9_BS, PSA4_IRQ2, PSA4_SDHID2, |
| 219 | PSB15_SIOTXD, PSB15_SIUBOSLD, PSB14_SIORXD, PSB14_SIUBISLD, |
| 220 | PSB13_SIOD, PSB13_SIUBILR, PSB12_SIOSTRB0, PSB12_SIUBIBT, |
| 221 | PSB11_SIOSTRB1, PSB11_SIUBOLR, PSB10_SIOSCK, PSB10_SIUBOBT, |
| 222 | PSB9_SIOMCK, PSB9_SIUMCKB, PSB8_SIOF0_MCK, PSB8_IRQ3, |
| 223 | PSB7_SIOF0_TXD, PSB7_IRDA_OUT, PSB6_SIOF0_RXD, PSB6_IRDA_IN, |
| 224 | PSB5_SIOF0_SCK, PSB5_TS_SCK, PSB4_SIOF0_SYNC, PSB4_TS_SDEN, |
| 225 | PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, PSB2_SIOF0_SS2, PSB2_SIM_RST, |
| 226 | PSB1_SIUMCKA, PSB1_SIOF1_MCK, PSB0_SIUAOSLD, PSB0_SIOF1_TXD, |
| 227 | PSC15_SIUAISLD, PSC15_SIOF1_RXD, PSC14_SIUAOBT, PSC14_SIOF1_SCK, |
| 228 | PSC13_SIUAOLR, PSC13_SIOF1_SYNC, PSC12_SIUAIBT, PSC12_SIOF1_SS1, |
| 229 | PSC11_SIUAILR, PSC11_SIOF1_SS2, PSC0_NAF, PSC0_VIO, |
| 230 | PSD13_VIO, PSD13_SCIF2, PSD12_VIO, PSD12_SCIF1, |
| 231 | PSD11_VIO, PSD11_SCIF1, PSD10_VIO_D0, PSD10_LCDLCLK, |
| 232 | PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, PSD8_SCIF0_SCK, PSD8_TPUTO, |
| 233 | PSD7_SCIF0_RTS, PSD7_SIUAOSPD, PSD6_SCIF0_CTS, PSD6_SIUAISPD, |
| 234 | PSD5_CS6B_CE1B, PSD5_LCDCS2, |
| 235 | PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, |
| 236 | PSD2_LCDDON, PSD2_LCDDON2, PSD0_LCDD19_LCDD0, PSD0_DV, |
| 237 | PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, |
| 238 | PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, |
| 239 | PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, PSE12_LCDVSYN2, PSE12_DACK, |
| 240 | PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, |
| 241 | PSE3_FLCTL, PSE3_VIO, PSE2_NAF2, PSE2_VIO_D10, |
| 242 | PSE1_NAF1, PSE1_VIO_D9, PSE0_NAF0, PSE0_VIO_D8, |
| 243 | |
| 244 | HIZA14_KEYSC, HIZA14_HIZ, |
| 245 | HIZA10_NAF, HIZA10_HIZ, |
| 246 | HIZA9_VIO, HIZA9_HIZ, |
| 247 | HIZA8_LCDC, HIZA8_HIZ, |
| 248 | HIZA7_LCDC, HIZA7_HIZ, |
| 249 | HIZA6_LCDC, HIZA6_HIZ, |
| 250 | HIZB4_SIUA, HIZB4_HIZ, |
| 251 | HIZB1_VIO, HIZB1_HIZ, |
| 252 | HIZB0_VIO, HIZB0_HIZ, |
| 253 | HIZC15_IRQ7, HIZC15_HIZ, |
| 254 | HIZC14_IRQ6, HIZC14_HIZ, |
| 255 | HIZC13_IRQ5, HIZC13_HIZ, |
| 256 | HIZC12_IRQ4, HIZC12_HIZ, |
| 257 | HIZC11_IRQ3, HIZC11_HIZ, |
| 258 | HIZC10_IRQ2, HIZC10_HIZ, |
| 259 | HIZC9_IRQ1, HIZC9_HIZ, |
| 260 | HIZC8_IRQ0, HIZC8_HIZ, |
| 261 | MSELB9_VIO, MSELB9_VIO2, |
| 262 | MSELB8_RGB, MSELB8_SYS, |
| 263 | PINMUX_FUNCTION_END, |
| 264 | }; |
| 265 | |
Laurent Pinchart | 533743d | 2013-07-15 13:03:20 +0200 | [diff] [blame] | 266 | static const u16 pinmux_data[] = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 267 | /* PTA */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 268 | PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), |
| 269 | PINMUX_DATA(PTA6_DATA, PTA6_IN), |
| 270 | PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT), |
| 271 | PINMUX_DATA(PTA4_DATA, PTA4_IN), |
| 272 | PINMUX_DATA(PTA3_DATA, PTA3_IN), |
| 273 | PINMUX_DATA(PTA2_DATA, PTA2_IN), |
| 274 | PINMUX_DATA(PTA1_DATA, PTA1_IN), |
| 275 | PINMUX_DATA(PTA0_DATA, PTA0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 276 | |
| 277 | /* PTB */ |
| 278 | PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT), |
| 279 | PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT), |
| 280 | PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT), |
| 281 | PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT), |
| 282 | PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT), |
| 283 | PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT), |
| 284 | PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT), |
| 285 | PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT), |
| 286 | |
| 287 | /* PTC */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 288 | PINMUX_DATA(PTC7_DATA, PTC7_IN), |
| 289 | PINMUX_DATA(PTC5_DATA, PTC5_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 290 | PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT), |
| 291 | PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT), |
| 292 | PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT), |
| 293 | PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT), |
| 294 | |
| 295 | /* PTD */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 296 | PINMUX_DATA(PTD7_DATA, PTD7_IN), |
| 297 | PINMUX_DATA(PTD6_DATA, PTD6_OUT, PTD6_IN), |
| 298 | PINMUX_DATA(PTD5_DATA, PTD5_OUT, PTD5_IN), |
| 299 | PINMUX_DATA(PTD4_DATA, PTD4_OUT, PTD4_IN), |
| 300 | PINMUX_DATA(PTD3_DATA, PTD3_OUT, PTD3_IN), |
| 301 | PINMUX_DATA(PTD2_DATA, PTD2_OUT, PTD2_IN), |
| 302 | PINMUX_DATA(PTD1_DATA, PTD1_OUT, PTD1_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 303 | PINMUX_DATA(PTD0_DATA, PTD0_OUT), |
| 304 | |
| 305 | /* PTE */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 306 | PINMUX_DATA(PTE7_DATA, PTE7_OUT, PTE7_IN), |
| 307 | PINMUX_DATA(PTE6_DATA, PTE6_OUT, PTE6_IN), |
| 308 | PINMUX_DATA(PTE5_DATA, PTE5_OUT, PTE5_IN), |
| 309 | PINMUX_DATA(PTE4_DATA, PTE4_OUT, PTE4_IN), |
| 310 | PINMUX_DATA(PTE1_DATA, PTE1_OUT, PTE1_IN), |
| 311 | PINMUX_DATA(PTE0_DATA, PTE0_OUT, PTE0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 312 | |
| 313 | /* PTF */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 314 | PINMUX_DATA(PTF6_DATA, PTF6_OUT, PTF6_IN), |
| 315 | PINMUX_DATA(PTF5_DATA, PTF5_OUT, PTF5_IN), |
| 316 | PINMUX_DATA(PTF4_DATA, PTF4_OUT, PTF4_IN), |
| 317 | PINMUX_DATA(PTF3_DATA, PTF3_OUT, PTF3_IN), |
| 318 | PINMUX_DATA(PTF2_DATA, PTF2_OUT, PTF2_IN), |
| 319 | PINMUX_DATA(PTF1_DATA, PTF1_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 320 | PINMUX_DATA(PTF0_DATA, PTF0_OUT), |
| 321 | |
| 322 | /* PTG */ |
| 323 | PINMUX_DATA(PTG4_DATA, PTG4_OUT), |
| 324 | PINMUX_DATA(PTG3_DATA, PTG3_OUT), |
| 325 | PINMUX_DATA(PTG2_DATA, PTG2_OUT), |
| 326 | PINMUX_DATA(PTG1_DATA, PTG1_OUT), |
| 327 | PINMUX_DATA(PTG0_DATA, PTG0_OUT), |
| 328 | |
| 329 | /* PTH */ |
| 330 | PINMUX_DATA(PTH7_DATA, PTH7_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 331 | PINMUX_DATA(PTH6_DATA, PTH6_OUT, PTH6_IN), |
| 332 | PINMUX_DATA(PTH5_DATA, PTH5_OUT, PTH5_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 333 | PINMUX_DATA(PTH4_DATA, PTH4_OUT), |
| 334 | PINMUX_DATA(PTH3_DATA, PTH3_OUT), |
| 335 | PINMUX_DATA(PTH2_DATA, PTH2_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 336 | PINMUX_DATA(PTH1_DATA, PTH1_OUT, PTH1_IN), |
| 337 | PINMUX_DATA(PTH0_DATA, PTH0_OUT, PTH0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 338 | |
| 339 | /* PTJ */ |
| 340 | PINMUX_DATA(PTJ7_DATA, PTJ7_OUT), |
| 341 | PINMUX_DATA(PTJ6_DATA, PTJ6_OUT), |
| 342 | PINMUX_DATA(PTJ5_DATA, PTJ5_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 343 | PINMUX_DATA(PTJ1_DATA, PTJ1_OUT, PTJ1_IN), |
| 344 | PINMUX_DATA(PTJ0_DATA, PTJ0_OUT, PTJ0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 345 | |
| 346 | /* PTK */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 347 | PINMUX_DATA(PTK6_DATA, PTK6_OUT, PTK6_IN), |
| 348 | PINMUX_DATA(PTK5_DATA, PTK5_OUT, PTK5_IN), |
| 349 | PINMUX_DATA(PTK4_DATA, PTK4_OUT, PTK4_IN), |
| 350 | PINMUX_DATA(PTK3_DATA, PTK3_OUT, PTK3_IN), |
| 351 | PINMUX_DATA(PTK2_DATA, PTK2_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 352 | PINMUX_DATA(PTK1_DATA, PTK1_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 353 | PINMUX_DATA(PTK0_DATA, PTK0_OUT, PTK0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 354 | |
| 355 | /* PTL */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 356 | PINMUX_DATA(PTL7_DATA, PTL7_OUT, PTL7_IN), |
| 357 | PINMUX_DATA(PTL6_DATA, PTL6_OUT, PTL6_IN), |
| 358 | PINMUX_DATA(PTL5_DATA, PTL5_OUT, PTL5_IN), |
| 359 | PINMUX_DATA(PTL4_DATA, PTL4_OUT, PTL4_IN), |
| 360 | PINMUX_DATA(PTL3_DATA, PTL3_OUT, PTL3_IN), |
| 361 | PINMUX_DATA(PTL2_DATA, PTL2_OUT, PTL2_IN), |
| 362 | PINMUX_DATA(PTL1_DATA, PTL1_OUT, PTL1_IN), |
| 363 | PINMUX_DATA(PTL0_DATA, PTL0_OUT, PTL0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 364 | |
| 365 | /* PTM */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 366 | PINMUX_DATA(PTM7_DATA, PTM7_OUT, PTM7_IN), |
| 367 | PINMUX_DATA(PTM6_DATA, PTM6_OUT, PTM6_IN), |
| 368 | PINMUX_DATA(PTM5_DATA, PTM5_OUT, PTM5_IN), |
| 369 | PINMUX_DATA(PTM4_DATA, PTM4_OUT, PTM4_IN), |
| 370 | PINMUX_DATA(PTM3_DATA, PTM3_OUT, PTM3_IN), |
| 371 | PINMUX_DATA(PTM2_DATA, PTM2_OUT, PTM2_IN), |
| 372 | PINMUX_DATA(PTM1_DATA, PTM1_OUT, PTM1_IN), |
| 373 | PINMUX_DATA(PTM0_DATA, PTM0_OUT, PTM0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 374 | |
| 375 | /* PTN */ |
| 376 | PINMUX_DATA(PTN7_DATA, PTN7_OUT, PTN7_IN), |
| 377 | PINMUX_DATA(PTN6_DATA, PTN6_OUT, PTN6_IN), |
| 378 | PINMUX_DATA(PTN5_DATA, PTN5_OUT, PTN5_IN), |
| 379 | PINMUX_DATA(PTN4_DATA, PTN4_OUT, PTN4_IN), |
| 380 | PINMUX_DATA(PTN3_DATA, PTN3_OUT, PTN3_IN), |
| 381 | PINMUX_DATA(PTN2_DATA, PTN2_OUT, PTN2_IN), |
| 382 | PINMUX_DATA(PTN1_DATA, PTN1_OUT, PTN1_IN), |
| 383 | PINMUX_DATA(PTN0_DATA, PTN0_OUT, PTN0_IN), |
| 384 | |
| 385 | /* PTQ */ |
| 386 | PINMUX_DATA(PTQ6_DATA, PTQ6_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 387 | PINMUX_DATA(PTQ5_DATA, PTQ5_OUT, PTQ5_IN), |
| 388 | PINMUX_DATA(PTQ4_DATA, PTQ4_OUT, PTQ4_IN), |
| 389 | PINMUX_DATA(PTQ3_DATA, PTQ3_OUT, PTQ3_IN), |
| 390 | PINMUX_DATA(PTQ2_DATA, PTQ2_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 391 | PINMUX_DATA(PTQ1_DATA, PTQ1_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 392 | PINMUX_DATA(PTQ0_DATA, PTQ0_OUT, PTQ0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 393 | |
| 394 | /* PTR */ |
| 395 | PINMUX_DATA(PTR4_DATA, PTR4_OUT), |
| 396 | PINMUX_DATA(PTR3_DATA, PTR3_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 397 | PINMUX_DATA(PTR2_DATA, PTR2_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 398 | PINMUX_DATA(PTR1_DATA, PTR1_OUT), |
| 399 | PINMUX_DATA(PTR0_DATA, PTR0_OUT), |
| 400 | |
| 401 | /* PTS */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 402 | PINMUX_DATA(PTS4_DATA, PTS4_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 403 | PINMUX_DATA(PTS3_DATA, PTS3_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 404 | PINMUX_DATA(PTS2_DATA, PTS2_OUT, PTS2_IN), |
| 405 | PINMUX_DATA(PTS1_DATA, PTS1_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 406 | PINMUX_DATA(PTS0_DATA, PTS0_OUT), |
| 407 | |
| 408 | /* PTT */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 409 | PINMUX_DATA(PTT4_DATA, PTT4_OUT, PTT4_IN), |
| 410 | PINMUX_DATA(PTT3_DATA, PTT3_OUT, PTT3_IN), |
| 411 | PINMUX_DATA(PTT2_DATA, PTT2_OUT, PTT2_IN), |
| 412 | PINMUX_DATA(PTT1_DATA, PTT1_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 413 | PINMUX_DATA(PTT0_DATA, PTT0_OUT), |
| 414 | |
| 415 | /* PTU */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 416 | PINMUX_DATA(PTU4_DATA, PTU4_OUT, PTU4_IN), |
| 417 | PINMUX_DATA(PTU3_DATA, PTU3_OUT, PTU3_IN), |
| 418 | PINMUX_DATA(PTU2_DATA, PTU2_OUT, PTU2_IN), |
| 419 | PINMUX_DATA(PTU1_DATA, PTU1_IN), |
| 420 | PINMUX_DATA(PTU0_DATA, PTU0_OUT, PTU0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 421 | |
| 422 | /* PTV */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 423 | PINMUX_DATA(PTV4_DATA, PTV4_OUT, PTV4_IN), |
| 424 | PINMUX_DATA(PTV3_DATA, PTV3_OUT, PTV3_IN), |
| 425 | PINMUX_DATA(PTV2_DATA, PTV2_OUT, PTV2_IN), |
| 426 | PINMUX_DATA(PTV1_DATA, PTV1_OUT, PTV1_IN), |
| 427 | PINMUX_DATA(PTV0_DATA, PTV0_OUT, PTV0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 428 | |
| 429 | /* PTW */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 430 | PINMUX_DATA(PTW6_DATA, PTW6_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 431 | PINMUX_DATA(PTW5_DATA, PTW5_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 432 | PINMUX_DATA(PTW4_DATA, PTW4_OUT, PTW4_IN), |
| 433 | PINMUX_DATA(PTW3_DATA, PTW3_OUT, PTW3_IN), |
| 434 | PINMUX_DATA(PTW2_DATA, PTW2_OUT, PTW2_IN), |
| 435 | PINMUX_DATA(PTW1_DATA, PTW1_OUT, PTW1_IN), |
| 436 | PINMUX_DATA(PTW0_DATA, PTW0_OUT, PTW0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 437 | |
| 438 | /* PTX */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 439 | PINMUX_DATA(PTX6_DATA, PTX6_OUT, PTX6_IN), |
| 440 | PINMUX_DATA(PTX5_DATA, PTX5_OUT, PTX5_IN), |
| 441 | PINMUX_DATA(PTX4_DATA, PTX4_OUT, PTX4_IN), |
| 442 | PINMUX_DATA(PTX3_DATA, PTX3_OUT, PTX3_IN), |
| 443 | PINMUX_DATA(PTX2_DATA, PTX2_OUT, PTX2_IN), |
| 444 | PINMUX_DATA(PTX1_DATA, PTX1_OUT, PTX1_IN), |
| 445 | PINMUX_DATA(PTX0_DATA, PTX0_OUT, PTX0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 446 | |
| 447 | /* PTY */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 448 | PINMUX_DATA(PTY5_DATA, PTY5_OUT, PTY5_IN), |
| 449 | PINMUX_DATA(PTY4_DATA, PTY4_OUT, PTY4_IN), |
| 450 | PINMUX_DATA(PTY3_DATA, PTY3_OUT, PTY3_IN), |
| 451 | PINMUX_DATA(PTY2_DATA, PTY2_OUT, PTY2_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 452 | PINMUX_DATA(PTY1_DATA, PTY1_OUT), |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 453 | PINMUX_DATA(PTY0_DATA, PTY0_OUT, PTY0_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 454 | |
| 455 | /* PTZ */ |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 456 | PINMUX_DATA(PTZ5_DATA, PTZ5_IN), |
| 457 | PINMUX_DATA(PTZ4_DATA, PTZ4_IN), |
| 458 | PINMUX_DATA(PTZ3_DATA, PTZ3_IN), |
| 459 | PINMUX_DATA(PTZ2_DATA, PTZ2_IN), |
| 460 | PINMUX_DATA(PTZ1_DATA, PTZ1_IN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 461 | |
| 462 | /* SCIF0 */ |
| 463 | PINMUX_DATA(SCIF0_TXD_MARK, SCIF0_TXD), |
| 464 | PINMUX_DATA(SCIF0_RXD_MARK, SCIF0_RXD), |
| 465 | PINMUX_DATA(SCIF0_RTS_MARK, PSD7_SCIF0_RTS, SCIF0_RTS_SIUAOSPD), |
| 466 | PINMUX_DATA(SCIF0_CTS_MARK, PSD6_SCIF0_CTS, SCIF0_CTS_SIUAISPD), |
| 467 | PINMUX_DATA(SCIF0_SCK_MARK, PSD8_SCIF0_SCK, SCIF0_SCK_TPUTO), |
| 468 | |
| 469 | /* SCIF1 */ |
| 470 | PINMUX_DATA(SCIF1_TXD_MARK, PSD11_SCIF1, VIO_D5_SCIF1_TXD), |
| 471 | PINMUX_DATA(SCIF1_RXD_MARK, PSD11_SCIF1, VIO_D6_SCIF1_RXD), |
| 472 | PINMUX_DATA(SCIF1_RTS_MARK, PSD12_SCIF1, VIO_CLK_SCIF1_RTS), |
| 473 | PINMUX_DATA(SCIF1_CTS_MARK, PSD12_SCIF1, VIO_VD_SCIF1_CTS), |
| 474 | PINMUX_DATA(SCIF1_SCK_MARK, PSD11_SCIF1, VIO_D7_SCIF1_SCK), |
| 475 | |
| 476 | /* SCIF2 */ |
| 477 | PINMUX_DATA(SCIF2_TXD_MARK, PSD13_SCIF2, VIO_STEM_SCIF2_TXD), |
| 478 | PINMUX_DATA(SCIF2_RXD_MARK, PSD13_SCIF2, VIO_HD_SCIF2_RXD), |
| 479 | PINMUX_DATA(SCIF2_RTS_MARK, PSD13_SCIF2, VIO_CKO_SCIF2_RTS), |
| 480 | PINMUX_DATA(SCIF2_CTS_MARK, PSD13_SCIF2, VIO_FLD_SCIF2_CTS), |
| 481 | PINMUX_DATA(SCIF2_SCK_MARK, PSD13_SCIF2, VIO_STEX_SCIF2_SCK), |
| 482 | |
| 483 | /* SIO */ |
| 484 | PINMUX_DATA(SIOTXD_MARK, PSB15_SIOTXD, SIOTXD_SIUBOSLD), |
| 485 | PINMUX_DATA(SIORXD_MARK, PSB14_SIORXD, SIORXD_SIUBISLD), |
| 486 | PINMUX_DATA(SIOD_MARK, PSB13_SIOD, SIOD_SIUBILR), |
| 487 | PINMUX_DATA(SIOSTRB0_MARK, PSB12_SIOSTRB0, SIOSTRB0_SIUBIBT), |
| 488 | PINMUX_DATA(SIOSTRB1_MARK, PSB11_SIOSTRB1, SIOSTRB1_SIUBOLR), |
| 489 | PINMUX_DATA(SIOSCK_MARK, PSB10_SIOSCK, SIOSCK_SIUBOBT), |
| 490 | PINMUX_DATA(SIOMCK_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIOMCK, PTF6), |
| 491 | |
| 492 | /* CEU */ |
| 493 | PINMUX_DATA(VIO_D15_MARK, PSC0_VIO, HIZA10_NAF, NAF7_VIO_D15), |
| 494 | PINMUX_DATA(VIO_D14_MARK, PSC0_VIO, HIZA10_NAF, NAF6_VIO_D14), |
| 495 | PINMUX_DATA(VIO_D13_MARK, PSC0_VIO, HIZA10_NAF, NAF5_VIO_D13), |
| 496 | PINMUX_DATA(VIO_D12_MARK, PSC0_VIO, HIZA10_NAF, NAF4_VIO_D12), |
| 497 | PINMUX_DATA(VIO_D11_MARK, PSC0_VIO, HIZA10_NAF, NAF3_VIO_D11), |
| 498 | PINMUX_DATA(VIO_D10_MARK, PSE2_VIO_D10, HIZB0_VIO, NAF2_VIO_D10), |
| 499 | PINMUX_DATA(VIO_D9_MARK, PSE1_VIO_D9, HIZB0_VIO, NAF1_VIO_D9), |
| 500 | PINMUX_DATA(VIO_D8_MARK, PSE0_VIO_D8, HIZB0_VIO, NAF0_VIO_D8), |
| 501 | PINMUX_DATA(VIO_D7_MARK, PSD11_VIO, VIO_D7_SCIF1_SCK), |
| 502 | PINMUX_DATA(VIO_D6_MARK, PSD11_VIO, VIO_D6_SCIF1_RXD), |
| 503 | PINMUX_DATA(VIO_D5_MARK, PSD11_VIO, VIO_D5_SCIF1_TXD), |
| 504 | PINMUX_DATA(VIO_D4_MARK, VIO_D4), |
| 505 | PINMUX_DATA(VIO_D3_MARK, VIO_D3), |
| 506 | PINMUX_DATA(VIO_D2_MARK, VIO_D2), |
| 507 | PINMUX_DATA(VIO_D1_MARK, VIO_D1), |
| 508 | PINMUX_DATA(VIO_D0_MARK, PSD10_VIO_D0, VIO_D0_LCDLCLK), |
| 509 | PINMUX_DATA(VIO_CLK_MARK, PSD12_VIO, MSELB9_VIO, VIO_CLK_SCIF1_RTS), |
| 510 | PINMUX_DATA(VIO_VD_MARK, PSD12_VIO, MSELB9_VIO, VIO_VD_SCIF1_CTS), |
| 511 | PINMUX_DATA(VIO_HD_MARK, PSD13_VIO, MSELB9_VIO, VIO_HD_SCIF2_RXD), |
| 512 | PINMUX_DATA(VIO_FLD_MARK, PSD13_VIO, HIZA9_VIO, VIO_FLD_SCIF2_CTS), |
| 513 | PINMUX_DATA(VIO_CKO_MARK, PSD13_VIO, HIZA9_VIO, VIO_CKO_SCIF2_RTS), |
| 514 | PINMUX_DATA(VIO_STEX_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEX_SCIF2_SCK), |
| 515 | PINMUX_DATA(VIO_STEM_MARK, PSD13_VIO, HIZA9_VIO, VIO_STEM_SCIF2_TXD), |
| 516 | PINMUX_DATA(VIO_VD2_MARK, PSE3_VIO, MSELB9_VIO2, |
| 517 | HIZB0_VIO, FOE_VIO_VD2), |
| 518 | PINMUX_DATA(VIO_HD2_MARK, PSE3_VIO, MSELB9_VIO2, |
| 519 | HIZB1_VIO, FCE_VIO_HD2), |
| 520 | PINMUX_DATA(VIO_CLK2_MARK, PSE3_VIO, MSELB9_VIO2, |
| 521 | HIZB1_VIO, FRB_VIO_CLK2), |
| 522 | |
| 523 | /* LCDC */ |
| 524 | PINMUX_DATA(LCDD23_MARK, HIZA8_LCDC, LCDD23), |
| 525 | PINMUX_DATA(LCDD22_MARK, HIZA8_LCDC, LCDD22), |
| 526 | PINMUX_DATA(LCDD21_MARK, HIZA8_LCDC, LCDD21), |
| 527 | PINMUX_DATA(LCDD20_MARK, HIZA8_LCDC, LCDD20), |
| 528 | PINMUX_DATA(LCDD19_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD19_DV_CLKI), |
| 529 | PINMUX_DATA(LCDD18_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD18_DV_CLK), |
| 530 | PINMUX_DATA(LCDD17_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, |
| 531 | LCDD17_DV_HSYNC), |
| 532 | PINMUX_DATA(LCDD16_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, |
| 533 | LCDD16_DV_VSYNC), |
| 534 | PINMUX_DATA(LCDD15_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD15_DV_D15), |
| 535 | PINMUX_DATA(LCDD14_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD14_DV_D14), |
| 536 | PINMUX_DATA(LCDD13_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD13_DV_D13), |
| 537 | PINMUX_DATA(LCDD12_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD12_DV_D12), |
| 538 | PINMUX_DATA(LCDD11_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD11_DV_D11), |
| 539 | PINMUX_DATA(LCDD10_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD10_DV_D10), |
| 540 | PINMUX_DATA(LCDD9_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD9_DV_D9), |
| 541 | PINMUX_DATA(LCDD8_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD8_DV_D8), |
| 542 | PINMUX_DATA(LCDD7_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD7_DV_D7), |
| 543 | PINMUX_DATA(LCDD6_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD6_DV_D6), |
| 544 | PINMUX_DATA(LCDD5_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD5_DV_D5), |
| 545 | PINMUX_DATA(LCDD4_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD4_DV_D4), |
| 546 | PINMUX_DATA(LCDD3_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD3_DV_D3), |
| 547 | PINMUX_DATA(LCDD2_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD2_DV_D2), |
| 548 | PINMUX_DATA(LCDD1_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD1_DV_D1), |
| 549 | PINMUX_DATA(LCDD0_MARK, PSD0_LCDD19_LCDD0, HIZA8_LCDC, LCDD0_DV_D0), |
| 550 | PINMUX_DATA(LCDLCLK_MARK, PSD10_LCDLCLK, VIO_D0_LCDLCLK), |
| 551 | /* Main LCD */ |
| 552 | PINMUX_DATA(LCDDON_MARK, PSD2_LCDDON, HIZA7_LCDC, LCDDON_LCDDON2), |
| 553 | PINMUX_DATA(LCDVCPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, |
| 554 | HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), |
| 555 | PINMUX_DATA(LCDVEPWC_MARK, PSD3_LCDVEPWC_LCDVCPWC, |
| 556 | HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), |
| 557 | PINMUX_DATA(LCDVSYN_MARK, HIZA7_LCDC, LCDVSYN), |
| 558 | /* Main LCD - RGB Mode */ |
| 559 | PINMUX_DATA(LCDDCK_MARK, MSELB8_RGB, HIZA8_LCDC, LCDDCK_LCDWR), |
| 560 | PINMUX_DATA(LCDHSYN_MARK, MSELB8_RGB, HIZA7_LCDC, LCDHSYN_LCDCS), |
| 561 | PINMUX_DATA(LCDDISP_MARK, MSELB8_RGB, HIZA7_LCDC, LCDDISP_LCDRS), |
| 562 | /* Main LCD - SYS Mode */ |
| 563 | PINMUX_DATA(LCDRS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDDISP_LCDRS), |
| 564 | PINMUX_DATA(LCDCS_MARK, MSELB8_SYS, HIZA7_LCDC, LCDHSYN_LCDCS), |
| 565 | PINMUX_DATA(LCDWR_MARK, MSELB8_SYS, HIZA8_LCDC, LCDDCK_LCDWR), |
| 566 | PINMUX_DATA(LCDRD_MARK, HIZA7_LCDC, LCDRD), |
| 567 | /* Sub LCD - SYS Mode */ |
| 568 | PINMUX_DATA(LCDDON2_MARK, PSD2_LCDDON2, HIZA7_LCDC, LCDDON_LCDDON2), |
| 569 | PINMUX_DATA(LCDVCPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, |
| 570 | HIZA6_LCDC, LCDVCPWC_LCDVCPWC2), |
| 571 | PINMUX_DATA(LCDVEPWC2_MARK, PSD3_LCDVEPWC2_LCDVCPWC2, |
| 572 | HIZA6_LCDC, LCDVEPWC_LCDVEPWC2), |
| 573 | PINMUX_DATA(LCDVSYN2_MARK, PSE12_LCDVSYN2, HIZA8_LCDC, LCDVSYN2_DACK), |
| 574 | PINMUX_DATA(LCDCS2_MARK, PSD5_LCDCS2, CS6B_CE1B_LCDCS2), |
| 575 | |
| 576 | /* BSC */ |
| 577 | PINMUX_DATA(IOIS16_MARK, IOIS16), |
| 578 | PINMUX_DATA(A25_MARK, A25), |
| 579 | PINMUX_DATA(A24_MARK, A24), |
| 580 | PINMUX_DATA(A23_MARK, A23), |
| 581 | PINMUX_DATA(A22_MARK, A22), |
| 582 | PINMUX_DATA(BS_MARK, PSA9_BS, IRQ4_BS), |
| 583 | PINMUX_DATA(CS6B_CE1B_MARK, PSD5_CS6B_CE1B, CS6B_CE1B_LCDCS2), |
| 584 | PINMUX_DATA(WAIT_MARK, WAIT), |
| 585 | PINMUX_DATA(CS6A_CE2B_MARK, CS6A_CE2B), |
| 586 | |
| 587 | /* SBSC */ |
| 588 | PINMUX_DATA(HPD63_MARK, HPD63), |
| 589 | PINMUX_DATA(HPD62_MARK, HPD62), |
| 590 | PINMUX_DATA(HPD61_MARK, HPD61), |
| 591 | PINMUX_DATA(HPD60_MARK, HPD60), |
| 592 | PINMUX_DATA(HPD59_MARK, HPD59), |
| 593 | PINMUX_DATA(HPD58_MARK, HPD58), |
| 594 | PINMUX_DATA(HPD57_MARK, HPD57), |
| 595 | PINMUX_DATA(HPD56_MARK, HPD56), |
| 596 | PINMUX_DATA(HPD55_MARK, HPD55), |
| 597 | PINMUX_DATA(HPD54_MARK, HPD54), |
| 598 | PINMUX_DATA(HPD53_MARK, HPD53), |
| 599 | PINMUX_DATA(HPD52_MARK, HPD52), |
| 600 | PINMUX_DATA(HPD51_MARK, HPD51), |
| 601 | PINMUX_DATA(HPD50_MARK, HPD50), |
| 602 | PINMUX_DATA(HPD49_MARK, HPD49), |
| 603 | PINMUX_DATA(HPD48_MARK, HPD48), |
| 604 | PINMUX_DATA(HPDQM7_MARK, HPDQM7), |
| 605 | PINMUX_DATA(HPDQM6_MARK, HPDQM6), |
| 606 | PINMUX_DATA(HPDQM5_MARK, HPDQM5), |
| 607 | PINMUX_DATA(HPDQM4_MARK, HPDQM4), |
| 608 | |
| 609 | /* IRQ */ |
| 610 | PINMUX_DATA(IRQ0_MARK, HIZC8_IRQ0, IRQ0), |
| 611 | PINMUX_DATA(IRQ1_MARK, HIZC9_IRQ1, IRQ1), |
| 612 | PINMUX_DATA(IRQ2_MARK, PSA4_IRQ2, HIZC10_IRQ2, IRQ2_SDHID2), |
| 613 | PINMUX_DATA(IRQ3_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_IRQ3, |
| 614 | HIZC11_IRQ3, PTQ0), |
| 615 | PINMUX_DATA(IRQ4_MARK, PSA9_IRQ4, HIZC12_IRQ4, IRQ4_BS), |
| 616 | PINMUX_DATA(IRQ5_MARK, HIZC13_IRQ5, IRQ5), |
| 617 | PINMUX_DATA(IRQ6_MARK, PSA15_IRQ6, HIZC14_IRQ6, KEYIN0_IRQ6), |
| 618 | PINMUX_DATA(IRQ7_MARK, PSA14_IRQ7, HIZC15_IRQ7, KEYIN4_IRQ7), |
| 619 | |
| 620 | /* SDHI */ |
| 621 | PINMUX_DATA(SDHICD_MARK, SDHICD), |
| 622 | PINMUX_DATA(SDHIWP_MARK, SDHIWP), |
| 623 | PINMUX_DATA(SDHID3_MARK, SDHID3), |
| 624 | PINMUX_DATA(SDHID2_MARK, PSA4_SDHID2, IRQ2_SDHID2), |
| 625 | PINMUX_DATA(SDHID1_MARK, SDHID1), |
| 626 | PINMUX_DATA(SDHID0_MARK, SDHID0), |
| 627 | PINMUX_DATA(SDHICMD_MARK, SDHICMD), |
| 628 | PINMUX_DATA(SDHICLK_MARK, SDHICLK), |
| 629 | |
| 630 | /* SIU - Port A */ |
| 631 | PINMUX_DATA(SIUAOLR_MARK, PSC13_SIUAOLR, HIZB4_SIUA, SIUAOLR_SIOF1_SYNC), |
| 632 | PINMUX_DATA(SIUAOBT_MARK, PSC14_SIUAOBT, HIZB4_SIUA, SIUAOBT_SIOF1_SCK), |
| 633 | PINMUX_DATA(SIUAISLD_MARK, PSC15_SIUAISLD, HIZB4_SIUA, SIUAISLD_SIOF1_RXD), |
| 634 | PINMUX_DATA(SIUAILR_MARK, PSC11_SIUAILR, HIZB4_SIUA, SIUAILR_SIOF1_SS2), |
| 635 | PINMUX_DATA(SIUAIBT_MARK, PSC12_SIUAIBT, HIZB4_SIUA, SIUAIBT_SIOF1_SS1), |
| 636 | PINMUX_DATA(SIUAOSLD_MARK, PSB0_SIUAOSLD, HIZB4_SIUA, SIUAOSLD_SIOF1_TXD), |
| 637 | PINMUX_DATA(SIUMCKA_MARK, PSE11_SIUMCKA_SIOF1_MCK, HIZB4_SIUA, PSB1_SIUMCKA, PTK0), |
| 638 | PINMUX_DATA(SIUFCKA_MARK, PSE11_SIUFCKA, HIZB4_SIUA, PTK0), |
| 639 | |
| 640 | /* SIU - Port B */ |
| 641 | PINMUX_DATA(SIUBOLR_MARK, PSB11_SIUBOLR, SIOSTRB1_SIUBOLR), |
| 642 | PINMUX_DATA(SIUBOBT_MARK, PSB10_SIUBOBT, SIOSCK_SIUBOBT), |
| 643 | PINMUX_DATA(SIUBISLD_MARK, PSB14_SIUBISLD, SIORXD_SIUBISLD), |
| 644 | PINMUX_DATA(SIUBILR_MARK, PSB13_SIUBILR, SIOD_SIUBILR), |
| 645 | PINMUX_DATA(SIUBIBT_MARK, PSB12_SIUBIBT, SIOSTRB0_SIUBIBT), |
| 646 | PINMUX_DATA(SIUBOSLD_MARK, PSB15_SIUBOSLD, SIOTXD_SIUBOSLD), |
| 647 | PINMUX_DATA(SIUMCKB_MARK, PSD9_SIOMCK_SIUMCKB, PSB9_SIUMCKB, PTF6), |
| 648 | PINMUX_DATA(SIUFCKB_MARK, PSD9_SIUFCKB, PTF6), |
| 649 | |
| 650 | /* AUD */ |
| 651 | PINMUX_DATA(AUDSYNC_MARK, AUDSYNC), |
| 652 | PINMUX_DATA(AUDATA3_MARK, AUDATA3), |
| 653 | PINMUX_DATA(AUDATA2_MARK, AUDATA2), |
| 654 | PINMUX_DATA(AUDATA1_MARK, AUDATA1), |
| 655 | PINMUX_DATA(AUDATA0_MARK, AUDATA0), |
| 656 | |
| 657 | /* DMAC */ |
| 658 | PINMUX_DATA(DACK_MARK, PSE12_DACK, LCDVSYN2_DACK), |
| 659 | PINMUX_DATA(DREQ0_MARK, DREQ0), |
| 660 | |
| 661 | /* VOU */ |
| 662 | PINMUX_DATA(DV_CLKI_MARK, PSD0_DV, LCDD19_DV_CLKI), |
| 663 | PINMUX_DATA(DV_CLK_MARK, PSD0_DV, LCDD18_DV_CLK), |
| 664 | PINMUX_DATA(DV_HSYNC_MARK, PSD0_DV, LCDD17_DV_HSYNC), |
| 665 | PINMUX_DATA(DV_VSYNC_MARK, PSD0_DV, LCDD16_DV_VSYNC), |
| 666 | PINMUX_DATA(DV_D15_MARK, PSD0_DV, LCDD15_DV_D15), |
| 667 | PINMUX_DATA(DV_D14_MARK, PSD0_DV, LCDD14_DV_D14), |
| 668 | PINMUX_DATA(DV_D13_MARK, PSD0_DV, LCDD13_DV_D13), |
| 669 | PINMUX_DATA(DV_D12_MARK, PSD0_DV, LCDD12_DV_D12), |
| 670 | PINMUX_DATA(DV_D11_MARK, PSD0_DV, LCDD11_DV_D11), |
| 671 | PINMUX_DATA(DV_D10_MARK, PSD0_DV, LCDD10_DV_D10), |
| 672 | PINMUX_DATA(DV_D9_MARK, PSD0_DV, LCDD9_DV_D9), |
| 673 | PINMUX_DATA(DV_D8_MARK, PSD0_DV, LCDD8_DV_D8), |
| 674 | PINMUX_DATA(DV_D7_MARK, PSD0_DV, LCDD7_DV_D7), |
| 675 | PINMUX_DATA(DV_D6_MARK, PSD0_DV, LCDD6_DV_D6), |
| 676 | PINMUX_DATA(DV_D5_MARK, PSD0_DV, LCDD5_DV_D5), |
| 677 | PINMUX_DATA(DV_D4_MARK, PSD0_DV, LCDD4_DV_D4), |
| 678 | PINMUX_DATA(DV_D3_MARK, PSD0_DV, LCDD3_DV_D3), |
| 679 | PINMUX_DATA(DV_D2_MARK, PSD0_DV, LCDD2_DV_D2), |
| 680 | PINMUX_DATA(DV_D1_MARK, PSD0_DV, LCDD1_DV_D1), |
| 681 | PINMUX_DATA(DV_D0_MARK, PSD0_DV, LCDD0_DV_D0), |
| 682 | |
| 683 | /* CPG */ |
| 684 | PINMUX_DATA(STATUS0_MARK, STATUS0), |
| 685 | PINMUX_DATA(PDSTATUS_MARK, PDSTATUS), |
| 686 | |
| 687 | /* SIOF0 */ |
| 688 | PINMUX_DATA(SIOF0_MCK_MARK, PSE15_SIOF0_MCK_IRQ3, PSB8_SIOF0_MCK, PTQ0), |
| 689 | PINMUX_DATA(SIOF0_SCK_MARK, PSB5_SIOF0_SCK, SIOF0_SCK_TS_SCK), |
| 690 | PINMUX_DATA(SIOF0_SYNC_MARK, PSB4_SIOF0_SYNC, SIOF0_SYNC_TS_SDEN), |
| 691 | PINMUX_DATA(SIOF0_SS1_MARK, PSB3_SIOF0_SS1, SIOF0_SS1_TS_SPSYNC), |
| 692 | PINMUX_DATA(SIOF0_SS2_MARK, PSB2_SIOF0_SS2, SIOF0_SS2_SIM_RST), |
| 693 | PINMUX_DATA(SIOF0_TXD_MARK, PSE14_SIOF0_TXD_IRDA_OUT, |
| 694 | PSB7_SIOF0_TXD, PTQ1), |
| 695 | PINMUX_DATA(SIOF0_RXD_MARK, PSE13_SIOF0_RXD_IRDA_IN, |
| 696 | PSB6_SIOF0_RXD, PTQ2), |
| 697 | |
| 698 | /* SIOF1 */ |
| 699 | PINMUX_DATA(SIOF1_MCK_MARK, PSE11_SIUMCKA_SIOF1_MCK, |
| 700 | PSB1_SIOF1_MCK, PTK0), |
| 701 | PINMUX_DATA(SIOF1_SCK_MARK, PSC14_SIOF1_SCK, SIUAOBT_SIOF1_SCK), |
| 702 | PINMUX_DATA(SIOF1_SYNC_MARK, PSC13_SIOF1_SYNC, SIUAOLR_SIOF1_SYNC), |
| 703 | PINMUX_DATA(SIOF1_SS1_MARK, PSC12_SIOF1_SS1, SIUAIBT_SIOF1_SS1), |
| 704 | PINMUX_DATA(SIOF1_SS2_MARK, PSC11_SIOF1_SS2, SIUAILR_SIOF1_SS2), |
| 705 | PINMUX_DATA(SIOF1_TXD_MARK, PSB0_SIOF1_TXD, SIUAOSLD_SIOF1_TXD), |
| 706 | PINMUX_DATA(SIOF1_RXD_MARK, PSC15_SIOF1_RXD, SIUAISLD_SIOF1_RXD), |
| 707 | |
| 708 | /* SIM */ |
| 709 | PINMUX_DATA(SIM_D_MARK, PSE15_SIM_D, PTQ0), |
| 710 | PINMUX_DATA(SIM_CLK_MARK, PSE14_SIM_CLK, PTQ1), |
| 711 | PINMUX_DATA(SIM_RST_MARK, PSB2_SIM_RST, SIOF0_SS2_SIM_RST), |
| 712 | |
| 713 | /* TSIF */ |
| 714 | PINMUX_DATA(TS_SDAT_MARK, PSE13_TS_SDAT, PTQ2), |
| 715 | PINMUX_DATA(TS_SCK_MARK, PSB5_TS_SCK, SIOF0_SCK_TS_SCK), |
| 716 | PINMUX_DATA(TS_SDEN_MARK, PSB4_TS_SDEN, SIOF0_SYNC_TS_SDEN), |
| 717 | PINMUX_DATA(TS_SPSYNC_MARK, PSB3_TS_SPSYNC, SIOF0_SS1_TS_SPSYNC), |
| 718 | |
| 719 | /* IRDA */ |
| 720 | PINMUX_DATA(IRDA_IN_MARK, PSE13_SIOF0_RXD_IRDA_IN, PSB6_IRDA_IN, PTQ2), |
| 721 | PINMUX_DATA(IRDA_OUT_MARK, PSE14_SIOF0_TXD_IRDA_OUT, |
| 722 | PSB7_IRDA_OUT, PTQ1), |
| 723 | |
| 724 | /* TPU */ |
| 725 | PINMUX_DATA(TPUTO_MARK, PSD8_TPUTO, SCIF0_SCK_TPUTO), |
| 726 | |
| 727 | /* FLCTL */ |
| 728 | PINMUX_DATA(FCE_MARK, PSE3_FLCTL, FCE_VIO_HD2), |
| 729 | PINMUX_DATA(NAF7_MARK, PSC0_NAF, HIZA10_NAF, NAF7_VIO_D15), |
| 730 | PINMUX_DATA(NAF6_MARK, PSC0_NAF, HIZA10_NAF, NAF6_VIO_D14), |
| 731 | PINMUX_DATA(NAF5_MARK, PSC0_NAF, HIZA10_NAF, NAF5_VIO_D13), |
| 732 | PINMUX_DATA(NAF4_MARK, PSC0_NAF, HIZA10_NAF, NAF4_VIO_D12), |
| 733 | PINMUX_DATA(NAF3_MARK, PSC0_NAF, HIZA10_NAF, NAF3_VIO_D11), |
| 734 | PINMUX_DATA(NAF2_MARK, PSE2_NAF2, HIZB0_VIO, NAF2_VIO_D10), |
| 735 | PINMUX_DATA(NAF1_MARK, PSE1_NAF1, HIZB0_VIO, NAF1_VIO_D9), |
| 736 | PINMUX_DATA(NAF0_MARK, PSE0_NAF0, HIZB0_VIO, NAF0_VIO_D8), |
| 737 | PINMUX_DATA(FCDE_MARK, FCDE), |
| 738 | PINMUX_DATA(FOE_MARK, PSE3_FLCTL, HIZB0_VIO, FOE_VIO_VD2), |
| 739 | PINMUX_DATA(FSC_MARK, FSC), |
| 740 | PINMUX_DATA(FWE_MARK, FWE), |
| 741 | PINMUX_DATA(FRB_MARK, PSE3_FLCTL, FRB_VIO_CLK2), |
| 742 | |
| 743 | /* KEYSC */ |
| 744 | PINMUX_DATA(KEYIN0_MARK, PSA15_KEYIN0, HIZC14_IRQ6, KEYIN0_IRQ6), |
| 745 | PINMUX_DATA(KEYIN1_MARK, HIZA14_KEYSC, KEYIN1), |
| 746 | PINMUX_DATA(KEYIN2_MARK, HIZA14_KEYSC, KEYIN2), |
| 747 | PINMUX_DATA(KEYIN3_MARK, HIZA14_KEYSC, KEYIN3), |
| 748 | PINMUX_DATA(KEYIN4_MARK, PSA14_KEYIN4, HIZC15_IRQ7, KEYIN4_IRQ7), |
| 749 | PINMUX_DATA(KEYOUT0_MARK, HIZA14_KEYSC, KEYOUT0), |
| 750 | PINMUX_DATA(KEYOUT1_MARK, HIZA14_KEYSC, KEYOUT1), |
| 751 | PINMUX_DATA(KEYOUT2_MARK, HIZA14_KEYSC, KEYOUT2), |
| 752 | PINMUX_DATA(KEYOUT3_MARK, HIZA14_KEYSC, KEYOUT3), |
| 753 | PINMUX_DATA(KEYOUT4_IN6_MARK, HIZA14_KEYSC, KEYOUT4_IN6), |
| 754 | PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), |
| 755 | }; |
| 756 | |
Laurent Pinchart | f41a1ef | 2013-12-16 20:25:16 +0100 | [diff] [blame] | 757 | static const struct sh_pfc_pin pinmux_pins[] = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 758 | /* PTA */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 759 | PINMUX_GPIO(PTA7), |
| 760 | PINMUX_GPIO(PTA6), |
| 761 | PINMUX_GPIO(PTA5), |
| 762 | PINMUX_GPIO(PTA4), |
| 763 | PINMUX_GPIO(PTA3), |
| 764 | PINMUX_GPIO(PTA2), |
| 765 | PINMUX_GPIO(PTA1), |
| 766 | PINMUX_GPIO(PTA0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 767 | |
| 768 | /* PTB */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 769 | PINMUX_GPIO(PTB7), |
| 770 | PINMUX_GPIO(PTB6), |
| 771 | PINMUX_GPIO(PTB5), |
| 772 | PINMUX_GPIO(PTB4), |
| 773 | PINMUX_GPIO(PTB3), |
| 774 | PINMUX_GPIO(PTB2), |
| 775 | PINMUX_GPIO(PTB1), |
| 776 | PINMUX_GPIO(PTB0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 777 | |
| 778 | /* PTC */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 779 | PINMUX_GPIO(PTC7), |
| 780 | PINMUX_GPIO(PTC5), |
| 781 | PINMUX_GPIO(PTC4), |
| 782 | PINMUX_GPIO(PTC3), |
| 783 | PINMUX_GPIO(PTC2), |
| 784 | PINMUX_GPIO(PTC0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 785 | |
| 786 | /* PTD */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 787 | PINMUX_GPIO(PTD7), |
| 788 | PINMUX_GPIO(PTD6), |
| 789 | PINMUX_GPIO(PTD5), |
| 790 | PINMUX_GPIO(PTD4), |
| 791 | PINMUX_GPIO(PTD3), |
| 792 | PINMUX_GPIO(PTD2), |
| 793 | PINMUX_GPIO(PTD1), |
| 794 | PINMUX_GPIO(PTD0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 795 | |
| 796 | /* PTE */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 797 | PINMUX_GPIO(PTE7), |
| 798 | PINMUX_GPIO(PTE6), |
| 799 | PINMUX_GPIO(PTE5), |
| 800 | PINMUX_GPIO(PTE4), |
| 801 | PINMUX_GPIO(PTE1), |
| 802 | PINMUX_GPIO(PTE0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 803 | |
| 804 | /* PTF */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 805 | PINMUX_GPIO(PTF6), |
| 806 | PINMUX_GPIO(PTF5), |
| 807 | PINMUX_GPIO(PTF4), |
| 808 | PINMUX_GPIO(PTF3), |
| 809 | PINMUX_GPIO(PTF2), |
| 810 | PINMUX_GPIO(PTF1), |
| 811 | PINMUX_GPIO(PTF0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 812 | |
| 813 | /* PTG */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 814 | PINMUX_GPIO(PTG4), |
| 815 | PINMUX_GPIO(PTG3), |
| 816 | PINMUX_GPIO(PTG2), |
| 817 | PINMUX_GPIO(PTG1), |
| 818 | PINMUX_GPIO(PTG0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 819 | |
| 820 | /* PTH */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 821 | PINMUX_GPIO(PTH7), |
| 822 | PINMUX_GPIO(PTH6), |
| 823 | PINMUX_GPIO(PTH5), |
| 824 | PINMUX_GPIO(PTH4), |
| 825 | PINMUX_GPIO(PTH3), |
| 826 | PINMUX_GPIO(PTH2), |
| 827 | PINMUX_GPIO(PTH1), |
| 828 | PINMUX_GPIO(PTH0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 829 | |
| 830 | /* PTJ */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 831 | PINMUX_GPIO(PTJ7), |
| 832 | PINMUX_GPIO(PTJ6), |
| 833 | PINMUX_GPIO(PTJ5), |
| 834 | PINMUX_GPIO(PTJ1), |
| 835 | PINMUX_GPIO(PTJ0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 836 | |
| 837 | /* PTK */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 838 | PINMUX_GPIO(PTK6), |
| 839 | PINMUX_GPIO(PTK5), |
| 840 | PINMUX_GPIO(PTK4), |
| 841 | PINMUX_GPIO(PTK3), |
| 842 | PINMUX_GPIO(PTK2), |
| 843 | PINMUX_GPIO(PTK1), |
| 844 | PINMUX_GPIO(PTK0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 845 | |
| 846 | /* PTL */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 847 | PINMUX_GPIO(PTL7), |
| 848 | PINMUX_GPIO(PTL6), |
| 849 | PINMUX_GPIO(PTL5), |
| 850 | PINMUX_GPIO(PTL4), |
| 851 | PINMUX_GPIO(PTL3), |
| 852 | PINMUX_GPIO(PTL2), |
| 853 | PINMUX_GPIO(PTL1), |
| 854 | PINMUX_GPIO(PTL0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 855 | |
| 856 | /* PTM */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 857 | PINMUX_GPIO(PTM7), |
| 858 | PINMUX_GPIO(PTM6), |
| 859 | PINMUX_GPIO(PTM5), |
| 860 | PINMUX_GPIO(PTM4), |
| 861 | PINMUX_GPIO(PTM3), |
| 862 | PINMUX_GPIO(PTM2), |
| 863 | PINMUX_GPIO(PTM1), |
| 864 | PINMUX_GPIO(PTM0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 865 | |
| 866 | /* PTN */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 867 | PINMUX_GPIO(PTN7), |
| 868 | PINMUX_GPIO(PTN6), |
| 869 | PINMUX_GPIO(PTN5), |
| 870 | PINMUX_GPIO(PTN4), |
| 871 | PINMUX_GPIO(PTN3), |
| 872 | PINMUX_GPIO(PTN2), |
| 873 | PINMUX_GPIO(PTN1), |
| 874 | PINMUX_GPIO(PTN0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 875 | |
| 876 | /* PTQ */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 877 | PINMUX_GPIO(PTQ6), |
| 878 | PINMUX_GPIO(PTQ5), |
| 879 | PINMUX_GPIO(PTQ4), |
| 880 | PINMUX_GPIO(PTQ3), |
| 881 | PINMUX_GPIO(PTQ2), |
| 882 | PINMUX_GPIO(PTQ1), |
| 883 | PINMUX_GPIO(PTQ0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 884 | |
| 885 | /* PTR */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 886 | PINMUX_GPIO(PTR4), |
| 887 | PINMUX_GPIO(PTR3), |
| 888 | PINMUX_GPIO(PTR2), |
| 889 | PINMUX_GPIO(PTR1), |
| 890 | PINMUX_GPIO(PTR0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 891 | |
| 892 | /* PTS */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 893 | PINMUX_GPIO(PTS4), |
| 894 | PINMUX_GPIO(PTS3), |
| 895 | PINMUX_GPIO(PTS2), |
| 896 | PINMUX_GPIO(PTS1), |
| 897 | PINMUX_GPIO(PTS0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 898 | |
| 899 | /* PTT */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 900 | PINMUX_GPIO(PTT4), |
| 901 | PINMUX_GPIO(PTT3), |
| 902 | PINMUX_GPIO(PTT2), |
| 903 | PINMUX_GPIO(PTT1), |
| 904 | PINMUX_GPIO(PTT0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 905 | |
| 906 | /* PTU */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 907 | PINMUX_GPIO(PTU4), |
| 908 | PINMUX_GPIO(PTU3), |
| 909 | PINMUX_GPIO(PTU2), |
| 910 | PINMUX_GPIO(PTU1), |
| 911 | PINMUX_GPIO(PTU0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 912 | |
| 913 | /* PTV */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 914 | PINMUX_GPIO(PTV4), |
| 915 | PINMUX_GPIO(PTV3), |
| 916 | PINMUX_GPIO(PTV2), |
| 917 | PINMUX_GPIO(PTV1), |
| 918 | PINMUX_GPIO(PTV0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 919 | |
| 920 | /* PTW */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 921 | PINMUX_GPIO(PTW6), |
| 922 | PINMUX_GPIO(PTW5), |
| 923 | PINMUX_GPIO(PTW4), |
| 924 | PINMUX_GPIO(PTW3), |
| 925 | PINMUX_GPIO(PTW2), |
| 926 | PINMUX_GPIO(PTW1), |
| 927 | PINMUX_GPIO(PTW0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 928 | |
| 929 | /* PTX */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 930 | PINMUX_GPIO(PTX6), |
| 931 | PINMUX_GPIO(PTX5), |
| 932 | PINMUX_GPIO(PTX4), |
| 933 | PINMUX_GPIO(PTX3), |
| 934 | PINMUX_GPIO(PTX2), |
| 935 | PINMUX_GPIO(PTX1), |
| 936 | PINMUX_GPIO(PTX0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 937 | |
| 938 | /* PTY */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 939 | PINMUX_GPIO(PTY5), |
| 940 | PINMUX_GPIO(PTY4), |
| 941 | PINMUX_GPIO(PTY3), |
| 942 | PINMUX_GPIO(PTY2), |
| 943 | PINMUX_GPIO(PTY1), |
| 944 | PINMUX_GPIO(PTY0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 945 | |
| 946 | /* PTZ */ |
Laurent Pinchart | 7cbb0e5 | 2013-07-15 21:16:25 +0200 | [diff] [blame] | 947 | PINMUX_GPIO(PTZ5), |
| 948 | PINMUX_GPIO(PTZ4), |
| 949 | PINMUX_GPIO(PTZ3), |
| 950 | PINMUX_GPIO(PTZ2), |
| 951 | PINMUX_GPIO(PTZ1), |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 952 | }; |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 953 | |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 954 | #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) |
| 955 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 956 | static const struct pinmux_func pinmux_func_gpios[] = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 957 | /* SCIF0 */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 958 | GPIO_FN(SCIF0_TXD), |
| 959 | GPIO_FN(SCIF0_RXD), |
| 960 | GPIO_FN(SCIF0_RTS), |
| 961 | GPIO_FN(SCIF0_CTS), |
| 962 | GPIO_FN(SCIF0_SCK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 963 | |
| 964 | /* SCIF1 */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 965 | GPIO_FN(SCIF1_TXD), |
| 966 | GPIO_FN(SCIF1_RXD), |
| 967 | GPIO_FN(SCIF1_RTS), |
| 968 | GPIO_FN(SCIF1_CTS), |
| 969 | GPIO_FN(SCIF1_SCK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 970 | |
| 971 | /* SCIF2 */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 972 | GPIO_FN(SCIF2_TXD), |
| 973 | GPIO_FN(SCIF2_RXD), |
| 974 | GPIO_FN(SCIF2_RTS), |
| 975 | GPIO_FN(SCIF2_CTS), |
| 976 | GPIO_FN(SCIF2_SCK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 977 | |
| 978 | /* SIO */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 979 | GPIO_FN(SIOTXD), |
| 980 | GPIO_FN(SIORXD), |
| 981 | GPIO_FN(SIOD), |
| 982 | GPIO_FN(SIOSTRB0), |
| 983 | GPIO_FN(SIOSTRB1), |
| 984 | GPIO_FN(SIOSCK), |
| 985 | GPIO_FN(SIOMCK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 986 | |
| 987 | /* CEU */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 988 | GPIO_FN(VIO_D15), |
| 989 | GPIO_FN(VIO_D14), |
| 990 | GPIO_FN(VIO_D13), |
| 991 | GPIO_FN(VIO_D12), |
| 992 | GPIO_FN(VIO_D11), |
| 993 | GPIO_FN(VIO_D10), |
| 994 | GPIO_FN(VIO_D9), |
| 995 | GPIO_FN(VIO_D8), |
| 996 | GPIO_FN(VIO_D7), |
| 997 | GPIO_FN(VIO_D6), |
| 998 | GPIO_FN(VIO_D5), |
| 999 | GPIO_FN(VIO_D4), |
| 1000 | GPIO_FN(VIO_D3), |
| 1001 | GPIO_FN(VIO_D2), |
| 1002 | GPIO_FN(VIO_D1), |
| 1003 | GPIO_FN(VIO_D0), |
| 1004 | GPIO_FN(VIO_CLK), |
| 1005 | GPIO_FN(VIO_VD), |
| 1006 | GPIO_FN(VIO_HD), |
| 1007 | GPIO_FN(VIO_FLD), |
| 1008 | GPIO_FN(VIO_CKO), |
| 1009 | GPIO_FN(VIO_STEX), |
| 1010 | GPIO_FN(VIO_STEM), |
| 1011 | GPIO_FN(VIO_VD2), |
| 1012 | GPIO_FN(VIO_HD2), |
| 1013 | GPIO_FN(VIO_CLK2), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1014 | |
| 1015 | /* LCDC */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1016 | GPIO_FN(LCDD23), |
| 1017 | GPIO_FN(LCDD22), |
| 1018 | GPIO_FN(LCDD21), |
| 1019 | GPIO_FN(LCDD20), |
| 1020 | GPIO_FN(LCDD19), |
| 1021 | GPIO_FN(LCDD18), |
| 1022 | GPIO_FN(LCDD17), |
| 1023 | GPIO_FN(LCDD16), |
| 1024 | GPIO_FN(LCDD15), |
| 1025 | GPIO_FN(LCDD14), |
| 1026 | GPIO_FN(LCDD13), |
| 1027 | GPIO_FN(LCDD12), |
| 1028 | GPIO_FN(LCDD11), |
| 1029 | GPIO_FN(LCDD10), |
| 1030 | GPIO_FN(LCDD9), |
| 1031 | GPIO_FN(LCDD8), |
| 1032 | GPIO_FN(LCDD7), |
| 1033 | GPIO_FN(LCDD6), |
| 1034 | GPIO_FN(LCDD5), |
| 1035 | GPIO_FN(LCDD4), |
| 1036 | GPIO_FN(LCDD3), |
| 1037 | GPIO_FN(LCDD2), |
| 1038 | GPIO_FN(LCDD1), |
| 1039 | GPIO_FN(LCDD0), |
| 1040 | GPIO_FN(LCDLCLK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1041 | /* Main LCD */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1042 | GPIO_FN(LCDDON), |
| 1043 | GPIO_FN(LCDVCPWC), |
| 1044 | GPIO_FN(LCDVEPWC), |
| 1045 | GPIO_FN(LCDVSYN), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1046 | /* Main LCD - RGB Mode */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1047 | GPIO_FN(LCDDCK), |
| 1048 | GPIO_FN(LCDHSYN), |
| 1049 | GPIO_FN(LCDDISP), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1050 | /* Main LCD - SYS Mode */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1051 | GPIO_FN(LCDRS), |
| 1052 | GPIO_FN(LCDCS), |
| 1053 | GPIO_FN(LCDWR), |
| 1054 | GPIO_FN(LCDRD), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1055 | /* Sub LCD - SYS Mode */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1056 | GPIO_FN(LCDDON2), |
| 1057 | GPIO_FN(LCDVCPWC2), |
| 1058 | GPIO_FN(LCDVEPWC2), |
| 1059 | GPIO_FN(LCDVSYN2), |
| 1060 | GPIO_FN(LCDCS2), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1061 | |
| 1062 | /* BSC */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1063 | GPIO_FN(IOIS16), |
| 1064 | GPIO_FN(A25), |
| 1065 | GPIO_FN(A24), |
| 1066 | GPIO_FN(A23), |
| 1067 | GPIO_FN(A22), |
| 1068 | GPIO_FN(BS), |
| 1069 | GPIO_FN(CS6B_CE1B), |
| 1070 | GPIO_FN(WAIT), |
| 1071 | GPIO_FN(CS6A_CE2B), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1072 | |
| 1073 | /* SBSC */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1074 | GPIO_FN(HPD63), |
| 1075 | GPIO_FN(HPD62), |
| 1076 | GPIO_FN(HPD61), |
| 1077 | GPIO_FN(HPD60), |
| 1078 | GPIO_FN(HPD59), |
| 1079 | GPIO_FN(HPD58), |
| 1080 | GPIO_FN(HPD57), |
| 1081 | GPIO_FN(HPD56), |
| 1082 | GPIO_FN(HPD55), |
| 1083 | GPIO_FN(HPD54), |
| 1084 | GPIO_FN(HPD53), |
| 1085 | GPIO_FN(HPD52), |
| 1086 | GPIO_FN(HPD51), |
| 1087 | GPIO_FN(HPD50), |
| 1088 | GPIO_FN(HPD49), |
| 1089 | GPIO_FN(HPD48), |
| 1090 | GPIO_FN(HPDQM7), |
| 1091 | GPIO_FN(HPDQM6), |
| 1092 | GPIO_FN(HPDQM5), |
| 1093 | GPIO_FN(HPDQM4), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1094 | |
| 1095 | /* IRQ */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1096 | GPIO_FN(IRQ0), |
| 1097 | GPIO_FN(IRQ1), |
| 1098 | GPIO_FN(IRQ2), |
| 1099 | GPIO_FN(IRQ3), |
| 1100 | GPIO_FN(IRQ4), |
| 1101 | GPIO_FN(IRQ5), |
| 1102 | GPIO_FN(IRQ6), |
| 1103 | GPIO_FN(IRQ7), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1104 | |
| 1105 | /* SDHI */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1106 | GPIO_FN(SDHICD), |
| 1107 | GPIO_FN(SDHIWP), |
| 1108 | GPIO_FN(SDHID3), |
| 1109 | GPIO_FN(SDHID2), |
| 1110 | GPIO_FN(SDHID1), |
| 1111 | GPIO_FN(SDHID0), |
| 1112 | GPIO_FN(SDHICMD), |
| 1113 | GPIO_FN(SDHICLK), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1114 | |
| 1115 | /* SIU - Port A */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1116 | GPIO_FN(SIUAOLR), |
| 1117 | GPIO_FN(SIUAOBT), |
| 1118 | GPIO_FN(SIUAISLD), |
| 1119 | GPIO_FN(SIUAILR), |
| 1120 | GPIO_FN(SIUAIBT), |
| 1121 | GPIO_FN(SIUAOSLD), |
| 1122 | GPIO_FN(SIUMCKA), |
| 1123 | GPIO_FN(SIUFCKA), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1124 | |
| 1125 | /* SIU - Port B */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1126 | GPIO_FN(SIUBOLR), |
| 1127 | GPIO_FN(SIUBOBT), |
| 1128 | GPIO_FN(SIUBISLD), |
| 1129 | GPIO_FN(SIUBILR), |
| 1130 | GPIO_FN(SIUBIBT), |
| 1131 | GPIO_FN(SIUBOSLD), |
| 1132 | GPIO_FN(SIUMCKB), |
| 1133 | GPIO_FN(SIUFCKB), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1134 | |
| 1135 | /* AUD */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1136 | GPIO_FN(AUDSYNC), |
| 1137 | GPIO_FN(AUDATA3), |
| 1138 | GPIO_FN(AUDATA2), |
| 1139 | GPIO_FN(AUDATA1), |
| 1140 | GPIO_FN(AUDATA0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1141 | |
| 1142 | /* DMAC */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1143 | GPIO_FN(DACK), |
| 1144 | GPIO_FN(DREQ0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1145 | |
| 1146 | /* VOU */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1147 | GPIO_FN(DV_CLKI), |
| 1148 | GPIO_FN(DV_CLK), |
| 1149 | GPIO_FN(DV_HSYNC), |
| 1150 | GPIO_FN(DV_VSYNC), |
| 1151 | GPIO_FN(DV_D15), |
| 1152 | GPIO_FN(DV_D14), |
| 1153 | GPIO_FN(DV_D13), |
| 1154 | GPIO_FN(DV_D12), |
| 1155 | GPIO_FN(DV_D11), |
| 1156 | GPIO_FN(DV_D10), |
| 1157 | GPIO_FN(DV_D9), |
| 1158 | GPIO_FN(DV_D8), |
| 1159 | GPIO_FN(DV_D7), |
| 1160 | GPIO_FN(DV_D6), |
| 1161 | GPIO_FN(DV_D5), |
| 1162 | GPIO_FN(DV_D4), |
| 1163 | GPIO_FN(DV_D3), |
| 1164 | GPIO_FN(DV_D2), |
| 1165 | GPIO_FN(DV_D1), |
| 1166 | GPIO_FN(DV_D0), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1167 | |
| 1168 | /* CPG */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1169 | GPIO_FN(STATUS0), |
| 1170 | GPIO_FN(PDSTATUS), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1171 | |
| 1172 | /* SIOF0 */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1173 | GPIO_FN(SIOF0_MCK), |
| 1174 | GPIO_FN(SIOF0_SCK), |
| 1175 | GPIO_FN(SIOF0_SYNC), |
| 1176 | GPIO_FN(SIOF0_SS1), |
| 1177 | GPIO_FN(SIOF0_SS2), |
| 1178 | GPIO_FN(SIOF0_TXD), |
| 1179 | GPIO_FN(SIOF0_RXD), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1180 | |
| 1181 | /* SIOF1 */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1182 | GPIO_FN(SIOF1_MCK), |
| 1183 | GPIO_FN(SIOF1_SCK), |
| 1184 | GPIO_FN(SIOF1_SYNC), |
| 1185 | GPIO_FN(SIOF1_SS1), |
| 1186 | GPIO_FN(SIOF1_SS2), |
| 1187 | GPIO_FN(SIOF1_TXD), |
| 1188 | GPIO_FN(SIOF1_RXD), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1189 | |
| 1190 | /* SIM */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1191 | GPIO_FN(SIM_D), |
| 1192 | GPIO_FN(SIM_CLK), |
| 1193 | GPIO_FN(SIM_RST), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1194 | |
| 1195 | /* TSIF */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1196 | GPIO_FN(TS_SDAT), |
| 1197 | GPIO_FN(TS_SCK), |
| 1198 | GPIO_FN(TS_SDEN), |
| 1199 | GPIO_FN(TS_SPSYNC), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1200 | |
| 1201 | /* IRDA */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1202 | GPIO_FN(IRDA_IN), |
| 1203 | GPIO_FN(IRDA_OUT), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1204 | |
| 1205 | /* TPU */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1206 | GPIO_FN(TPUTO), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1207 | |
| 1208 | /* FLCTL */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1209 | GPIO_FN(FCE), |
| 1210 | GPIO_FN(NAF7), |
| 1211 | GPIO_FN(NAF6), |
| 1212 | GPIO_FN(NAF5), |
| 1213 | GPIO_FN(NAF4), |
| 1214 | GPIO_FN(NAF3), |
| 1215 | GPIO_FN(NAF2), |
| 1216 | GPIO_FN(NAF1), |
| 1217 | GPIO_FN(NAF0), |
| 1218 | GPIO_FN(FCDE), |
| 1219 | GPIO_FN(FOE), |
| 1220 | GPIO_FN(FSC), |
| 1221 | GPIO_FN(FWE), |
| 1222 | GPIO_FN(FRB), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1223 | |
| 1224 | /* KEYSC */ |
Laurent Pinchart | 35ad427 | 2012-11-28 22:05:49 +0100 | [diff] [blame] | 1225 | GPIO_FN(KEYIN0), |
| 1226 | GPIO_FN(KEYIN1), |
| 1227 | GPIO_FN(KEYIN2), |
| 1228 | GPIO_FN(KEYIN3), |
| 1229 | GPIO_FN(KEYIN4), |
| 1230 | GPIO_FN(KEYOUT0), |
| 1231 | GPIO_FN(KEYOUT1), |
| 1232 | GPIO_FN(KEYOUT2), |
| 1233 | GPIO_FN(KEYOUT3), |
| 1234 | GPIO_FN(KEYOUT4_IN6), |
| 1235 | GPIO_FN(KEYOUT5_IN5), |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1236 | }; |
| 1237 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 1238 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1239 | { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1240 | VIO_D7_SCIF1_SCK, PTA7_OUT, 0, PTA7_IN, |
| 1241 | VIO_D6_SCIF1_RXD, 0, 0, PTA6_IN, |
| 1242 | VIO_D5_SCIF1_TXD, PTA5_OUT, 0, PTA5_IN, |
| 1243 | VIO_D4, 0, 0, PTA4_IN, |
| 1244 | VIO_D3, 0, 0, PTA3_IN, |
| 1245 | VIO_D2, 0, 0, PTA2_IN, |
| 1246 | VIO_D1, 0, 0, PTA1_IN, |
| 1247 | VIO_D0_LCDLCLK, 0, 0, PTA0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1248 | }, |
| 1249 | { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) { |
| 1250 | HPD55, PTB7_OUT, 0, PTB7_IN, |
| 1251 | HPD54, PTB6_OUT, 0, PTB6_IN, |
| 1252 | HPD53, PTB5_OUT, 0, PTB5_IN, |
| 1253 | HPD52, PTB4_OUT, 0, PTB4_IN, |
| 1254 | HPD51, PTB3_OUT, 0, PTB3_IN, |
| 1255 | HPD50, PTB2_OUT, 0, PTB2_IN, |
| 1256 | HPD49, PTB1_OUT, 0, PTB1_IN, |
| 1257 | HPD48, PTB0_OUT, 0, PTB0_IN } |
| 1258 | }, |
| 1259 | { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1260 | 0, 0, 0, PTC7_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1261 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1262 | IOIS16, 0, 0, PTC5_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1263 | HPDQM7, PTC4_OUT, 0, PTC4_IN, |
| 1264 | HPDQM6, PTC3_OUT, 0, PTC3_IN, |
| 1265 | HPDQM5, PTC2_OUT, 0, PTC2_IN, |
| 1266 | 0, 0, 0, 0, |
| 1267 | HPDQM4, PTC0_OUT, 0, PTC0_IN } |
| 1268 | }, |
| 1269 | { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1270 | SDHICD, 0, 0, PTD7_IN, |
| 1271 | SDHIWP, PTD6_OUT, 0, PTD6_IN, |
| 1272 | SDHID3, PTD5_OUT, 0, PTD5_IN, |
| 1273 | IRQ2_SDHID2, PTD4_OUT, 0, PTD4_IN, |
| 1274 | SDHID1, PTD3_OUT, 0, PTD3_IN, |
| 1275 | SDHID0, PTD2_OUT, 0, PTD2_IN, |
| 1276 | SDHICMD, PTD1_OUT, 0, PTD1_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1277 | SDHICLK, PTD0_OUT, 0, 0 } |
| 1278 | }, |
| 1279 | { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1280 | A25, PTE7_OUT, 0, PTE7_IN, |
| 1281 | A24, PTE6_OUT, 0, PTE6_IN, |
| 1282 | A23, PTE5_OUT, 0, PTE5_IN, |
| 1283 | A22, PTE4_OUT, 0, PTE4_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1284 | 0, 0, 0, 0, |
| 1285 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1286 | IRQ5, PTE1_OUT, 0, PTE1_IN, |
| 1287 | IRQ4_BS, PTE0_OUT, 0, PTE0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1288 | }, |
| 1289 | { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) { |
| 1290 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1291 | PTF6, PTF6_OUT, 0, PTF6_IN, |
| 1292 | SIOSCK_SIUBOBT, PTF5_OUT, 0, PTF5_IN, |
| 1293 | SIOSTRB1_SIUBOLR, PTF4_OUT, 0, PTF4_IN, |
| 1294 | SIOSTRB0_SIUBIBT, PTF3_OUT, 0, PTF3_IN, |
| 1295 | SIOD_SIUBILR, PTF2_OUT, 0, PTF2_IN, |
| 1296 | SIORXD_SIUBISLD, 0, 0, PTF1_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1297 | SIOTXD_SIUBOSLD, PTF0_OUT, 0, 0 } |
| 1298 | }, |
| 1299 | { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) { |
| 1300 | 0, 0, 0, 0, |
| 1301 | 0, 0, 0, 0, |
| 1302 | 0, 0, 0, 0, |
| 1303 | AUDSYNC, PTG4_OUT, 0, 0, |
| 1304 | AUDATA3, PTG3_OUT, 0, 0, |
| 1305 | AUDATA2, PTG2_OUT, 0, 0, |
| 1306 | AUDATA1, PTG1_OUT, 0, 0, |
| 1307 | AUDATA0, PTG0_OUT, 0, 0 } |
| 1308 | }, |
| 1309 | { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) { |
| 1310 | LCDVCPWC_LCDVCPWC2, PTH7_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1311 | LCDVSYN2_DACK, PTH6_OUT, 0, PTH6_IN, |
| 1312 | LCDVSYN, PTH5_OUT, 0, PTH5_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1313 | LCDDISP_LCDRS, PTH4_OUT, 0, 0, |
| 1314 | LCDHSYN_LCDCS, PTH3_OUT, 0, 0, |
| 1315 | LCDDON_LCDDON2, PTH2_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1316 | LCDD17_DV_HSYNC, PTH1_OUT, 0, PTH1_IN, |
| 1317 | LCDD16_DV_VSYNC, PTH0_OUT, 0, PTH0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1318 | }, |
| 1319 | { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) { |
| 1320 | STATUS0, PTJ7_OUT, 0, 0, |
| 1321 | 0, PTJ6_OUT, 0, 0, |
| 1322 | PDSTATUS, PTJ5_OUT, 0, 0, |
| 1323 | 0, 0, 0, 0, |
| 1324 | 0, 0, 0, 0, |
| 1325 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1326 | IRQ1, PTJ1_OUT, 0, PTJ1_IN, |
| 1327 | IRQ0, PTJ0_OUT, 0, PTJ0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1328 | }, |
| 1329 | { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) { |
| 1330 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1331 | SIUAILR_SIOF1_SS2, PTK6_OUT, 0, PTK6_IN, |
| 1332 | SIUAIBT_SIOF1_SS1, PTK5_OUT, 0, PTK5_IN, |
| 1333 | SIUAOLR_SIOF1_SYNC, PTK4_OUT, 0, PTK4_IN, |
| 1334 | SIUAOBT_SIOF1_SCK, PTK3_OUT, 0, PTK3_IN, |
| 1335 | SIUAISLD_SIOF1_RXD, 0, 0, PTK2_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1336 | SIUAOSLD_SIOF1_TXD, PTK1_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1337 | PTK0, PTK0_OUT, 0, PTK0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1338 | }, |
| 1339 | { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1340 | LCDD15_DV_D15, PTL7_OUT, 0, PTL7_IN, |
| 1341 | LCDD14_DV_D14, PTL6_OUT, 0, PTL6_IN, |
| 1342 | LCDD13_DV_D13, PTL5_OUT, 0, PTL5_IN, |
| 1343 | LCDD12_DV_D12, PTL4_OUT, 0, PTL4_IN, |
| 1344 | LCDD11_DV_D11, PTL3_OUT, 0, PTL3_IN, |
| 1345 | LCDD10_DV_D10, PTL2_OUT, 0, PTL2_IN, |
| 1346 | LCDD9_DV_D9, PTL1_OUT, 0, PTL1_IN, |
| 1347 | LCDD8_DV_D8, PTL0_OUT, 0, PTL0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1348 | }, |
| 1349 | { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) { |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1350 | LCDD7_DV_D7, PTM7_OUT, 0, PTM7_IN, |
| 1351 | LCDD6_DV_D6, PTM6_OUT, 0, PTM6_IN, |
| 1352 | LCDD5_DV_D5, PTM5_OUT, 0, PTM5_IN, |
| 1353 | LCDD4_DV_D4, PTM4_OUT, 0, PTM4_IN, |
| 1354 | LCDD3_DV_D3, PTM3_OUT, 0, PTM3_IN, |
| 1355 | LCDD2_DV_D2, PTM2_OUT, 0, PTM2_IN, |
| 1356 | LCDD1_DV_D1, PTM1_OUT, 0, PTM1_IN, |
| 1357 | LCDD0_DV_D0, PTM0_OUT, 0, PTM0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1358 | }, |
| 1359 | { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) { |
| 1360 | HPD63, PTN7_OUT, 0, PTN7_IN, |
| 1361 | HPD62, PTN6_OUT, 0, PTN6_IN, |
| 1362 | HPD61, PTN5_OUT, 0, PTN5_IN, |
| 1363 | HPD60, PTN4_OUT, 0, PTN4_IN, |
| 1364 | HPD59, PTN3_OUT, 0, PTN3_IN, |
| 1365 | HPD58, PTN2_OUT, 0, PTN2_IN, |
| 1366 | HPD57, PTN1_OUT, 0, PTN1_IN, |
| 1367 | HPD56, PTN0_OUT, 0, PTN0_IN } |
| 1368 | }, |
| 1369 | { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) { |
| 1370 | 0, 0, 0, 0, |
| 1371 | SIOF0_SS2_SIM_RST, PTQ6_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1372 | SIOF0_SS1_TS_SPSYNC, PTQ5_OUT, 0, PTQ5_IN, |
| 1373 | SIOF0_SYNC_TS_SDEN, PTQ4_OUT, 0, PTQ4_IN, |
| 1374 | SIOF0_SCK_TS_SCK, PTQ3_OUT, 0, PTQ3_IN, |
| 1375 | PTQ2, 0, 0, PTQ2_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1376 | PTQ1, PTQ1_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1377 | PTQ0, PTQ0_OUT, 0, PTQ0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1378 | }, |
| 1379 | { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) { |
| 1380 | 0, 0, 0, 0, |
| 1381 | 0, 0, 0, 0, |
| 1382 | 0, 0, 0, 0, |
| 1383 | LCDRD, PTR4_OUT, 0, 0, |
| 1384 | CS6B_CE1B_LCDCS2, PTR3_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1385 | WAIT, 0, 0, PTR2_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1386 | LCDDCK_LCDWR, PTR1_OUT, 0, 0, |
| 1387 | LCDVEPWC_LCDVEPWC2, PTR0_OUT, 0, 0 } |
| 1388 | }, |
| 1389 | { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) { |
| 1390 | 0, 0, 0, 0, |
| 1391 | 0, 0, 0, 0, |
| 1392 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1393 | SCIF0_CTS_SIUAISPD, 0, 0, PTS4_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1394 | SCIF0_RTS_SIUAOSPD, PTS3_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1395 | SCIF0_SCK_TPUTO, PTS2_OUT, 0, PTS2_IN, |
| 1396 | SCIF0_RXD, 0, 0, PTS1_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1397 | SCIF0_TXD, PTS0_OUT, 0, 0 } |
| 1398 | }, |
| 1399 | { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) { |
| 1400 | 0, 0, 0, 0, |
| 1401 | 0, 0, 0, 0, |
| 1402 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1403 | FOE_VIO_VD2, PTT4_OUT, 0, PTT4_IN, |
| 1404 | FWE, PTT3_OUT, 0, PTT3_IN, |
| 1405 | FSC, PTT2_OUT, 0, PTT2_IN, |
| 1406 | DREQ0, 0, 0, PTT1_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1407 | FCDE, PTT0_OUT, 0, 0 } |
| 1408 | }, |
| 1409 | { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) { |
| 1410 | 0, 0, 0, 0, |
| 1411 | 0, 0, 0, 0, |
| 1412 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1413 | NAF2_VIO_D10, PTU4_OUT, 0, PTU4_IN, |
| 1414 | NAF1_VIO_D9, PTU3_OUT, 0, PTU3_IN, |
| 1415 | NAF0_VIO_D8, PTU2_OUT, 0, PTU2_IN, |
| 1416 | FRB_VIO_CLK2, 0, 0, PTU1_IN, |
| 1417 | FCE_VIO_HD2, PTU0_OUT, 0, PTU0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1418 | }, |
| 1419 | { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) { |
| 1420 | 0, 0, 0, 0, |
| 1421 | 0, 0, 0, 0, |
| 1422 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1423 | NAF7_VIO_D15, PTV4_OUT, 0, PTV4_IN, |
| 1424 | NAF6_VIO_D14, PTV3_OUT, 0, PTV3_IN, |
| 1425 | NAF5_VIO_D13, PTV2_OUT, 0, PTV2_IN, |
| 1426 | NAF4_VIO_D12, PTV1_OUT, 0, PTV1_IN, |
| 1427 | NAF3_VIO_D11, PTV0_OUT, 0, PTV0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1428 | }, |
| 1429 | { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) { |
| 1430 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1431 | VIO_FLD_SCIF2_CTS, 0, 0, PTW6_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1432 | VIO_CKO_SCIF2_RTS, PTW5_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1433 | VIO_STEX_SCIF2_SCK, PTW4_OUT, 0, PTW4_IN, |
| 1434 | VIO_STEM_SCIF2_TXD, PTW3_OUT, 0, PTW3_IN, |
| 1435 | VIO_HD_SCIF2_RXD, PTW2_OUT, 0, PTW2_IN, |
| 1436 | VIO_VD_SCIF1_CTS, PTW1_OUT, 0, PTW1_IN, |
| 1437 | VIO_CLK_SCIF1_RTS, PTW0_OUT, 0, PTW0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1438 | }, |
| 1439 | { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) { |
| 1440 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1441 | CS6A_CE2B, PTX6_OUT, 0, PTX6_IN, |
| 1442 | LCDD23, PTX5_OUT, 0, PTX5_IN, |
| 1443 | LCDD22, PTX4_OUT, 0, PTX4_IN, |
| 1444 | LCDD21, PTX3_OUT, 0, PTX3_IN, |
| 1445 | LCDD20, PTX2_OUT, 0, PTX2_IN, |
| 1446 | LCDD19_DV_CLKI, PTX1_OUT, 0, PTX1_IN, |
| 1447 | LCDD18_DV_CLK, PTX0_OUT, 0, PTX0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1448 | }, |
| 1449 | { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) { |
| 1450 | 0, 0, 0, 0, |
| 1451 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1452 | KEYOUT5_IN5, PTY5_OUT, 0, PTY5_IN, |
| 1453 | KEYOUT4_IN6, PTY4_OUT, 0, PTY4_IN, |
| 1454 | KEYOUT3, PTY3_OUT, 0, PTY3_IN, |
| 1455 | KEYOUT2, PTY2_OUT, 0, PTY2_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1456 | KEYOUT1, PTY1_OUT, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1457 | KEYOUT0, PTY0_OUT, 0, PTY0_IN } |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1458 | }, |
| 1459 | { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) { |
| 1460 | 0, 0, 0, 0, |
| 1461 | 0, 0, 0, 0, |
Laurent Pinchart | 48b888b | 2013-07-14 19:56:02 +0200 | [diff] [blame] | 1462 | KEYIN4_IRQ7, 0, 0, PTZ5_IN, |
| 1463 | KEYIN3, 0, 0, PTZ4_IN, |
| 1464 | KEYIN2, 0, 0, PTZ3_IN, |
| 1465 | KEYIN1, 0, 0, PTZ2_IN, |
| 1466 | KEYIN0_IRQ6, 0, 0, PTZ1_IN, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1467 | 0, 0, 0, 0 } |
| 1468 | }, |
| 1469 | { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) { |
| 1470 | PSA15_KEYIN0, PSA15_IRQ6, |
| 1471 | PSA14_KEYIN4, PSA14_IRQ7, |
| 1472 | 0, 0, |
| 1473 | 0, 0, |
| 1474 | 0, 0, |
| 1475 | 0, 0, |
| 1476 | PSA9_IRQ4, PSA9_BS, |
| 1477 | 0, 0, |
| 1478 | 0, 0, |
| 1479 | 0, 0, |
| 1480 | 0, 0, |
| 1481 | PSA4_IRQ2, PSA4_SDHID2, |
| 1482 | 0, 0, |
| 1483 | 0, 0, |
| 1484 | 0, 0, |
| 1485 | 0, 0 } |
| 1486 | }, |
| 1487 | { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) { |
| 1488 | PSB15_SIOTXD, PSB15_SIUBOSLD, |
| 1489 | PSB14_SIORXD, PSB14_SIUBISLD, |
| 1490 | PSB13_SIOD, PSB13_SIUBILR, |
| 1491 | PSB12_SIOSTRB0, PSB12_SIUBIBT, |
| 1492 | PSB11_SIOSTRB1, PSB11_SIUBOLR, |
| 1493 | PSB10_SIOSCK, PSB10_SIUBOBT, |
| 1494 | PSB9_SIOMCK, PSB9_SIUMCKB, |
| 1495 | PSB8_SIOF0_MCK, PSB8_IRQ3, |
| 1496 | PSB7_SIOF0_TXD, PSB7_IRDA_OUT, |
| 1497 | PSB6_SIOF0_RXD, PSB6_IRDA_IN, |
| 1498 | PSB5_SIOF0_SCK, PSB5_TS_SCK, |
| 1499 | PSB4_SIOF0_SYNC, PSB4_TS_SDEN, |
| 1500 | PSB3_SIOF0_SS1, PSB3_TS_SPSYNC, |
| 1501 | PSB2_SIOF0_SS2, PSB2_SIM_RST, |
| 1502 | PSB1_SIUMCKA, PSB1_SIOF1_MCK, |
| 1503 | PSB0_SIUAOSLD, PSB0_SIOF1_TXD } |
| 1504 | }, |
| 1505 | { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) { |
| 1506 | PSC15_SIUAISLD, PSC15_SIOF1_RXD, |
| 1507 | PSC14_SIUAOBT, PSC14_SIOF1_SCK, |
| 1508 | PSC13_SIUAOLR, PSC13_SIOF1_SYNC, |
| 1509 | PSC12_SIUAIBT, PSC12_SIOF1_SS1, |
| 1510 | PSC11_SIUAILR, PSC11_SIOF1_SS2, |
| 1511 | 0, 0, |
| 1512 | 0, 0, |
| 1513 | 0, 0, |
| 1514 | 0, 0, |
| 1515 | 0, 0, |
| 1516 | 0, 0, |
| 1517 | 0, 0, |
| 1518 | 0, 0, |
| 1519 | 0, 0, |
| 1520 | 0, 0, |
| 1521 | PSC0_NAF, PSC0_VIO } |
| 1522 | }, |
| 1523 | { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) { |
| 1524 | 0, 0, |
| 1525 | 0, 0, |
| 1526 | PSD13_VIO, PSD13_SCIF2, |
| 1527 | PSD12_VIO, PSD12_SCIF1, |
| 1528 | PSD11_VIO, PSD11_SCIF1, |
| 1529 | PSD10_VIO_D0, PSD10_LCDLCLK, |
| 1530 | PSD9_SIOMCK_SIUMCKB, PSD9_SIUFCKB, |
| 1531 | PSD8_SCIF0_SCK, PSD8_TPUTO, |
| 1532 | PSD7_SCIF0_RTS, PSD7_SIUAOSPD, |
| 1533 | PSD6_SCIF0_CTS, PSD6_SIUAISPD, |
| 1534 | PSD5_CS6B_CE1B, PSD5_LCDCS2, |
| 1535 | 0, 0, |
| 1536 | PSD3_LCDVEPWC_LCDVCPWC, PSD3_LCDVEPWC2_LCDVCPWC2, |
| 1537 | PSD2_LCDDON, PSD2_LCDDON2, |
| 1538 | 0, 0, |
| 1539 | PSD0_LCDD19_LCDD0, PSD0_DV } |
| 1540 | }, |
| 1541 | { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) { |
| 1542 | PSE15_SIOF0_MCK_IRQ3, PSE15_SIM_D, |
| 1543 | PSE14_SIOF0_TXD_IRDA_OUT, PSE14_SIM_CLK, |
| 1544 | PSE13_SIOF0_RXD_IRDA_IN, PSE13_TS_SDAT, |
| 1545 | PSE12_LCDVSYN2, PSE12_DACK, |
| 1546 | PSE11_SIUMCKA_SIOF1_MCK, PSE11_SIUFCKA, |
| 1547 | 0, 0, |
| 1548 | 0, 0, |
| 1549 | 0, 0, |
| 1550 | 0, 0, |
| 1551 | 0, 0, |
| 1552 | 0, 0, |
| 1553 | 0, 0, |
| 1554 | PSE3_FLCTL, PSE3_VIO, |
| 1555 | PSE2_NAF2, PSE2_VIO_D10, |
| 1556 | PSE1_NAF1, PSE1_VIO_D9, |
| 1557 | PSE0_NAF0, PSE0_VIO_D8 } |
| 1558 | }, |
| 1559 | { PINMUX_CFG_REG("HIZCRA", 0xa4050158, 16, 1) { |
| 1560 | 0, 0, |
| 1561 | HIZA14_KEYSC, HIZA14_HIZ, |
| 1562 | 0, 0, |
| 1563 | 0, 0, |
| 1564 | 0, 0, |
| 1565 | HIZA10_NAF, HIZA10_HIZ, |
| 1566 | HIZA9_VIO, HIZA9_HIZ, |
| 1567 | HIZA8_LCDC, HIZA8_HIZ, |
| 1568 | HIZA7_LCDC, HIZA7_HIZ, |
| 1569 | HIZA6_LCDC, HIZA6_HIZ, |
| 1570 | 0, 0, |
| 1571 | 0, 0, |
| 1572 | 0, 0, |
| 1573 | 0, 0, |
| 1574 | 0, 0, |
| 1575 | 0, 0 } |
| 1576 | }, |
| 1577 | { PINMUX_CFG_REG("HIZCRB", 0xa405015a, 16, 1) { |
| 1578 | 0, 0, |
| 1579 | 0, 0, |
| 1580 | 0, 0, |
| 1581 | 0, 0, |
| 1582 | 0, 0, |
| 1583 | 0, 0, |
| 1584 | 0, 0, |
| 1585 | 0, 0, |
| 1586 | 0, 0, |
| 1587 | 0, 0, |
| 1588 | 0, 0, |
| 1589 | HIZB4_SIUA, HIZB4_HIZ, |
| 1590 | 0, 0, |
| 1591 | 0, 0, |
| 1592 | HIZB1_VIO, HIZB1_HIZ, |
| 1593 | HIZB0_VIO, HIZB0_HIZ } |
| 1594 | }, |
| 1595 | { PINMUX_CFG_REG("HIZCRC", 0xa405015c, 16, 1) { |
| 1596 | HIZC15_IRQ7, HIZC15_HIZ, |
| 1597 | HIZC14_IRQ6, HIZC14_HIZ, |
| 1598 | HIZC13_IRQ5, HIZC13_HIZ, |
| 1599 | HIZC12_IRQ4, HIZC12_HIZ, |
| 1600 | HIZC11_IRQ3, HIZC11_HIZ, |
| 1601 | HIZC10_IRQ2, HIZC10_HIZ, |
| 1602 | HIZC9_IRQ1, HIZC9_HIZ, |
| 1603 | HIZC8_IRQ0, HIZC8_HIZ, |
| 1604 | 0, 0, |
| 1605 | 0, 0, |
| 1606 | 0, 0, |
| 1607 | 0, 0, |
| 1608 | 0, 0, |
| 1609 | 0, 0, |
| 1610 | 0, 0, |
| 1611 | 0, 0 } |
| 1612 | }, |
| 1613 | { PINMUX_CFG_REG("MSELCRB", 0xa4050182, 16, 1) { |
| 1614 | 0, 0, |
| 1615 | 0, 0, |
| 1616 | 0, 0, |
| 1617 | 0, 0, |
| 1618 | 0, 0, |
| 1619 | 0, 0, |
| 1620 | MSELB9_VIO, MSELB9_VIO2, |
| 1621 | MSELB8_RGB, MSELB8_SYS, |
| 1622 | 0, 0, |
| 1623 | 0, 0, |
| 1624 | 0, 0, |
| 1625 | 0, 0, |
| 1626 | 0, 0, |
| 1627 | 0, 0, |
| 1628 | 0, 0, |
| 1629 | 0, 0 } |
| 1630 | }, |
| 1631 | {} |
| 1632 | }; |
| 1633 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 1634 | static const struct pinmux_data_reg pinmux_data_regs[] = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1635 | { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { |
| 1636 | PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, |
| 1637 | PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } |
| 1638 | }, |
| 1639 | { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) { |
| 1640 | PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA, |
| 1641 | PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA } |
| 1642 | }, |
| 1643 | { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) { |
| 1644 | PTC7_DATA, 0, PTC5_DATA, PTC4_DATA, |
| 1645 | PTC3_DATA, PTC2_DATA, 0, PTC0_DATA } |
| 1646 | }, |
| 1647 | { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) { |
| 1648 | PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA, |
| 1649 | PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA } |
| 1650 | }, |
| 1651 | { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) { |
| 1652 | PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA, |
| 1653 | 0, 0, PTE1_DATA, PTE0_DATA } |
| 1654 | }, |
| 1655 | { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) { |
| 1656 | 0, PTF6_DATA, PTF5_DATA, PTF4_DATA, |
| 1657 | PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA } |
| 1658 | }, |
| 1659 | { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) { |
| 1660 | 0, 0, 0, PTG4_DATA, |
| 1661 | PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA } |
| 1662 | }, |
| 1663 | { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) { |
| 1664 | PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA, |
| 1665 | PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA } |
| 1666 | }, |
| 1667 | { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) { |
| 1668 | PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0, |
| 1669 | 0, 0, PTJ1_DATA, PTJ0_DATA } |
| 1670 | }, |
| 1671 | { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) { |
| 1672 | 0, PTK6_DATA, PTK5_DATA, PTK4_DATA, |
| 1673 | PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA } |
| 1674 | }, |
| 1675 | { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) { |
| 1676 | PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA, |
| 1677 | PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA } |
| 1678 | }, |
| 1679 | { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) { |
| 1680 | PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA, |
| 1681 | PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA } |
| 1682 | }, |
| 1683 | { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) { |
| 1684 | PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA, |
| 1685 | PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA } |
| 1686 | }, |
| 1687 | { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) { |
| 1688 | 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA, |
| 1689 | PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA } |
| 1690 | }, |
| 1691 | { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) { |
| 1692 | 0, 0, 0, PTR4_DATA, |
| 1693 | PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA } |
| 1694 | }, |
| 1695 | { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) { |
| 1696 | 0, 0, 0, PTS4_DATA, |
| 1697 | PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA } |
| 1698 | }, |
| 1699 | { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) { |
| 1700 | 0, 0, 0, PTT4_DATA, |
| 1701 | PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA } |
| 1702 | }, |
| 1703 | { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) { |
| 1704 | 0, 0, 0, PTU4_DATA, |
| 1705 | PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA } |
| 1706 | }, |
| 1707 | { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) { |
| 1708 | 0, 0, 0, PTV4_DATA, |
| 1709 | PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA } |
| 1710 | }, |
| 1711 | { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) { |
| 1712 | 0, PTW6_DATA, PTW5_DATA, PTW4_DATA, |
| 1713 | PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA } |
| 1714 | }, |
| 1715 | { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) { |
| 1716 | 0, PTX6_DATA, PTX5_DATA, PTX4_DATA, |
| 1717 | PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA } |
| 1718 | }, |
| 1719 | { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) { |
| 1720 | 0, PTY6_DATA, PTY5_DATA, PTY4_DATA, |
| 1721 | PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA } |
| 1722 | }, |
| 1723 | { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) { |
| 1724 | 0, 0, PTZ5_DATA, PTZ4_DATA, |
| 1725 | PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA } |
| 1726 | }, |
| 1727 | { }, |
| 1728 | }; |
| 1729 | |
Laurent Pinchart | cd3c1be | 2013-02-16 18:47:05 +0100 | [diff] [blame] | 1730 | const struct sh_pfc_soc_info sh7722_pinmux_info = { |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1731 | .name = "sh7722_pfc", |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1732 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1733 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1734 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
| 1735 | |
Laurent Pinchart | a373ed0 | 2012-11-29 13:24:07 +0100 | [diff] [blame] | 1736 | .pins = pinmux_pins, |
| 1737 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
| 1738 | .func_gpios = pinmux_func_gpios, |
| 1739 | .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), |
Laurent Pinchart | d7a7ca5 | 2012-11-28 17:51:00 +0100 | [diff] [blame] | 1740 | |
Laurent Pinchart | f5e25ae | 2012-12-15 23:51:33 +0100 | [diff] [blame] | 1741 | .cfg_regs = pinmux_config_regs, |
| 1742 | .data_regs = pinmux_data_regs, |
| 1743 | |
| 1744 | .gpio_data = pinmux_data, |
| 1745 | .gpio_data_size = ARRAY_SIZE(pinmux_data), |
| 1746 | }; |