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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 1999,2001
4 *
5 * Author: J.E.J.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/kernel/voyager_smp.c
8 *
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
11 */
James Bottomley153f8052005-07-13 09:38:05 -040012#include <linux/module.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013#include <linux/mm.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/mc146818rtc.h>
17#include <linux/cache.h>
18#include <linux/interrupt.h>
19#include <linux/smp_lock.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/bootmem.h>
23#include <linux/completion.h>
24#include <asm/desc.h>
25#include <asm/voyager.h>
26#include <asm/vic.h>
27#include <asm/mtrr.h>
28#include <asm/pgalloc.h>
29#include <asm/tlbflush.h>
30#include <asm/arch_hooks.h>
Jeremy Fitzhardinge62111192006-12-07 02:14:02 +010031#include <asm/pda.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070032
Linus Torvalds1da177e2005-04-16 15:20:36 -070033/* TLB state -- visible externally, indexed physically */
34DEFINE_PER_CPU(struct tlb_state, cpu_tlbstate) ____cacheline_aligned = { &init_mm, 0 };
35
36/* CPU IRQ affinity -- set to all ones initially */
37static unsigned long cpu_irq_affinity[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = ~0UL };
38
39/* per CPU data structure (for /proc/cpuinfo et al), visible externally
40 * indexed physically */
41struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
James Bottomley153f8052005-07-13 09:38:05 -040042EXPORT_SYMBOL(cpu_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -070043
44/* physical ID of the CPU used to boot the system */
45unsigned char boot_cpu_id;
46
47/* The memory line addresses for the Quad CPIs */
48struct voyager_qic_cpi *voyager_quad_cpi_addr[NR_CPUS] __cacheline_aligned;
49
50/* The masks for the Extended VIC processors, filled in by cat_init */
51__u32 voyager_extended_vic_processors = 0;
52
53/* Masks for the extended Quad processors which cannot be VIC booted */
54__u32 voyager_allowed_boot_processors = 0;
55
56/* The mask for the Quad Processors (both extended and non-extended) */
57__u32 voyager_quad_processors = 0;
58
59/* Total count of live CPUs, used in process.c to display
60 * the CPU information and in irq.c for the per CPU irq
61 * activity count. Finally exported by i386_ksyms.c */
62static int voyager_extended_cpus = 1;
63
64/* Have we found an SMP box - used by time.c to do the profiling
65 interrupt for timeslicing; do not set to 1 until the per CPU timer
66 interrupt is active */
67int smp_found_config = 0;
68
69/* Used for the invalidate map that's also checked in the spinlock */
70static volatile unsigned long smp_invalidate_needed;
71
72/* Bitmask of currently online CPUs - used by setup.c for
73 /proc/cpuinfo, visible externally but still physical */
74cpumask_t cpu_online_map = CPU_MASK_NONE;
James Bottomley153f8052005-07-13 09:38:05 -040075EXPORT_SYMBOL(cpu_online_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -070076
77/* Bitmask of CPUs present in the system - exported by i386_syms.c, used
78 * by scheduler but indexed physically */
79cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
80
81
82/* The internal functions */
83static void send_CPI(__u32 cpuset, __u8 cpi);
84static void ack_CPI(__u8 cpi);
85static int ack_QIC_CPI(__u8 cpi);
86static void ack_special_QIC_CPI(__u8 cpi);
87static void ack_VIC_CPI(__u8 cpi);
88static void send_CPI_allbutself(__u8 cpi);
James Bottomleyc7717462006-10-12 22:21:16 -050089static void mask_vic_irq(unsigned int irq);
90static void unmask_vic_irq(unsigned int irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -070091static unsigned int startup_vic_irq(unsigned int irq);
92static void enable_local_vic_irq(unsigned int irq);
93static void disable_local_vic_irq(unsigned int irq);
94static void before_handle_vic_irq(unsigned int irq);
95static void after_handle_vic_irq(unsigned int irq);
96static void set_vic_irq_affinity(unsigned int irq, cpumask_t mask);
97static void ack_vic_irq(unsigned int irq);
98static void vic_enable_cpi(void);
99static void do_boot_cpu(__u8 cpuid);
100static void do_quad_bootstrap(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
102int hard_smp_processor_id(void);
Fernando Vazquez2654c082006-09-30 23:29:08 -0700103int safe_smp_processor_id(void);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104
105/* Inline functions */
106static inline void
107send_one_QIC_CPI(__u8 cpu, __u8 cpi)
108{
109 voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi =
110 (smp_processor_id() << 16) + cpi;
111}
112
113static inline void
114send_QIC_CPI(__u32 cpuset, __u8 cpi)
115{
116 int cpu;
117
118 for_each_online_cpu(cpu) {
119 if(cpuset & (1<<cpu)) {
120#ifdef VOYAGER_DEBUG
121 if(!cpu_isset(cpu, cpu_online_map))
122 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi, cpu));
123#endif
124 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
125 }
126 }
127}
128
129static inline void
David Howells7d12e782006-10-05 14:55:46 +0100130wrapper_smp_local_timer_interrupt(void)
Dominik Hackl6431e6a2005-05-24 19:29:46 -0700131{
132 irq_enter();
David Howells7d12e782006-10-05 14:55:46 +0100133 smp_local_timer_interrupt();
Dominik Hackl6431e6a2005-05-24 19:29:46 -0700134 irq_exit();
135}
136
137static inline void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138send_one_CPI(__u8 cpu, __u8 cpi)
139{
140 if(voyager_quad_processors & (1<<cpu))
141 send_one_QIC_CPI(cpu, cpi - QIC_CPI_OFFSET);
142 else
143 send_CPI(1<<cpu, cpi);
144}
145
146static inline void
147send_CPI_allbutself(__u8 cpi)
148{
149 __u8 cpu = smp_processor_id();
150 __u32 mask = cpus_addr(cpu_online_map)[0] & ~(1 << cpu);
151 send_CPI(mask, cpi);
152}
153
154static inline int
155is_cpu_quad(void)
156{
157 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
158 return ((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER);
159}
160
161static inline int
162is_cpu_extended(void)
163{
164 __u8 cpu = hard_smp_processor_id();
165
166 return(voyager_extended_vic_processors & (1<<cpu));
167}
168
169static inline int
170is_cpu_vic_boot(void)
171{
172 __u8 cpu = hard_smp_processor_id();
173
174 return(voyager_extended_vic_processors
175 & voyager_allowed_boot_processors & (1<<cpu));
176}
177
178
179static inline void
180ack_CPI(__u8 cpi)
181{
182 switch(cpi) {
183 case VIC_CPU_BOOT_CPI:
184 if(is_cpu_quad() && !is_cpu_vic_boot())
185 ack_QIC_CPI(cpi);
186 else
187 ack_VIC_CPI(cpi);
188 break;
189 case VIC_SYS_INT:
190 case VIC_CMN_INT:
191 /* These are slightly strange. Even on the Quad card,
192 * They are vectored as VIC CPIs */
193 if(is_cpu_quad())
194 ack_special_QIC_CPI(cpi);
195 else
196 ack_VIC_CPI(cpi);
197 break;
198 default:
199 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi);
200 break;
201 }
202}
203
204/* local variables */
205
206/* The VIC IRQ descriptors -- these look almost identical to the
207 * 8259 IRQs except that masks and things must be kept per processor
208 */
James Bottomleyc7717462006-10-12 22:21:16 -0500209static struct irq_chip vic_chip = {
210 .name = "VIC",
211 .startup = startup_vic_irq,
212 .mask = mask_vic_irq,
213 .unmask = unmask_vic_irq,
214 .set_affinity = set_vic_irq_affinity,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700215};
216
217/* used to count up as CPUs are brought on line (starts at 0) */
218static int cpucount = 0;
219
220/* steal a page from the bottom of memory for the trampoline and
221 * squirrel its address away here. This will be in kernel virtual
222 * space */
223static __u32 trampoline_base;
224
225/* The per cpu profile stuff - used in smp_local_timer_interrupt */
226static DEFINE_PER_CPU(int, prof_multiplier) = 1;
227static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
228static DEFINE_PER_CPU(int, prof_counter) = 1;
229
230/* the map used to check if a CPU has booted */
231static __u32 cpu_booted_map;
232
233/* the synchronize flag used to hold all secondary CPUs spinning in
234 * a tight loop until the boot sequence is ready for them */
235static cpumask_t smp_commenced_mask = CPU_MASK_NONE;
236
237/* This is for the new dynamic CPU boot code */
238cpumask_t cpu_callin_map = CPU_MASK_NONE;
239cpumask_t cpu_callout_map = CPU_MASK_NONE;
James Bottomley153f8052005-07-13 09:38:05 -0400240EXPORT_SYMBOL(cpu_callout_map);
Andrew Morton7a8ef1c2006-02-10 01:51:08 -0800241cpumask_t cpu_possible_map = CPU_MASK_NONE;
Zwane Mwaikambo4ad8d382005-09-03 15:56:51 -0700242EXPORT_SYMBOL(cpu_possible_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243
244/* The per processor IRQ masks (these are usually kept in sync) */
245static __u16 vic_irq_mask[NR_CPUS] __cacheline_aligned;
246
247/* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
248static __u16 vic_irq_enable_mask[NR_CPUS] __cacheline_aligned = { 0 };
249
250/* Lock for enable/disable of VIC interrupts */
251static __cacheline_aligned DEFINE_SPINLOCK(vic_irq_lock);
252
253/* The boot processor is correctly set up in PC mode when it
254 * comes up, but the secondaries need their master/slave 8259
255 * pairs initializing correctly */
256
257/* Interrupt counters (per cpu) and total - used to try to
258 * even up the interrupt handling routines */
259static long vic_intr_total = 0;
260static long vic_intr_count[NR_CPUS] __cacheline_aligned = { 0 };
261static unsigned long vic_tick[NR_CPUS] __cacheline_aligned = { 0 };
262
263/* Since we can only use CPI0, we fake all the other CPIs */
264static unsigned long vic_cpi_mailbox[NR_CPUS] __cacheline_aligned;
265
266/* debugging routine to read the isr of the cpu's pic */
267static inline __u16
268vic_read_isr(void)
269{
270 __u16 isr;
271
272 outb(0x0b, 0xa0);
273 isr = inb(0xa0) << 8;
274 outb(0x0b, 0x20);
275 isr |= inb(0x20);
276
277 return isr;
278}
279
280static __init void
281qic_setup(void)
282{
283 if(!is_cpu_quad()) {
284 /* not a quad, no setup */
285 return;
286 }
287 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
288 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
289
290 if(is_cpu_extended()) {
291 /* the QIC duplicate of the VIC base register */
292 outb(VIC_DEFAULT_CPI_BASE, QIC_VIC_CPI_BASE_REGISTER);
293 outb(QIC_DEFAULT_CPI_BASE, QIC_CPI_BASE_REGISTER);
294
295 /* FIXME: should set up the QIC timer and memory parity
296 * error vectors here */
297 }
298}
299
300static __init void
301vic_setup_pic(void)
302{
303 outb(1, VIC_REDIRECT_REGISTER_1);
304 /* clear the claim registers for dynamic routing */
305 outb(0, VIC_CLAIM_REGISTER_0);
306 outb(0, VIC_CLAIM_REGISTER_1);
307
308 outb(0, VIC_PRIORITY_REGISTER);
309 /* Set the Primary and Secondary Microchannel vector
310 * bases to be the same as the ordinary interrupts
311 *
312 * FIXME: This would be more efficient using separate
313 * vectors. */
314 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
315 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
316 /* Now initiallise the master PIC belonging to this CPU by
317 * sending the four ICWs */
318
319 /* ICW1: level triggered, ICW4 needed */
320 outb(0x19, 0x20);
321
322 /* ICW2: vector base */
323 outb(FIRST_EXTERNAL_VECTOR, 0x21);
324
325 /* ICW3: slave at line 2 */
326 outb(0x04, 0x21);
327
328 /* ICW4: 8086 mode */
329 outb(0x01, 0x21);
330
331 /* now the same for the slave PIC */
332
333 /* ICW1: level trigger, ICW4 needed */
334 outb(0x19, 0xA0);
335
336 /* ICW2: slave vector base */
337 outb(FIRST_EXTERNAL_VECTOR + 8, 0xA1);
338
339 /* ICW3: slave ID */
340 outb(0x02, 0xA1);
341
342 /* ICW4: 8086 mode */
343 outb(0x01, 0xA1);
344}
345
346static void
347do_quad_bootstrap(void)
348{
349 if(is_cpu_quad() && is_cpu_vic_boot()) {
350 int i;
351 unsigned long flags;
352 __u8 cpuid = hard_smp_processor_id();
353
354 local_irq_save(flags);
355
356 for(i = 0; i<4; i++) {
357 /* FIXME: this would be >>3 &0x7 on the 32 way */
358 if(((cpuid >> 2) & 0x03) == i)
359 /* don't lower our own mask! */
360 continue;
361
362 /* masquerade as local Quad CPU */
363 outb(QIC_CPUID_ENABLE | i, QIC_PROCESSOR_ID);
364 /* enable the startup CPI */
365 outb(QIC_BOOT_CPI_MASK, QIC_MASK_REGISTER1);
366 /* restore cpu id */
367 outb(0, QIC_PROCESSOR_ID);
368 }
369 local_irq_restore(flags);
370 }
371}
372
373
374/* Set up all the basic stuff: read the SMP config and make all the
375 * SMP information reflect only the boot cpu. All others will be
376 * brought on-line later. */
377void __init
378find_smp_config(void)
379{
380 int i;
381
382 boot_cpu_id = hard_smp_processor_id();
383
384 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id);
385
386 /* initialize the CPU structures (moved from smp_boot_cpus) */
387 for(i=0; i<NR_CPUS; i++) {
388 cpu_irq_affinity[i] = ~0;
389 }
390 cpu_online_map = cpumask_of_cpu(boot_cpu_id);
391
392 /* The boot CPU must be extended */
393 voyager_extended_vic_processors = 1<<boot_cpu_id;
394 /* initially, all of the first 8 cpu's can boot */
395 voyager_allowed_boot_processors = 0xff;
396 /* set up everything for just this CPU, we can alter
397 * this as we start the other CPUs later */
398 /* now get the CPU disposition from the extended CMOS */
399 cpus_addr(phys_cpu_present_map)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
400 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
401 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 2) << 16;
402 cpus_addr(phys_cpu_present_map)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 3) << 24;
James Bottomleyf68a1062006-02-24 13:04:11 -0800403 cpu_possible_map = phys_cpu_present_map;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map)[0]);
405 /* Here we set up the VIC to enable SMP */
406 /* enable the CPIs by writing the base vector to their register */
407 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
408 outb(1, VIC_REDIRECT_REGISTER_1);
409 /* set the claim registers for static routing --- Boot CPU gets
410 * all interrupts untill all other CPUs started */
411 outb(0xff, VIC_CLAIM_REGISTER_0);
412 outb(0xff, VIC_CLAIM_REGISTER_1);
413 /* Set the Primary and Secondary Microchannel vector
414 * bases to be the same as the ordinary interrupts
415 *
416 * FIXME: This would be more efficient using separate
417 * vectors. */
418 outb(FIRST_EXTERNAL_VECTOR, VIC_PRIMARY_MC_BASE);
419 outb(FIRST_EXTERNAL_VECTOR, VIC_SECONDARY_MC_BASE);
420
421 /* Finally tell the firmware that we're driving */
422 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT) | VOYAGER_IN_CONTROL_FLAG,
423 VOYAGER_SUS_IN_CONTROL_PORT);
424
425 current_thread_info()->cpu = boot_cpu_id;
Jeremy Fitzhardinge62111192006-12-07 02:14:02 +0100426 write_pda(cpu_number, boot_cpu_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427}
428
429/*
430 * The bootstrap kernel entry code has set these up. Save them
431 * for a given CPU, id is physical */
432void __init
433smp_store_cpu_info(int id)
434{
435 struct cpuinfo_x86 *c=&cpu_data[id];
436
437 *c = boot_cpu_data;
438
439 identify_cpu(c);
440}
441
442/* set up the trampoline and return the physical address of the code */
443static __u32 __init
444setup_trampoline(void)
445{
446 /* these two are global symbols in trampoline.S */
447 extern __u8 trampoline_end[];
448 extern __u8 trampoline_data[];
449
450 memcpy((__u8 *)trampoline_base, trampoline_data,
451 trampoline_end - trampoline_data);
452 return virt_to_phys((__u8 *)trampoline_base);
453}
454
455/* Routine initially called when a non-boot CPU is brought online */
456static void __init
457start_secondary(void *unused)
458{
459 __u8 cpuid = hard_smp_processor_id();
460 /* external functions not defined in the headers */
461 extern void calibrate_delay(void);
462
Jeremy Fitzhardinge62111192006-12-07 02:14:02 +0100463 secondary_cpu_init();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700464
465 /* OK, we're in the routine */
466 ack_CPI(VIC_CPU_BOOT_CPI);
467
468 /* setup the 8259 master slave pair belonging to this CPU ---
469 * we won't actually receive any until the boot CPU
470 * relinquishes it's static routing mask */
471 vic_setup_pic();
472
473 qic_setup();
474
475 if(is_cpu_quad() && !is_cpu_vic_boot()) {
476 /* clear the boot CPI */
477 __u8 dummy;
478
479 dummy = voyager_quad_cpi_addr[cpuid]->qic_cpi[VIC_CPU_BOOT_CPI].cpi;
480 printk("read dummy %d\n", dummy);
481 }
482
483 /* lower the mask to receive CPIs */
484 vic_enable_cpi();
485
486 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid, &cpuid));
487
488 /* enable interrupts */
489 local_irq_enable();
490
491 /* get our bogomips */
492 calibrate_delay();
493
494 /* save our processor parameters */
495 smp_store_cpu_info(cpuid);
496
497 /* if we're a quad, we may need to bootstrap other CPUs */
498 do_quad_bootstrap();
499
500 /* FIXME: this is rather a poor hack to prevent the CPU
501 * activating softirqs while it's supposed to be waiting for
502 * permission to proceed. Without this, the new per CPU stuff
503 * in the softirqs will fail */
504 local_irq_disable();
505 cpu_set(cpuid, cpu_callin_map);
506
507 /* signal that we're done */
508 cpu_booted_map = 1;
509
510 while (!cpu_isset(cpuid, smp_commenced_mask))
511 rep_nop();
512 local_irq_enable();
513
514 local_flush_tlb();
515
516 cpu_set(cpuid, cpu_online_map);
517 wmb();
518 cpu_idle();
519}
520
521
522/* Routine to kick start the given CPU and wait for it to report ready
523 * (or timeout in startup). When this routine returns, the requested
524 * CPU is either fully running and configured or known to be dead.
525 *
526 * We call this routine sequentially 1 CPU at a time, so no need for
527 * locking */
528
529static void __init
530do_boot_cpu(__u8 cpu)
531{
532 struct task_struct *idle;
533 int timeout;
534 unsigned long flags;
535 int quad_boot = (1<<cpu) & voyager_quad_processors
536 & ~( voyager_extended_vic_processors
537 & voyager_allowed_boot_processors);
538
539 /* For the 486, we can't use the 4Mb page table trick, so
540 * must map a region of memory */
541#ifdef CONFIG_M486
542 int i;
543 unsigned long *page_table_copies = (unsigned long *)
544 __get_free_page(GFP_KERNEL);
545#endif
546 pgd_t orig_swapper_pg_dir0;
547
548 /* This is an area in head.S which was used to set up the
549 * initial kernel stack. We need to alter this to give the
550 * booting CPU a new stack (taken from its idle process) */
551 extern struct {
552 __u8 *esp;
553 unsigned short ss;
554 } stack_start;
555 /* This is the format of the CPI IDT gate (in real mode) which
556 * we're hijacking to boot the CPU */
557 union IDTFormat {
558 struct seg {
559 __u16 Offset;
560 __u16 Segment;
561 } idt;
562 __u32 val;
563 } hijack_source;
564
565 __u32 *hijack_vector;
566 __u32 start_phys_address = setup_trampoline();
567
568 /* There's a clever trick to this: The linux trampoline is
569 * compiled to begin at absolute location zero, so make the
570 * address zero but have the data segment selector compensate
571 * for the actual address */
572 hijack_source.idt.Offset = start_phys_address & 0x000F;
573 hijack_source.idt.Segment = (start_phys_address >> 4) & 0xFFFF;
574
575 cpucount++;
576 idle = fork_idle(cpu);
577 if(IS_ERR(idle))
578 panic("failed fork for CPU%d", cpu);
579 idle->thread.eip = (unsigned long) start_secondary;
580 /* init_tasks (in sched.c) is indexed logically */
581 stack_start.esp = (void *) idle->thread.esp;
582
Jeremy Fitzhardinge62111192006-12-07 02:14:02 +0100583 /* Pre-allocate and initialize the CPU's GDT and PDA so it
584 doesn't have to do any memory allocation during the
585 delicate CPU-bringup phase. */
586 if (!init_gdt(cpu, idle)) {
587 printk(KERN_INFO "Couldn't allocate GDT/PDA for CPU %d\n", cpu);
588 cpucount--;
589 return;
590 }
591
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592 irq_ctx_init(cpu);
593
594 /* Note: Don't modify initial ss override */
595 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu,
596 (unsigned long)hijack_source.val, hijack_source.idt.Segment,
597 hijack_source.idt.Offset, stack_start.esp));
598 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
599 * (so that the booting CPU can find start_32 */
600 orig_swapper_pg_dir0 = swapper_pg_dir[0];
601#ifdef CONFIG_M486
602 if(page_table_copies == NULL)
603 panic("No free memory for 486 page tables\n");
604 for(i = 0; i < PAGE_SIZE/sizeof(unsigned long); i++)
605 page_table_copies[i] = (i * PAGE_SIZE)
606 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
607
608 ((unsigned long *)swapper_pg_dir)[0] =
609 ((virt_to_phys(page_table_copies)) & PAGE_MASK)
610 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
611#else
612 ((unsigned long *)swapper_pg_dir)[0] =
613 (virt_to_phys(pg0) & PAGE_MASK)
614 | _PAGE_RW | _PAGE_USER | _PAGE_PRESENT;
615#endif
616
617 if(quad_boot) {
618 printk("CPU %d: non extended Quad boot\n", cpu);
619 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + QIC_DEFAULT_CPI_BASE)*4);
620 *hijack_vector = hijack_source.val;
621 } else {
622 printk("CPU%d: extended VIC boot\n", cpu);
623 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_CPI + VIC_DEFAULT_CPI_BASE)*4);
624 *hijack_vector = hijack_source.val;
625 /* VIC errata, may also receive interrupt at this address */
626 hijack_vector = (__u32 *)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI + VIC_DEFAULT_CPI_BASE)*4);
627 *hijack_vector = hijack_source.val;
628 }
629 /* All non-boot CPUs start with interrupts fully masked. Need
630 * to lower the mask of the CPI we're about to send. We do
631 * this in the VIC by masquerading as the processor we're
632 * about to boot and lowering its interrupt mask */
633 local_irq_save(flags);
634 if(quad_boot) {
635 send_one_QIC_CPI(cpu, VIC_CPU_BOOT_CPI);
636 } else {
637 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
638 /* here we're altering registers belonging to `cpu' */
639
640 outb(VIC_BOOT_INTERRUPT_MASK, 0x21);
641 /* now go back to our original identity */
642 outb(boot_cpu_id, VIC_PROCESSOR_ID);
643
644 /* and boot the CPU */
645
646 send_CPI((1<<cpu), VIC_CPU_BOOT_CPI);
647 }
648 cpu_booted_map = 0;
649 local_irq_restore(flags);
650
651 /* now wait for it to become ready (or timeout) */
652 for(timeout = 0; timeout < 50000; timeout++) {
653 if(cpu_booted_map)
654 break;
655 udelay(100);
656 }
657 /* reset the page table */
658 swapper_pg_dir[0] = orig_swapper_pg_dir0;
659 local_flush_tlb();
660#ifdef CONFIG_M486
661 free_page((unsigned long)page_table_copies);
662#endif
663
664 if (cpu_booted_map) {
665 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
666 cpu, smp_processor_id()));
667
668 printk("CPU%d: ", cpu);
669 print_cpu_info(&cpu_data[cpu]);
670 wmb();
671 cpu_set(cpu, cpu_callout_map);
James Bottomley3c101cf2006-06-26 21:33:09 -0500672 cpu_set(cpu, cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 }
674 else {
675 printk("CPU%d FAILED TO BOOT: ", cpu);
676 if (*((volatile unsigned char *)phys_to_virt(start_phys_address))==0xA5)
677 printk("Stuck.\n");
678 else
679 printk("Not responding.\n");
680
681 cpucount--;
682 }
683}
684
685void __init
686smp_boot_cpus(void)
687{
688 int i;
689
690 /* CAT BUS initialisation must be done after the memory */
691 /* FIXME: The L4 has a catbus too, it just needs to be
692 * accessed in a totally different way */
693 if(voyager_level == 5) {
694 voyager_cat_init();
695
696 /* now that the cat has probed the Voyager System Bus, sanity
697 * check the cpu map */
698 if( ((voyager_quad_processors | voyager_extended_vic_processors)
699 & cpus_addr(phys_cpu_present_map)[0]) != cpus_addr(phys_cpu_present_map)[0]) {
700 /* should panic */
701 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
702 }
703 } else if(voyager_level == 4)
704 voyager_extended_vic_processors = cpus_addr(phys_cpu_present_map)[0];
705
706 /* this sets up the idle task to run on the current cpu */
707 voyager_extended_cpus = 1;
708 /* Remove the global_irq_holder setting, it triggers a BUG() on
709 * schedule at the moment */
710 //global_irq_holder = boot_cpu_id;
711
712 /* FIXME: Need to do something about this but currently only works
713 * on CPUs with a tsc which none of mine have.
714 smp_tune_scheduling();
715 */
716 smp_store_cpu_info(boot_cpu_id);
717 printk("CPU%d: ", boot_cpu_id);
718 print_cpu_info(&cpu_data[boot_cpu_id]);
719
720 if(is_cpu_quad()) {
721 /* booting on a Quad CPU */
722 printk("VOYAGER SMP: Boot CPU is Quad\n");
723 qic_setup();
724 do_quad_bootstrap();
725 }
726
727 /* enable our own CPIs */
728 vic_enable_cpi();
729
730 cpu_set(boot_cpu_id, cpu_online_map);
731 cpu_set(boot_cpu_id, cpu_callout_map);
732
733 /* loop over all the extended VIC CPUs and boot them. The
734 * Quad CPUs must be bootstrapped by their extended VIC cpu */
735 for(i = 0; i < NR_CPUS; i++) {
736 if(i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map))
737 continue;
738 do_boot_cpu(i);
739 /* This udelay seems to be needed for the Quad boots
740 * don't remove unless you know what you're doing */
741 udelay(1000);
742 }
743 /* we could compute the total bogomips here, but why bother?,
744 * Code added from smpboot.c */
745 {
746 unsigned long bogosum = 0;
747 for (i = 0; i < NR_CPUS; i++)
748 if (cpu_isset(i, cpu_online_map))
749 bogosum += cpu_data[i].loops_per_jiffy;
750 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
751 cpucount+1,
752 bogosum/(500000/HZ),
753 (bogosum/(5000/HZ))%100);
754 }
755 voyager_extended_cpus = hweight32(voyager_extended_vic_processors);
756 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus, num_booting_cpus() - voyager_extended_cpus);
757 /* that's it, switch to symmetric mode */
758 outb(0, VIC_PRIORITY_REGISTER);
759 outb(0, VIC_CLAIM_REGISTER_0);
760 outb(0, VIC_CLAIM_REGISTER_1);
761
762 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
763}
764
765/* Reload the secondary CPUs task structure (this function does not
766 * return ) */
767void __init
768initialize_secondary(void)
769{
770#if 0
771 // AC kernels only
772 set_current(hard_get_current());
773#endif
774
775 /*
James Bottomley9ee79a32007-01-22 09:18:31 -0600776 * switch to the per CPU GDT we already set up
777 * in do_boot_cpu()
778 */
779 cpu_set_gdt(current_thread_info()->cpu);
780
781 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 * We don't actually need to load the full TSS,
783 * basically just the stack pointer and the eip.
784 */
785
786 asm volatile(
787 "movl %0,%%esp\n\t"
788 "jmp *%1"
789 :
790 :"r" (current->thread.esp),"r" (current->thread.eip));
791}
792
793/* handle a Voyager SYS_INT -- If we don't, the base board will
794 * panic the system.
795 *
796 * System interrupts occur because some problem was detected on the
797 * various busses. To find out what you have to probe all the
798 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
799fastcall void
800smp_vic_sys_interrupt(struct pt_regs *regs)
801{
802 ack_CPI(VIC_SYS_INT);
David Howells7d12e782006-10-05 14:55:46 +0100803 printk("Voyager SYSTEM INTERRUPT\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700804}
805
806/* Handle a voyager CMN_INT; These interrupts occur either because of
807 * a system status change or because a single bit memory error
808 * occurred. FIXME: At the moment, ignore all this. */
809fastcall void
810smp_vic_cmn_interrupt(struct pt_regs *regs)
811{
812 static __u8 in_cmn_int = 0;
813 static DEFINE_SPINLOCK(cmn_int_lock);
814
815 /* common ints are broadcast, so make sure we only do this once */
816 _raw_spin_lock(&cmn_int_lock);
817 if(in_cmn_int)
818 goto unlock_end;
819
820 in_cmn_int++;
821 _raw_spin_unlock(&cmn_int_lock);
822
823 VDEBUG(("Voyager COMMON INTERRUPT\n"));
824
825 if(voyager_level == 5)
826 voyager_cat_do_common_interrupt();
827
828 _raw_spin_lock(&cmn_int_lock);
829 in_cmn_int = 0;
830 unlock_end:
831 _raw_spin_unlock(&cmn_int_lock);
832 ack_CPI(VIC_CMN_INT);
833}
834
835/*
836 * Reschedule call back. Nothing to do, all the work is done
837 * automatically when we return from the interrupt. */
838static void
839smp_reschedule_interrupt(void)
840{
841 /* do nothing */
842}
843
844static struct mm_struct * flush_mm;
845static unsigned long flush_va;
846static DEFINE_SPINLOCK(tlbstate_lock);
847#define FLUSH_ALL 0xffffffff
848
849/*
850 * We cannot call mmdrop() because we are in interrupt context,
851 * instead update mm->cpu_vm_mask.
852 *
853 * We need to reload %cr3 since the page tables may be going
854 * away from under us..
855 */
856static inline void
857leave_mm (unsigned long cpu)
858{
859 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
860 BUG();
861 cpu_clear(cpu, per_cpu(cpu_tlbstate, cpu).active_mm->cpu_vm_mask);
862 load_cr3(swapper_pg_dir);
863}
864
865
866/*
867 * Invalidate call-back
868 */
869static void
870smp_invalidate_interrupt(void)
871{
872 __u8 cpu = smp_processor_id();
873
874 if (!test_bit(cpu, &smp_invalidate_needed))
875 return;
876 /* This will flood messages. Don't uncomment unless you see
877 * Problems with cross cpu invalidation
878 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
879 smp_processor_id()));
880 */
881
882 if (flush_mm == per_cpu(cpu_tlbstate, cpu).active_mm) {
883 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK) {
884 if (flush_va == FLUSH_ALL)
885 local_flush_tlb();
886 else
887 __flush_tlb_one(flush_va);
888 } else
889 leave_mm(cpu);
890 }
891 smp_mb__before_clear_bit();
892 clear_bit(cpu, &smp_invalidate_needed);
893 smp_mb__after_clear_bit();
894}
895
896/* All the new flush operations for 2.4 */
897
898
899/* This routine is called with a physical cpu mask */
900static void
901flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
902 unsigned long va)
903{
904 int stuck = 50000;
905
906 if (!cpumask)
907 BUG();
908 if ((cpumask & cpus_addr(cpu_online_map)[0]) != cpumask)
909 BUG();
910 if (cpumask & (1 << smp_processor_id()))
911 BUG();
912 if (!mm)
913 BUG();
914
915 spin_lock(&tlbstate_lock);
916
917 flush_mm = mm;
918 flush_va = va;
919 atomic_set_mask(cpumask, &smp_invalidate_needed);
920 /*
921 * We have to send the CPI only to
922 * CPUs affected.
923 */
924 send_CPI(cpumask, VIC_INVALIDATE_CPI);
925
926 while (smp_invalidate_needed) {
927 mb();
928 if(--stuck == 0) {
929 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
930 break;
931 }
932 }
933
934 /* Uncomment only to debug invalidation problems
935 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
936 */
937
938 flush_mm = NULL;
939 flush_va = 0;
940 spin_unlock(&tlbstate_lock);
941}
942
943void
944flush_tlb_current_task(void)
945{
946 struct mm_struct *mm = current->mm;
947 unsigned long cpu_mask;
948
949 preempt_disable();
950
951 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
952 local_flush_tlb();
953 if (cpu_mask)
954 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
955
956 preempt_enable();
957}
958
959
960void
961flush_tlb_mm (struct mm_struct * mm)
962{
963 unsigned long cpu_mask;
964
965 preempt_disable();
966
967 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
968
969 if (current->active_mm == mm) {
970 if (current->mm)
971 local_flush_tlb();
972 else
973 leave_mm(smp_processor_id());
974 }
975 if (cpu_mask)
976 flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
977
978 preempt_enable();
979}
980
981void flush_tlb_page(struct vm_area_struct * vma, unsigned long va)
982{
983 struct mm_struct *mm = vma->vm_mm;
984 unsigned long cpu_mask;
985
986 preempt_disable();
987
988 cpu_mask = cpus_addr(mm->cpu_vm_mask)[0] & ~(1 << smp_processor_id());
989 if (current->active_mm == mm) {
990 if(current->mm)
991 __flush_tlb_one(va);
992 else
993 leave_mm(smp_processor_id());
994 }
995
996 if (cpu_mask)
997 flush_tlb_others(cpu_mask, mm, va);
998
999 preempt_enable();
1000}
James Bottomley153f8052005-07-13 09:38:05 -04001001EXPORT_SYMBOL(flush_tlb_page);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001002
1003/* enable the requested IRQs */
1004static void
1005smp_enable_irq_interrupt(void)
1006{
1007 __u8 irq;
1008 __u8 cpu = get_cpu();
1009
1010 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu,
1011 vic_irq_enable_mask[cpu]));
1012
1013 spin_lock(&vic_irq_lock);
1014 for(irq = 0; irq < 16; irq++) {
1015 if(vic_irq_enable_mask[cpu] & (1<<irq))
1016 enable_local_vic_irq(irq);
1017 }
1018 vic_irq_enable_mask[cpu] = 0;
1019 spin_unlock(&vic_irq_lock);
1020
1021 put_cpu_no_resched();
1022}
1023
1024/*
1025 * CPU halt call-back
1026 */
1027static void
1028smp_stop_cpu_function(void *dummy)
1029{
1030 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1031 cpu_clear(smp_processor_id(), cpu_online_map);
1032 local_irq_disable();
1033 for(;;)
Zachary Amsdenf2ab4462005-09-03 15:56:42 -07001034 halt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001035}
1036
1037static DEFINE_SPINLOCK(call_lock);
1038
1039struct call_data_struct {
1040 void (*func) (void *info);
1041 void *info;
1042 volatile unsigned long started;
1043 volatile unsigned long finished;
1044 int wait;
1045};
1046
1047static struct call_data_struct * call_data;
1048
1049/* execute a thread on a new CPU. The function to be called must be
1050 * previously set up. This is used to schedule a function for
1051 * execution on all CPU's - set up the function then broadcast a
1052 * function_interrupt CPI to come here on each CPU */
1053static void
1054smp_call_function_interrupt(void)
1055{
1056 void (*func) (void *info) = call_data->func;
1057 void *info = call_data->info;
1058 /* must take copy of wait because call_data may be replaced
1059 * unless the function is waiting for us to finish */
1060 int wait = call_data->wait;
1061 __u8 cpu = smp_processor_id();
1062
1063 /*
1064 * Notify initiating CPU that I've grabbed the data and am
1065 * about to execute the function
1066 */
1067 mb();
1068 if(!test_and_clear_bit(cpu, &call_data->started)) {
1069 /* If the bit wasn't set, this could be a replay */
1070 printk(KERN_WARNING "VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu);
1071 return;
1072 }
1073 /*
1074 * At this point the info structure may be out of scope unless wait==1
1075 */
1076 irq_enter();
1077 (*func)(info);
1078 irq_exit();
1079 if (wait) {
1080 mb();
1081 clear_bit(cpu, &call_data->finished);
1082 }
1083}
1084
James Bottomley0293ca82007-04-30 11:24:05 -05001085static int
1086__smp_call_function_mask (void (*func) (void *info), void *info, int retry,
1087 int wait, __u32 mask)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088{
1089 struct call_data_struct data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090
1091 mask &= ~(1<<smp_processor_id());
1092
1093 if (!mask)
1094 return 0;
1095
1096 /* Can deadlock when called with interrupts disabled */
1097 WARN_ON(irqs_disabled());
1098
1099 data.func = func;
1100 data.info = info;
1101 data.started = mask;
1102 data.wait = wait;
1103 if (wait)
1104 data.finished = mask;
1105
1106 spin_lock(&call_lock);
1107 call_data = &data;
1108 wmb();
1109 /* Send a message to all other CPUs and wait for them to respond */
James Bottomley0293ca82007-04-30 11:24:05 -05001110 send_CPI(mask, VIC_CALL_FUNCTION_CPI);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001111
1112 /* Wait for response */
1113 while (data.started)
1114 barrier();
1115
1116 if (wait)
1117 while (data.finished)
1118 barrier();
1119
1120 spin_unlock(&call_lock);
1121
1122 return 0;
1123}
James Bottomley0293ca82007-04-30 11:24:05 -05001124
1125/* Call this function on all CPUs using the function_interrupt above
1126 <func> The function to run. This must be fast and non-blocking.
1127 <info> An arbitrary pointer to pass to the function.
1128 <retry> If true, keep retrying until ready.
1129 <wait> If true, wait until function has completed on other CPUs.
1130 [RETURNS] 0 on success, else a negative status code. Does not return until
1131 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1132*/
1133int
1134smp_call_function(void (*func) (void *info), void *info, int retry,
1135 int wait)
1136{
1137 __u32 mask = cpus_addr(cpu_online_map)[0];
1138
1139 return __smp_call_function_mask(func, info, retry, wait, mask);
1140}
James Bottomley153f8052005-07-13 09:38:05 -04001141EXPORT_SYMBOL(smp_call_function);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
James Bottomley0293ca82007-04-30 11:24:05 -05001143/*
1144 * smp_call_function_single - Run a function on another CPU
1145 * @func: The function to run. This must be fast and non-blocking.
1146 * @info: An arbitrary pointer to pass to the function.
1147 * @nonatomic: Currently unused.
1148 * @wait: If true, wait until function has completed on other CPUs.
1149 *
1150 * Retrurns 0 on success, else a negative status code.
1151 *
1152 * Does not return until the remote CPU is nearly ready to execute <func>
1153 * or is or has executed.
1154 */
1155
1156int
1157smp_call_function_single(int cpu, void (*func) (void *info), void *info,
1158 int nonatomic, int wait)
1159{
1160 __u32 mask = 1 << cpu;
1161
1162 return __smp_call_function_mask(func, info, nonatomic, wait, mask);
1163}
1164EXPORT_SYMBOL(smp_call_function_single);
1165
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166/* Sorry about the name. In an APIC based system, the APICs
1167 * themselves are programmed to send a timer interrupt. This is used
1168 * by linux to reschedule the processor. Voyager doesn't have this,
1169 * so we use the system clock to interrupt one processor, which in
1170 * turn, broadcasts a timer CPI to all the others --- we receive that
1171 * CPI here. We don't use this actually for counting so losing
1172 * ticks doesn't matter
1173 *
1174 * FIXME: For those CPU's which actually have a local APIC, we could
1175 * try to use it to trigger this interrupt instead of having to
1176 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1177 * no local APIC, so I can't do this
1178 *
1179 * This function is currently a placeholder and is unused in the code */
1180fastcall void
1181smp_apic_timer_interrupt(struct pt_regs *regs)
1182{
David Howells7d12e782006-10-05 14:55:46 +01001183 struct pt_regs *old_regs = set_irq_regs(regs);
1184 wrapper_smp_local_timer_interrupt();
1185 set_irq_regs(old_regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186}
1187
1188/* All of the QUAD interrupt GATES */
1189fastcall void
1190smp_qic_timer_interrupt(struct pt_regs *regs)
1191{
David Howells7d12e782006-10-05 14:55:46 +01001192 struct pt_regs *old_regs = set_irq_regs(regs);
James Bottomley81c06b12006-10-12 22:25:03 -05001193 ack_QIC_CPI(QIC_TIMER_CPI);
1194 wrapper_smp_local_timer_interrupt();
David Howells7d12e782006-10-05 14:55:46 +01001195 set_irq_regs(old_regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001196}
1197
1198fastcall void
1199smp_qic_invalidate_interrupt(struct pt_regs *regs)
1200{
1201 ack_QIC_CPI(QIC_INVALIDATE_CPI);
1202 smp_invalidate_interrupt();
1203}
1204
1205fastcall void
1206smp_qic_reschedule_interrupt(struct pt_regs *regs)
1207{
1208 ack_QIC_CPI(QIC_RESCHEDULE_CPI);
1209 smp_reschedule_interrupt();
1210}
1211
1212fastcall void
1213smp_qic_enable_irq_interrupt(struct pt_regs *regs)
1214{
1215 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI);
1216 smp_enable_irq_interrupt();
1217}
1218
1219fastcall void
1220smp_qic_call_function_interrupt(struct pt_regs *regs)
1221{
1222 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI);
1223 smp_call_function_interrupt();
1224}
1225
1226fastcall void
1227smp_vic_cpi_interrupt(struct pt_regs *regs)
1228{
David Howells7d12e782006-10-05 14:55:46 +01001229 struct pt_regs *old_regs = set_irq_regs(regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001230 __u8 cpu = smp_processor_id();
1231
1232 if(is_cpu_quad())
1233 ack_QIC_CPI(VIC_CPI_LEVEL0);
1234 else
1235 ack_VIC_CPI(VIC_CPI_LEVEL0);
1236
1237 if(test_and_clear_bit(VIC_TIMER_CPI, &vic_cpi_mailbox[cpu]))
David Howells7d12e782006-10-05 14:55:46 +01001238 wrapper_smp_local_timer_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 if(test_and_clear_bit(VIC_INVALIDATE_CPI, &vic_cpi_mailbox[cpu]))
1240 smp_invalidate_interrupt();
1241 if(test_and_clear_bit(VIC_RESCHEDULE_CPI, &vic_cpi_mailbox[cpu]))
1242 smp_reschedule_interrupt();
1243 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI, &vic_cpi_mailbox[cpu]))
1244 smp_enable_irq_interrupt();
1245 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI, &vic_cpi_mailbox[cpu]))
1246 smp_call_function_interrupt();
David Howells7d12e782006-10-05 14:55:46 +01001247 set_irq_regs(old_regs);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001248}
1249
1250static void
1251do_flush_tlb_all(void* info)
1252{
1253 unsigned long cpu = smp_processor_id();
1254
1255 __flush_tlb_all();
1256 if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_LAZY)
1257 leave_mm(cpu);
1258}
1259
1260
1261/* flush the TLB of every active CPU in the system */
1262void
1263flush_tlb_all(void)
1264{
1265 on_each_cpu(do_flush_tlb_all, 0, 1, 1);
1266}
1267
1268/* used to set up the trampoline for other CPUs when the memory manager
1269 * is sorted out */
1270void __init
1271smp_alloc_memory(void)
1272{
1273 trampoline_base = (__u32)alloc_bootmem_low_pages(PAGE_SIZE);
1274 if(__pa(trampoline_base) >= 0x93000)
1275 BUG();
1276}
1277
1278/* send a reschedule CPI to one CPU by physical CPU number*/
1279void
1280smp_send_reschedule(int cpu)
1281{
1282 send_one_CPI(cpu, VIC_RESCHEDULE_CPI);
1283}
1284
1285
1286int
1287hard_smp_processor_id(void)
1288{
1289 __u8 i;
1290 __u8 cpumask = inb(VIC_PROC_WHO_AM_I);
1291 if((cpumask & QUAD_IDENTIFIER) == QUAD_IDENTIFIER)
1292 return cpumask & 0x1F;
1293
1294 for(i = 0; i < 8; i++) {
1295 if(cpumask & (1<<i))
1296 return i;
1297 }
1298 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask);
1299 return 0;
1300}
1301
Fernando Vazquez2654c082006-09-30 23:29:08 -07001302int
1303safe_smp_processor_id(void)
1304{
1305 return hard_smp_processor_id();
1306}
1307
Linus Torvalds1da177e2005-04-16 15:20:36 -07001308/* broadcast a halt to all other CPUs */
1309void
1310smp_send_stop(void)
1311{
1312 smp_call_function(smp_stop_cpu_function, NULL, 1, 1);
1313}
1314
1315/* this function is triggered in time.c when a clock tick fires
1316 * we need to re-broadcast the tick to all CPUs */
1317void
James Bottomley81c06b12006-10-12 22:25:03 -05001318smp_vic_timer_interrupt(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001319{
1320 send_CPI_allbutself(VIC_TIMER_CPI);
David Howells7d12e782006-10-05 14:55:46 +01001321 smp_local_timer_interrupt();
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322}
1323
Linus Torvalds1da177e2005-04-16 15:20:36 -07001324/* local (per CPU) timer interrupt. It does both profiling and
1325 * process statistics/rescheduling.
1326 *
1327 * We do profiling in every local tick, statistics/rescheduling
1328 * happen only every 'profiling multiplier' ticks. The default
1329 * multiplier is 1 and it can be changed by writing the new multiplier
1330 * value into /proc/profile.
1331 */
1332void
David Howells7d12e782006-10-05 14:55:46 +01001333smp_local_timer_interrupt(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001334{
1335 int cpu = smp_processor_id();
1336 long weight;
1337
David Howells7d12e782006-10-05 14:55:46 +01001338 profile_tick(CPU_PROFILING);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001339 if (--per_cpu(prof_counter, cpu) <= 0) {
1340 /*
1341 * The multiplier may have changed since the last time we got
1342 * to this point as a result of the user writing to
1343 * /proc/profile. In this case we need to adjust the APIC
1344 * timer accordingly.
1345 *
1346 * Interrupts are already masked off at this point.
1347 */
1348 per_cpu(prof_counter,cpu) = per_cpu(prof_multiplier, cpu);
1349 if (per_cpu(prof_counter, cpu) !=
1350 per_cpu(prof_old_multiplier, cpu)) {
1351 /* FIXME: need to update the vic timer tick here */
1352 per_cpu(prof_old_multiplier, cpu) =
1353 per_cpu(prof_counter, cpu);
1354 }
1355
James Bottomley81c06b12006-10-12 22:25:03 -05001356 update_process_times(user_mode_vm(get_irq_regs()));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357 }
1358
1359 if( ((1<<cpu) & voyager_extended_vic_processors) == 0)
1360 /* only extended VIC processors participate in
1361 * interrupt distribution */
1362 return;
1363
1364 /*
1365 * We take the 'long' return path, and there every subsystem
1366 * grabs the apropriate locks (kernel lock/ irq lock).
1367 *
1368 * we might want to decouple profiling from the 'long path',
1369 * and do the profiling totally in assembly.
1370 *
1371 * Currently this isn't too much of an issue (performance wise),
1372 * we can take more than 100K local irqs per second on a 100 MHz P5.
1373 */
1374
1375 if((++vic_tick[cpu] & 0x7) != 0)
1376 return;
1377 /* get here every 16 ticks (about every 1/6 of a second) */
1378
1379 /* Change our priority to give someone else a chance at getting
1380 * the IRQ. The algorithm goes like this:
1381 *
1382 * In the VIC, the dynamically routed interrupt is always
1383 * handled by the lowest priority eligible (i.e. receiving
1384 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1385 * lowest processor number gets it.
1386 *
1387 * The priority of a CPU is controlled by a special per-CPU
1388 * VIC priority register which is 3 bits wide 0 being lowest
1389 * and 7 highest priority..
1390 *
1391 * Therefore we subtract the average number of interrupts from
1392 * the number we've fielded. If this number is negative, we
1393 * lower the activity count and if it is positive, we raise
1394 * it.
1395 *
1396 * I'm afraid this still leads to odd looking interrupt counts:
1397 * the totals are all roughly equal, but the individual ones
1398 * look rather skewed.
1399 *
1400 * FIXME: This algorithm is total crap when mixed with SMP
1401 * affinity code since we now try to even up the interrupt
1402 * counts when an affinity binding is keeping them on a
1403 * particular CPU*/
1404 weight = (vic_intr_count[cpu]*voyager_extended_cpus
1405 - vic_intr_total) >> 4;
1406 weight += 4;
1407 if(weight > 7)
1408 weight = 7;
1409 if(weight < 0)
1410 weight = 0;
1411
1412 outb((__u8)weight, VIC_PRIORITY_REGISTER);
1413
1414#ifdef VOYAGER_DEBUG
1415 if((vic_tick[cpu] & 0xFFF) == 0) {
1416 /* print this message roughly every 25 secs */
1417 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1418 cpu, vic_tick[cpu], weight);
1419 }
1420#endif
1421}
1422
1423/* setup the profiling timer */
1424int
1425setup_profiling_timer(unsigned int multiplier)
1426{
1427 int i;
1428
1429 if ( (!multiplier))
1430 return -EINVAL;
1431
1432 /*
1433 * Set the new multiplier for each CPU. CPUs don't start using the
1434 * new values until the next timer interrupt in which they do process
1435 * accounting.
1436 */
1437 for (i = 0; i < NR_CPUS; ++i)
1438 per_cpu(prof_multiplier, i) = multiplier;
1439
1440 return 0;
1441}
1442
James Bottomleyc7717462006-10-12 22:21:16 -05001443/* This is a bit of a mess, but forced on us by the genirq changes
1444 * there's no genirq handler that really does what voyager wants
1445 * so hack it up with the simple IRQ handler */
1446static void fastcall
1447handle_vic_irq(unsigned int irq, struct irq_desc *desc)
1448{
1449 before_handle_vic_irq(irq);
1450 handle_simple_irq(irq, desc);
1451 after_handle_vic_irq(irq);
1452}
1453
Linus Torvalds1da177e2005-04-16 15:20:36 -07001454
1455/* The CPIs are handled in the per cpu 8259s, so they must be
1456 * enabled to be received: FIX: enabling the CPIs in the early
1457 * boot sequence interferes with bug checking; enable them later
1458 * on in smp_init */
1459#define VIC_SET_GATE(cpi, vector) \
1460 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1461#define QIC_SET_GATE(cpi, vector) \
1462 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1463
1464void __init
1465smp_intr_init(void)
1466{
1467 int i;
1468
1469 /* initialize the per cpu irq mask to all disabled */
1470 for(i = 0; i < NR_CPUS; i++)
1471 vic_irq_mask[i] = 0xFFFF;
1472
1473 VIC_SET_GATE(VIC_CPI_LEVEL0, vic_cpi_interrupt);
1474
1475 VIC_SET_GATE(VIC_SYS_INT, vic_sys_interrupt);
1476 VIC_SET_GATE(VIC_CMN_INT, vic_cmn_interrupt);
1477
1478 QIC_SET_GATE(QIC_TIMER_CPI, qic_timer_interrupt);
1479 QIC_SET_GATE(QIC_INVALIDATE_CPI, qic_invalidate_interrupt);
1480 QIC_SET_GATE(QIC_RESCHEDULE_CPI, qic_reschedule_interrupt);
1481 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI, qic_enable_irq_interrupt);
1482 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI, qic_call_function_interrupt);
1483
1484
1485 /* now put the VIC descriptor into the first 48 IRQs
1486 *
1487 * This is for later: first 16 correspond to PC IRQs; next 16
1488 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1489 for(i = 0; i < 48; i++)
James Bottomleyc7717462006-10-12 22:21:16 -05001490 set_irq_chip_and_handler(i, &vic_chip, handle_vic_irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001491}
1492
1493/* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1494 * processor to receive CPI */
1495static void
1496send_CPI(__u32 cpuset, __u8 cpi)
1497{
1498 int cpu;
1499 __u32 quad_cpuset = (cpuset & voyager_quad_processors);
1500
1501 if(cpi < VIC_START_FAKE_CPI) {
1502 /* fake CPI are only used for booting, so send to the
1503 * extended quads as well---Quads must be VIC booted */
1504 outb((__u8)(cpuset), VIC_CPI_Registers[cpi]);
1505 return;
1506 }
1507 if(quad_cpuset)
1508 send_QIC_CPI(quad_cpuset, cpi);
1509 cpuset &= ~quad_cpuset;
1510 cpuset &= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1511 if(cpuset == 0)
1512 return;
1513 for_each_online_cpu(cpu) {
1514 if(cpuset & (1<<cpu))
1515 set_bit(cpi, &vic_cpi_mailbox[cpu]);
1516 }
1517 if(cpuset)
1518 outb((__u8)cpuset, VIC_CPI_Registers[VIC_CPI_LEVEL0]);
1519}
1520
1521/* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1522 * set the cache line to shared by reading it.
1523 *
1524 * DON'T make this inline otherwise the cache line read will be
1525 * optimised away
1526 * */
1527static int
1528ack_QIC_CPI(__u8 cpi) {
1529 __u8 cpu = hard_smp_processor_id();
1530
1531 cpi &= 7;
1532
1533 outb(1<<cpi, QIC_INTERRUPT_CLEAR1);
1534 return voyager_quad_cpi_addr[cpu]->qic_cpi[cpi].cpi;
1535}
1536
1537static void
1538ack_special_QIC_CPI(__u8 cpi)
1539{
1540 switch(cpi) {
1541 case VIC_CMN_INT:
1542 outb(QIC_CMN_INT, QIC_INTERRUPT_CLEAR0);
1543 break;
1544 case VIC_SYS_INT:
1545 outb(QIC_SYS_INT, QIC_INTERRUPT_CLEAR0);
1546 break;
1547 }
1548 /* also clear at the VIC, just in case (nop for non-extended proc) */
1549 ack_VIC_CPI(cpi);
1550}
1551
1552/* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1553static void
1554ack_VIC_CPI(__u8 cpi)
1555{
1556#ifdef VOYAGER_DEBUG
1557 unsigned long flags;
1558 __u16 isr;
1559 __u8 cpu = smp_processor_id();
1560
1561 local_irq_save(flags);
1562 isr = vic_read_isr();
1563 if((isr & (1<<(cpi &7))) == 0) {
1564 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu, cpi);
1565 }
1566#endif
1567 /* send specific EOI; the two system interrupts have
1568 * bit 4 set for a separate vector but behave as the
1569 * corresponding 3 bit intr */
1570 outb_p(0x60|(cpi & 7),0x20);
1571
1572#ifdef VOYAGER_DEBUG
1573 if((vic_read_isr() & (1<<(cpi &7))) != 0) {
1574 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu, cpi);
1575 }
1576 local_irq_restore(flags);
1577#endif
1578}
1579
1580/* cribbed with thanks from irq.c */
1581#define __byte(x,y) (((unsigned char *)&(y))[x])
1582#define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1583#define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1584
1585static unsigned int
1586startup_vic_irq(unsigned int irq)
1587{
James Bottomleyc7717462006-10-12 22:21:16 -05001588 unmask_vic_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001589
1590 return 0;
1591}
1592
1593/* The enable and disable routines. This is where we run into
1594 * conflicting architectural philosophy. Fundamentally, the voyager
1595 * architecture does not expect to have to disable interrupts globally
1596 * (the IRQ controllers belong to each CPU). The processor masquerade
1597 * which is used to start the system shouldn't be used in a running OS
1598 * since it will cause great confusion if two separate CPUs drive to
1599 * the same IRQ controller (I know, I've tried it).
1600 *
1601 * The solution is a variant on the NCR lazy SPL design:
1602 *
1603 * 1) To disable an interrupt, do nothing (other than set the
1604 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1605 *
1606 * 2) If the interrupt dares to come in, raise the local mask against
1607 * it (this will result in all the CPU masks being raised
1608 * eventually).
1609 *
1610 * 3) To enable the interrupt, lower the mask on the local CPU and
1611 * broadcast an Interrupt enable CPI which causes all other CPUs to
1612 * adjust their masks accordingly. */
1613
1614static void
James Bottomleyc7717462006-10-12 22:21:16 -05001615unmask_vic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616{
1617 /* linux doesn't to processor-irq affinity, so enable on
1618 * all CPUs we know about */
1619 int cpu = smp_processor_id(), real_cpu;
1620 __u16 mask = (1<<irq);
1621 __u32 processorList = 0;
1622 unsigned long flags;
1623
James Bottomleyc7717462006-10-12 22:21:16 -05001624 VDEBUG(("VOYAGER: unmask_vic_irq(%d) CPU%d affinity 0x%lx\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625 irq, cpu, cpu_irq_affinity[cpu]));
1626 spin_lock_irqsave(&vic_irq_lock, flags);
1627 for_each_online_cpu(real_cpu) {
1628 if(!(voyager_extended_vic_processors & (1<<real_cpu)))
1629 continue;
1630 if(!(cpu_irq_affinity[real_cpu] & mask)) {
1631 /* irq has no affinity for this CPU, ignore */
1632 continue;
1633 }
1634 if(real_cpu == cpu) {
1635 enable_local_vic_irq(irq);
1636 }
1637 else if(vic_irq_mask[real_cpu] & mask) {
1638 vic_irq_enable_mask[real_cpu] |= mask;
1639 processorList |= (1<<real_cpu);
1640 }
1641 }
1642 spin_unlock_irqrestore(&vic_irq_lock, flags);
1643 if(processorList)
1644 send_CPI(processorList, VIC_ENABLE_IRQ_CPI);
1645}
1646
1647static void
James Bottomleyc7717462006-10-12 22:21:16 -05001648mask_vic_irq(unsigned int irq)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649{
1650 /* lazy disable, do nothing */
1651}
1652
1653static void
1654enable_local_vic_irq(unsigned int irq)
1655{
1656 __u8 cpu = smp_processor_id();
1657 __u16 mask = ~(1 << irq);
1658 __u16 old_mask = vic_irq_mask[cpu];
1659
1660 vic_irq_mask[cpu] &= mask;
1661 if(vic_irq_mask[cpu] == old_mask)
1662 return;
1663
1664 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1665 irq, cpu));
1666
1667 if (irq & 8) {
1668 outb_p(cached_A1(cpu),0xA1);
1669 (void)inb_p(0xA1);
1670 }
1671 else {
1672 outb_p(cached_21(cpu),0x21);
1673 (void)inb_p(0x21);
1674 }
1675}
1676
1677static void
1678disable_local_vic_irq(unsigned int irq)
1679{
1680 __u8 cpu = smp_processor_id();
1681 __u16 mask = (1 << irq);
1682 __u16 old_mask = vic_irq_mask[cpu];
1683
1684 if(irq == 7)
1685 return;
1686
1687 vic_irq_mask[cpu] |= mask;
1688 if(old_mask == vic_irq_mask[cpu])
1689 return;
1690
1691 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1692 irq, cpu));
1693
1694 if (irq & 8) {
1695 outb_p(cached_A1(cpu),0xA1);
1696 (void)inb_p(0xA1);
1697 }
1698 else {
1699 outb_p(cached_21(cpu),0x21);
1700 (void)inb_p(0x21);
1701 }
1702}
1703
1704/* The VIC is level triggered, so the ack can only be issued after the
1705 * interrupt completes. However, we do Voyager lazy interrupt
1706 * handling here: It is an extremely expensive operation to mask an
1707 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1708 * this interrupt actually comes in, then we mask and ack here to push
1709 * the interrupt off to another CPU */
1710static void
1711before_handle_vic_irq(unsigned int irq)
1712{
1713 irq_desc_t *desc = irq_desc + irq;
1714 __u8 cpu = smp_processor_id();
1715
1716 _raw_spin_lock(&vic_irq_lock);
1717 vic_intr_total++;
1718 vic_intr_count[cpu]++;
1719
1720 if(!(cpu_irq_affinity[cpu] & (1<<irq))) {
1721 /* The irq is not in our affinity mask, push it off
1722 * onto another CPU */
1723 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1724 irq, cpu));
1725 disable_local_vic_irq(irq);
1726 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1727 * actually calling the interrupt routine */
1728 desc->status |= IRQ_REPLAY | IRQ_INPROGRESS;
1729 } else if(desc->status & IRQ_DISABLED) {
1730 /* Damn, the interrupt actually arrived, do the lazy
1731 * disable thing. The interrupt routine in irq.c will
1732 * not handle a IRQ_DISABLED interrupt, so nothing more
1733 * need be done here */
1734 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1735 irq, cpu));
1736 disable_local_vic_irq(irq);
1737 desc->status |= IRQ_REPLAY;
1738 } else {
1739 desc->status &= ~IRQ_REPLAY;
1740 }
1741
1742 _raw_spin_unlock(&vic_irq_lock);
1743}
1744
1745/* Finish the VIC interrupt: basically mask */
1746static void
1747after_handle_vic_irq(unsigned int irq)
1748{
1749 irq_desc_t *desc = irq_desc + irq;
1750
1751 _raw_spin_lock(&vic_irq_lock);
1752 {
1753 unsigned int status = desc->status & ~IRQ_INPROGRESS;
1754#ifdef VOYAGER_DEBUG
1755 __u16 isr;
1756#endif
1757
1758 desc->status = status;
1759 if ((status & IRQ_DISABLED))
1760 disable_local_vic_irq(irq);
1761#ifdef VOYAGER_DEBUG
1762 /* DEBUG: before we ack, check what's in progress */
1763 isr = vic_read_isr();
1764 if((isr & (1<<irq) && !(status & IRQ_REPLAY)) == 0) {
1765 int i;
1766 __u8 cpu = smp_processor_id();
1767 __u8 real_cpu;
1768 int mask; /* Um... initialize me??? --RR */
1769
1770 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1771 cpu, irq);
KAMEZAWA Hiroyukic89125992006-03-28 01:56:39 -08001772 for_each_possible_cpu(real_cpu, mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001773
1774 outb(VIC_CPU_MASQUERADE_ENABLE | real_cpu,
1775 VIC_PROCESSOR_ID);
1776 isr = vic_read_isr();
1777 if(isr & (1<<irq)) {
1778 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1779 real_cpu, irq);
1780 ack_vic_irq(irq);
1781 }
1782 outb(cpu, VIC_PROCESSOR_ID);
1783 }
1784 }
1785#endif /* VOYAGER_DEBUG */
1786 /* as soon as we ack, the interrupt is eligible for
1787 * receipt by another CPU so everything must be in
1788 * order here */
1789 ack_vic_irq(irq);
1790 if(status & IRQ_REPLAY) {
1791 /* replay is set if we disable the interrupt
1792 * in the before_handle_vic_irq() routine, so
1793 * clear the in progress bit here to allow the
1794 * next CPU to handle this correctly */
1795 desc->status &= ~(IRQ_REPLAY | IRQ_INPROGRESS);
1796 }
1797#ifdef VOYAGER_DEBUG
1798 isr = vic_read_isr();
1799 if((isr & (1<<irq)) != 0)
1800 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1801 irq, isr);
1802#endif /* VOYAGER_DEBUG */
1803 }
1804 _raw_spin_unlock(&vic_irq_lock);
1805
1806 /* All code after this point is out of the main path - the IRQ
1807 * may be intercepted by another CPU if reasserted */
1808}
1809
1810
1811/* Linux processor - interrupt affinity manipulations.
1812 *
1813 * For each processor, we maintain a 32 bit irq affinity mask.
1814 * Initially it is set to all 1's so every processor accepts every
1815 * interrupt. In this call, we change the processor's affinity mask:
1816 *
1817 * Change from enable to disable:
1818 *
1819 * If the interrupt ever comes in to the processor, we will disable it
1820 * and ack it to push it off to another CPU, so just accept the mask here.
1821 *
1822 * Change from disable to enable:
1823 *
1824 * change the mask and then do an interrupt enable CPI to re-enable on
1825 * the selected processors */
1826
1827void
1828set_vic_irq_affinity(unsigned int irq, cpumask_t mask)
1829{
1830 /* Only extended processors handle interrupts */
1831 unsigned long real_mask;
1832 unsigned long irq_mask = 1 << irq;
1833 int cpu;
1834
1835 real_mask = cpus_addr(mask)[0] & voyager_extended_vic_processors;
1836
1837 if(cpus_addr(mask)[0] == 0)
1838 /* can't have no cpu's to accept the interrupt -- extremely
1839 * bad things will happen */
1840 return;
1841
1842 if(irq == 0)
1843 /* can't change the affinity of the timer IRQ. This
1844 * is due to the constraint in the voyager
1845 * architecture that the CPI also comes in on and IRQ
1846 * line and we have chosen IRQ0 for this. If you
1847 * raise the mask on this interrupt, the processor
1848 * will no-longer be able to accept VIC CPIs */
1849 return;
1850
1851 if(irq >= 32)
1852 /* You can only have 32 interrupts in a voyager system
1853 * (and 32 only if you have a secondary microchannel
1854 * bus) */
1855 return;
1856
1857 for_each_online_cpu(cpu) {
1858 unsigned long cpu_mask = 1 << cpu;
1859
1860 if(cpu_mask & real_mask) {
1861 /* enable the interrupt for this cpu */
1862 cpu_irq_affinity[cpu] |= irq_mask;
1863 } else {
1864 /* disable the interrupt for this cpu */
1865 cpu_irq_affinity[cpu] &= ~irq_mask;
1866 }
1867 }
1868 /* this is magic, we now have the correct affinity maps, so
1869 * enable the interrupt. This will send an enable CPI to
1870 * those cpu's who need to enable it in their local masks,
1871 * causing them to correct for the new affinity . If the
1872 * interrupt is currently globally disabled, it will simply be
1873 * disabled again as it comes in (voyager lazy disable). If
1874 * the affinity map is tightened to disable the interrupt on a
1875 * cpu, it will be pushed off when it comes in */
James Bottomleyc7717462006-10-12 22:21:16 -05001876 unmask_vic_irq(irq);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001877}
1878
1879static void
1880ack_vic_irq(unsigned int irq)
1881{
1882 if (irq & 8) {
1883 outb(0x62,0x20); /* Specific EOI to cascade */
1884 outb(0x60|(irq & 7),0xA0);
1885 } else {
1886 outb(0x60 | (irq & 7),0x20);
1887 }
1888}
1889
1890/* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1891 * but are not vectored by it. This means that the 8259 mask must be
1892 * lowered to receive them */
1893static __init void
1894vic_enable_cpi(void)
1895{
1896 __u8 cpu = smp_processor_id();
1897
1898 /* just take a copy of the current mask (nop for boot cpu) */
1899 vic_irq_mask[cpu] = vic_irq_mask[boot_cpu_id];
1900
1901 enable_local_vic_irq(VIC_CPI_LEVEL0);
1902 enable_local_vic_irq(VIC_CPI_LEVEL1);
1903 /* for sys int and cmn int */
1904 enable_local_vic_irq(7);
1905
1906 if(is_cpu_quad()) {
1907 outb(QIC_DEFAULT_MASK0, QIC_MASK_REGISTER0);
1908 outb(QIC_CPI_ENABLE, QIC_MASK_REGISTER1);
1909 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1910 cpu, QIC_CPI_ENABLE));
1911 }
1912
1913 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1914 cpu, vic_irq_mask[cpu]));
1915}
1916
1917void
1918voyager_smp_dump()
1919{
1920 int old_cpu = smp_processor_id(), cpu;
1921
1922 /* dump the interrupt masks of each processor */
1923 for_each_online_cpu(cpu) {
1924 __u16 imr, isr, irr;
1925 unsigned long flags;
1926
1927 local_irq_save(flags);
1928 outb(VIC_CPU_MASQUERADE_ENABLE | cpu, VIC_PROCESSOR_ID);
1929 imr = (inb(0xa1) << 8) | inb(0x21);
1930 outb(0x0a, 0xa0);
1931 irr = inb(0xa0) << 8;
1932 outb(0x0a, 0x20);
1933 irr |= inb(0x20);
1934 outb(0x0b, 0xa0);
1935 isr = inb(0xa0) << 8;
1936 outb(0x0b, 0x20);
1937 isr |= inb(0x20);
1938 outb(old_cpu, VIC_PROCESSOR_ID);
1939 local_irq_restore(flags);
1940 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1941 cpu, vic_irq_mask[cpu], imr, irr, isr);
1942#if 0
1943 /* These lines are put in to try to unstick an un ack'd irq */
1944 if(isr != 0) {
1945 int irq;
1946 for(irq=0; irq<16; irq++) {
1947 if(isr & (1<<irq)) {
1948 printk("\tCPU%d: ack irq %d\n",
1949 cpu, irq);
1950 local_irq_save(flags);
1951 outb(VIC_CPU_MASQUERADE_ENABLE | cpu,
1952 VIC_PROCESSOR_ID);
1953 ack_vic_irq(irq);
1954 outb(old_cpu, VIC_PROCESSOR_ID);
1955 local_irq_restore(flags);
1956 }
1957 }
1958 }
1959#endif
1960 }
1961}
1962
1963void
1964smp_voyager_power_off(void *dummy)
1965{
1966 if(smp_processor_id() == boot_cpu_id)
1967 voyager_power_off();
1968 else
1969 smp_stop_cpu_function(NULL);
1970}
1971
1972void __init
1973smp_prepare_cpus(unsigned int max_cpus)
1974{
1975 /* FIXME: ignore max_cpus for now */
1976 smp_boot_cpus();
1977}
1978
1979void __devinit smp_prepare_boot_cpu(void)
1980{
1981 cpu_set(smp_processor_id(), cpu_online_map);
1982 cpu_set(smp_processor_id(), cpu_callout_map);
Zwane Mwaikambo4ad8d382005-09-03 15:56:51 -07001983 cpu_set(smp_processor_id(), cpu_possible_map);
James Bottomley3c101cf2006-06-26 21:33:09 -05001984 cpu_set(smp_processor_id(), cpu_present_map);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001985}
1986
1987int __devinit
1988__cpu_up(unsigned int cpu)
1989{
1990 /* This only works at boot for x86. See "rewrite" above. */
1991 if (cpu_isset(cpu, smp_commenced_mask))
1992 return -ENOSYS;
1993
1994 /* In case one didn't come up */
1995 if (!cpu_isset(cpu, cpu_callin_map))
1996 return -EIO;
1997 /* Unleash the CPU! */
1998 cpu_set(cpu, smp_commenced_mask);
1999 while (!cpu_isset(cpu, cpu_online_map))
2000 mb();
2001 return 0;
2002}
2003
2004void __init
2005smp_cpus_done(unsigned int max_cpus)
2006{
2007 zap_low_mappings();
2008}
Andrew Morton033ab7f2006-06-30 01:55:50 -07002009
2010void __init
2011smp_setup_processor_id(void)
2012{
2013 current_thread_info()->cpu = hard_smp_processor_id();
Jeremy Fitzhardinge62111192006-12-07 02:14:02 +01002014 write_pda(cpu_number, hard_smp_processor_id());
Andrew Morton033ab7f2006-06-30 01:55:50 -07002015}