| /* |
| * PCIe host controller driver for Freescale i.MX6 SoCs |
| * |
| * Copyright (C) 2013 Kosagi |
| * http://www.kosagi.com |
| * |
| * Author: Sean Cross <xobs@kosagi.com> |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| #include <linux/clk.h> |
| #include <linux/delay.h> |
| #include <linux/gpio.h> |
| #include <linux/kernel.h> |
| #include <linux/mfd/syscon.h> |
| #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> |
| #include <linux/module.h> |
| #include <linux/of_gpio.h> |
| #include <linux/of_device.h> |
| #include <linux/pci.h> |
| #include <linux/platform_device.h> |
| #include <linux/regmap.h> |
| #include <linux/resource.h> |
| #include <linux/signal.h> |
| #include <linux/types.h> |
| #include <linux/interrupt.h> |
| |
| #include "pcie-designware.h" |
| |
| #define to_imx6_pcie(x) dev_get_drvdata((x)->dev) |
| |
| enum imx6_pcie_variants { |
| IMX6Q, |
| IMX6SX, |
| IMX6QP, |
| }; |
| |
| struct imx6_pcie { |
| struct dw_pcie *pci; |
| int reset_gpio; |
| bool gpio_active_high; |
| struct clk *pcie_bus; |
| struct clk *pcie_phy; |
| struct clk *pcie_inbound_axi; |
| struct clk *pcie; |
| struct regmap *iomuxc_gpr; |
| enum imx6_pcie_variants variant; |
| u32 tx_deemph_gen1; |
| u32 tx_deemph_gen2_3p5db; |
| u32 tx_deemph_gen2_6db; |
| u32 tx_swing_full; |
| u32 tx_swing_low; |
| int link_gen; |
| }; |
| |
| /* PCIe Root Complex registers (memory-mapped) */ |
| #define PCIE_RC_LCR 0x7c |
| #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1 |
| #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2 |
| #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf |
| |
| #define PCIE_RC_LCSR 0x80 |
| |
| /* PCIe Port Logic registers (memory-mapped) */ |
| #define PL_OFFSET 0x700 |
| #define PCIE_PL_PFLR (PL_OFFSET + 0x08) |
| #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16) |
| #define PCIE_PL_PFLR_FORCE_LINK (1 << 15) |
| #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) |
| #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) |
| #define PCIE_PHY_DEBUG_R1_XMLH_LINK_IN_TRAINING (1 << 29) |
| #define PCIE_PHY_DEBUG_R1_XMLH_LINK_UP (1 << 4) |
| |
| #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) |
| #define PCIE_PHY_CTRL_DATA_LOC 0 |
| #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 |
| #define PCIE_PHY_CTRL_CAP_DAT_LOC 17 |
| #define PCIE_PHY_CTRL_WR_LOC 18 |
| #define PCIE_PHY_CTRL_RD_LOC 19 |
| |
| #define PCIE_PHY_STAT (PL_OFFSET + 0x110) |
| #define PCIE_PHY_STAT_ACK_LOC 16 |
| |
| #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C |
| #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) |
| |
| /* PHY registers (not memory-mapped) */ |
| #define PCIE_PHY_RX_ASIC_OUT 0x100D |
| #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0) |
| |
| #define PHY_RX_OVRD_IN_LO 0x1005 |
| #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) |
| #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) |
| |
| static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| u32 val; |
| u32 max_iterations = 10; |
| u32 wait_counter = 0; |
| |
| do { |
| val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); |
| val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; |
| wait_counter++; |
| |
| if (val == exp_val) |
| return 0; |
| |
| udelay(1); |
| } while (wait_counter < max_iterations); |
| |
| return -ETIMEDOUT; |
| } |
| |
| static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| u32 val; |
| int ret; |
| |
| val = addr << PCIE_PHY_CTRL_DATA_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); |
| |
| val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); |
| |
| ret = pcie_phy_poll_ack(imx6_pcie, 1); |
| if (ret) |
| return ret; |
| |
| val = addr << PCIE_PHY_CTRL_DATA_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val); |
| |
| return pcie_phy_poll_ack(imx6_pcie, 0); |
| } |
| |
| /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ |
| static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| u32 val, phy_ctl; |
| int ret; |
| |
| ret = pcie_phy_wait_ack(imx6_pcie, addr); |
| if (ret) |
| return ret; |
| |
| /* assert Read signal */ |
| phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl); |
| |
| ret = pcie_phy_poll_ack(imx6_pcie, 1); |
| if (ret) |
| return ret; |
| |
| val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT); |
| *data = val & 0xffff; |
| |
| /* deassert Read signal */ |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00); |
| |
| return pcie_phy_poll_ack(imx6_pcie, 0); |
| } |
| |
| static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| u32 var; |
| int ret; |
| |
| /* write addr */ |
| /* cap addr */ |
| ret = pcie_phy_wait_ack(imx6_pcie, addr); |
| if (ret) |
| return ret; |
| |
| var = data << PCIE_PHY_CTRL_DATA_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); |
| |
| /* capture data */ |
| var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); |
| |
| ret = pcie_phy_poll_ack(imx6_pcie, 1); |
| if (ret) |
| return ret; |
| |
| /* deassert cap data */ |
| var = data << PCIE_PHY_CTRL_DATA_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); |
| |
| /* wait for ack de-assertion */ |
| ret = pcie_phy_poll_ack(imx6_pcie, 0); |
| if (ret) |
| return ret; |
| |
| /* assert wr signal */ |
| var = 0x1 << PCIE_PHY_CTRL_WR_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); |
| |
| /* wait for ack */ |
| ret = pcie_phy_poll_ack(imx6_pcie, 1); |
| if (ret) |
| return ret; |
| |
| /* deassert wr signal */ |
| var = data << PCIE_PHY_CTRL_DATA_LOC; |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var); |
| |
| /* wait for ack de-assertion */ |
| ret = pcie_phy_poll_ack(imx6_pcie, 0); |
| if (ret) |
| return ret; |
| |
| dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0); |
| |
| return 0; |
| } |
| |
| static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie) |
| { |
| u32 tmp; |
| |
| pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); |
| tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN | |
| PHY_RX_OVRD_IN_LO_RX_PLL_EN); |
| pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); |
| |
| usleep_range(2000, 3000); |
| |
| pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp); |
| tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN | |
| PHY_RX_OVRD_IN_LO_RX_PLL_EN); |
| pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp); |
| } |
| |
| /* Added for PCI abort handling */ |
| static int imx6q_pcie_abort_handler(unsigned long addr, |
| unsigned int fsr, struct pt_regs *regs) |
| { |
| return 0; |
| } |
| |
| static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie) |
| { |
| switch (imx6_pcie->variant) { |
| case IMX6SX: |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6SX_GPR12_PCIE_TEST_POWERDOWN, |
| IMX6SX_GPR12_PCIE_TEST_POWERDOWN); |
| /* Force PCIe PHY reset */ |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, |
| IMX6SX_GPR5_PCIE_BTNRST_RESET, |
| IMX6SX_GPR5_PCIE_BTNRST_RESET); |
| break; |
| case IMX6QP: |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_SW_RST, |
| IMX6Q_GPR1_PCIE_SW_RST); |
| break; |
| case IMX6Q: |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); |
| break; |
| } |
| } |
| |
| static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct device *dev = pci->dev; |
| int ret = 0; |
| |
| switch (imx6_pcie->variant) { |
| case IMX6SX: |
| ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); |
| if (ret) { |
| dev_err(dev, "unable to enable pcie_axi clock\n"); |
| break; |
| } |
| |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0); |
| break; |
| case IMX6QP: /* FALLTHROUGH */ |
| case IMX6Q: |
| /* power up core phy and enable ref clock */ |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); |
| /* |
| * the async reset input need ref clock to sync internally, |
| * when the ref clock comes after reset, internal synced |
| * reset time is too short, cannot meet the requirement. |
| * add one ~10us delay here. |
| */ |
| udelay(10); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); |
| break; |
| } |
| |
| return ret; |
| } |
| |
| static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct device *dev = pci->dev; |
| int ret; |
| |
| ret = clk_prepare_enable(imx6_pcie->pcie_phy); |
| if (ret) { |
| dev_err(dev, "unable to enable pcie_phy clock\n"); |
| return; |
| } |
| |
| ret = clk_prepare_enable(imx6_pcie->pcie_bus); |
| if (ret) { |
| dev_err(dev, "unable to enable pcie_bus clock\n"); |
| goto err_pcie_bus; |
| } |
| |
| ret = clk_prepare_enable(imx6_pcie->pcie); |
| if (ret) { |
| dev_err(dev, "unable to enable pcie clock\n"); |
| goto err_pcie; |
| } |
| |
| ret = imx6_pcie_enable_ref_clk(imx6_pcie); |
| if (ret) { |
| dev_err(dev, "unable to enable pcie ref clock\n"); |
| goto err_ref_clk; |
| } |
| |
| /* allow the clocks to stabilize */ |
| usleep_range(200, 500); |
| |
| /* Some boards don't have PCIe reset GPIO. */ |
| if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
| gpio_set_value_cansleep(imx6_pcie->reset_gpio, |
| imx6_pcie->gpio_active_high); |
| msleep(100); |
| gpio_set_value_cansleep(imx6_pcie->reset_gpio, |
| !imx6_pcie->gpio_active_high); |
| } |
| |
| switch (imx6_pcie->variant) { |
| case IMX6SX: |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, |
| IMX6SX_GPR5_PCIE_BTNRST_RESET, 0); |
| break; |
| case IMX6QP: |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, |
| IMX6Q_GPR1_PCIE_SW_RST, 0); |
| |
| usleep_range(200, 500); |
| break; |
| case IMX6Q: /* Nothing to do */ |
| break; |
| } |
| |
| return; |
| |
| err_ref_clk: |
| clk_disable_unprepare(imx6_pcie->pcie); |
| err_pcie: |
| clk_disable_unprepare(imx6_pcie->pcie_bus); |
| err_pcie_bus: |
| clk_disable_unprepare(imx6_pcie->pcie_phy); |
| } |
| |
| static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) |
| { |
| if (imx6_pcie->variant == IMX6SX) |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6SX_GPR12_PCIE_RX_EQ_MASK, |
| IMX6SX_GPR12_PCIE_RX_EQ_2); |
| |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); |
| |
| /* configure constant input signal to the pcie ctrl and phy */ |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6Q_GPR12_LOS_LEVEL, 9 << 4); |
| |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
| IMX6Q_GPR8_TX_DEEMPH_GEN1, |
| imx6_pcie->tx_deemph_gen1 << 0); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
| IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, |
| imx6_pcie->tx_deemph_gen2_3p5db << 6); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
| IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, |
| imx6_pcie->tx_deemph_gen2_6db << 12); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
| IMX6Q_GPR8_TX_SWING_FULL, |
| imx6_pcie->tx_swing_full << 18); |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, |
| IMX6Q_GPR8_TX_SWING_LOW, |
| imx6_pcie->tx_swing_low << 25); |
| } |
| |
| static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct device *dev = pci->dev; |
| |
| /* check if the link is up or not */ |
| if (!dw_pcie_wait_for_link(pci)) |
| return 0; |
| |
| dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", |
| dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), |
| dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); |
| return -ETIMEDOUT; |
| } |
| |
| static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct device *dev = pci->dev; |
| u32 tmp; |
| unsigned int retries; |
| |
| for (retries = 0; retries < 200; retries++) { |
| tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); |
| /* Test if the speed change finished. */ |
| if (!(tmp & PORT_LOGIC_SPEED_CHANGE)) |
| return 0; |
| usleep_range(100, 1000); |
| } |
| |
| dev_err(dev, "Speed change timeout\n"); |
| return -EINVAL; |
| } |
| |
| static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg) |
| { |
| struct imx6_pcie *imx6_pcie = arg; |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct pcie_port *pp = &pci->pp; |
| |
| return dw_handle_msi_irq(pp); |
| } |
| |
| static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct device *dev = pci->dev; |
| u32 tmp; |
| int ret; |
| |
| /* |
| * Force Gen1 operation when starting the link. In case the link is |
| * started in Gen2 mode, there is a possibility the devices on the |
| * bus will not be detected at all. This happens with PCIe switches. |
| */ |
| tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); |
| tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; |
| tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1; |
| dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); |
| |
| /* Start LTSSM. */ |
| regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, |
| IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); |
| |
| ret = imx6_pcie_wait_for_link(imx6_pcie); |
| if (ret) |
| goto err_reset_phy; |
| |
| if (imx6_pcie->link_gen == 2) { |
| /* Allow Gen2 mode after the link is up. */ |
| tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR); |
| tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK; |
| tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2; |
| dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp); |
| } else { |
| dev_info(dev, "Link: Gen2 disabled\n"); |
| } |
| |
| /* |
| * Start Directed Speed Change so the best possible speed both link |
| * partners support can be negotiated. |
| */ |
| tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL); |
| tmp |= PORT_LOGIC_SPEED_CHANGE; |
| dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp); |
| |
| ret = imx6_pcie_wait_for_speed_change(imx6_pcie); |
| if (ret) { |
| dev_err(dev, "Failed to bring link up!\n"); |
| goto err_reset_phy; |
| } |
| |
| /* Make sure link training is finished as well! */ |
| ret = imx6_pcie_wait_for_link(imx6_pcie); |
| if (ret) { |
| dev_err(dev, "Failed to bring link up!\n"); |
| goto err_reset_phy; |
| } |
| |
| tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR); |
| dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf); |
| return 0; |
| |
| err_reset_phy: |
| dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n", |
| dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0), |
| dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1)); |
| imx6_pcie_reset_phy(imx6_pcie); |
| return ret; |
| } |
| |
| static void imx6_pcie_host_init(struct pcie_port *pp) |
| { |
| struct dw_pcie *pci = to_dw_pcie_from_pp(pp); |
| struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci); |
| |
| imx6_pcie_assert_core_reset(imx6_pcie); |
| imx6_pcie_init_phy(imx6_pcie); |
| imx6_pcie_deassert_core_reset(imx6_pcie); |
| dw_pcie_setup_rc(pp); |
| imx6_pcie_establish_link(imx6_pcie); |
| |
| if (IS_ENABLED(CONFIG_PCI_MSI)) |
| dw_pcie_msi_init(pp); |
| } |
| |
| static int imx6_pcie_link_up(struct dw_pcie *pci) |
| { |
| return dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1) & |
| PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; |
| } |
| |
| static struct dw_pcie_host_ops imx6_pcie_host_ops = { |
| .host_init = imx6_pcie_host_init, |
| }; |
| |
| static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie, |
| struct platform_device *pdev) |
| { |
| struct dw_pcie *pci = imx6_pcie->pci; |
| struct pcie_port *pp = &pci->pp; |
| struct device *dev = &pdev->dev; |
| int ret; |
| |
| if (IS_ENABLED(CONFIG_PCI_MSI)) { |
| pp->msi_irq = platform_get_irq_byname(pdev, "msi"); |
| if (pp->msi_irq <= 0) { |
| dev_err(dev, "failed to get MSI irq\n"); |
| return -ENODEV; |
| } |
| |
| ret = devm_request_irq(dev, pp->msi_irq, |
| imx6_pcie_msi_handler, |
| IRQF_SHARED | IRQF_NO_THREAD, |
| "mx6-pcie-msi", imx6_pcie); |
| if (ret) { |
| dev_err(dev, "failed to request MSI irq\n"); |
| return ret; |
| } |
| } |
| |
| pp->root_bus_nr = -1; |
| pp->ops = &imx6_pcie_host_ops; |
| |
| ret = dw_pcie_host_init(pp); |
| if (ret) { |
| dev_err(dev, "failed to initialize host\n"); |
| return ret; |
| } |
| |
| return 0; |
| } |
| |
| static const struct dw_pcie_ops dw_pcie_ops = { |
| .link_up = imx6_pcie_link_up, |
| }; |
| |
| static int __init imx6_pcie_probe(struct platform_device *pdev) |
| { |
| struct device *dev = &pdev->dev; |
| struct dw_pcie *pci; |
| struct imx6_pcie *imx6_pcie; |
| struct resource *dbi_base; |
| struct device_node *node = dev->of_node; |
| int ret; |
| |
| imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL); |
| if (!imx6_pcie) |
| return -ENOMEM; |
| |
| pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); |
| if (!pci) |
| return -ENOMEM; |
| |
| pci->dev = dev; |
| pci->ops = &dw_pcie_ops; |
| |
| imx6_pcie->pci = pci; |
| imx6_pcie->variant = |
| (enum imx6_pcie_variants)of_device_get_match_data(dev); |
| |
| /* Added for PCI abort handling */ |
| hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, |
| "imprecise external abort"); |
| |
| dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| pci->dbi_base = devm_ioremap_resource(dev, dbi_base); |
| if (IS_ERR(pci->dbi_base)) |
| return PTR_ERR(pci->dbi_base); |
| |
| /* Fetch GPIOs */ |
| imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); |
| imx6_pcie->gpio_active_high = of_property_read_bool(node, |
| "reset-gpio-active-high"); |
| if (gpio_is_valid(imx6_pcie->reset_gpio)) { |
| ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, |
| imx6_pcie->gpio_active_high ? |
| GPIOF_OUT_INIT_HIGH : |
| GPIOF_OUT_INIT_LOW, |
| "PCIe reset"); |
| if (ret) { |
| dev_err(dev, "unable to get reset gpio\n"); |
| return ret; |
| } |
| } |
| |
| /* Fetch clocks */ |
| imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); |
| if (IS_ERR(imx6_pcie->pcie_phy)) { |
| dev_err(dev, "pcie_phy clock source missing or invalid\n"); |
| return PTR_ERR(imx6_pcie->pcie_phy); |
| } |
| |
| imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); |
| if (IS_ERR(imx6_pcie->pcie_bus)) { |
| dev_err(dev, "pcie_bus clock source missing or invalid\n"); |
| return PTR_ERR(imx6_pcie->pcie_bus); |
| } |
| |
| imx6_pcie->pcie = devm_clk_get(dev, "pcie"); |
| if (IS_ERR(imx6_pcie->pcie)) { |
| dev_err(dev, "pcie clock source missing or invalid\n"); |
| return PTR_ERR(imx6_pcie->pcie); |
| } |
| |
| if (imx6_pcie->variant == IMX6SX) { |
| imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, |
| "pcie_inbound_axi"); |
| if (IS_ERR(imx6_pcie->pcie_inbound_axi)) { |
| dev_err(dev, "pcie_inbound_axi clock missing or invalid\n"); |
| return PTR_ERR(imx6_pcie->pcie_inbound_axi); |
| } |
| } |
| |
| /* Grab GPR config register range */ |
| imx6_pcie->iomuxc_gpr = |
| syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); |
| if (IS_ERR(imx6_pcie->iomuxc_gpr)) { |
| dev_err(dev, "unable to find iomuxc registers\n"); |
| return PTR_ERR(imx6_pcie->iomuxc_gpr); |
| } |
| |
| /* Grab PCIe PHY Tx Settings */ |
| if (of_property_read_u32(node, "fsl,tx-deemph-gen1", |
| &imx6_pcie->tx_deemph_gen1)) |
| imx6_pcie->tx_deemph_gen1 = 0; |
| |
| if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", |
| &imx6_pcie->tx_deemph_gen2_3p5db)) |
| imx6_pcie->tx_deemph_gen2_3p5db = 0; |
| |
| if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", |
| &imx6_pcie->tx_deemph_gen2_6db)) |
| imx6_pcie->tx_deemph_gen2_6db = 20; |
| |
| if (of_property_read_u32(node, "fsl,tx-swing-full", |
| &imx6_pcie->tx_swing_full)) |
| imx6_pcie->tx_swing_full = 127; |
| |
| if (of_property_read_u32(node, "fsl,tx-swing-low", |
| &imx6_pcie->tx_swing_low)) |
| imx6_pcie->tx_swing_low = 127; |
| |
| /* Limit link speed */ |
| ret = of_property_read_u32(node, "fsl,max-link-speed", |
| &imx6_pcie->link_gen); |
| if (ret) |
| imx6_pcie->link_gen = 1; |
| |
| platform_set_drvdata(pdev, imx6_pcie); |
| |
| ret = imx6_add_pcie_port(imx6_pcie, pdev); |
| if (ret < 0) |
| return ret; |
| |
| return 0; |
| } |
| |
| static void imx6_pcie_shutdown(struct platform_device *pdev) |
| { |
| struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev); |
| |
| /* bring down link, so bootloader gets clean state in case of reboot */ |
| imx6_pcie_assert_core_reset(imx6_pcie); |
| } |
| |
| static const struct of_device_id imx6_pcie_of_match[] = { |
| { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, }, |
| { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, }, |
| { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, }, |
| {}, |
| }; |
| |
| static struct platform_driver imx6_pcie_driver = { |
| .driver = { |
| .name = "imx6q-pcie", |
| .of_match_table = imx6_pcie_of_match, |
| }, |
| .shutdown = imx6_pcie_shutdown, |
| }; |
| |
| static int __init imx6_pcie_init(void) |
| { |
| return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); |
| } |
| device_initcall(imx6_pcie_init); |