| /* |
| * Copyright (c) 2018 Samsung Electronics Co., Ltd. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * Device Tree binding constants for Exynos9820 clock controller. |
| */ |
| |
| #ifndef _DT_BINDINGS_CLOCK_EXYNOS_9820_H |
| #define _DT_BINDINGS_CLOCK_EXYNOS_9820_H |
| |
| #define NONE (0 + 0) |
| #define OSCCLK (0 + 1) |
| |
| /* NUMBER FOR APM DRIVER STARTS FROM 10 */ |
| #define CLK_APM_BASE (10) |
| #define UMUX_DLL (CLK_APM_BASE + 0) |
| #define UMUX_CLKMUX_APM_RCO (CLK_APM_BASE + 1) |
| #define GATE_GREBEINTEGRATION_GREBE (CLK_APM_BASE + 2) |
| #define GATE_GREBEINTEGRATION_DBG (CLK_APM_BASE + 3) |
| #define GATE_GREBEINTEGRATION_DBGCORE_GREBE (CLK_APM_BASE + 4) |
| #define GATE_GREBEINTEGRATION_DBGCORE_DBG (CLK_APM_BASE + 5) |
| #define GATE_INTMEM (CLK_APM_BASE + 6) |
| #define GATE_MAILBOX_APM_AP (CLK_APM_BASE + 7) |
| #define GATE_MAILBOX_APM_CP (CLK_APM_BASE + 8) |
| #define GATE_MAILBOX_APM_VTS (CLK_APM_BASE + 9) |
| #define GATE_MAILBOX_AP_CP (CLK_APM_BASE + 10) |
| #define GATE_MAILBOX_AP_CP_S (CLK_APM_BASE + 11) |
| #define GATE_MAILBOX_AP_DBGCORE (CLK_APM_BASE + 12) |
| #define GATE_PEM (CLK_APM_BASE + 13) |
| #define GATE_PMU_INTR_GEN (CLK_APM_BASE + 14) |
| #define GATE_RSTNSYNC_CLK_APM_BUS_GREBE (CLK_APM_BASE + 15) |
| #define GATE_RSTNSYNC_CLK_APM_BUS_GREBE_DBG (CLK_APM_BASE + 16) |
| #define GATE_SPEEDY_APM (CLK_APM_BASE + 17) |
| #define GATE_SPEEDY_SUB_APM (CLK_APM_BASE + 18) |
| #define GATE_SYSREG_APM (CLK_APM_BASE + 19) |
| #define GATE_WDT_APM (CLK_APM_BASE + 20) |
| #define DOUT_CLKCMU_VTS_BUS (CLK_APM_BASE + 21) |
| #define DOUT_CLKCMU_CMGP_BUS (CLK_APM_BASE + 22) |
| |
| /* NUMBER FOR ABOX DRIVER STARTS FROM 50 */ |
| #define CLK_ABOX_BASE (50) |
| #define GATE_ABOX_ACLK (CLK_ABOX_BASE + 0) |
| #define GATE_ABOX_BCLK_DSIF (CLK_ABOX_BASE + 1) |
| #define GATE_ABOX_BCLK0 (CLK_ABOX_BASE + 2) |
| #define GATE_ABOX_BCLK1 (CLK_ABOX_BASE + 3) |
| #define GATE_ABOX_BCLK2 (CLK_ABOX_BASE + 4) |
| #define GATE_ABOX_BCLK3 (CLK_ABOX_BASE + 5) |
| #define GATE_ABOX_CNT (CLK_ABOX_BASE + 6) |
| #define GATE_AUD_CMU_AUD (CLK_ABOX_BASE + 7) |
| #define GATE_BTM_AUD (CLK_ABOX_BASE + 8) |
| #define GATE_DFTMUX_AUD (CLK_ABOX_BASE + 9) |
| #define GATE_DMIC (CLK_ABOX_BASE + 10) |
| #define GATE_GPIO_AUD (CLK_ABOX_BASE + 11) |
| #define GATE_PPMU_AUD (CLK_ABOX_BASE + 12) |
| #define GATE_SMMU_AUD (CLK_ABOX_BASE + 13) |
| #define GATE_SYSREG_AUD (CLK_ABOX_BASE + 14) |
| #define GATE_WDT_AUD (CLK_ABOX_BASE + 15) |
| #define DOUT_CLK_AUD_DSIF (CLK_ABOX_BASE + 16) |
| #define DOUT_CLK_AUD_UAIF0 (CLK_ABOX_BASE + 17) |
| #define DOUT_CLK_AUD_UAIF1 (CLK_ABOX_BASE + 18) |
| #define DOUT_CLK_AUD_UAIF2 (CLK_ABOX_BASE + 19) |
| #define DOUT_CLK_AUD_UAIF3 (CLK_ABOX_BASE + 20) |
| #define DOUT_CLK_AUD_CPU_ACLK (CLK_ABOX_BASE + 21) |
| #define DOUT_CLK_AUD_BUS (CLK_ABOX_BASE + 22) |
| #define DOUT_CLK_AUD_BUSP (CLK_ABOX_BASE + 23) |
| #define DOUT_CLK_AUD_DMIC (CLK_ABOX_BASE + 24) |
| #define DOUT_CLK_AUD_CNT (CLK_ABOX_BASE + 25) |
| #define DOUT_CLK_AUD_MCLK (CLK_ABOX_BASE + 26) |
| #define PLL_OUT_AUD0 (CLK_ABOX_BASE + 27) |
| #define PLL_OUT_AUD1 (CLK_ABOX_BASE + 28) |
| #define PLL_OUT_MMC (CLK_ABOX_BASE + 29) |
| #define DOUT_CLK_AUD_AUDIF (CLK_ABOX_BASE + 30) |
| |
| /* NUMBER FOR BUSC DRIVER STARTS FROM 100 */ |
| #define CLK_BUSC_BASE (100) |
| #define GATE_MMCACHE (CLK_BUSC_BASE + 0) |
| #define GATE_PDMA0 (CLK_BUSC_BASE + 1) |
| #define GATE_PPFW (CLK_BUSC_BASE + 2) |
| #define GATE_SBIC (CLK_BUSC_BASE + 3) |
| #define GATE_SIREX (CLK_BUSC_BASE + 4) |
| #define GATE_SPDMA (CLK_BUSC_BASE + 5) |
| #define GATE_SYSREG_BUSC (CLK_BUSC_BASE + 6) |
| #define UMUX_CLKCMU_BUSC_BUS (CLK_BUSC_BASE + 7) |
| |
| /* NUMBER FOR BUSC DRIVER STARTS FROM 110 */ |
| #define CLK_CMGP_BASE (110) |
| #define GATE_ADC_CMGP_S0 (CLK_CMGP_BASE + 0) |
| #define GATE_ADC_CMGP_S1 (CLK_CMGP_BASE + 1) |
| #define GATE_CMGP_CMU_CMGP (CLK_CMGP_BASE + 2) |
| #define GATE_GPIO_CMGP (CLK_CMGP_BASE + 3) |
| #define GATE_I2C_CMGP0 (CLK_CMGP_BASE + 4) |
| #define GATE_I2C_CMGP1 (CLK_CMGP_BASE + 5) |
| #define GATE_I2C_CMGP2 (CLK_CMGP_BASE + 6) |
| #define GATE_I2C_CMGP3 (CLK_CMGP_BASE + 7) |
| #define GATE_SYSREG_CMGP (CLK_CMGP_BASE + 8) |
| #define GATE_SYSREG_CMGP2APM (CLK_CMGP_BASE + 9) |
| #define GATE_SYSREG_CMGP2CP (CLK_CMGP_BASE + 10) |
| #define GATE_SYSREG_CMGP2PMU_AP (CLK_CMGP_BASE + 11) |
| #define GATE_USI_CMGP0 (CLK_CMGP_BASE + 12) |
| #define GATE_USI_CMGP1 (CLK_CMGP_BASE + 13) |
| #define GATE_USI_CMGP2 (CLK_CMGP_BASE + 14) |
| #define GATE_USI_CMGP3 (CLK_CMGP_BASE + 15) |
| #define DOUT_CLK_I2C_CMGP0 (CLK_CMGP_BASE + 16) |
| #define DOUT_CLK_USI_CMGP1 (CLK_CMGP_BASE + 17) |
| #define DOUT_CLK_USI_CMGP0 (CLK_CMGP_BASE + 18) |
| #define DOUT_CLK_USI_CMGP2 (CLK_CMGP_BASE + 19) |
| #define DOUT_CLK_USI_CMGP3 (CLK_CMGP_BASE + 20) |
| #define DOUT_CLK_CMGP_ADC (CLK_CMGP_BASE + 21) |
| #define DOUT_CLK_I2C_CMGP1 (CLK_CMGP_BASE + 22) |
| #define DOUT_CLK_I2C_CMGP2 (CLK_CMGP_BASE + 23) |
| #define DOUT_CLK_I2C_CMGP3 (CLK_CMGP_BASE + 24) |
| #define DOUT_CLK_CMGP_BUS (CLK_CMGP_BASE + 25) |
| #define UMUX_CLKCMU_CMGP_BUS (CLK_CMGP_BASE + 26) |
| |
| /* NUMBER FOR CMU DRIVER STARTS FROM 150 */ |
| #define CLK_CMU_BASE (150) |
| #define GATE_CMU_CMU_CMUREF (CLK_CMU_BASE + 0) |
| #define GATE_DFTMUX_TOP_CIS_CLK0 (CLK_CMU_BASE + 1) |
| #define GATE_DFTMUX_TOP_CIS_CLK1 (CLK_CMU_BASE + 2) |
| #define GATE_DFTMUX_TOP_CIS_CLK2 (CLK_CMU_BASE + 3) |
| #define GATE_DFTMUX_TOP_CIS_CLK3 (CLK_CMU_BASE + 4) |
| #define GATE_DFTMUX_TOP_CIS_CLK4 (CLK_CMU_BASE + 5) |
| #define GATE_OTP (CLK_CMU_BASE + 6) |
| #define CIS_CLK0 (CLK_CMU_BASE + 7) |
| #define CIS_CLK1 (CLK_CMU_BASE + 8) |
| #define CIS_CLK2 (CLK_CMU_BASE + 9) |
| #define CIS_CLK3 (CLK_CMU_BASE + 10) |
| #define CIS_CLK4 (CLK_CMU_BASE + 11) |
| |
| /* NUMBER FOR CORE DRIVER STARTS FROM 170 */ |
| #define CLK_CORE_BASE (170) |
| #define GATE_TREX_D_CORE (CLK_CORE_BASE + 0) |
| #define GATE_TREX_P0_CORE (CLK_CORE_BASE + 1) |
| #define GATE_TREX_P1_CORE (CLK_CORE_BASE + 2) |
| |
| /* NUMBER FOR DPU DRIVER STARTS FROM 200 */ |
| #define CLK_DPU_BASE (200) |
| #define UMUX_CLKCMU_DPU_BUS (CLK_DPU_BASE + 0) |
| #define GATE_DPU_DPU (CLK_DPU_BASE + 1) |
| #define GATE_DPU_DPU_DMA (CLK_DPU_BASE + 2) |
| #define GATE_DPU_DPU_DPP (CLK_DPU_BASE + 3) |
| #define GATE_DPU_DPU_WB_MUX (CLK_DPU_BASE + 4) |
| #define GATE_DPU_CMU_DPU (CLK_DPU_BASE + 5) |
| #define GATE_SYSMMU_DPUD0 (CLK_DPU_BASE + 6) |
| #define GATE_SYSMMU_DPUD1 (CLK_DPU_BASE + 7) |
| #define GATE_SYSMMU_DPUD2 (CLK_DPU_BASE + 8) |
| #define GATE_SYSREG_DPU (CLK_DPU_BASE + 9) |
| |
| /* NUMBER FOR DSPM DRIVER STARTS FROM 220 */ |
| #define CLK_DSPM_BASE (220) |
| #define UMUX_CLKCMU_DSPM_BUS (CLK_DSPM_BASE + 0) |
| #define UMUX_CLKCMU_DSPM_BUS_OTF (CLK_DSPM_BASE + 1) |
| #define GATE_SCORE_TS_II (CLK_DSPM_BASE + 2) |
| #define GATE_SYSMMU_DSPM0 (CLK_DSPM_BASE + 3) |
| #define GATE_SYSMMU_DSPM1 (CLK_DSPM_BASE + 4) |
| #define GATE_SYSREG_DSPM (CLK_DSPM_BASE + 5) |
| #define GATE_VGEN_LITE_DSPM (CLK_DSPM_BASE + 6) |
| |
| /* NUMBER FOR DSPS DRIVER STARTS FROM 240 */ |
| #define CLK_DSPS_BASE (240) |
| #define UMUX_CLKCMU_DSPS_BUS (CLK_DSPS_BASE + 0) |
| #define UMUX_CLKCMU_DSPS_AUD (CLK_DSPS_BASE + 1) |
| #define GATE_SCORE_BARON (CLK_DSPS_BASE + 2) |
| |
| /* NUMBER FOR FSYS0 DRIVER STARTS FROM 250 */ |
| #define CLK_FSYS0_BASE (250) |
| #define UMUX_CLKCMU_FSYS0_BUS (CLK_FSYS0_BASE + 0) |
| #define UMUX_CLKCMU_FSYS0_DPGTC (CLK_FSYS0_BASE + 1) |
| #define UMUX_CLKCMU_FSYS0_PCIE (CLK_FSYS0_BASE + 2) |
| #define GATE_DP_LINK (CLK_FSYS0_BASE + 3) |
| #define GATE_DP_LINK_GTC (CLK_FSYS0_BASE + 4) |
| #define GATE_GPIO_FSYS0 (CLK_FSYS0_BASE + 5) |
| #define GATE_PCIE_GEN3_DBI_A (CLK_FSYS0_BASE + 6) |
| #define GATE_PCIE_GEN3_MSTR_SLV_A (CLK_FSYS0_BASE + 7) |
| #define GATE_PCIE_GEN3_APB_A (CLK_FSYS0_BASE + 8) |
| #define GATE_PCIE_GEN3_DBI_B (CLK_FSYS0_BASE + 9) |
| #define GATE_PCIE_GEN3_MSTR_SLV_B (CLK_FSYS0_BASE + 10) |
| #define GATE_PCIE_GEN3_APB_B (CLK_FSYS0_BASE + 11) |
| #define GATE_PCIE_GEN3_SCLK (CLK_FSYS0_BASE + 12) |
| #define GATE_PCIE_GEN3_PCS_APB (CLK_FSYS0_BASE + 13) |
| #define GATE_PCIE_GEN3_IF_CMN (CLK_FSYS0_BASE + 14) |
| #define GATE_PCIE_GEN3_IF_LN0 (CLK_FSYS0_BASE + 15) |
| #define GATE_PCIE_GEN3_IF_LN1 (CLK_FSYS0_BASE + 16) |
| #define GATE_PCIE_IA_GEN3A (CLK_FSYS0_BASE + 17) |
| #define GATE_PCIE_IA_GEN3B (CLK_FSYS0_BASE + 18) |
| #define GATE_SYSMMU_PCIE_GEN3A (CLK_FSYS0_BASE + 19) |
| #define GATE_SYSMMU_PCIE_GEN3B (CLK_FSYS0_BASE + 20) |
| #define GATE_SYSREG_FSYS0 (CLK_FSYS0_BASE + 21) |
| |
| /* NUMBER FOR FSYS0A DRIVER STARTS FROM 280 */ |
| #define CLK_FSYS0A_BASE (280) |
| #define UMUX_CLKCMU_FSYS0A_BUS (CLK_FSYS0A_BASE + 0) |
| #define UMUX_CLKCMU_FSYS0A_USB31DRD (CLK_FSYS0A_BASE + 1) |
| #define UMUX_CLKCMU_FSYS0A_USBDP_DEBUG (CLK_FSYS0A_BASE + 2) |
| #define GATE_USB31DRD_REF (CLK_FSYS0A_BASE + 3) |
| #define GATE_USB31DRD_SLV_CTRL (CLK_FSYS0A_BASE + 4) |
| #define GATE_USB31DRD_SLV_LINK (CLK_FSYS0A_BASE + 5) |
| #define GATE_USB31DRD_APB (CLK_FSYS0A_BASE + 6) |
| #define GATE_USB31DRD_PCS (CLK_FSYS0A_BASE + 7) |
| #define USB31DRD (CLK_FSYS0A_BASE + 8) |
| |
| /* NUMBER FOR FSYS1 DRIVER STARTS FROM 290 */ |
| #define CLK_FSYS1_BASE (290) |
| #define UMUX_CLKCMU_FSYS1_BUS (CLK_FSYS1_BASE + 0) |
| #define UMUX_CLKCMU_FSYS1_MMC_CARD (CLK_FSYS1_BASE + 1) |
| #define UMUX_CLKCMU_FSYS1_PCIE (CLK_FSYS1_BASE + 2) |
| #define UMUX_CLKCMU_FSYS1_UFS_CARD (CLK_FSYS1_BASE + 3) |
| #define UMUX_CLKCMU_FSYS1_UFS_EMBD (CLK_FSYS1_BASE + 4) |
| #define UMUX_PLL_MMC (CLK_FSYS1_BASE + 5) |
| #define GATE_MMC_CARD (CLK_FSYS1_BASE + 6) |
| #define GATE_PCIE_GEN2_MSTR (CLK_FSYS1_BASE + 7) |
| #define GATE_PCIE_GEN2_PCS (CLK_FSYS1_BASE + 8) |
| #define GATE_PCIE_GEN2_PHY (CLK_FSYS1_BASE + 9) |
| #define GATE_PCIE_GEN2_DBI (CLK_FSYS1_BASE + 10) |
| #define GATE_PCIE_GEN2_APB (CLK_FSYS1_BASE + 11) |
| #define GATE_PCIE_GEN2_SOCPLL (CLK_FSYS1_BASE + 12) |
| #define GATE_PCIE_IA_GEN2 (CLK_FSYS1_BASE + 13) |
| #define GATE_RTIC (CLK_FSYS1_BASE + 14) |
| #define GATE_SSS (CLK_FSYS1_BASE + 15) |
| #define GATE_SYSMMU_FSYS1 (CLK_FSYS1_BASE + 16) |
| #define GATE_UFS_CARD (CLK_FSYS1_BASE + 17) |
| #define GATE_UFS_CARD_FMP (CLK_FSYS1_BASE + 18) |
| #define GATE_UFS_EMBD (CLK_FSYS1_BASE + 19) |
| #define GATE_UFS_EMBD_FMP (CLK_FSYS1_BASE + 20) |
| #define DOUT_CLK_FSYS1_MMC_CARD (CLK_FSYS1_BASE + 21) |
| #define UFS_EMBD (CLK_FSYS1_BASE + 22) |
| |
| /* NUMBER FOR G2D DRIVER STARTS FROM 320 */ |
| #define CLK_G2D_BASE (320) |
| #define UMUX_CLKCMU_G2D_G2D (CLK_G2D_BASE + 0) |
| #define UMUX_CLKCMU_G2D_MSCL (CLK_G2D_BASE + 1) |
| #define GATE_G2D (CLK_G2D_BASE + 2) |
| #define GATE_JPEG (CLK_G2D_BASE + 3) |
| #define GATE_JSQZ (CLK_G2D_BASE + 4) |
| #define GATE_MSCL (CLK_G2D_BASE + 5) |
| #define GATE_SYSMMU_G2DD0 (CLK_G2D_BASE + 6) |
| #define GATE_SYSMMU_G2DD1 (CLK_G2D_BASE + 7) |
| #define GATE_SYSMMU_G2DD2 (CLK_G2D_BASE + 8) |
| |
| /* NUMBER FOR G3D DRIVER STARTS FROM 340 */ |
| #define CLK_G3D_BASE (340) |
| #define GATE_GPU (CLK_G3D_BASE + 0) |
| |
| /* NUMBER FOR ISPHQ DRIVER STARTS FROM 350 */ |
| #define CLK_ISPHQ_BASE (350) |
| #define UMUX_CLKCMU_ISPHQ_BUS (CLK_ISPHQ_BASE + 0) |
| #define GATE_ISPHQ_CMU_ISPHQ (CLK_ISPHQ_BASE + 1) |
| #define GATE_IS_ISPHQ_ISPHQ (CLK_ISPHQ_BASE + 2) |
| #define GATE_IS_ISPHQ_SYSMMU_ISPHQ (CLK_ISPHQ_BASE + 3) |
| #define GATE_IS_ISPHQ_VGEN_LITE_ISPHQ (CLK_ISPHQ_BASE + 4) |
| #define GATE_IS_ISPHQ_ISPHQ_C2COM (CLK_ISPHQ_BASE + 5) |
| |
| /* NUMBER FOR ISPHQ DRIVER STARTS FROM 360 */ |
| #define CLK_ISPLP_BASE (360) |
| #define UMUX_CLKCMU_ISPLP_BUS (CLK_ISPLP_BASE + 0) |
| #define UMUX_CLKCMU_ISPLP_GDC (CLK_ISPLP_BASE + 1) |
| #define GATE_IS_ISPLP_MC_SCALER (CLK_ISPLP_BASE + 2) |
| #define GATE_IS_ISPLP_ISPLP (CLK_ISPLP_BASE + 3) |
| #define GATE_IS_ISPLP_SYSMMU_ISPLP0 (CLK_ISPLP_BASE + 4) |
| #define GATE_IS_ISPLP_SYSMMU_ISPLP1 (CLK_ISPLP_BASE + 5) |
| #define GATE_IS_ISPLP_GDC (CLK_ISPLP_BASE + 6) |
| #define GATE_IS_ISPLP_VGEN_LITE (CLK_ISPLP_BASE + 7) |
| #define GATE_IS_ISPLP_ISPLP_C2 (CLK_ISPLP_BASE + 8) |
| |
| /* NUMBER FOR ISPPRE DRIVER STARTS FROM 380 */ |
| #define CLK_ISPPRE_BASE (380) |
| #define UMUX_CLKCMU_ISPPRE_BUS (CLK_ISPPRE_BASE + 0) |
| #define GATE_IS_ISPPRE_CSIS0 (CLK_ISPPRE_BASE + 1) |
| #define GATE_IS_ISPPRE_CSIS1 (CLK_ISPPRE_BASE + 2) |
| #define GATE_IS_ISPPRE_CSIS2 (CLK_ISPPRE_BASE + 3) |
| #define GATE_IS_ISPPRE_CSIS3 (CLK_ISPPRE_BASE + 4) |
| #define GATE_IS_ISPPRE_PDP_TOP_DMA (CLK_ISPPRE_BASE + 5) |
| #define GATE_IS_ISPPRE_SYSMMU_ISPPRE (CLK_ISPPRE_BASE + 6) |
| #define GATE_IS_ISPPRE_3AA0 (CLK_ISPPRE_BASE + 7) |
| #define GATE_IS_ISPPRE_3AA1 (CLK_ISPPRE_BASE + 8) |
| #define GATE_IS_ISPPRE_PDP_TOP_CORE_TOP (CLK_ISPPRE_BASE + 9) |
| #define GATE_IS_ISPPRE_CSISX4_PDP_RDMA (CLK_ISPPRE_BASE + 10) |
| #define GATE_IS_ISPPRE_VGEN_LITE (CLK_ISPPRE_BASE + 11) |
| #define GATE_IS_ISPPRE_VGEN_LITE1 (CLK_ISPPRE_BASE + 12) |
| #define GATE_IS_ISPPRE_CSIS3_1 (CLK_ISPPRE_BASE + 13) |
| #define GATE_IS_ISPPRE_CSISX4_PDP_DMA (CLK_ISPPRE_BASE + 14) |
| #define GATE_IS_ISPPRE_VGEN_LITE2 (CLK_ISPPRE_BASE + 15) |
| #define GATE_IS_ISPPRE_PAFSTAT0 (CLK_ISPPRE_BASE + 16) |
| #define GATE_IS_ISPPRE_PAFSTAT1 (CLK_ISPPRE_BASE + 17) |
| #define GATE_IS_ISPPRE_QCH_VPP (CLK_ISPPRE_BASE + 18) |
| |
| /* NUMBER FOR IVA DRIVER STARTS FROM 410 */ |
| #define CLK_IVA_BASE (410) |
| #define UMUX_CLKCMU_IVA_BUS (CLK_IVA_BASE + 0) |
| #define GATE_IVA_IVA (CLK_IVA_BASE + 1) |
| #define GATE_IVA_IVA_DEBUG (CLK_IVA_BASE + 2) |
| #define GATE_IVA_INTMEM (CLK_IVA_BASE + 3) |
| #define GATE_SYSMMU_IVA (CLK_IVA_BASE + 4) |
| #define GATE_TREX_RB1_IVA (CLK_IVA_BASE + 5) |
| |
| /* NUMBER FOR IVA DRIVER STARTS FROM 420 */ |
| #define CLK_MFC_BASE (420) |
| #define UMUX_CLKCMU_MFC_MFC (CLK_MFC_BASE + 0) |
| #define UMUX_CLKCMU_MFC_WFD (CLK_MFC_BASE + 1) |
| #define GATE_MFC (CLK_MFC_BASE + 2) |
| #define GATE_SYSMMU_MFCD0 (CLK_MFC_BASE + 3) |
| #define GATE_SYSMMU_MFCD1 (CLK_MFC_BASE + 4) |
| #define GATE_WFD (CLK_MFC_BASE + 5) |
| |
| /* NUMBER FOR NPU0 DRIVER STARTS FROM 440 */ |
| #define CLK_NPU0_BASE (440) |
| #define UMUX_CLKCMU_NPU0_BUS (CLK_NPU0_BASE + 0) |
| #define UMUX_CLKCMU_NPU0_CPU (CLK_NPU0_BASE + 1) |
| #define GATE_NPUC (CLK_NPU0_BASE + 2) |
| #define GATE_NPUD_UNIT0 (CLK_NPU0_BASE + 3) |
| #define GATE_SMMU_NPU0 (CLK_NPU0_BASE + 4) |
| #define DOUT_CLK_NPU0_BUSP (CLK_NPU0_BASE + 5) |
| #define DOUT_CLK_NPU0_CPU (CLK_NPU0_BASE + 6) |
| |
| /* NUMBER FOR NPU1 DRIVER STARTS FROM 460 */ |
| #define CLK_NPU1_BASE (460) |
| #define UMUX_CLKCMU_NPU1_BUS (CLK_NPU1_BASE + 0) |
| #define DOUT_CLK_NPU1_BUSP (CLK_NPU1_BASE + 1) |
| |
| /* NUMBER FOR PERIC0 DRIVER STARTS FROM 470 */ |
| #define CLK_PERIC0_BASE (470) |
| #define UMUX_CLKCMU_PERIC0_BUS (CLK_PERIC0_BASE + 0) |
| #define UMUX_CLKCMU_PERIC0_USI00_USI (CLK_PERIC0_BASE + 1) |
| #define UMUX_CLKCMU_PERIC0_USI01_USI (CLK_PERIC0_BASE + 2) |
| #define UMUX_CLKCMU_PERIC0_USI02_USI (CLK_PERIC0_BASE + 3) |
| #define UMUX_CLKCMU_PERIC0_USI03_USI (CLK_PERIC0_BASE + 4) |
| #define UMUX_CLKCMU_PERIC0_USI04_USI (CLK_PERIC0_BASE + 5) |
| #define UMUX_CLKCMU_PERIC0_USI05_USI (CLK_PERIC0_BASE + 6) |
| #define UMUX_CLKCMU_PERIC0_USI_I2C (CLK_PERIC0_BASE + 7) |
| #define UMUX_CLKCMU_PERIC0_USI12_USI (CLK_PERIC0_BASE + 8) |
| #define UMUX_CLKCMU_PERIC0_USE13_USI (CLK_PERIC0_BASE + 9) |
| #define UMUX_CLKCMU_PERIC0_USI14_USI (CLK_PERIC0_BASE + 10) |
| #define UMUX_CLKCMU_PERIC0_USI15_USI (CLK_PERIC0_BASE + 11) |
| #define UMUX_CLKCMU_PERIC0_UART_DBG (CLK_PERIC0_BASE + 12) |
| #define GATE_GPIO_PERIC0 (CLK_PERIC0_BASE + 13) |
| #define GATE_PWM (CLK_PERIC0_BASE + 14) |
| #define GATE_UART_DBG (CLK_PERIC0_BASE + 15) |
| #define GATE_USI00_I2C (CLK_PERIC0_BASE + 16) |
| #define GATE_USI00_USI (CLK_PERIC0_BASE + 17) |
| #define GATE_USI01_I2C (CLK_PERIC0_BASE + 18) |
| #define GATE_USI01_USI (CLK_PERIC0_BASE + 19) |
| #define GATE_USI02_I2C (CLK_PERIC0_BASE + 20) |
| #define GATE_USI02_USI (CLK_PERIC0_BASE + 21) |
| #define GATE_USI03_I2C (CLK_PERIC0_BASE + 22) |
| #define GATE_USI03_USI (CLK_PERIC0_BASE + 23) |
| #define GATE_USI04_I2C (CLK_PERIC0_BASE + 24) |
| #define GATE_USI04_USI (CLK_PERIC0_BASE + 25) |
| #define GATE_USI05_I2C (CLK_PERIC0_BASE + 26) |
| #define GATE_USI05_USI (CLK_PERIC0_BASE + 27) |
| #define GATE_USI12_I2C (CLK_PERIC0_BASE + 28) |
| #define GATE_USI12_USI (CLK_PERIC0_BASE + 29) |
| #define GATE_USI13_I2C (CLK_PERIC0_BASE + 30) |
| #define GATE_USI13_USI (CLK_PERIC0_BASE + 31) |
| #define GATE_USI14_I2C (CLK_PERIC0_BASE + 32) |
| #define GATE_USI14_USI (CLK_PERIC0_BASE + 33) |
| #define GATE_USI15_I2C (CLK_PERIC0_BASE + 34) |
| #define GATE_USI15_USI (CLK_PERIC0_BASE + 35) |
| #define DOUT_CLK_PERIC0_USI00_USI (CLK_PERIC0_BASE + 36) |
| #define DOUT_CLK_PERIC0_USI01_USI (CLK_PERIC0_BASE + 37) |
| #define DOUT_CLK_PERIC0_USI02_USI (CLK_PERIC0_BASE + 38) |
| #define DOUT_CLK_PERIC0_USI03_USI (CLK_PERIC0_BASE + 39) |
| #define DOUT_CLK_PERIC0_USI04_USI (CLK_PERIC0_BASE + 40) |
| #define DOUT_CLK_PERIC0_USI05_USI (CLK_PERIC0_BASE + 41) |
| #define DOUT_CLK_PERIC0_USI_I2C (CLK_PERIC0_BASE + 42) |
| #define UART_DBG (CLK_PERIC0_BASE + 43) |
| #define DOUT_CLK_PERIC0_USI12_USI (CLK_PERIC0_BASE + 44) |
| #define DOUT_CLK_PERIC0_USI13_USI (CLK_PERIC0_BASE + 45) |
| #define DOUT_CLK_PERIC0_USI14_USI (CLK_PERIC0_BASE + 46) |
| #define DOUT_CLK_PERIC0_USI15_USI (CLK_PERIC0_BASE + 47) |
| |
| /* NUMBER FOR PERIC1 DRIVER STARTS FROM 530 */ |
| #define CLK_PERIC1_BASE (530) |
| #define UMUX_CLKCMU_PERIC1_BUS (CLK_PERIC1_BASE + 0) |
| #define UMUX_CLKCMU_PERIC1_UART_BT (CLK_PERIC1_BASE + 1) |
| #define UMUX_CLKCMU_PERIC1_USI_I2C (CLK_PERIC1_BASE + 2) |
| #define UMUX_CLKCMU_PERIC1_USI06_USI (CLK_PERIC1_BASE + 3) |
| #define UMUX_CLKCMU_PERIC1_USI07_USI (CLK_PERIC1_BASE + 4) |
| #define UMUX_CLKCMU_PERIC1_USI08_USI (CLK_PERIC1_BASE + 5) |
| #define UMUX_CLKCMU_PERIC1_USI09_USI (CLK_PERIC1_BASE + 6) |
| #define UMUX_CLKCMU_PERIC1_USI10_USI (CLK_PERIC1_BASE + 7) |
| #define UMUX_CLKCMU_PERIC1_USI11_USI (CLK_PERIC1_BASE + 8) |
| #define UMUX_CLKCMU_PERIC1_SPI_CAM0 (CLK_PERIC1_BASE + 9) |
| #define UMUX_CLKCMU_PERIC1_I2C_CAM0 (CLK_PERIC1_BASE + 10) |
| #define UMUX_CLKCMU_PERIC1_I2C_CAM1 (CLK_PERIC1_BASE + 11) |
| #define UMUX_CLKCMU_PERIC1_I2C_CAM2 (CLK_PERIC1_BASE + 12) |
| #define UMUX_CLKCMU_PERIC1_I2C_CAM3 (CLK_PERIC1_BASE + 13) |
| #define UMUX_CLKCMU_PERIC1_USI16_USI (CLK_PERIC1_BASE + 14) |
| #define UMUX_CLKCMU_PERIC1_USI17_USI (CLK_PERIC1_BASE + 15) |
| #define GATE_GPIO_PERIC1 (CLK_PERIC1_BASE + 16) |
| #define GATE_I2C_CAM0 (CLK_PERIC1_BASE + 17) |
| #define GATE_I2C_CAM1 (CLK_PERIC1_BASE + 18) |
| #define GATE_I2C_CAM2 (CLK_PERIC1_BASE + 19) |
| #define GATE_I2C_CAM3 (CLK_PERIC1_BASE + 20) |
| #define GATE_I3C_I3C (CLK_PERIC1_BASE + 21) |
| #define GATE_I3C_DMY (CLK_PERIC1_BASE + 22) |
| #define GATE_SPI_CAM0 (CLK_PERIC1_BASE + 23) |
| #define GATE_UART_BT (CLK_PERIC1_BASE + 24) |
| #define GATE_USI06_I2C (CLK_PERIC1_BASE + 25) |
| #define GATE_USI06_USI (CLK_PERIC1_BASE + 26) |
| #define GATE_USI07_I2C (CLK_PERIC1_BASE + 27) |
| #define GATE_USI07_USI (CLK_PERIC1_BASE + 28) |
| #define GATE_USI08_I2C (CLK_PERIC1_BASE + 29) |
| #define GATE_USI08_USI (CLK_PERIC1_BASE + 30) |
| #define GATE_USI09_I2C (CLK_PERIC1_BASE + 31) |
| #define GATE_USI09_USI (CLK_PERIC1_BASE + 32) |
| #define GATE_USI10_I2C (CLK_PERIC1_BASE + 33) |
| #define GATE_USI10_USI (CLK_PERIC1_BASE + 34) |
| #define GATE_USI11_I2C (CLK_PERIC1_BASE + 35) |
| #define GATE_USI11_USI (CLK_PERIC1_BASE + 36) |
| #define GATE_USI16_I3C_DMY (CLK_PERIC1_BASE + 37) |
| #define GATE_USI16_I3C_I3C (CLK_PERIC1_BASE + 38) |
| #define GATE_USI16_USI (CLK_PERIC1_BASE + 39) |
| #define GATE_USI17_I2C (CLK_PERIC1_BASE + 40) |
| #define GATE_USI17_USI (CLK_PERIC1_BASE + 41) |
| #define DOUT_CLK_PERIC1_UART_BT (CLK_PERIC1_BASE + 42) |
| #define DOUT_CLK_PERIC1_USI_I2C (CLK_PERIC1_BASE + 43) |
| #define DOUT_CLK_PERIC1_USI06_USI (CLK_PERIC1_BASE + 44) |
| #define DOUT_CLK_PERIC1_USI07_USI (CLK_PERIC1_BASE + 45) |
| #define DOUT_CLK_PERIC1_USI08_USI (CLK_PERIC1_BASE + 46) |
| #define DOUT_CLK_PERIC1_I2C_CAM0 (CLK_PERIC1_BASE + 47) |
| #define DOUT_CLK_PERIC1_I2C_CAM1 (CLK_PERIC1_BASE + 48) |
| #define DOUT_CLK_PERIC1_I2C_CAM2 (CLK_PERIC1_BASE + 49) |
| #define DOUT_CLK_PERIC1_I2C_CAM3 (CLK_PERIC1_BASE + 50) |
| #define DOUT_CLK_PERIC1_SPI_CAM0 (CLK_PERIC1_BASE + 51) |
| #define DOUT_CLK_PERIC1_USI09_USI (CLK_PERIC1_BASE + 52) |
| #define DOUT_CLK_PERIC1_USI10_USI (CLK_PERIC1_BASE + 53) |
| #define DOUT_CLK_PERIC1_USI11_USI (CLK_PERIC1_BASE + 54) |
| #define DOUT_CLK_PERIC1_USI16_USI (CLK_PERIC1_BASE + 55) |
| #define DOUT_CLK_PERIC1_USI17_USI (CLK_PERIC1_BASE + 56) |
| |
| /* NUMBER FOR PERIS DRIVER STARTS FROM 600 */ |
| #define CLK_PERIS_BASE (600) |
| #define UMUX_CLKCMU_PERIS_BUS (CLK_PERIS_BASE + 0) |
| #define GATE_GIC (CLK_PERIS_BASE + 1) |
| #define GATE_MCT (CLK_PERIS_BASE + 2) |
| #define GATE_OTP_CON_BIRA (CLK_PERIS_BASE + 3) |
| #define GATE_OTP_CON_BISR (CLK_PERIS_BASE + 4) |
| #define GATE_OTP_CON_TOP (CLK_PERIS_BASE + 5) |
| #define GATE_PERIS_CMU_PERIS (CLK_PERIS_BASE + 6) |
| #define GATE_SYSREG_PERIS (CLK_PERIS_BASE + 7) |
| #define GATE_TMU_SUB (CLK_PERIS_BASE + 8) |
| #define GATE_TMU_TOP (CLK_PERIS_BASE + 9) |
| #define GATE_WDT_CLUSTER0 (CLK_PERIS_BASE + 10) |
| #define GATE_WDT_CLUSTER2 (CLK_PERIS_BASE + 11) |
| |
| /* NUMBER FOR VRA2 DRIVER STARTS FROM 620 */ |
| #define CLK_VRA2_BASE (620) |
| #define UMUX_CLKCMU_VRA2_BUS (CLK_VRA2_BASE + 0) |
| #define GATE_VRA2 (CLK_VRA2_BASE + 1) |
| #define DOUT_CLK_VRA2_BUSP (CLK_VRA2_BASE + 2) |
| #define UMUX_CLKCMU_VRA2_STR (CLK_VRA2_BASE + 3) |
| #define GATE_STR (CLK_VRA2_BASE + 4) |
| #define GATE_SYSMMU_VRA2 (CLK_VRA2_BASE + 5) |
| |
| /* NUMBER FOR VTS DRIVER STARTS FROM 630 */ |
| #define CLK_VTS_BASE (630) |
| #define UMUX_CLKCMU_VTS_BUS (CLK_VTS_BASE + 0) |
| #define UMUX_CLKCMU_VTS_RCO (CLK_VTS_BASE + 1) |
| #define GATE_CORTEXM4INTEGRATION_CPU (CLK_VTS_BASE + 2) |
| #define GATE_DMIC_IF_PCLK (CLK_VTS_BASE + 3) |
| #define GATE_DMIC_IF_DMIC_CLK (CLK_VTS_BASE + 4) |
| #define GATE_DMIC_IF_3RD_PCLK (CLK_VTS_BASE + 5) |
| #define GATE_DMIC_IF_3RD_DMIC_CLK (CLK_VTS_BASE + 6) |
| #define GATE_GPIO_VTS (CLK_VTS_BASE + 7) |
| #define GATE_HWACG_SYS_DMIC0 (CLK_VTS_BASE + 8) |
| #define GATE_HWACG_SYS_DMIC1 (CLK_VTS_BASE + 9) |
| #define GATE_HWACG_SYS_DMIC2 (CLK_VTS_BASE + 10) |
| #define GATE_HWACG_SYS_DMIC3 (CLK_VTS_BASE + 11) |
| #define GATE_MAILBOX_ABOX_VTS (CLK_VTS_BASE + 12) |
| #define GATE_MAILBOX_AP_VTS (CLK_VTS_BASE + 13) |
| #define GATE_SWEEPER_C_VTS (CLK_VTS_BASE + 14) |
| #define GATE_SYSREG_VTS (CLK_VTS_BASE + 15) |
| #define GATE_TIMER_VTS (CLK_VTS_BASE + 16) |
| #define GATE_WDT_VTS (CLK_VTS_BASE + 17) |
| #define DOUT_CLK_VTS_DMIC_IF (CLK_VTS_BASE + 18) |
| #define DOUT_CLK_VTS_DMIC (CLK_VTS_BASE + 19) |
| #define DOUT_CLK_VTS_DMIC_DIV2 (CLK_VTS_BASE + 20) |
| #define DOUT_CLK_VTS_BUS (CLK_VTS_BASE + 21) |
| |
| /* NUMBER FOR CLKOUT PORT STARTS FROM 920 */ |
| #define CLK_CLKOUT_BASE (900) |
| #define OSC_NFC (CLK_CLKOUT_BASE + 0) |
| #define OSC_AUD (CLK_CLKOUT_BASE + 1) |
| |
| /* NUMBER FOR SYSMMU DRIVER STARTS FROM 1180 */ |
| #define CLK_SYSMMU_BASE (1180) |
| |
| /* NUMBER OF DVFS DRIVER STARTS FROM 1200 */ |
| #define CLK_DVFS_BASE (1200) |
| |
| /* must be greater than maximal clock id */ |
| #define CLK_NR_CLKS (1125 + 1) |
| |
| #define ACPM_DVFS_MIF (0x0B040000) |
| #define ACPM_DVFS_INT (0x0B040001) |
| #define ACPM_DVFS_CPUCL0 (0x0B040002) |
| #define ACPM_DVFS_CPUCL1 (0x0B040003) |
| #define ACPM_DVFS_CPUCL2 (0x0B040004) |
| #define ACPM_DVFS_NPU (0x0B040005) |
| #define ACPM_DVFS_DISP (0x0B040006) |
| #define ACPM_DVFS_SCORE (0x0B040007) |
| #define ACPM_DVFS_AUD (0x0B040008) |
| #define ACPM_DVS_CP (0x0B040009) |
| #define ACPM_DVFS_G3D (0x0B04000A) |
| #define ACPM_DVFS_INTCAM (0x0B04000B) |
| #define ACPM_DVFS_CAM (0x0B04000C) |
| #define ACPM_DVFS_IVA (0x0B04000D) |
| #define ACPM_DVFS_MFC (0x0B04000E) |
| |
| #define EWF_CMU_APM (0) |
| #define EWF_CMU_AUD (1) |
| #define EWF_CMU_BUSC (3) |
| #define EWF_CMU_VRA2 (4) |
| #define EWF_CMU_CMGP (5) |
| #define EWF_CMU_CORE (6) |
| #define EWF_CMU_CPUCL0 (7) |
| #define EWF_CMU_CPUCL1 (8) |
| #define EWF_CMU_CPUCL2 (9) |
| #define EWF_CMU_NPU0 (10) |
| #define EWF_CMU_NPU1 (11) |
| #define EWF_CMU_DPU (12) |
| #define EWF_CMU_DSPM (13) |
| #define EWF_CMU_DSPS (14) |
| #define EWF_CMU_FSYS0 (15) |
| #define EWF_CMU_FSYS1 (16) |
| #define EWF_CMU_G2D (17) |
| #define EWF_CMU_G3D (18) |
| #define EWF_CMU_ISPHQ (19) |
| #define EWF_CMU_ISPLP (20) |
| #define EWF_CMU_ISPPRE (21) |
| #define EWF_CMU_IVA (22) |
| #define EWF_CMU_MFC (23) |
| #define EWF_CMU_MIF0 (24) |
| #define EWF_CMU_MIF1 (25) |
| #define EWF_CMU_MIF2 (26) |
| #define EWF_CMU_MIF3 (27) |
| #define EWF_CMU_PERIC0 (28) |
| #define EWF_CMU_PERIC1 (29) |
| #define EWF_CMU_PERIS (30) |
| #define EWF_CMU_VTS (31) |
| |
| #endif /* _DT_BINDINGS_CLOCK_EXYNOS_9820_H */ |