| menu "DesignWare PCI Core Support" |
| |
| config PCIE_DW |
| bool |
| |
| config PCIE_DW_HOST |
| bool |
| depends on PCI |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIE_DW |
| |
| config PCIE_DW_EP |
| bool |
| depends on PCI_ENDPOINT |
| select PCIE_DW |
| |
| config PCI_DRA7XX |
| bool "TI DRA7xx PCIe controller" |
| depends on SOC_DRA7XX || COMPILE_TEST |
| depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT |
| depends on OF && HAS_IOMEM && TI_PIPE3 |
| help |
| Enables support for the PCIe controller in the DRA7xx SoC. There |
| are two instances of PCIe controller in DRA7xx. This controller can |
| work either as EP or RC. In order to enable host-specific features |
| PCI_DRA7XX_HOST must be selected and in order to enable device- |
| specific features PCI_DRA7XX_EP must be selected. This uses |
| the DesignWare core. |
| |
| if PCI_DRA7XX |
| |
| config PCI_DRA7XX_HOST |
| bool "PCI DRA7xx Host Mode" |
| depends on PCI |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIE_DW_HOST |
| default y |
| help |
| Enables support for the PCIe controller in the DRA7xx SoC to work in |
| host mode. |
| |
| config PCI_DRA7XX_EP |
| bool "PCI DRA7xx Endpoint Mode" |
| depends on PCI_ENDPOINT |
| select PCIE_DW_EP |
| help |
| Enables support for the PCIe controller in the DRA7xx SoC to work in |
| endpoint mode. |
| |
| endif |
| |
| config PCIE_DW_PLAT |
| bool "Platform bus based DesignWare PCIe Controller" |
| depends on PCI |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIE_DW_HOST |
| ---help--- |
| This selects the DesignWare PCIe controller support. Select this if |
| you have a PCIe controller on Platform bus. |
| |
| If you have a controller with this interface, say Y or M here. |
| |
| If unsure, say N. |
| |
| config PCI_EXYNOS |
| bool "Samsung Exynos PCIe controller" |
| depends on PCI |
| depends on ARCH_EXYNOS && OF |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| |
| config EXYNOS_PCIE_IOMMU |
| bool "Enable Exynos PCIe IOMMU" |
| depends on PCI_EXYNOS && IOMMU_SUPPORT |
| |
| config PCIE_IOMMU_HISTORY_LOG |
| bool "Enable Exynos PCIe IOMMU Map/Unmap History" |
| depends on EXYNOS_PCIE_IOMMU |
| default y |
| help |
| Say Y here if you want to see map/unmap informations for |
| debugging prupopse. It stores map/unmap requested address and |
| size. |
| If no problmes, say N. |
| |
| config SEC_PANIC_PCIE_ERR |
| depends on PCI_EXYNOS |
| default n |
| bool "Force PANIC on PCIe Main Errors" |
| |
| config PCI_IMX6 |
| bool "Freescale i.MX6 PCIe controller" |
| depends on PCI |
| depends on SOC_IMX6Q |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| |
| config PCIE_SPEAR13XX |
| bool "STMicroelectronics SPEAr PCIe controller" |
| depends on PCI |
| depends on ARCH_SPEAR13XX |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here if you want PCIe support on SPEAr13XX SoCs. |
| |
| config PCI_KEYSTONE |
| bool "TI Keystone PCIe controller" |
| depends on PCI |
| depends on ARCH_KEYSTONE |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here if you want to enable PCI controller support on Keystone |
| SoCs. The PCI controller on Keystone is based on DesignWare hardware |
| and therefore the driver re-uses the DesignWare core functions to |
| implement the driver. |
| |
| config PCI_LAYERSCAPE |
| bool "Freescale Layerscape PCIe controller" |
| depends on PCI |
| depends on OF && (ARM || ARCH_LAYERSCAPE) |
| depends on PCI_MSI_IRQ_DOMAIN |
| select MFD_SYSCON |
| select PCIE_DW_HOST |
| help |
| Say Y here if you want PCIe controller support on Layerscape SoCs. |
| |
| config PCI_HISI |
| depends on OF && ARM64 |
| bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" |
| depends on PCI |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| select PCI_HOST_COMMON |
| help |
| Say Y here if you want PCIe controller support on HiSilicon |
| Hip05 and Hip06 SoCs |
| |
| config PCIE_QCOM |
| bool "Qualcomm PCIe controller" |
| depends on PCI |
| depends on ARCH_QCOM && OF |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here to enable PCIe controller support on Qualcomm SoCs. The |
| PCIe controller uses the DesignWare core plus Qualcomm-specific |
| hardware wrappers. |
| |
| config PCIE_ARMADA_8K |
| bool "Marvell Armada-8K PCIe controller" |
| depends on PCI |
| depends on ARCH_MVEBU |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here if you want to enable PCIe controller support on |
| Armada-8K SoCs. The PCIe controller on Armada-8K is based on |
| DesignWare hardware and therefore the driver re-uses the |
| DesignWare core functions to implement the driver. |
| |
| config PCIE_ARTPEC6 |
| bool "Axis ARTPEC-6 PCIe controller" |
| depends on PCI |
| depends on MACH_ARTPEC6 |
| depends on PCI_MSI_IRQ_DOMAIN |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here to enable PCIe controller support on Axis ARTPEC-6 |
| SoCs. This PCIe controller uses the DesignWare core. |
| |
| config PCIE_KIRIN |
| depends on OF && ARM64 |
| bool "HiSilicon Kirin series SoCs PCIe controllers" |
| depends on PCI |
| select PCIEPORTBUS |
| select PCIE_DW_HOST |
| help |
| Say Y here if you want PCIe controller support |
| on HiSilicon Kirin series SoCs. |
| |
| endmenu |