| #ifndef __CMUCAL_VCLK_H__ |
| #define __CMUCAL_VCLK_H__ |
| |
| #include "../cmucal.h" |
| |
| enum vclk_id { |
| |
| /* DVFS VCLK*/ |
| VCLK_VDDI = DFS_VCLK_TYPE, |
| VCLK_VDD_MIF, |
| VCLK_VDD_CAM, |
| VCLK_VDD_CHEETAH, |
| VCLK_VDD_ANANKE, |
| VCLK_VDD_PROMETHEUS, |
| end_of_dfs_vclk, |
| num_of_dfs_vclk = end_of_dfs_vclk - DFS_VCLK_TYPE, |
| |
| |
| /* SPECIAL VCLK*/ |
| VCLK_MUX_CLK_AUD_UAIF3 = (MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE, |
| VCLK_MUX_BUC_CMUREF, |
| VCLK_MUX_CLK_CMGP_ADC, |
| VCLK_CLKCMU_CMGP_BUS, |
| VCLK_CLKCMU_APM_BUS, |
| VCLK_MUX_CMU_CMUREF, |
| VCLK_MUX_CORE_CMUREF, |
| VCLK_MUX_CPUCL0_CMUREF, |
| VCLK_MUX_CPUCL1_CMUREF, |
| VCLK_MUX_CPUCL2_CMUREF, |
| VCLK_MUX_MIF_CMUREF, |
| VCLK_MUX_MIF1_CMUREF, |
| VCLK_MUX_MIF2_CMUREF, |
| VCLK_MUX_MIF3_CMUREF, |
| VCLK_CLKCMU_FSYS0_DPGTC, |
| VCLK_MUX_CLKCMU_FSYS0_PCIE, |
| VCLK_MUX_CLKCMU_FSYS0A_USBDP_DEBUG, |
| VCLK_MUX_CLKCMU_FSYS1_PCIE, |
| VCLK_CLKCMU_FSYS1_UFS_EMBD, |
| VCLK_DIV_CLK_I2C_CMGP0, |
| VCLK_DIV_CLK_USI_CMGP1, |
| VCLK_DIV_CLK_USI_CMGP0, |
| VCLK_DIV_CLK_USI_CMGP2, |
| VCLK_DIV_CLK_USI_CMGP3, |
| VCLK_DIV_CLK_I2C_CMGP1, |
| VCLK_DIV_CLK_I2C_CMGP2, |
| VCLK_DIV_CLK_I2C_CMGP3, |
| VCLK_CLKCMU_HPM, |
| VCLK_CLKCMU_CIS_CLK0, |
| VCLK_CLKCMU_CIS_CLK1, |
| VCLK_CLKCMU_CIS_CLK2, |
| VCLK_CLKCMU_CIS_CLK3, |
| VCLK_CLKCMU_CIS_CLK4, |
| VCLK_DIV_CLK_CPUCL0_CMUREF, |
| VCLK_DIV_CLK_CLUSTER0_PERIPHCLK, |
| VCLK_DIV_CLK_CPUCL1_CMUREF, |
| VCLK_DIV_CLK_CPUCL2_CMUREF, |
| VCLK_DIV_CLK_CLUSTER2_ATCLK, |
| VCLK_DIV_CLK_FSYS1_MMC_CARD, |
| VCLK_DIV_CLK_MIF_PRE, |
| VCLK_DIV_CLK_MIF1_PRE, |
| VCLK_DIV_CLK_MIF2_PRE, |
| VCLK_DIV_CLK_MIF3_PRE, |
| VCLK_DIV_CLK_PERIC0_USI00_USI, |
| VCLK_MUX_CLKCMU_PERIC0_IP, |
| VCLK_DIV_CLK_PERIC0_USI01_USI, |
| VCLK_DIV_CLK_PERIC0_USI02_USI, |
| VCLK_DIV_CLK_PERIC0_USI03_USI, |
| VCLK_DIV_CLK_PERIC0_USI04_USI, |
| VCLK_DIV_CLK_PERIC0_USI05_USI, |
| VCLK_DIV_CLK_PERIC0_UART_DBG, |
| VCLK_DIV_CLK_PERIC0_USI12_USI, |
| VCLK_DIV_CLK_PERIC0_USI13_USI, |
| VCLK_DIV_CLK_PERIC0_USI14_USI, |
| VCLK_DIV_CLK_PERIC0_USI15_USI, |
| VCLK_DIV_CLK_PERIC1_UART_BT, |
| VCLK_MUX_CLKCMU_PERIC1_IP, |
| VCLK_DIV_CLK_PERIC1_USI06_USI, |
| VCLK_DIV_CLK_PERIC1_USI07_USI, |
| VCLK_DIV_CLK_PERIC1_USI08_USI, |
| VCLK_DIV_CLK_PERIC1_I2C_CAM0, |
| VCLK_DIV_CLK_PERIC1_I2C_CAM1, |
| VCLK_DIV_CLK_PERIC1_I2C_CAM2, |
| VCLK_DIV_CLK_PERIC1_I2C_CAM3, |
| VCLK_DIV_CLK_PERIC1_SPI_CAM0, |
| VCLK_DIV_CLK_PERIC1_USI09_USI, |
| VCLK_DIV_CLK_PERIC1_USI10_USI, |
| VCLK_DIV_CLK_PERIC1_USI11_USI, |
| VCLK_DIV_CLK_PERIC1_USI16_USI, |
| VCLK_DIV_CLK_PERIC1_USI17_USI, |
| VCLK_DIV_CLK_VTS_DMIC, |
| end_of_vclk, |
| num_of_vclk = end_of_vclk - ((MASK_OF_ID & end_of_dfs_vclk) | VCLK_TYPE), |
| |
| |
| /* COMMON VCLK*/ |
| VCLK_BLK_CMU = (MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE, |
| VCLK_BLK_CPUCL0, |
| VCLK_BLK_MIF1, |
| VCLK_BLK_MIF2, |
| VCLK_BLK_MIF3, |
| VCLK_BLK_APM, |
| VCLK_BLK_DSPS, |
| VCLK_BLK_G3D, |
| VCLK_BLK_S2D, |
| VCLK_BLK_VTS, |
| VCLK_BLK_AUD, |
| VCLK_BLK_BUSC, |
| VCLK_BLK_CMGP, |
| VCLK_BLK_CORE, |
| VCLK_BLK_CPUCL2, |
| VCLK_BLK_DPU, |
| VCLK_BLK_DSPM, |
| VCLK_BLK_G2D, |
| VCLK_BLK_ISPHQ, |
| VCLK_BLK_ISPLP, |
| VCLK_BLK_ISPPRE, |
| VCLK_BLK_IVA, |
| VCLK_BLK_MFC, |
| VCLK_BLK_NPU1, |
| VCLK_BLK_PERIC0, |
| VCLK_BLK_PERIC1, |
| VCLK_BLK_VRA2, |
| end_of_common_vclk, |
| num_of_common_vclk = end_of_common_vclk - ((MASK_OF_ID & end_of_vclk) | COMMON_VCLK_TYPE), |
| |
| |
| /* GATE VCLK*/ |
| VCLK_IP_LHS_AXI_D_APM = (MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE, |
| VCLK_IP_LHM_AXI_P_APM, |
| VCLK_IP_WDT_APM, |
| VCLK_IP_SYSREG_APM, |
| VCLK_IP_MAILBOX_APM_AP, |
| VCLK_IP_APBIF_PMU_ALIVE, |
| VCLK_IP_INTMEM, |
| VCLK_IP_LHM_AXI_C_MODEM, |
| VCLK_IP_LHS_AXI_G_SCAN2DRAM, |
| VCLK_IP_PMU_INTR_GEN, |
| VCLK_IP_PEM, |
| VCLK_IP_SPEEDY_APM, |
| VCLK_IP_XIU_DP_APM, |
| VCLK_IP_APM_CMU_APM, |
| VCLK_IP_VGEN_LITE_APM, |
| VCLK_IP_GREBEINTEGRATION, |
| VCLK_IP_APBIF_GPIO_ALIVE, |
| VCLK_IP_APBIF_TOP_RTC, |
| VCLK_IP_MAILBOX_AP_CP, |
| VCLK_IP_MAILBOX_AP_CP_S, |
| VCLK_IP_GREBEINTEGRATION_DBGCORE, |
| VCLK_IP_DTZPC_APM, |
| VCLK_IP_LHM_AXI_C_VTS, |
| VCLK_IP_MAILBOX_APM_VTS, |
| VCLK_IP_MAILBOX_AP_DBGCORE, |
| VCLK_IP_LHS_AXI_LP_VTS, |
| VCLK_IP_MAILBOX_APM_CP, |
| VCLK_IP_LHS_AXI_G_DBGCORE, |
| VCLK_IP_APBIF_RTC, |
| VCLK_IP_LHS_AXI_C_CMGP, |
| VCLK_IP_SPEEDY_SUB_APM, |
| VCLK_IP_AUD_CMU_AUD, |
| VCLK_IP_LHS_AXI_D_AUD, |
| VCLK_IP_PPMU_AUD, |
| VCLK_IP_SYSREG_AUD, |
| VCLK_IP_ABOX, |
| VCLK_IP_LHS_ATB_T0_AUD, |
| VCLK_IP_GPIO_AUD, |
| VCLK_IP_AXI_US_32TO128, |
| VCLK_IP_BTM_AUD, |
| VCLK_IP_PERI_AXI_ASB, |
| VCLK_IP_LHM_AXI_P_AUD, |
| VCLK_IP_WDT_AUD, |
| VCLK_IP_DMIC, |
| VCLK_IP_TREX_AUD, |
| VCLK_IP_DFTMUX_AUD, |
| VCLK_IP_SMMU_AUD, |
| VCLK_IP_WRAP2_CONV_AUD, |
| VCLK_IP_XIU_P_AUD, |
| VCLK_IP_AD_APB_SMMU_AUD, |
| VCLK_IP_AXI2APB_AUD, |
| VCLK_IP_AD_APB_SMMU_AUD_S, |
| VCLK_IP_LHS_ATB_T1_AUD, |
| VCLK_IP_VGEN_LITE_AUD, |
| VCLK_IP_BUSC_CMU_BUSC, |
| VCLK_IP_AXI2APB_BUSCP0, |
| VCLK_IP_AXI2APB_BUSC_TDP, |
| VCLK_IP_SYSREG_BUSC, |
| VCLK_IP_BUSIF_CMUTOPC, |
| VCLK_IP_TREX_D0_BUSC, |
| VCLK_IP_TREX_P_BUSC, |
| VCLK_IP_LHS_AXI_P_MIF0, |
| VCLK_IP_LHS_AXI_P_MIF1, |
| VCLK_IP_LHS_AXI_P_MIF2, |
| VCLK_IP_LHS_AXI_P_MIF3, |
| VCLK_IP_LHS_AXI_P_PERIS, |
| VCLK_IP_LHS_AXI_P_PERIC0, |
| VCLK_IP_LHS_AXI_P_PERIC1, |
| VCLK_IP_ASYNCSFR_WR_SMC, |
| VCLK_IP_LHS_AXI_D_IVASC, |
| VCLK_IP_LHM_ACEL_D0_G2D, |
| VCLK_IP_LHM_ACEL_D1_G2D, |
| VCLK_IP_LHM_ACEL_D2_G2D, |
| VCLK_IP_LHM_ACEL_D_FSYS0, |
| VCLK_IP_LHM_ACEL_D_IVA, |
| VCLK_IP_LHM_ACEL_D_NPU, |
| VCLK_IP_LHM_AXI_D0_DPU, |
| VCLK_IP_LHM_AXI_D0_MFC, |
| VCLK_IP_LHM_AXI_D_ISPPRE, |
| VCLK_IP_LHM_AXI_D1_DPU, |
| VCLK_IP_LHM_AXI_D1_MFC, |
| VCLK_IP_LHM_AXI_D2_DPU, |
| VCLK_IP_LHM_AXI_D0_ISPLP, |
| VCLK_IP_LHS_AXI_P_DPU, |
| VCLK_IP_LHS_AXI_P_ISPPRE, |
| VCLK_IP_LHS_AXI_P_DSPM, |
| VCLK_IP_LHS_AXI_P_FSYS0, |
| VCLK_IP_LHS_AXI_P_G2D, |
| VCLK_IP_LHS_AXI_P_ISPHQ, |
| VCLK_IP_LHS_AXI_P_ISPLP, |
| VCLK_IP_LHS_AXI_P_IVA, |
| VCLK_IP_LHS_AXI_P_MFC, |
| VCLK_IP_LHM_ACEL_D_FSYS1, |
| VCLK_IP_LHM_AXI_D_APM, |
| VCLK_IP_LHM_AXI_D1_ISPLP, |
| VCLK_IP_LHS_AXI_P_FSYS1, |
| VCLK_IP_SIREX, |
| VCLK_IP_LHM_ACEL_D0_DSPM, |
| VCLK_IP_LHM_ACEL_D1_DSPM, |
| VCLK_IP_LHM_AXI_D_ISPHQ, |
| VCLK_IP_TREX_RB_BUSC, |
| VCLK_IP_PPFW, |
| VCLK_IP_WRAP2_CONV_BUSC, |
| VCLK_IP_VGEN_PDMA0, |
| VCLK_IP_VGEN_LITE_BUSC, |
| VCLK_IP_HPM_BUSC, |
| VCLK_IP_BUSIF_HPMBUSC, |
| VCLK_IP_PDMA0, |
| VCLK_IP_SBIC, |
| VCLK_IP_SPDMA, |
| VCLK_IP_AD_APB_DIT, |
| VCLK_IP_DIT, |
| VCLK_IP_D_TZPC_BUSC, |
| VCLK_IP_LHS_AXI_P_NPU, |
| VCLK_IP_MMCACHE, |
| VCLK_IP_TREX_D1_BUSC, |
| VCLK_IP_AXI2APB_BUSCP1, |
| VCLK_IP_LHM_AXI_D_AUD, |
| VCLK_IP_LHS_AXI_P_AUD, |
| VCLK_IP_LHS_DBG_G_BUSC, |
| VCLK_IP_LHM_AXI_D_VTS, |
| VCLK_IP_LHS_AXI_P_VTS, |
| VCLK_IP_QE_SPDMA, |
| VCLK_IP_QE_PDMA0, |
| VCLK_IP_XIU_D_BUSC, |
| VCLK_IP_BAAW_P_VTS, |
| VCLK_IP_AXI_US_64TO128, |
| VCLK_IP_BAAW_P_NPU, |
| VCLK_IP_LHM_AXI_D_VRA2, |
| VCLK_IP_CMGP_CMU_CMGP, |
| VCLK_IP_ADC_CMGP, |
| VCLK_IP_GPIO_CMGP, |
| VCLK_IP_I2C_CMGP0, |
| VCLK_IP_I2C_CMGP1, |
| VCLK_IP_I2C_CMGP2, |
| VCLK_IP_I2C_CMGP3, |
| VCLK_IP_SYSREG_CMGP, |
| VCLK_IP_USI_CMGP0, |
| VCLK_IP_USI_CMGP1, |
| VCLK_IP_USI_CMGP2, |
| VCLK_IP_USI_CMGP3, |
| VCLK_IP_SYSREG_CMGP2CP, |
| VCLK_IP_SYSREG_CMGP2PMU_AP, |
| VCLK_IP_DTZPC_CMGP, |
| VCLK_IP_LHM_AXI_C_CMGP, |
| VCLK_IP_SYSREG_CMGP2APM, |
| VCLK_IP_CORE_CMU_CORE, |
| VCLK_IP_SYSREG_CORE, |
| VCLK_IP_AXI2APB_CORE_0, |
| VCLK_IP_MPACE2AXI_0, |
| VCLK_IP_MPACE2AXI_1, |
| VCLK_IP_PPC_DEBUG_CCI, |
| VCLK_IP_TREX_P0_CORE, |
| VCLK_IP_PPMU_CPUCL2_0, |
| VCLK_IP_LHM_DBG_G0_DMC, |
| VCLK_IP_LHM_DBG_G1_DMC, |
| VCLK_IP_LHM_DBG_G2_DMC, |
| VCLK_IP_LHM_DBG_G3_DMC, |
| VCLK_IP_LHS_ATB_T_BDU, |
| VCLK_IP_ADM_APB_G_BDU, |
| VCLK_IP_BDU, |
| VCLK_IP_TREX_P1_CORE, |
| VCLK_IP_AXI2APB_CORE_TP, |
| VCLK_IP_PPFW_G3D, |
| VCLK_IP_LHS_AXI_P_G3D, |
| VCLK_IP_LHS_AXI_P_CPUCL0, |
| VCLK_IP_LHS_AXI_P_CPUCL2, |
| VCLK_IP_LHM_AXI_D0_CP, |
| VCLK_IP_LHM_ACE_D0_G3D, |
| VCLK_IP_LHM_ACE_D1_G3D, |
| VCLK_IP_LHM_ACE_D2_G3D, |
| VCLK_IP_LHM_ACE_D3_G3D, |
| VCLK_IP_TREX_D_CORE, |
| VCLK_IP_HPM_CORE, |
| VCLK_IP_BUSIF_HPMCORE, |
| VCLK_IP_BPS_D0_G3D, |
| VCLK_IP_BPS_D1_G3D, |
| VCLK_IP_BPS_D2_G3D, |
| VCLK_IP_BPS_D3_G3D, |
| VCLK_IP_PPCFW_G3D, |
| VCLK_IP_LHS_AXI_P_CP, |
| VCLK_IP_APB_ASYNC_PPFW_G3D, |
| VCLK_IP_BAAW_CP, |
| VCLK_IP_BPS_P_G3D, |
| VCLK_IP_LHS_AXI_P_APM, |
| VCLK_IP_PPMU_CPUCL2_1, |
| VCLK_IP_D_TZPC_CORE, |
| VCLK_IP_AXI2APB_CORE_1, |
| VCLK_IP_XIU_P_CORE, |
| VCLK_IP_PPC_CPUCL2_0, |
| VCLK_IP_PPC_CPUCL2_1, |
| VCLK_IP_PPC_G3D0, |
| VCLK_IP_PPC_G3D1, |
| VCLK_IP_PPC_G3D2, |
| VCLK_IP_PPC_G3D3, |
| VCLK_IP_PPC_IRPS0, |
| VCLK_IP_PPC_IRPS1, |
| VCLK_IP_LHM_AXI_D1_CP, |
| VCLK_IP_LHS_AXI_L_CORE, |
| VCLK_IP_AXI2APB_CORE_2, |
| VCLK_IP_LHM_AXI_L_CORE, |
| VCLK_IP_LHM_ACE_D0_CLUSTER0, |
| VCLK_IP_LHM_ACE_D1_CLUSTER0, |
| VCLK_IP_PPC_CPUCL0_0, |
| VCLK_IP_PPC_CPUCL0_1, |
| VCLK_IP_PPMU_CPUCL0_0, |
| VCLK_IP_PPMU_CPUCL0_1, |
| VCLK_IP_LHM_DBG_G_BUSC, |
| VCLK_IP_MPACE_ASB_D0_MIF, |
| VCLK_IP_MPACE_ASB_D1_MIF, |
| VCLK_IP_MPACE_ASB_D2_MIF, |
| VCLK_IP_MPACE_ASB_D3_MIF, |
| VCLK_IP_AXI_ASB_CSSYS, |
| VCLK_IP_LHM_AXI_G_CSSYS, |
| VCLK_IP_CCI, |
| VCLK_IP_AXI2APB_CPUCL0, |
| VCLK_IP_SYSREG_CPUCL0, |
| VCLK_IP_BUSIF_HPMCPUCL0, |
| VCLK_IP_CSSYS, |
| VCLK_IP_LHM_ATB_T0_AUD, |
| VCLK_IP_LHM_ATB_T_BDU, |
| VCLK_IP_LHM_ATB_T0_CLUSTER0, |
| VCLK_IP_LHM_ATB_T0_CLUSTER2, |
| VCLK_IP_LHM_ATB_T1_CLUSTER0, |
| VCLK_IP_LHM_ATB_T1_CLUSTER2, |
| VCLK_IP_LHM_ATB_T2_CLUSTER0, |
| VCLK_IP_LHM_ATB_T3_CLUSTER0, |
| VCLK_IP_SECJTAG, |
| VCLK_IP_LHM_AXI_P_CPUCL0, |
| VCLK_IP_LHS_ACE_D0_CLUSTER0, |
| VCLK_IP_LHS_ATB_T0_CLUSTER0, |
| VCLK_IP_LHS_ATB_T1_CLUSTER0, |
| VCLK_IP_LHS_ATB_T2_CLUSTER0, |
| VCLK_IP_LHS_ATB_T3_CLUSTER0, |
| VCLK_IP_ADM_APB_G_CLUSTER0, |
| VCLK_IP_CPUCL0_CMU_CPUCL0, |
| VCLK_IP_CPUCL0, |
| VCLK_IP_LHM_ATB_T4_CLUSTER0, |
| VCLK_IP_LHM_ATB_T5_CLUSTER0, |
| VCLK_IP_LHS_ACE_D1_CLUSTER0, |
| VCLK_IP_LHS_ATB_T4_CLUSTER0, |
| VCLK_IP_LHS_ATB_T5_CLUSTER0, |
| VCLK_IP_D_TZPC_CPUCL0, |
| VCLK_IP_LHM_ATB_T1_AUD, |
| VCLK_IP_LHS_AXI_G_INT_CSSYS, |
| VCLK_IP_LHM_AXI_G_INT_CSSYS, |
| VCLK_IP_LHS_AXI_G_INT_DBGCORE, |
| VCLK_IP_LHM_AXI_G_INT_DBGCORE, |
| VCLK_IP_XIU_P_CPUCL0, |
| VCLK_IP_XIU_DP_CSSYS, |
| VCLK_IP_TREX_CPUCL0, |
| VCLK_IP_AXI_US_32TO64_G_DBGCORE, |
| VCLK_IP_LHS_AXI_G_CSSYS, |
| VCLK_IP_HPM_CPUCL0_1, |
| VCLK_IP_HPM_CPUCL0_0, |
| VCLK_IP_APB_ASYNC_P_CSSYS_0, |
| VCLK_IP_LHS_AXI_G_INT_ETR, |
| VCLK_IP_LHM_AXI_G_DBGCORE, |
| VCLK_IP_LHM_AXI_G_INT_ETR, |
| VCLK_IP_AXI2APB_P_CSSYS, |
| VCLK_IP_BPS_CPUCL0, |
| VCLK_IP_CPUCL1_CMU_CPUCL1, |
| VCLK_IP_CPUCL1, |
| VCLK_IP_CPUCL2_CMU_CPUCL2, |
| VCLK_IP_SYSREG_CPUCL2, |
| VCLK_IP_BUSIF_HPMCPUCL2, |
| VCLK_IP_HPM_CPUCL2_0, |
| VCLK_IP_CLUSTER2, |
| VCLK_IP_AXI2APB_CPUCL2, |
| VCLK_IP_LHM_AXI_P_CPUCL2, |
| VCLK_IP_HPM_CPUCL2_1, |
| VCLK_IP_HPM_CPUCL2_2, |
| VCLK_IP_D_TZPC_CPUCL2, |
| VCLK_IP_DPU_CMU_DPU, |
| VCLK_IP_BTM_DPUD0, |
| VCLK_IP_BTM_DPUD1, |
| VCLK_IP_SYSREG_DPU, |
| VCLK_IP_AXI2APB_DPUP1, |
| VCLK_IP_AXI2APB_DPUP0, |
| VCLK_IP_SYSMMU_DPUD0, |
| VCLK_IP_LHM_AXI_P_DPU, |
| VCLK_IP_LHS_AXI_D1_DPU, |
| VCLK_IP_XIU_P_DPU, |
| VCLK_IP_AD_APB_DECON0, |
| VCLK_IP_AD_APB_DECON1, |
| VCLK_IP_AD_APB_MIPI_DSIM1, |
| VCLK_IP_AD_APB_DPP, |
| VCLK_IP_LHS_AXI_D2_DPU, |
| VCLK_IP_BTM_DPUD2, |
| VCLK_IP_SYSMMU_DPUD2, |
| VCLK_IP_AD_APB_DPU_DMA, |
| VCLK_IP_AD_APB_DPU_WB_MUX, |
| VCLK_IP_SYSMMU_DPUD1, |
| VCLK_IP_PPMU_DPUD0, |
| VCLK_IP_PPMU_DPUD1, |
| VCLK_IP_PPMU_DPUD2, |
| VCLK_IP_AD_APB_MIPI_DSIM0, |
| VCLK_IP_AD_APB_DECON2, |
| VCLK_IP_AD_APB_SYSMMU_DPUD0, |
| VCLK_IP_AD_APB_SYSMMU_DPUD0_S, |
| VCLK_IP_AD_APB_SYSMMU_DPUD1, |
| VCLK_IP_AD_APB_SYSMMU_DPUD1_S, |
| VCLK_IP_AD_APB_SYSMMU_DPUD2, |
| VCLK_IP_AD_APB_SYSMMU_DPUD2_S, |
| VCLK_IP_DPU, |
| VCLK_IP_WRAPPER_FOR_S5I6280_HSI_DCPHY_COMBO_TOP, |
| VCLK_IP_AD_APB_DPU_DMA_PGEN, |
| VCLK_IP_LHS_AXI_D0_DPU, |
| VCLK_IP_D_TZPC_DPU, |
| VCLK_IP_AD_APB_MCD, |
| VCLK_IP_DSPM_CMU_DSPM, |
| VCLK_IP_SYSREG_DSPM, |
| VCLK_IP_AXI2APB_DSPM, |
| VCLK_IP_PPMU_DSPM0, |
| VCLK_IP_SYSMMU_DSPM0, |
| VCLK_IP_BTM_DSPM0, |
| VCLK_IP_LHM_AXI_P_DSPM, |
| VCLK_IP_LHS_ACEL_D0_DSPM, |
| VCLK_IP_LHM_AXI_P_IVADSPM, |
| VCLK_IP_LHS_AXI_P_DSPMIVA, |
| VCLK_IP_WRAP2_CONV_DSPM, |
| VCLK_IP_AD_APB_DSPM0, |
| VCLK_IP_AD_APB_DSPM1, |
| VCLK_IP_AD_APB_DSPM3, |
| VCLK_IP_AD_AXI_DSPM0, |
| VCLK_IP_BTM_DSPM1, |
| VCLK_IP_LHS_ACEL_D1_DSPM, |
| VCLK_IP_LHS_AXI_P_DSPMDSPS, |
| VCLK_IP_PPMU_DSPM1, |
| VCLK_IP_SYSMMU_DSPM1, |
| VCLK_IP_ADM_APB_DSPM, |
| VCLK_IP_LHM_AXI_D0_DSPSDSPM, |
| VCLK_IP_XIU_P_DSPM, |
| VCLK_IP_VGEN_LITE_DSPM, |
| VCLK_IP_AD_APB_DSPM2, |
| VCLK_IP_SCORE_TS_II, |
| VCLK_IP_D_TZPC_DSPM, |
| VCLK_IP_LHM_AST_ISPPREDSPM, |
| VCLK_IP_LHM_AST_ISPLPDSPM, |
| VCLK_IP_LHM_AST_ISPHQDSPM, |
| VCLK_IP_LHS_AST_DSPMISPPRE, |
| VCLK_IP_LHS_AST_DSPMISPLP, |
| VCLK_IP_XIU_D_DSPM, |
| VCLK_IP_BAAW_DSPM, |
| VCLK_IP_LHS_AXI_D_DSPMNPU0, |
| VCLK_IP_DSPS_CMU_DSPS, |
| VCLK_IP_AXI2APB_DSPS, |
| VCLK_IP_LHM_AXI_P_DSPMDSPS, |
| VCLK_IP_SYSREG_DSPS, |
| VCLK_IP_LHS_AXI_D_DSPSIVA, |
| VCLK_IP_LHS_AXI_D0_DSPSDSPM, |
| VCLK_IP_SCORE_BARON, |
| VCLK_IP_LHM_AXI_D_IVADSPS, |
| VCLK_IP_D_TZPC_DSPS, |
| VCLK_IP_VGEN_LITE_DSPS, |
| VCLK_IP_FSYS0_CMU_FSYS0, |
| VCLK_IP_LHS_ACEL_D_FSYS0, |
| VCLK_IP_LHM_AXI_P_FSYS0, |
| VCLK_IP_GPIO_FSYS0, |
| VCLK_IP_SYSREG_FSYS0, |
| VCLK_IP_XIU_D_FSYS0, |
| VCLK_IP_BTM_FSYS0, |
| VCLK_IP_DP_LINK, |
| VCLK_IP_VGEN_LITE_FSYS0, |
| VCLK_IP_LHM_AXI_D_USB, |
| VCLK_IP_LHS_AXI_P_USB, |
| VCLK_IP_PPMU_FSYS0, |
| VCLK_IP_SYSMMU_PCIE_GEN3A, |
| VCLK_IP_SYSMMU_PCIE_GEN3B, |
| VCLK_IP_XIU_P0_FSYS0, |
| VCLK_IP_PCIE_GEN3, |
| VCLK_IP_PCIE_IA_GEN3A, |
| VCLK_IP_PCIE_IA_GEN3B, |
| VCLK_IP_D_TZPC_FSYS0, |
| VCLK_IP_FSYS0A_CMU_FSYS0A, |
| VCLK_IP_USB31DRD, |
| VCLK_IP_LHM_AXI_P_USB, |
| VCLK_IP_LHS_AXI_D_USB, |
| VCLK_IP_FSYS1_CMU_FSYS1, |
| VCLK_IP_MMC_CARD, |
| VCLK_IP_PCIE_GEN2, |
| VCLK_IP_SSS, |
| VCLK_IP_RTIC, |
| VCLK_IP_SYSREG_FSYS1, |
| VCLK_IP_GPIO_FSYS1, |
| VCLK_IP_LHS_ACEL_D_FSYS1, |
| VCLK_IP_LHM_AXI_P_FSYS1, |
| VCLK_IP_XIU_D_FSYS1, |
| VCLK_IP_XIU_P_FSYS1, |
| VCLK_IP_PPMU_FSYS1, |
| VCLK_IP_BTM_FSYS1, |
| VCLK_IP_UFS_CARD, |
| VCLK_IP_ADM_AHB_SSS, |
| VCLK_IP_SYSMMU_FSYS1, |
| VCLK_IP_VGEN_LITE_FSYS1, |
| VCLK_IP_PCIE_IA_GEN2, |
| VCLK_IP_D_TZPC_FSYS1, |
| VCLK_IP_UFS_EMBD, |
| VCLK_IP_PUF, |
| VCLK_IP_QE_RTIC, |
| VCLK_IP_QE_SSS, |
| VCLK_IP_BAAW_SSS, |
| VCLK_IP_G2D_CMU_G2D, |
| VCLK_IP_PPMU_G2DD0, |
| VCLK_IP_PPMU_G2DD1, |
| VCLK_IP_SYSMMU_G2DD0, |
| VCLK_IP_SYSREG_G2D, |
| VCLK_IP_LHS_ACEL_D0_G2D, |
| VCLK_IP_LHS_ACEL_D1_G2D, |
| VCLK_IP_LHM_AXI_P_G2D, |
| VCLK_IP_AS_P_G2D, |
| VCLK_IP_AXI2APB_G2DP0, |
| VCLK_IP_BTM_G2DD0, |
| VCLK_IP_BTM_G2DD1, |
| VCLK_IP_XIU_P_G2D, |
| VCLK_IP_AXI2APB_G2DP1, |
| VCLK_IP_BTM_G2DD2, |
| VCLK_IP_QE_JPEG, |
| VCLK_IP_QE_MSCL, |
| VCLK_IP_SYSMMU_G2DD2, |
| VCLK_IP_PPMU_G2DD2, |
| VCLK_IP_LHS_ACEL_D2_G2D, |
| VCLK_IP_AS_P_JPEG, |
| VCLK_IP_XIU_D_G2D, |
| VCLK_IP_AS_P_MSCL, |
| VCLK_IP_AS_P_ASTC, |
| VCLK_IP_AS_P_SYSMMU_NS_G2DD0, |
| VCLK_IP_AS_P_SYSMMU_NS_G2DD2, |
| VCLK_IP_AS_P_SYSMMU_S_G2DD0, |
| VCLK_IP_AS_P_SYSMMU_S_G2DD2, |
| VCLK_IP_QE_ASTC, |
| VCLK_IP_VGEN_LITE_G2D, |
| VCLK_IP_G2D, |
| VCLK_IP_AS_P_SYSMMU_NS_G2DD1, |
| VCLK_IP_AS_P_SYSMMU_S_G2DD1, |
| VCLK_IP_SYSMMU_G2DD1, |
| VCLK_IP_JPEG, |
| VCLK_IP_MSCL, |
| VCLK_IP_ASTC, |
| VCLK_IP_AS_P_JSQZ, |
| VCLK_IP_QE_JSQZ, |
| VCLK_IP_D_TZPC_G2D, |
| VCLK_IP_JSQZ, |
| VCLK_IP_XIU_P_G3D, |
| VCLK_IP_LHM_AXI_P_G3D, |
| VCLK_IP_BUSIF_HPMG3D, |
| VCLK_IP_HPM_G3D0, |
| VCLK_IP_SYSREG_G3D, |
| VCLK_IP_G3D_CMU_G3D, |
| VCLK_IP_LHS_AXI_G3DSFR, |
| VCLK_IP_VGEN_LITE_G3D, |
| VCLK_IP_GPU, |
| VCLK_IP_AXI2APB_G3D, |
| VCLK_IP_LHM_AXI_G3DSFR, |
| VCLK_IP_GRAY2BIN_G3D, |
| VCLK_IP_D_TZPC_G3D, |
| VCLK_IP_ASB_G3D, |
| VCLK_IP_LHM_AXI_P_ISPHQ, |
| VCLK_IP_LHS_AXI_D_ISPHQ, |
| VCLK_IP_IS_ISPHQ, |
| VCLK_IP_SYSREG_ISPHQ, |
| VCLK_IP_ISPHQ_CMU_ISPHQ, |
| VCLK_IP_LHM_ATB_ISPPREISPHQ, |
| VCLK_IP_LHS_ATB_ISPHQISPLP, |
| VCLK_IP_BTM_ISPHQ, |
| VCLK_IP_LHM_ATB_VO_ISPLPISPHQ, |
| VCLK_IP_LHS_AST_VO_ISPHQISPPRE, |
| VCLK_IP_D_TZPC_ISPHQ, |
| VCLK_IP_LHS_AST_ISPHQDSPM, |
| VCLK_IP_LHM_AXI_P_ISPLP, |
| VCLK_IP_LHS_AXI_D0_ISPLP, |
| VCLK_IP_BTM_ISPLP0, |
| VCLK_IP_IS_ISPLP, |
| VCLK_IP_SYSREG_ISPLP, |
| VCLK_IP_ISPLP_CMU_ISPLP, |
| VCLK_IP_BTM_ISPLP1, |
| VCLK_IP_LHS_AXI_D1_ISPLP, |
| VCLK_IP_LHM_ATB_ISPHQISPLP, |
| VCLK_IP_LHM_AST_VO_ISPPREISPLP, |
| VCLK_IP_LHM_ATB_ISPPREISPLP, |
| VCLK_IP_LHS_ATB_VO_ISPLPISPHQ, |
| VCLK_IP_D_TZPC_ISPLP, |
| VCLK_IP_LHS_AST_ISPLPDSPM, |
| VCLK_IP_LHM_AST_DSPMISPLP, |
| VCLK_IP_LHS_AXI_P_ISPLPVRA2, |
| VCLK_IP_LHM_AXI_D_VRA2ISPLP, |
| VCLK_IP_IS_ISPPRE, |
| VCLK_IP_LHS_AXI_D_ISPPRE, |
| VCLK_IP_BTM_ISPPRE, |
| VCLK_IP_LHM_AXI_P_ISPPRE, |
| VCLK_IP_SYSREG_ISPPRE, |
| VCLK_IP_ISPPRE_CMU_ISPPRE, |
| VCLK_IP_LHS_ATB_ISPPREISPLP, |
| VCLK_IP_LHS_ATB_ISPPREISPHQ, |
| VCLK_IP_D_TZPC_ISPPRE, |
| VCLK_IP_LHS_AST_ISPPREDSPM, |
| VCLK_IP_LHM_AST_DSPMISPPRE, |
| VCLK_IP_BUSIF_HPMISPPRE, |
| VCLK_IP_HPM_ISPPRE, |
| VCLK_IP_D_TZPC_ISPPRE1, |
| VCLK_IP_LHS_AST_VO_ISPPREISPLP, |
| VCLK_IP_LHM_AST_VO_ISPHQISPPRE, |
| VCLK_IP_IVA_CMU_IVA, |
| VCLK_IP_LHS_ACEL_D_IVA, |
| VCLK_IP_LHS_AXI_D_IVADSPS, |
| VCLK_IP_LHS_AXI_P_IVADSPM, |
| VCLK_IP_LHM_AXI_P_DSPMIVA, |
| VCLK_IP_LHM_AXI_P_IVA, |
| VCLK_IP_BTM_IVA, |
| VCLK_IP_PPMU_IVA, |
| VCLK_IP_SYSMMU_IVA, |
| VCLK_IP_XIU_P_IVA, |
| VCLK_IP_AD_APB_IVA0, |
| VCLK_IP_AXI2APB_2M_IVA, |
| VCLK_IP_AXI2APB_IVA, |
| VCLK_IP_SYSREG_IVA, |
| VCLK_IP_LHM_AXI_D_IVASC, |
| VCLK_IP_ADM_DAP_IVA, |
| VCLK_IP_LHM_AXI_D_DSPSIVA, |
| VCLK_IP_AD_APB_IVA1, |
| VCLK_IP_AD_APB_IVA2, |
| VCLK_IP_VGEN_LITE_IVA, |
| VCLK_IP_IVA, |
| VCLK_IP_IVA_INTMEM, |
| VCLK_IP_XIU_D0_IVA, |
| VCLK_IP_XIU_D1_IVA, |
| VCLK_IP_D_TZPC_IVA, |
| VCLK_IP_XIU_D2_IVA, |
| VCLK_IP_TREX_RB1_IVA, |
| VCLK_IP_QE_IVA, |
| VCLK_IP_WRAP2_CONV_IVA, |
| VCLK_IP_MFC_CMU_MFC, |
| VCLK_IP_AS_APB_MFC, |
| VCLK_IP_AXI2APB_MFC, |
| VCLK_IP_SYSREG_MFC, |
| VCLK_IP_LHS_AXI_D0_MFC, |
| VCLK_IP_LHS_AXI_D1_MFC, |
| VCLK_IP_LHM_AXI_P_MFC, |
| VCLK_IP_SYSMMU_MFCD0, |
| VCLK_IP_SYSMMU_MFCD1, |
| VCLK_IP_PPMU_MFCD0, |
| VCLK_IP_PPMU_MFCD1, |
| VCLK_IP_BTM_MFCD0, |
| VCLK_IP_BTM_MFCD1, |
| VCLK_IP_AS_APB_SYSMMU_NS_MFCD0, |
| VCLK_IP_AS_APB_SYSMMU_NS_MFCD1, |
| VCLK_IP_AS_APB_SYSMMU_S_MFCD0, |
| VCLK_IP_AS_APB_SYSMMU_S_MFCD1, |
| VCLK_IP_AS_APB_WFD_NS, |
| VCLK_IP_AS_AXI_WFD, |
| VCLK_IP_PPMU_MFCD2, |
| VCLK_IP_XIU_D_MFC, |
| VCLK_IP_AS_APB_WFD_S, |
| VCLK_IP_VGEN_MFC, |
| VCLK_IP_MFC, |
| VCLK_IP_WFD, |
| VCLK_IP_LH_ATB_MFC, |
| VCLK_IP_D_TZPC_MFC, |
| VCLK_IP_MIF_CMU_MIF, |
| VCLK_IP_DDRPHY, |
| VCLK_IP_SYSREG_MIF, |
| VCLK_IP_BUSIF_HPMMIF, |
| VCLK_IP_LHM_AXI_P_MIF, |
| VCLK_IP_AXI2APB_MIF, |
| VCLK_IP_PPC_DVFS, |
| VCLK_IP_PPC_DEBUG, |
| VCLK_IP_APBBR_DDRPHY, |
| VCLK_IP_APBBR_DMC, |
| VCLK_IP_APBBR_DMCTZ, |
| VCLK_IP_HPM_MIF, |
| VCLK_IP_DMC, |
| VCLK_IP_QCH_ADAPTER_PPC_DEBUG, |
| VCLK_IP_QCH_ADAPTER_PPC_DVFS, |
| VCLK_IP_D_TZPC_MIF, |
| VCLK_IP_HPM_MIF1, |
| VCLK_IP_MIF1_CMU_MIF1, |
| VCLK_IP_APBBR_DDRPHY1, |
| VCLK_IP_APBBR_DMC1, |
| VCLK_IP_APBBR_DMCTZ1, |
| VCLK_IP_AXI2APB_MIF1, |
| VCLK_IP_BUSIF_HPMMIF1, |
| VCLK_IP_DDRPHY1, |
| VCLK_IP_DMC1, |
| VCLK_IP_LHM_AXI_P_MIF1, |
| VCLK_IP_PPMUPPC_DEBUG1, |
| VCLK_IP_PPMUPPC_DVFS1, |
| VCLK_IP_SYSREG_MIF1, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DEBUG1, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DVFS1, |
| VCLK_IP_HPM_MIF2, |
| VCLK_IP_APBBR_DDRPHY2, |
| VCLK_IP_APBBR_DMC2, |
| VCLK_IP_APBBR_DMCTZ2, |
| VCLK_IP_AXI2APB_MIF2, |
| VCLK_IP_BUSIF_HPMMIF2, |
| VCLK_IP_DDRPHY2, |
| VCLK_IP_DMC2, |
| VCLK_IP_LHM_AXI_P_MIF2, |
| VCLK_IP_PPMUPPC_DEBUG2, |
| VCLK_IP_PPMUPPC_DVFS2, |
| VCLK_IP_SYSREG_MIF2, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DEBUG2, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DVFS2, |
| VCLK_IP_MIF2_CMU_MIF2, |
| VCLK_IP_HPM_MIF3, |
| VCLK_IP_APBBR_DDRPHY3, |
| VCLK_IP_APBBR_DMC3, |
| VCLK_IP_APBBR_DMCTZ3, |
| VCLK_IP_AXI2APB_MIF3, |
| VCLK_IP_BUSIF_HPMMIF3, |
| VCLK_IP_DDRPHY3, |
| VCLK_IP_DMC3, |
| VCLK_IP_LHM_AXI_P_MIF3, |
| VCLK_IP_PPMUPPC_DEBUG3, |
| VCLK_IP_PPMUPPC_DVFS3, |
| VCLK_IP_SYSREG_MIF3, |
| VCLK_IP_MIF3_CMU_MIF3, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DEBUG3, |
| VCLK_IP_QCH_ADAPTER_PPMUPPC_DVFS3, |
| VCLK_IP_LHS_ACEL_D_NPU, |
| VCLK_IP_LHS_AXI_P_NPU1, |
| VCLK_IP_NPU0_CMU_NPU0, |
| VCLK_IP_APB_ASYNC_SI0, |
| VCLK_IP_APB_ASYNC_SMMU_NS, |
| VCLK_IP_AXI2APB_NPU0, |
| VCLK_IP_BTM_NPU0, |
| VCLK_IP_D_TZPC_NPU0, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_0, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_1, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_2, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_3, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_4, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_5, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_6, |
| VCLK_IP_LHM_AST_D_NPUD1_D1_7, |
| VCLK_IP_LHM_AST_P_NPU1_DONE, |
| VCLK_IP_LHM_AXI_D_DSPMNPU0, |
| VCLK_IP_LHM_AXI_P_NPU, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_0, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_1, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_2, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_3, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_4, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_5, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_6, |
| VCLK_IP_LHS_AST_D_NPUD0_D1_7, |
| VCLK_IP_LHS_AST_P_NPUD1_SETREG, |
| VCLK_IP_LHS_AXI_D_IDPSRAM1, |
| VCLK_IP_LHS_AXI_D_IDPSRAM3, |
| VCLK_IP_NPUC, |
| VCLK_IP_NPUD_UNIT0, |
| VCLK_IP_PPMU_CPUDMA, |
| VCLK_IP_PPMU_RFM, |
| VCLK_IP_QE_CPUDMA, |
| VCLK_IP_QE_RFM, |
| VCLK_IP_SMMU_NPU0, |
| VCLK_IP_SYSREG_NPU0, |
| VCLK_IP_XIU_D_NPU0, |
| VCLK_IP_APB_ASYNC_SMMU_S, |
| VCLK_IP_VGEN_LITE_NPU0, |
| VCLK_IP_PPMU_NPU0, |
| VCLK_IP_NPU0_PPC_WRAPPER, |
| VCLK_IP_NPU1_CMU_NPU1, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_0, |
| VCLK_IP_LHM_AXI_P_NPU1, |
| VCLK_IP_APB_ASYNC_SI1, |
| VCLK_IP_AXI2APB_NPU1, |
| VCLK_IP_D_TZPC_NPU1, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_1, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_2, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_3, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_4, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_5, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_6, |
| VCLK_IP_LHM_AST_D_NPUD0_D1_7, |
| VCLK_IP_LHM_AST_P_NPUD1_SETREG, |
| VCLK_IP_LHM_AXI_D_IDPSRAM1, |
| VCLK_IP_LHM_AXI_D_IDPSRAM3, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_0, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_1, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_2, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_3, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_4, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_5, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_6, |
| VCLK_IP_LHS_AST_D_NPUD1_D1_7, |
| VCLK_IP_SYSREG_NPU1, |
| VCLK_IP_LHS_AST_P_NPU1_DONE, |
| VCLK_IP_NPUD_UNIT1, |
| VCLK_IP_PPMU_NPU1, |
| VCLK_IP_NPU1_PPC_WRAPPER, |
| VCLK_IP_GPIO_PERIC0, |
| VCLK_IP_PWM, |
| VCLK_IP_SYSREG_PERIC0, |
| VCLK_IP_USI00_USI, |
| VCLK_IP_USI01_USI, |
| VCLK_IP_USI02_USI, |
| VCLK_IP_USI03_USI, |
| VCLK_IP_AXI2APB_PERIC0P0, |
| VCLK_IP_PERIC0_CMU_PERIC0, |
| VCLK_IP_USI04_USI, |
| VCLK_IP_AXI2APB_PERIC0P1, |
| VCLK_IP_USI05_USI, |
| VCLK_IP_USI00_I2C, |
| VCLK_IP_USI01_I2C, |
| VCLK_IP_USI02_I2C, |
| VCLK_IP_USI03_I2C, |
| VCLK_IP_USI04_I2C, |
| VCLK_IP_USI05_I2C, |
| VCLK_IP_UART_DBG, |
| VCLK_IP_XIU_P_PERIC0, |
| VCLK_IP_LHM_AXI_P_PERIC0, |
| VCLK_IP_USI12_USI, |
| VCLK_IP_USI12_I2C, |
| VCLK_IP_USI13_I2C, |
| VCLK_IP_USI13_USI, |
| VCLK_IP_USI14_USI, |
| VCLK_IP_USI14_I2C, |
| VCLK_IP_D_TZPC_PERIC0, |
| VCLK_IP_USI15_I2C, |
| VCLK_IP_USI15_USI, |
| VCLK_IP_AXI2APB_PERIC1P1, |
| VCLK_IP_GPIO_PERIC1, |
| VCLK_IP_SYSREG_PERIC1, |
| VCLK_IP_UART_BT, |
| VCLK_IP_I2C_CAM1, |
| VCLK_IP_I2C_CAM2, |
| VCLK_IP_I2C_CAM3, |
| VCLK_IP_USI06_USI, |
| VCLK_IP_USI07_USI, |
| VCLK_IP_USI08_USI, |
| VCLK_IP_I2C_CAM0, |
| VCLK_IP_XIU_P_PERIC1, |
| VCLK_IP_AXI2APB_PERIC1P0, |
| VCLK_IP_PERIC1_CMU_PERIC1, |
| VCLK_IP_SPI_CAM0, |
| VCLK_IP_USI09_USI, |
| VCLK_IP_USI06_I2C, |
| VCLK_IP_USI10_USI, |
| VCLK_IP_USI07_I2C, |
| VCLK_IP_USI08_I2C, |
| VCLK_IP_USI09_I2C, |
| VCLK_IP_USI10_I2C, |
| VCLK_IP_LHM_AXI_P_PERIC1, |
| VCLK_IP_USI11_USI, |
| VCLK_IP_USI11_I2C, |
| VCLK_IP_D_TZPC_PERIC1, |
| VCLK_IP_I3C, |
| VCLK_IP_USI16_USI, |
| VCLK_IP_USI17_USI, |
| VCLK_IP_USI16_I3C, |
| VCLK_IP_USI17_I2C, |
| VCLK_IP_AXI2APB_PERISP, |
| VCLK_IP_XIU_P_PERIS, |
| VCLK_IP_SYSREG_PERIS, |
| VCLK_IP_WDT_CLUSTER2, |
| VCLK_IP_WDT_CLUSTER0, |
| VCLK_IP_PERIS_CMU_PERIS, |
| VCLK_IP_AD_AXI_P_PERIS, |
| VCLK_IP_OTP_CON_BIRA, |
| VCLK_IP_GIC, |
| VCLK_IP_LHM_AXI_P_PERIS, |
| VCLK_IP_MCT, |
| VCLK_IP_OTP_CON_TOP, |
| VCLK_IP_D_TZPC_PERIS, |
| VCLK_IP_TMU_SUB, |
| VCLK_IP_TMU_TOP, |
| VCLK_IP_OTP_CON_BISR, |
| VCLK_IP_S2D_CMU_S2D, |
| VCLK_IP_VRA2_CMU_VRA2, |
| VCLK_IP_AS_APB_VRA2, |
| VCLK_IP_AXI2APB_VRA2, |
| VCLK_IP_D_TZPC_VRA2, |
| VCLK_IP_LHM_AXI_P_ISPLPVRA2, |
| VCLK_IP_LHS_AXI_D_VRA2ISPLP, |
| VCLK_IP_QE_VRA2, |
| VCLK_IP_SYSREG_VRA2, |
| VCLK_IP_VGEN_LITE_VRA2, |
| VCLK_IP_VRA2, |
| VCLK_IP_AS_APB_STR, |
| VCLK_IP_BTM_VRA2, |
| VCLK_IP_PPMU_VRA2, |
| VCLK_IP_SYSMMU_VRA2, |
| VCLK_IP_STR, |
| VCLK_IP_LHS_AXI_D_VRA2, |
| VCLK_IP_DMIC_IF, |
| VCLK_IP_SYSREG_VTS, |
| VCLK_IP_VTS_CMU_VTS, |
| VCLK_IP_AHB_BUSMATRIX, |
| VCLK_IP_LHM_AXI_P_VTS, |
| VCLK_IP_GPIO_VTS, |
| VCLK_IP_WDT_VTS, |
| VCLK_IP_DMIC_AHB0, |
| VCLK_IP_DMIC_AHB1, |
| VCLK_IP_LHS_AXI_C_VTS, |
| VCLK_IP_ASYNCINTERRUPT, |
| VCLK_IP_HWACG_SYS_DMIC0, |
| VCLK_IP_HWACG_SYS_DMIC1, |
| VCLK_IP_SS_VTS_GLUE, |
| VCLK_IP_CORTEXM4INTEGRATION, |
| VCLK_IP_U_DMIC_CLK_MUX, |
| VCLK_IP_LHM_AXI_LP_VTS, |
| VCLK_IP_LHS_AXI_D_VTS, |
| VCLK_IP_BAAW_C_VTS, |
| VCLK_IP_D_TZPC_VTS, |
| VCLK_IP_VGEN_LITE, |
| VCLK_IP_BPS_LP_VTS, |
| VCLK_IP_BPS_P_VTS, |
| VCLK_IP_XHB_LP_VTS, |
| VCLK_IP_XHB_P_VTS, |
| VCLK_IP_SWEEPER_C_VTS, |
| VCLK_IP_SWEEPER_D_VTS, |
| VCLK_IP_BAAW_D_VTS, |
| VCLK_IP_MAILBOX_ABOX_VTS, |
| VCLK_IP_DMIC_AHB2, |
| VCLK_IP_DMIC_AHB3, |
| VCLK_IP_HWACG_SYS_DMIC2, |
| VCLK_IP_HWACG_SYS_DMIC3, |
| VCLK_IP_DMIC_IF_3RD, |
| VCLK_IP_MAILBOX_AP_VTS, |
| VCLK_IP_TIMER, |
| end_of_gate_vclk, |
| num_of_gate_vclk = end_of_gate_vclk - ((MASK_OF_ID & end_of_common_vclk) | GATE_VCLK_TYPE), |
| |
| }; |
| #endif |