| #include "../cmucal.h" |
| #include "cmucal-sfr.h" |
| #include "cmucal-qch.h" |
| |
| unsigned int cmucal_qch_size = 771; |
| struct cmucal_qch cmucal_qch_list[] = { |
| CLK_QCH(APBIF_GPIO_ALIVE_QCH, QCH_CON_APBIF_GPIO_ALIVE_QCH_ENABLE, QCH_CON_APBIF_GPIO_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_GPIO_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_GPIO_ALIVE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBIF_PMU_ALIVE_QCH, QCH_CON_APBIF_PMU_ALIVE_QCH_ENABLE, QCH_CON_APBIF_PMU_ALIVE_QCH_CLOCK_REQ, QCH_CON_APBIF_PMU_ALIVE_QCH_EXPIRE_VAL, QCH_CON_APBIF_PMU_ALIVE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBIF_RTC_QCH, QCH_CON_APBIF_RTC_QCH_ENABLE, QCH_CON_APBIF_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_RTC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBIF_TOP_RTC_QCH, QCH_CON_APBIF_TOP_RTC_QCH_ENABLE, QCH_CON_APBIF_TOP_RTC_QCH_CLOCK_REQ, QCH_CON_APBIF_TOP_RTC_QCH_EXPIRE_VAL, QCH_CON_APBIF_TOP_RTC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APM_CMU_APM_QCH, QCH_CON_APM_CMU_APM_QCH_ENABLE, QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, QCH_CON_APM_CMU_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DTZPC_APM_QCH, QCH_CON_DTZPC_APM_QCH_ENABLE, QCH_CON_DTZPC_APM_QCH_CLOCK_REQ, QCH_CON_DTZPC_APM_QCH_EXPIRE_VAL, QCH_CON_DTZPC_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GREBEINTEGRATION_QCH_GREBE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_GREBE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GREBEINTEGRATION_QCH_DBG, QCH_CON_GREBEINTEGRATION_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_QCH_DBG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GREBEINTEGRATION_DBGCORE_QCH_GREBE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_ENABLE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_GREBE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GREBEINTEGRATION_DBGCORE_QCH_DBG, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_ENABLE, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_CLOCK_REQ, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_EXPIRE_VAL, QCH_CON_GREBEINTEGRATION_DBGCORE_QCH_DBG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(INTMEM_QCH, QCH_CON_INTMEM_QCH_ENABLE, QCH_CON_INTMEM_QCH_CLOCK_REQ, QCH_CON_INTMEM_QCH_EXPIRE_VAL, QCH_CON_INTMEM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_C_MODEM_QCH, QCH_CON_LHM_AXI_C_MODEM_QCH_ENABLE, QCH_CON_LHM_AXI_C_MODEM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_MODEM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_MODEM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_C_VTS_QCH, QCH_CON_LHM_AXI_C_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_C_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_APM_QCH, QCH_CON_LHM_AXI_P_APM_QCH_ENABLE, QCH_CON_LHM_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_C_CMGP_QCH, QCH_CON_LHS_AXI_C_CMGP_QCH_ENABLE, QCH_CON_LHS_AXI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_APM_QCH, QCH_CON_LHS_AXI_D_APM_QCH_ENABLE, QCH_CON_LHS_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_DBGCORE_QCH, QCH_CON_LHS_AXI_G_DBGCORE_QCH_ENABLE, QCH_CON_LHS_AXI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_SCAN2DRAM_QCH, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_ENABLE, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_LP_VTS_QCH, QCH_CON_LHS_AXI_LP_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_LP_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_LP_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_APM_AP_QCH, QCH_CON_MAILBOX_APM_AP_QCH_ENABLE, QCH_CON_MAILBOX_APM_AP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_AP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_AP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_APM_CP_QCH, QCH_CON_MAILBOX_APM_CP_QCH_ENABLE, QCH_CON_MAILBOX_APM_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_APM_VTS_QCH, QCH_CON_MAILBOX_APM_VTS_QCH_ENABLE, QCH_CON_MAILBOX_APM_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_APM_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_APM_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_AP_CP_QCH, QCH_CON_MAILBOX_AP_CP_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_AP_CP_S_QCH, QCH_CON_MAILBOX_AP_CP_S_QCH_ENABLE, QCH_CON_MAILBOX_AP_CP_S_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_CP_S_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_CP_S_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_AP_DBGCORE_QCH, QCH_CON_MAILBOX_AP_DBGCORE_QCH_ENABLE, QCH_CON_MAILBOX_AP_DBGCORE_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_DBGCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PEM_QCH, QCH_CON_PEM_QCH_ENABLE, QCH_CON_PEM_QCH_CLOCK_REQ, QCH_CON_PEM_QCH_EXPIRE_VAL, QCH_CON_PEM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PMU_INTR_GEN_QCH, QCH_CON_PMU_INTR_GEN_QCH_ENABLE, QCH_CON_PMU_INTR_GEN_QCH_CLOCK_REQ, QCH_CON_PMU_INTR_GEN_QCH_EXPIRE_VAL, QCH_CON_PMU_INTR_GEN_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_APM_BUS_QCH_GREBE, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG_ENABLE, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SPEEDY_APM_QCH, QCH_CON_SPEEDY_APM_QCH_ENABLE, QCH_CON_SPEEDY_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SPEEDY_SUB_APM_QCH, QCH_CON_SPEEDY_SUB_APM_QCH_ENABLE, QCH_CON_SPEEDY_SUB_APM_QCH_CLOCK_REQ, QCH_CON_SPEEDY_SUB_APM_QCH_EXPIRE_VAL, QCH_CON_SPEEDY_SUB_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_APM_QCH, QCH_CON_SYSREG_APM_QCH_ENABLE, QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_APM_QCH, QCH_CON_VGEN_LITE_APM_QCH_ENABLE, QCH_CON_VGEN_LITE_APM_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_APM_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WDT_APM_QCH, QCH_CON_WDT_APM_QCH_ENABLE, QCH_CON_WDT_APM_QCH_CLOCK_REQ, QCH_CON_WDT_APM_QCH_EXPIRE_VAL, QCH_CON_WDT_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_ACLK, QCH_CON_ABOX_QCH_ACLK_ENABLE, QCH_CON_ABOX_QCH_ACLK_CLOCK_REQ, QCH_CON_ABOX_QCH_ACLK_EXPIRE_VAL, QCH_CON_ABOX_QCH_ACLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_BCLK_DSIF, QCH_CON_ABOX_QCH_BCLK_DSIF_ENABLE, QCH_CON_ABOX_QCH_BCLK_DSIF_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK_DSIF_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK_DSIF_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_BCLK0, QCH_CON_ABOX_QCH_BCLK0_ENABLE, QCH_CON_ABOX_QCH_BCLK0_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK0_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_BCLK1, QCH_CON_ABOX_QCH_BCLK1_ENABLE, QCH_CON_ABOX_QCH_BCLK1_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK1_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_BCLK2, QCH_CON_ABOX_QCH_BCLK2_ENABLE, QCH_CON_ABOX_QCH_BCLK2_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK2_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_BCLK3, QCH_CON_ABOX_QCH_BCLK3_ENABLE, QCH_CON_ABOX_QCH_BCLK3_CLOCK_REQ, QCH_CON_ABOX_QCH_BCLK3_EXPIRE_VAL, QCH_CON_ABOX_QCH_BCLK3_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_DMY_QCH_CPU, DMYQCH_CON_ABOX_DMY_QCH_CPU_ENABLE, DMYQCH_CON_ABOX_DMY_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_DMY_QCH_CPU_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_CCLK_ASB, QCH_CON_ABOX_QCH_CCLK_ASB_ENABLE, QCH_CON_ABOX_QCH_CCLK_ASB_CLOCK_REQ, QCH_CON_ABOX_QCH_CCLK_ASB_EXPIRE_VAL, QCH_CON_ABOX_QCH_CCLK_ASB_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_DMY_QCH_IRQ, DMYQCH_CON_ABOX_DMY_QCH_IRQ_ENABLE, DMYQCH_CON_ABOX_DMY_QCH_IRQ_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ABOX_DMY_QCH_IRQ_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ABOX_QCH_CNT, QCH_CON_ABOX_QCH_CNT_ENABLE, QCH_CON_ABOX_QCH_CNT_CLOCK_REQ, QCH_CON_ABOX_QCH_CNT_EXPIRE_VAL, QCH_CON_ABOX_QCH_CNT_IGNORE_FORCE_PM_EN), |
| CLK_QCH(AUD_CMU_AUD_QCH, QCH_CON_AUD_CMU_AUD_QCH_ENABLE, QCH_CON_AUD_CMU_AUD_QCH_CLOCK_REQ, QCH_CON_AUD_CMU_AUD_QCH_EXPIRE_VAL, QCH_CON_AUD_CMU_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_AUD_QCH, QCH_CON_BTM_AUD_QCH_ENABLE, QCH_CON_BTM_AUD_QCH_CLOCK_REQ, QCH_CON_BTM_AUD_QCH_EXPIRE_VAL, QCH_CON_BTM_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_AUD_QCH, DMYQCH_CON_DFTMUX_AUD_QCH_ENABLE, DMYQCH_CON_DFTMUX_AUD_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_QCH, DMYQCH_CON_DMIC_QCH_ENABLE, DMYQCH_CON_DMIC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_AUD_QCH, QCH_CON_GPIO_AUD_QCH_ENABLE, QCH_CON_GPIO_AUD_QCH_CLOCK_REQ, QCH_CON_GPIO_AUD_QCH_EXPIRE_VAL, QCH_CON_GPIO_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_AUD_QCH, QCH_CON_LHM_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T0_AUD_QCH, QCH_CON_LHS_ATB_T0_AUD_QCH_ENABLE, QCH_CON_LHS_ATB_T0_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T0_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T0_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T1_AUD_QCH, QCH_CON_LHS_ATB_T1_AUD_QCH_ENABLE, QCH_CON_LHS_ATB_T1_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T1_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T1_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_AUD_QCH, QCH_CON_LHS_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_AUD_QCH, QCH_CON_PPMU_AUD_QCH_ENABLE, QCH_CON_PPMU_AUD_QCH_CLOCK_REQ, QCH_CON_PPMU_AUD_QCH_EXPIRE_VAL, QCH_CON_PPMU_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SMMU_AUD_QCH, QCH_CON_SMMU_AUD_QCH_ENABLE, QCH_CON_SMMU_AUD_QCH_CLOCK_REQ, QCH_CON_SMMU_AUD_QCH_EXPIRE_VAL, QCH_CON_SMMU_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_AUD_QCH, QCH_CON_SYSREG_AUD_QCH_ENABLE, QCH_CON_SYSREG_AUD_QCH_CLOCK_REQ, QCH_CON_SYSREG_AUD_QCH_EXPIRE_VAL, QCH_CON_SYSREG_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_AUD_QCH, QCH_CON_TREX_AUD_QCH_ENABLE, QCH_CON_TREX_AUD_QCH_CLOCK_REQ, QCH_CON_TREX_AUD_QCH_EXPIRE_VAL, QCH_CON_TREX_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_AUD_QCH, QCH_CON_VGEN_LITE_AUD_QCH_ENABLE, QCH_CON_VGEN_LITE_AUD_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_AUD_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WDT_AUD_QCH, QCH_CON_WDT_AUD_QCH_ENABLE, QCH_CON_WDT_AUD_QCH_CLOCK_REQ, QCH_CON_WDT_AUD_QCH_EXPIRE_VAL, QCH_CON_WDT_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_P_NPU_QCH, QCH_CON_BAAW_P_NPU_QCH_ENABLE, QCH_CON_BAAW_P_NPU_QCH_CLOCK_REQ, QCH_CON_BAAW_P_NPU_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_NPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_P_VTS_QCH, QCH_CON_BAAW_P_VTS_QCH_ENABLE, QCH_CON_BAAW_P_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_P_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_P_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSC_CMU_BUSC_QCH, QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, QCH_CON_BUSC_CMU_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_CMUTOPC_QCH, QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_CMUTOPC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMBUSC_QCH, QCH_CON_BUSIF_HPMBUSC_QCH_ENABLE, QCH_CON_BUSIF_HPMBUSC_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMBUSC_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMBUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_BUSC_CMUREF_QCH, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_BUSC_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DIT_QCH, QCH_CON_DIT_QCH_ENABLE, QCH_CON_DIT_QCH_CLOCK_REQ, QCH_CON_DIT_QCH_EXPIRE_VAL, QCH_CON_DIT_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_BUSC_QCH, QCH_CON_D_TZPC_BUSC_QCH_ENABLE, QCH_CON_D_TZPC_BUSC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_BUSC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D0_DSPM_QCH, QCH_CON_LHM_ACEL_D0_DSPM_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D0_G2D_QCH, QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D1_DSPM_QCH, QCH_CON_LHM_ACEL_D1_DSPM_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D1_G2D_QCH, QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D2_G2D_QCH, QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D_FSYS0_QCH, QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D_FSYS1_QCH, QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D_IVA_QCH, QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACEL_D_NPU_QCH, QCH_CON_LHM_ACEL_D_NPU_QCH_ENABLE, QCH_CON_LHM_ACEL_D_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_ACEL_D_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_ACEL_D_NPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D0_DPU_QCH, QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D0_ISPLP_QCH, QCH_CON_LHM_AXI_D0_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D0_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D0_MFC_QCH, QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D1_DPU_QCH, QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D1_ISPLP_QCH, QCH_CON_LHM_AXI_D1_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D1_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D1_MFC_QCH, QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D2_DPU_QCH, QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_APM_QCH, QCH_CON_LHM_AXI_D_APM_QCH_ENABLE, QCH_CON_LHM_AXI_D_APM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_APM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_AUD_QCH, QCH_CON_LHM_AXI_D_AUD_QCH_ENABLE, QCH_CON_LHM_AXI_D_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_ISPHQ_QCH, QCH_CON_LHM_AXI_D_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_ISPPRE_QCH, QCH_CON_LHM_AXI_D_ISPPRE_QCH_ENABLE, QCH_CON_LHM_AXI_D_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_VRA2_QCH, QCH_CON_LHM_AXI_D_VRA2_QCH_ENABLE, QCH_CON_LHM_AXI_D_VRA2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VRA2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_VTS_QCH, QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_IVASC_QCH, QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_AUD_QCH, QCH_CON_LHS_AXI_P_AUD_QCH_ENABLE, QCH_CON_LHS_AXI_P_AUD_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_AUD_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_DPU_QCH, QCH_CON_LHS_AXI_P_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_DSPM_QCH, QCH_CON_LHS_AXI_P_DSPM_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_FSYS0_QCH, QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_FSYS1_QCH, QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_G2D_QCH, QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_ISPHQ_QCH, QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_ISPLP_QCH, QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_ISPPRE_QCH, QCH_CON_LHS_AXI_P_ISPPRE_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_IVA_QCH, QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_MFC_QCH, QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_MIF0_QCH, QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_MIF1_QCH, QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_MIF2_QCH, QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_MIF3_QCH, QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_NPU_QCH, QCH_CON_LHS_AXI_P_NPU_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_PERIC0_QCH, QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_PERIC1_QCH, QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_PERIS_QCH, QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_VTS_QCH, QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_DBG_G_BUSC_QCH, DMYQCH_CON_LHS_DBG_G_BUSC_QCH_ENABLE, DMYQCH_CON_LHS_DBG_G_BUSC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_LHS_DBG_G_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MMCACHE_QCH, QCH_CON_MMCACHE_QCH_ENABLE, QCH_CON_MMCACHE_QCH_CLOCK_REQ, QCH_CON_MMCACHE_QCH_EXPIRE_VAL, QCH_CON_MMCACHE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PDMA0_QCH, QCH_CON_PDMA0_QCH_ENABLE, QCH_CON_PDMA0_QCH_CLOCK_REQ, QCH_CON_PDMA0_QCH_EXPIRE_VAL, QCH_CON_PDMA0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPFW_QCH, QCH_CON_PPFW_QCH_ENABLE, QCH_CON_PPFW_QCH_CLOCK_REQ, QCH_CON_PPFW_QCH_EXPIRE_VAL, QCH_CON_PPFW_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_PDMA0_QCH, QCH_CON_QE_PDMA0_QCH_ENABLE, QCH_CON_QE_PDMA0_QCH_CLOCK_REQ, QCH_CON_QE_PDMA0_QCH_EXPIRE_VAL, QCH_CON_QE_PDMA0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_SPDMA_QCH, QCH_CON_QE_SPDMA_QCH_ENABLE, QCH_CON_QE_SPDMA_QCH_CLOCK_REQ, QCH_CON_QE_SPDMA_QCH_EXPIRE_VAL, QCH_CON_QE_SPDMA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SBIC_QCH, QCH_CON_SBIC_QCH_ENABLE, QCH_CON_SBIC_QCH_CLOCK_REQ, QCH_CON_SBIC_QCH_EXPIRE_VAL, QCH_CON_SBIC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SIREX_QCH, QCH_CON_SIREX_QCH_ENABLE, QCH_CON_SIREX_QCH_CLOCK_REQ, QCH_CON_SIREX_QCH_EXPIRE_VAL, QCH_CON_SIREX_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SPDMA_QCH, QCH_CON_SPDMA_QCH_ENABLE, QCH_CON_SPDMA_QCH_CLOCK_REQ, QCH_CON_SPDMA_QCH_EXPIRE_VAL, QCH_CON_SPDMA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_BUSC_QCH, QCH_CON_SYSREG_BUSC_QCH_ENABLE, QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_D0_BUSC_QCH, QCH_CON_TREX_D0_BUSC_QCH_ENABLE, QCH_CON_TREX_D0_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D0_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D0_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_D1_BUSC_QCH, QCH_CON_TREX_D1_BUSC_QCH_ENABLE, QCH_CON_TREX_D1_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_D1_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_D1_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_P_BUSC_QCH, QCH_CON_TREX_P_BUSC_QCH_ENABLE, QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_P_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_RB_BUSC_QCH, QCH_CON_TREX_RB_BUSC_QCH_ENABLE, QCH_CON_TREX_RB_BUSC_QCH_CLOCK_REQ, QCH_CON_TREX_RB_BUSC_QCH_EXPIRE_VAL, QCH_CON_TREX_RB_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_BUSC_QCH, QCH_CON_VGEN_LITE_BUSC_QCH_ENABLE, QCH_CON_VGEN_LITE_BUSC_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_BUSC_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_BUSC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_PDMA0_QCH, QCH_CON_VGEN_PDMA0_QCH_ENABLE, QCH_CON_VGEN_PDMA0_QCH_CLOCK_REQ, QCH_CON_VGEN_PDMA0_QCH_EXPIRE_VAL, QCH_CON_VGEN_PDMA0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADC_CMGP_QCH_S0, QCH_CON_ADC_CMGP_QCH_S0_ENABLE, QCH_CON_ADC_CMGP_QCH_S0_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S0_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADC_CMGP_QCH_S1, QCH_CON_ADC_CMGP_QCH_S1_ENABLE, QCH_CON_ADC_CMGP_QCH_S1_CLOCK_REQ, QCH_CON_ADC_CMGP_QCH_S1_EXPIRE_VAL, QCH_CON_ADC_CMGP_QCH_S1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADC_CMGP_QCH_DMY, DMYQCH_CON_ADC_CMGP_QCH_DMY_ENABLE, DMYQCH_CON_ADC_CMGP_QCH_DMY_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADC_CMGP_QCH_DMY_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMGP_CMU_CMGP_QCH, QCH_CON_CMGP_CMU_CMGP_QCH_ENABLE, QCH_CON_CMGP_CMU_CMGP_QCH_CLOCK_REQ, QCH_CON_CMGP_CMU_CMGP_QCH_EXPIRE_VAL, QCH_CON_CMGP_CMU_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DTZPC_CMGP_QCH, QCH_CON_DTZPC_CMGP_QCH_ENABLE, QCH_CON_DTZPC_CMGP_QCH_CLOCK_REQ, QCH_CON_DTZPC_CMGP_QCH_EXPIRE_VAL, QCH_CON_DTZPC_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_CMGP_QCH, QCH_CON_GPIO_CMGP_QCH_ENABLE, QCH_CON_GPIO_CMGP_QCH_CLOCK_REQ, QCH_CON_GPIO_CMGP_QCH_EXPIRE_VAL, QCH_CON_GPIO_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CMGP0_QCH, QCH_CON_I2C_CMGP0_QCH_ENABLE, QCH_CON_I2C_CMGP0_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP0_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CMGP1_QCH, QCH_CON_I2C_CMGP1_QCH_ENABLE, QCH_CON_I2C_CMGP1_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP1_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CMGP2_QCH, QCH_CON_I2C_CMGP2_QCH_ENABLE, QCH_CON_I2C_CMGP2_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP2_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CMGP3_QCH, QCH_CON_I2C_CMGP3_QCH_ENABLE, QCH_CON_I2C_CMGP3_QCH_CLOCK_REQ, QCH_CON_I2C_CMGP3_QCH_EXPIRE_VAL, QCH_CON_I2C_CMGP3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_C_CMGP_QCH, QCH_CON_LHM_AXI_C_CMGP_QCH_ENABLE, QCH_CON_LHM_AXI_C_CMGP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_C_CMGP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_C_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CMGP_QCH, QCH_CON_SYSREG_CMGP_QCH_ENABLE, QCH_CON_SYSREG_CMGP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CMGP2APM_QCH, QCH_CON_SYSREG_CMGP2APM_QCH_ENABLE, QCH_CON_SYSREG_CMGP2APM_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2APM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CMGP2CP_QCH, QCH_CON_SYSREG_CMGP2CP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2CP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2CP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CMGP2PMU_AP_QCH, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_ENABLE, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_CLOCK_REQ, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CMGP2PMU_AP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI_CMGP0_QCH, QCH_CON_USI_CMGP0_QCH_ENABLE, QCH_CON_USI_CMGP0_QCH_CLOCK_REQ, QCH_CON_USI_CMGP0_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI_CMGP1_QCH, QCH_CON_USI_CMGP1_QCH_ENABLE, QCH_CON_USI_CMGP1_QCH_CLOCK_REQ, QCH_CON_USI_CMGP1_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI_CMGP2_QCH, QCH_CON_USI_CMGP2_QCH_ENABLE, QCH_CON_USI_CMGP2_QCH_CLOCK_REQ, QCH_CON_USI_CMGP2_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI_CMGP3_QCH, QCH_CON_USI_CMGP3_QCH_ENABLE, QCH_CON_USI_CMGP3_QCH_CLOCK_REQ, QCH_CON_USI_CMGP3_QCH_EXPIRE_VAL, QCH_CON_USI_CMGP3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CMU_CMUREF_QCH, DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CMU_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK0, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK2, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK3, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DFTMUX_TOP_QCH_CIS_CLK4, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_ENABLE, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK4_IGNORE_FORCE_PM_EN), |
| CLK_QCH(OTP_QCH, DMYQCH_CON_OTP_QCH_ENABLE, DMYQCH_CON_OTP_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_OTP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_CP_QCH, QCH_CON_BAAW_CP_QCH_ENABLE, QCH_CON_BAAW_CP_QCH_CLOCK_REQ, QCH_CON_BAAW_CP_QCH_EXPIRE_VAL, QCH_CON_BAAW_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BDU_QCH, QCH_CON_BDU_QCH_ENABLE, QCH_CON_BDU_QCH_CLOCK_REQ, QCH_CON_BDU_QCH_EXPIRE_VAL, QCH_CON_BDU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMCORE_QCH, QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CCI_QCH, DMYQCH_CON_CCI_QCH_ENABLE, DMYQCH_CON_CCI_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CCI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CORE_CMUREF_QCH, DMYQCH_CON_CMU_CORE_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CORE_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CORE_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CORE_CMU_CORE_QCH, QCH_CON_CORE_CMU_CORE_QCH_ENABLE, QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, QCH_CON_CORE_CMU_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_CORE_QCH, QCH_CON_D_TZPC_CORE_QCH_ENABLE, QCH_CON_D_TZPC_CORE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CORE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D0_CLUSTER0_QCH, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D0_G3D_QCH, QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D1_CLUSTER0_QCH, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D1_G3D_QCH, QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D2_G3D_QCH, QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ACE_D3_G3D_QCH, QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D0_CP_QCH, QCH_CON_LHM_AXI_D0_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D0_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D1_CP_QCH, QCH_CON_LHM_AXI_D1_CP_QCH_ENABLE, QCH_CON_LHM_AXI_D1_CP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D1_CP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D1_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G_CSSYS_QCH, QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_L_CORE_QCH, QCH_CON_LHM_AXI_L_CORE_QCH_ENABLE, QCH_CON_LHM_AXI_L_CORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_L_CORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_L_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T_BDU_QCH, QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_L_CORE_QCH, QCH_CON_LHS_AXI_L_CORE_QCH_ENABLE, QCH_CON_LHS_AXI_L_CORE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_L_CORE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_L_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_APM_QCH, QCH_CON_LHS_AXI_P_APM_QCH_ENABLE, QCH_CON_LHS_AXI_P_APM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_APM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_APM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_CP_QCH, QCH_CON_LHS_AXI_P_CP_QCH_ENABLE, QCH_CON_LHS_AXI_P_CP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_CPUCL0_QCH, QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_CPUCL2_QCH, QCH_CON_LHS_AXI_P_CPUCL2_QCH_ENABLE, QCH_CON_LHS_AXI_P_CPUCL2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_CPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_G3D_QCH, QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPCFW_G3D_QCH, QCH_CON_PPCFW_G3D_QCH_ENABLE, QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPCFW_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_CPUCL0_0_QCH, QCH_CON_PPC_CPUCL0_0_QCH_ENABLE, QCH_CON_PPC_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_CPUCL0_1_QCH, QCH_CON_PPC_CPUCL0_1_QCH_ENABLE, QCH_CON_PPC_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_CPUCL2_0_QCH, QCH_CON_PPC_CPUCL2_0_QCH_ENABLE, QCH_CON_PPC_CPUCL2_0_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL2_0_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL2_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_CPUCL2_1_QCH, QCH_CON_PPC_CPUCL2_1_QCH_ENABLE, QCH_CON_PPC_CPUCL2_1_QCH_CLOCK_REQ, QCH_CON_PPC_CPUCL2_1_QCH_EXPIRE_VAL, QCH_CON_PPC_CPUCL2_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_G3D0_QCH, QCH_CON_PPC_G3D0_QCH_ENABLE, QCH_CON_PPC_G3D0_QCH_CLOCK_REQ, QCH_CON_PPC_G3D0_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_G3D1_QCH, QCH_CON_PPC_G3D1_QCH_ENABLE, QCH_CON_PPC_G3D1_QCH_CLOCK_REQ, QCH_CON_PPC_G3D1_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_G3D2_QCH, QCH_CON_PPC_G3D2_QCH_ENABLE, QCH_CON_PPC_G3D2_QCH_CLOCK_REQ, QCH_CON_PPC_G3D2_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_G3D3_QCH, QCH_CON_PPC_G3D3_QCH_ENABLE, QCH_CON_PPC_G3D3_QCH_CLOCK_REQ, QCH_CON_PPC_G3D3_QCH_EXPIRE_VAL, QCH_CON_PPC_G3D3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_IRPS0_QCH, QCH_CON_PPC_IRPS0_QCH_ENABLE, QCH_CON_PPC_IRPS0_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS0_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPC_IRPS1_QCH, QCH_CON_PPC_IRPS1_QCH_ENABLE, QCH_CON_PPC_IRPS1_QCH_CLOCK_REQ, QCH_CON_PPC_IRPS1_QCH_EXPIRE_VAL, QCH_CON_PPC_IRPS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPFW_G3D_QCH, QCH_CON_PPFW_G3D_QCH_ENABLE, QCH_CON_PPFW_G3D_QCH_CLOCK_REQ, QCH_CON_PPFW_G3D_QCH_EXPIRE_VAL, QCH_CON_PPFW_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_CPUCL0_0_QCH, QCH_CON_PPMU_CPUCL0_0_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_CPUCL0_1_QCH, QCH_CON_PPMU_CPUCL0_1_QCH_ENABLE, QCH_CON_PPMU_CPUCL0_1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL0_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL0_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_CPUCL2_0_QCH, QCH_CON_PPMU_CPUCL2_0_QCH_ENABLE, QCH_CON_PPMU_CPUCL2_0_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL2_0_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL2_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_CPUCL2_1_QCH, QCH_CON_PPMU_CPUCL2_1_QCH_ENABLE, QCH_CON_PPMU_CPUCL2_1_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUCL2_1_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUCL2_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CORE_QCH, QCH_CON_SYSREG_CORE_QCH_ENABLE, QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_D_CORE_QCH, QCH_CON_TREX_D_CORE_QCH_ENABLE, QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_D_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_P0_CORE_QCH, QCH_CON_TREX_P0_CORE_QCH_ENABLE, QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P0_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_P1_CORE_QCH, QCH_CON_TREX_P1_CORE_QCH_ENABLE, QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, QCH_CON_TREX_P1_CORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADM_APB_G_CLUSTER0_QCH, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_ENABLE, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_G_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BPS_CPUCL0_QCH, QCH_CON_BPS_CPUCL0_QCH_ENABLE, QCH_CON_BPS_CPUCL0_QCH_CLOCK_REQ, QCH_CON_BPS_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_BPS_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMCPUCL0_QCH, QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL0_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL0_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL0_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_SCLK, QCH_CON_CPUCL0_QCH_SCLK_ENABLE, QCH_CON_CPUCL0_QCH_SCLK_CLOCK_REQ, QCH_CON_CPUCL0_QCH_SCLK_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_SCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_ATCLK, QCH_CON_CPUCL0_QCH_ATCLK_ENABLE, QCH_CON_CPUCL0_QCH_ATCLK_CLOCK_REQ, QCH_CON_CPUCL0_QCH_ATCLK_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_ATCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_PDBGCLK, QCH_CON_CPUCL0_QCH_PDBGCLK_ENABLE, QCH_CON_CPUCL0_QCH_PDBGCLK_CLOCK_REQ, QCH_CON_CPUCL0_QCH_PDBGCLK_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_PDBGCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_GIC, QCH_CON_CPUCL0_QCH_GIC_ENABLE, QCH_CON_CPUCL0_QCH_GIC_CLOCK_REQ, QCH_CON_CPUCL0_QCH_GIC_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_GIC_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_DBG_PD, QCH_CON_CPUCL0_QCH_DBG_PD_ENABLE, QCH_CON_CPUCL0_QCH_DBG_PD_CLOCK_REQ, QCH_CON_CPUCL0_QCH_DBG_PD_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_DBG_PD_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_PCLK, QCH_CON_CPUCL0_QCH_PCLK_ENABLE, QCH_CON_CPUCL0_QCH_PCLK_CLOCK_REQ, QCH_CON_CPUCL0_QCH_PCLK_EXPIRE_VAL, QCH_CON_CPUCL0_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_QCH_PERIPHCLK, DMYQCH_CON_CPUCL0_QCH_PERIPHCLK_ENABLE, DMYQCH_CON_CPUCL0_QCH_PERIPHCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL0_QCH_PERIPHCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL0_CMU_CPUCL0_QCH, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_CPUCL0_CMU_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CSSYS_QCH, QCH_CON_CSSYS_QCH_ENABLE, QCH_CON_CSSYS_QCH_CLOCK_REQ, QCH_CON_CSSYS_QCH_EXPIRE_VAL, QCH_CON_CSSYS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_CPUCL0_QCH, QCH_CON_D_TZPC_CPUCL0_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T0_AUD_QCH, QCH_CON_LHM_ATB_T0_AUD_QCH_ENABLE, QCH_CON_LHM_ATB_T0_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T0_CLUSTER0_QCH, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T0_CLUSTER2_QCH, QCH_CON_LHM_ATB_T0_CLUSTER2_QCH_ENABLE, QCH_CON_LHM_ATB_T0_CLUSTER2_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T0_CLUSTER2_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T0_CLUSTER2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T1_AUD_QCH, QCH_CON_LHM_ATB_T1_AUD_QCH_ENABLE, QCH_CON_LHM_ATB_T1_AUD_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_AUD_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_AUD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T1_CLUSTER0_QCH, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T1_CLUSTER2_QCH, QCH_CON_LHM_ATB_T1_CLUSTER2_QCH_ENABLE, QCH_CON_LHM_ATB_T1_CLUSTER2_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T1_CLUSTER2_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T1_CLUSTER2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T2_CLUSTER0_QCH, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T3_CLUSTER0_QCH, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T4_CLUSTER0_QCH, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T5_CLUSTER0_QCH, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_ENABLE, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_T_BDU_QCH, QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_T_BDU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G_DBGCORE_QCH, QCH_CON_LHM_AXI_G_DBGCORE_QCH_ENABLE, QCH_CON_LHM_AXI_G_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_DBGCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G_INT_CSSYS_QCH, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G_INT_DBGCORE_QCH, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G_INT_ETR_QCH, QCH_CON_LHM_AXI_G_INT_ETR_QCH_ENABLE, QCH_CON_LHM_AXI_G_INT_ETR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G_INT_ETR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_CPUCL0_QCH, QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D0_CLUSTER0_QCH, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D1_CLUSTER0_QCH, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T0_CLUSTER0_QCH, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T0_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T1_CLUSTER0_QCH, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T1_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T2_CLUSTER0_QCH, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T2_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T3_CLUSTER0_QCH, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T3_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T4_CLUSTER0_QCH, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T4_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_T5_CLUSTER0_QCH, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_ENABLE, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_T5_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_CSSYS_QCH, QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_CSSYS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_INT_CSSYS_QCH, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_CSSYS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_INT_DBGCORE_QCH, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_DBGCORE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G_INT_ETR_QCH, QCH_CON_LHS_AXI_G_INT_ETR_QCH_ENABLE, QCH_CON_LHS_AXI_G_INT_ETR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G_INT_ETR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G_INT_ETR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SECJTAG_QCH, QCH_CON_SECJTAG_QCH_ENABLE, QCH_CON_SECJTAG_QCH_CLOCK_REQ, QCH_CON_SECJTAG_QCH_EXPIRE_VAL, QCH_CON_SECJTAG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CPUCL0_QCH, QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_CPUCL0_QCH, QCH_CON_TREX_CPUCL0_QCH_ENABLE, QCH_CON_TREX_CPUCL0_QCH_CLOCK_REQ, QCH_CON_TREX_CPUCL0_QCH_EXPIRE_VAL, QCH_CON_TREX_CPUCL0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL1_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL1_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL1_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL1_QCH_MID, DMYQCH_CON_CPUCL1_QCH_MID_ENABLE, DMYQCH_CON_CPUCL1_QCH_MID_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CPUCL1_QCH_MID_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL1_CMU_CPUCL1_QCH, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, QCH_CON_CPUCL1_CMU_CPUCL1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMCPUCL2_QCH, QCH_CON_BUSIF_HPMCPUCL2_QCH_ENABLE, QCH_CON_BUSIF_HPMCPUCL2_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMCPUCL2_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMCPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CLUSTER2_QCH_CPU, DMYQCH_CON_CLUSTER2_QCH_CPU_ENABLE, DMYQCH_CON_CLUSTER2_QCH_CPU_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER2_QCH_CPU_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CLUSTER2_QCH_LHS_ATB_T0_CLUSTER2, QCH_CON_CLUSTER2_QCH_LHS_ATB_T0_CLUSTER2_ENABLE, QCH_CON_CLUSTER2_QCH_LHS_ATB_T0_CLUSTER2_CLOCK_REQ, QCH_CON_CLUSTER2_QCH_LHS_ATB_T0_CLUSTER2_EXPIRE_VAL, QCH_CON_CLUSTER2_QCH_LHS_ATB_T0_CLUSTER2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CLUSTER2_QCH_LHS_ATB_T1_CLUSTER2, QCH_CON_CLUSTER2_QCH_LHS_ATB_T1_CLUSTER2_ENABLE, QCH_CON_CLUSTER2_QCH_LHS_ATB_T1_CLUSTER2_CLOCK_REQ, QCH_CON_CLUSTER2_QCH_LHS_ATB_T1_CLUSTER2_EXPIRE_VAL, QCH_CON_CLUSTER2_QCH_LHS_ATB_T1_CLUSTER2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CLUSTER2_QCH_PCLKDBG, DMYQCH_CON_CLUSTER2_QCH_PCLKDBG_ENABLE, DMYQCH_CON_CLUSTER2_QCH_PCLKDBG_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CLUSTER2_QCH_PCLKDBG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL2_CMUREF_QCH, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_CPUCL2_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_CPUCL2_SHORTSTOP_QCH, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_ENABLE, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_CLOCK_REQ, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_EXPIRE_VAL, QCH_CON_CMU_CPUCL2_SHORTSTOP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CPUCL2_CMU_CPUCL2_QCH, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_ENABLE, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_CLOCK_REQ, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_CPUCL2_CMU_CPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_CPUCL2_QCH, QCH_CON_D_TZPC_CPUCL2_QCH_ENABLE, QCH_CON_D_TZPC_CPUCL2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_CPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_CPUCL2_QCH, QCH_CON_LHM_AXI_P_CPUCL2_QCH_ENABLE, QCH_CON_LHM_AXI_P_CPUCL2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_CPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_CPUCL2_QCH, QCH_CON_SYSREG_CPUCL2_QCH_ENABLE, QCH_CON_SYSREG_CPUCL2_QCH_CLOCK_REQ, QCH_CON_SYSREG_CPUCL2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_CPUCL2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_DPUD0_QCH, QCH_CON_BTM_DPUD0_QCH_ENABLE, QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_DPUD1_QCH, QCH_CON_BTM_DPUD1_QCH_ENABLE, QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_DPUD2_QCH, QCH_CON_BTM_DPUD2_QCH_ENABLE, QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL, QCH_CON_BTM_DPUD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DPU_QCH_DPU, QCH_CON_DPU_QCH_DPU_ENABLE, QCH_CON_DPU_QCH_DPU_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DPU_QCH_DPU_DMA, QCH_CON_DPU_QCH_DPU_DMA_ENABLE, QCH_CON_DPU_QCH_DPU_DMA_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DMA_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DMA_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DPU_QCH_DPU_DPP, QCH_CON_DPU_QCH_DPU_DPP_ENABLE, QCH_CON_DPU_QCH_DPU_DPP_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_DPP_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_DPP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DPU_QCH_DPU_WB_MUX, QCH_CON_DPU_QCH_DPU_WB_MUX_ENABLE, QCH_CON_DPU_QCH_DPU_WB_MUX_CLOCK_REQ, QCH_CON_DPU_QCH_DPU_WB_MUX_EXPIRE_VAL, QCH_CON_DPU_QCH_DPU_WB_MUX_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DPU_CMU_DPU_QCH, QCH_CON_DPU_CMU_DPU_QCH_ENABLE, QCH_CON_DPU_CMU_DPU_QCH_CLOCK_REQ, QCH_CON_DPU_CMU_DPU_QCH_EXPIRE_VAL, QCH_CON_DPU_CMU_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_DPU_QCH, QCH_CON_D_TZPC_DPU_QCH_ENABLE, QCH_CON_D_TZPC_DPU_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DPU_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_DPU_QCH, QCH_CON_LHM_AXI_P_DPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_DPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D0_DPU_QCH, QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D1_DPU_QCH, QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D2_DPU_QCH, QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D2_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_DPUD0_QCH, QCH_CON_PPMU_DPUD0_QCH_ENABLE, QCH_CON_PPMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_DPUD1_QCH, QCH_CON_PPMU_DPUD1_QCH_ENABLE, QCH_CON_PPMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_DPUD2_QCH, QCH_CON_PPMU_DPUD2_QCH_ENABLE, QCH_CON_PPMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_PPMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_DPUD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_DPUD0_QCH, QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_DPUD1_QCH, QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_DPUD2_QCH, QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DPUD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_DPU_QCH, QCH_CON_SYSREG_DPU_QCH_ENABLE, QCH_CON_SYSREG_DPU_QCH_CLOCK_REQ, QCH_CON_SYSREG_DPU_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADM_APB_DSPM_QCH, DMYQCH_CON_ADM_APB_DSPM_QCH_ENABLE, DMYQCH_CON_ADM_APB_DSPM_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_APB_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_DSPM_QCH, QCH_CON_BAAW_DSPM_QCH_ENABLE, QCH_CON_BAAW_DSPM_QCH_CLOCK_REQ, QCH_CON_BAAW_DSPM_QCH_EXPIRE_VAL, QCH_CON_BAAW_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_DSPM0_QCH, QCH_CON_BTM_DSPM0_QCH_ENABLE, QCH_CON_BTM_DSPM0_QCH_CLOCK_REQ, QCH_CON_BTM_DSPM0_QCH_EXPIRE_VAL, QCH_CON_BTM_DSPM0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_DSPM1_QCH, QCH_CON_BTM_DSPM1_QCH_ENABLE, QCH_CON_BTM_DSPM1_QCH_CLOCK_REQ, QCH_CON_BTM_DSPM1_QCH_EXPIRE_VAL, QCH_CON_BTM_DSPM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DSPM_CMU_DSPM_QCH, QCH_CON_DSPM_CMU_DSPM_QCH_ENABLE, QCH_CON_DSPM_CMU_DSPM_QCH_CLOCK_REQ, QCH_CON_DSPM_CMU_DSPM_QCH_EXPIRE_VAL, QCH_CON_DSPM_CMU_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_DSPM_QCH, QCH_CON_D_TZPC_DSPM_QCH_ENABLE, QCH_CON_D_TZPC_DSPM_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DSPM_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_ISPHQDSPM_QCH, QCH_CON_LHM_AST_ISPHQDSPM_QCH_ENABLE, QCH_CON_LHM_AST_ISPHQDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ISPHQDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ISPHQDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_ISPLPDSPM_QCH, QCH_CON_LHM_AST_ISPLPDSPM_QCH_ENABLE, QCH_CON_LHM_AST_ISPLPDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ISPLPDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ISPLPDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_ISPPREDSPM_QCH, QCH_CON_LHM_AST_ISPPREDSPM_QCH_ENABLE, QCH_CON_LHM_AST_ISPPREDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AST_ISPPREDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_ISPPREDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D0_DSPSDSPM_QCH, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_ENABLE, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_DSPM_QCH, QCH_CON_LHM_AXI_P_DSPM_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_IVADSPM_QCH, QCH_CON_LHM_AXI_P_IVADSPM_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVADSPM_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVADSPM_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D0_DSPM_QCH, QCH_CON_LHS_ACEL_D0_DSPM_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D1_DSPM_QCH, QCH_CON_LHS_ACEL_D1_DSPM_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_DSPM_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_DSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_DSPMISPLP_QCH, QCH_CON_LHS_AST_DSPMISPLP_QCH_ENABLE, QCH_CON_LHS_AST_DSPMISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_DSPMISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_DSPMISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_DSPMISPPRE_QCH, QCH_CON_LHS_AST_DSPMISPPRE_QCH_ENABLE, QCH_CON_LHS_AST_DSPMISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AST_DSPMISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_DSPMISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_DSPMNPU0_QCH, QCH_CON_LHS_AXI_D_DSPMNPU0_QCH_ENABLE, QCH_CON_LHS_AXI_D_DSPMNPU0_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DSPMNPU0_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DSPMNPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_DSPMDSPS_QCH, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_DSPMIVA_QCH, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_ENABLE, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_DSPM0_QCH, QCH_CON_PPMU_DSPM0_QCH_ENABLE, QCH_CON_PPMU_DSPM0_QCH_CLOCK_REQ, QCH_CON_PPMU_DSPM0_QCH_EXPIRE_VAL, QCH_CON_PPMU_DSPM0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_DSPM1_QCH, QCH_CON_PPMU_DSPM1_QCH_ENABLE, QCH_CON_PPMU_DSPM1_QCH_CLOCK_REQ, QCH_CON_PPMU_DSPM1_QCH_EXPIRE_VAL, QCH_CON_PPMU_DSPM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SCORE_TS_II_QCH, QCH_CON_SCORE_TS_II_QCH_ENABLE, QCH_CON_SCORE_TS_II_QCH_CLOCK_REQ, QCH_CON_SCORE_TS_II_QCH_EXPIRE_VAL, QCH_CON_SCORE_TS_II_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_DSPM0_QCH, QCH_CON_SYSMMU_DSPM0_QCH_ENABLE, QCH_CON_SYSMMU_DSPM0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DSPM0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DSPM0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_DSPM1_QCH, QCH_CON_SYSMMU_DSPM1_QCH_ENABLE, QCH_CON_SYSMMU_DSPM1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_DSPM1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_DSPM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_DSPM_QCH, QCH_CON_SYSREG_DSPM_QCH_ENABLE, QCH_CON_SYSREG_DSPM_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSPM_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_DSPM_QCH, QCH_CON_VGEN_LITE_DSPM_QCH_ENABLE, QCH_CON_VGEN_LITE_DSPM_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_DSPM_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_DSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DSPS_CMU_DSPS_QCH, QCH_CON_DSPS_CMU_DSPS_QCH_ENABLE, QCH_CON_DSPS_CMU_DSPS_QCH_CLOCK_REQ, QCH_CON_DSPS_CMU_DSPS_QCH_EXPIRE_VAL, QCH_CON_DSPS_CMU_DSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_DSPS_QCH, QCH_CON_D_TZPC_DSPS_QCH_ENABLE, QCH_CON_D_TZPC_DSPS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_DSPS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_DSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_IVADSPS_QCH, QCH_CON_LHM_AXI_D_IVADSPS_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVADSPS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVADSPS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_DSPMDSPS_QCH, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPMDSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D0_DSPSDSPM_QCH, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_ENABLE, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_DSPSDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_DSPSIVA_QCH, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_ENABLE, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SCORE_BARON_QCH, QCH_CON_SCORE_BARON_QCH_ENABLE, QCH_CON_SCORE_BARON_QCH_CLOCK_REQ, QCH_CON_SCORE_BARON_QCH_EXPIRE_VAL, QCH_CON_SCORE_BARON_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_DSPS_QCH, QCH_CON_SYSREG_DSPS_QCH_ENABLE, QCH_CON_SYSREG_DSPS_QCH_CLOCK_REQ, QCH_CON_SYSREG_DSPS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_DSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_DSPS_QCH, QCH_CON_VGEN_LITE_DSPS_QCH_ENABLE, QCH_CON_VGEN_LITE_DSPS_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_DSPS_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_DSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_FSYS0_QCH, QCH_CON_BTM_FSYS0_QCH_ENABLE, QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DP_LINK_QCH, QCH_CON_DP_LINK_QCH_ENABLE, QCH_CON_DP_LINK_QCH_CLOCK_REQ, QCH_CON_DP_LINK_QCH_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DP_LINK_QCH_GTC, QCH_CON_DP_LINK_QCH_GTC_ENABLE, QCH_CON_DP_LINK_QCH_GTC_CLOCK_REQ, QCH_CON_DP_LINK_QCH_GTC_EXPIRE_VAL, QCH_CON_DP_LINK_QCH_GTC_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_FSYS0_QCH, QCH_CON_D_TZPC_FSYS0_QCH_ENABLE, QCH_CON_D_TZPC_FSYS0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_FSYS0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(FSYS0_CMU_FSYS0_QCH, QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_FSYS0_CMU_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_FSYS0_QCH, QCH_CON_GPIO_FSYS0_QCH_ENABLE, QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_USB_QCH, QCH_CON_LHM_AXI_D_USB_QCH_ENABLE, QCH_CON_LHM_AXI_D_USB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_USB_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_FSYS0_QCH, QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D_FSYS0_QCH, QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_USB_QCH, QCH_CON_LHS_AXI_P_USB_QCH_ENABLE, QCH_CON_LHS_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_DBI_A, QCH_CON_PCIE_GEN3_QCH_DBI_A_ENABLE, QCH_CON_PCIE_GEN3_QCH_DBI_A_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_DBI_A_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_DBI_A_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_MSTR_SLV_A, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_A_ENABLE, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_A_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_A_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_A_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_APB_A, QCH_CON_PCIE_GEN3_QCH_APB_A_ENABLE, QCH_CON_PCIE_GEN3_QCH_APB_A_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_APB_A_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_APB_A_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_DBI_B, QCH_CON_PCIE_GEN3_QCH_DBI_B_ENABLE, QCH_CON_PCIE_GEN3_QCH_DBI_B_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_DBI_B_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_DBI_B_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_MSTR_SLV_B, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_B_ENABLE, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_B_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_B_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_MSTR_SLV_B_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_APB_B, QCH_CON_PCIE_GEN3_QCH_APB_B_ENABLE, QCH_CON_PCIE_GEN3_QCH_APB_B_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_APB_B_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_APB_B_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_SCLK, DMYQCH_CON_PCIE_GEN3_QCH_SCLK_ENABLE, DMYQCH_CON_PCIE_GEN3_QCH_SCLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN3_QCH_SCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_PCS_APB, QCH_CON_PCIE_GEN3_QCH_PCS_APB_ENABLE, QCH_CON_PCIE_GEN3_QCH_PCS_APB_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_PCS_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_PCS_APB_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_IF_CMN, QCH_CON_PCIE_GEN3_QCH_IF_CMN_ENABLE, QCH_CON_PCIE_GEN3_QCH_IF_CMN_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_IF_CMN_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_IF_CMN_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_IF_LN0, QCH_CON_PCIE_GEN3_QCH_IF_LN0_ENABLE, QCH_CON_PCIE_GEN3_QCH_IF_LN0_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_IF_LN0_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_IF_LN0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN3_QCH_IF_LN1, QCH_CON_PCIE_GEN3_QCH_IF_LN1_ENABLE, QCH_CON_PCIE_GEN3_QCH_IF_LN1_CLOCK_REQ, QCH_CON_PCIE_GEN3_QCH_IF_LN1_EXPIRE_VAL, QCH_CON_PCIE_GEN3_QCH_IF_LN1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_IA_GEN3A_QCH, QCH_CON_PCIE_IA_GEN3A_QCH_ENABLE, QCH_CON_PCIE_IA_GEN3A_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN3A_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN3A_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_IA_GEN3B_QCH, QCH_CON_PCIE_IA_GEN3B_QCH_ENABLE, QCH_CON_PCIE_IA_GEN3B_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN3B_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN3B_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_FSYS0_QCH, QCH_CON_PPMU_FSYS0_QCH_ENABLE, QCH_CON_PPMU_FSYS0_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS0_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_PCIE_GEN3A_QCH, QCH_CON_SYSMMU_PCIE_GEN3A_QCH_ENABLE, QCH_CON_SYSMMU_PCIE_GEN3A_QCH_CLOCK_REQ, QCH_CON_SYSMMU_PCIE_GEN3A_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_PCIE_GEN3A_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_PCIE_GEN3B_QCH, QCH_CON_SYSMMU_PCIE_GEN3B_QCH_ENABLE, QCH_CON_SYSMMU_PCIE_GEN3B_QCH_CLOCK_REQ, QCH_CON_SYSMMU_PCIE_GEN3B_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_PCIE_GEN3B_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_FSYS0_QCH, QCH_CON_SYSREG_FSYS0_QCH_ENABLE, QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_FSYS0_QCH, QCH_CON_VGEN_LITE_FSYS0_QCH_ENABLE, QCH_CON_VGEN_LITE_FSYS0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_FSYS0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_FSYS0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(FSYS0A_CMU_FSYS0A_QCH, QCH_CON_FSYS0A_CMU_FSYS0A_QCH_ENABLE, QCH_CON_FSYS0A_CMU_FSYS0A_QCH_CLOCK_REQ, QCH_CON_FSYS0A_CMU_FSYS0A_QCH_EXPIRE_VAL, QCH_CON_FSYS0A_CMU_FSYS0A_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_USB_QCH, QCH_CON_LHM_AXI_P_USB_QCH_ENABLE, QCH_CON_LHM_AXI_P_USB_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_USB_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_USB_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_USB_QCH, QCH_CON_LHS_AXI_D_USB_QCH_ENABLE, QCH_CON_LHS_AXI_D_USB_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_USB_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_USB_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USB31DRD_QCH_REF, DMYQCH_CON_USB31DRD_QCH_REF_ENABLE, DMYQCH_CON_USB31DRD_QCH_REF_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USB31DRD_QCH_REF_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USB31DRD_QCH_SLV_CTRL, QCH_CON_USB31DRD_QCH_SLV_CTRL_ENABLE, QCH_CON_USB31DRD_QCH_SLV_CTRL_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_CTRL_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_CTRL_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USB31DRD_QCH_SLV_LINK, QCH_CON_USB31DRD_QCH_SLV_LINK_ENABLE, QCH_CON_USB31DRD_QCH_SLV_LINK_CLOCK_REQ, QCH_CON_USB31DRD_QCH_SLV_LINK_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_SLV_LINK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USB31DRD_QCH_APB, QCH_CON_USB31DRD_QCH_APB_ENABLE, QCH_CON_USB31DRD_QCH_APB_CLOCK_REQ, QCH_CON_USB31DRD_QCH_APB_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_APB_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USB31DRD_QCH_PCS, QCH_CON_USB31DRD_QCH_PCS_ENABLE, QCH_CON_USB31DRD_QCH_PCS_CLOCK_REQ, QCH_CON_USB31DRD_QCH_PCS_EXPIRE_VAL, QCH_CON_USB31DRD_QCH_PCS_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADM_AHB_SSS_QCH, QCH_CON_ADM_AHB_SSS_QCH_ENABLE, QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, QCH_CON_ADM_AHB_SSS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_SSS_QCH, QCH_CON_BAAW_SSS_QCH_ENABLE, QCH_CON_BAAW_SSS_QCH_CLOCK_REQ, QCH_CON_BAAW_SSS_QCH_EXPIRE_VAL, QCH_CON_BAAW_SSS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_FSYS1_QCH, QCH_CON_BTM_FSYS1_QCH_ENABLE, QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL, QCH_CON_BTM_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_FSYS1_QCH, QCH_CON_D_TZPC_FSYS1_QCH_ENABLE, QCH_CON_D_TZPC_FSYS1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_FSYS1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(FSYS1_CMU_FSYS1_QCH, QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_FSYS1_CMU_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_FSYS1_QCH, QCH_CON_GPIO_FSYS1_QCH_ENABLE, QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL, QCH_CON_GPIO_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_FSYS1_QCH, QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D_FSYS1_QCH, QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MMC_CARD_QCH, QCH_CON_MMC_CARD_QCH_ENABLE, QCH_CON_MMC_CARD_QCH_CLOCK_REQ, QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, QCH_CON_MMC_CARD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_MSTR, QCH_CON_PCIE_GEN2_QCH_MSTR_ENABLE, QCH_CON_PCIE_GEN2_QCH_MSTR_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_MSTR_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_MSTR_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_PCS, QCH_CON_PCIE_GEN2_QCH_PCS_ENABLE, QCH_CON_PCIE_GEN2_QCH_PCS_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PCS_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PCS_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_PHY, QCH_CON_PCIE_GEN2_QCH_PHY_ENABLE, QCH_CON_PCIE_GEN2_QCH_PHY_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_PHY_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_PHY_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_DBI, QCH_CON_PCIE_GEN2_QCH_DBI_ENABLE, QCH_CON_PCIE_GEN2_QCH_DBI_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_DBI_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_DBI_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_APB, QCH_CON_PCIE_GEN2_QCH_APB_ENABLE, QCH_CON_PCIE_GEN2_QCH_APB_CLOCK_REQ, QCH_CON_PCIE_GEN2_QCH_APB_EXPIRE_VAL, QCH_CON_PCIE_GEN2_QCH_APB_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_GEN2_QCH_SOCPLL, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_ENABLE, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PCIE_GEN2_QCH_SOCPLL_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PCIE_IA_GEN2_QCH, QCH_CON_PCIE_IA_GEN2_QCH_ENABLE, QCH_CON_PCIE_IA_GEN2_QCH_CLOCK_REQ, QCH_CON_PCIE_IA_GEN2_QCH_EXPIRE_VAL, QCH_CON_PCIE_IA_GEN2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_FSYS1_QCH, QCH_CON_PPMU_FSYS1_QCH_ENABLE, QCH_CON_PPMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_PPMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_PPMU_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PUF_QCH, DMYQCH_CON_PUF_QCH_ENABLE, DMYQCH_CON_PUF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_PUF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_RTIC_QCH, QCH_CON_QE_RTIC_QCH_ENABLE, QCH_CON_QE_RTIC_QCH_CLOCK_REQ, QCH_CON_QE_RTIC_QCH_EXPIRE_VAL, QCH_CON_QE_RTIC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_SSS_QCH, QCH_CON_QE_SSS_QCH_ENABLE, QCH_CON_QE_SSS_QCH_CLOCK_REQ, QCH_CON_QE_SSS_QCH_EXPIRE_VAL, QCH_CON_QE_SSS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RTIC_QCH, QCH_CON_RTIC_QCH_ENABLE, QCH_CON_RTIC_QCH_CLOCK_REQ, QCH_CON_RTIC_QCH_EXPIRE_VAL, QCH_CON_RTIC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SSS_QCH, QCH_CON_SSS_QCH_ENABLE, QCH_CON_SSS_QCH_CLOCK_REQ, QCH_CON_SSS_QCH_EXPIRE_VAL, QCH_CON_SSS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_FSYS1_QCH, QCH_CON_SYSMMU_FSYS1_QCH_ENABLE, QCH_CON_SYSMMU_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_FSYS1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_FSYS1_QCH, QCH_CON_SYSREG_FSYS1_QCH_ENABLE, QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UFS_CARD_QCH, QCH_CON_UFS_CARD_QCH_ENABLE, QCH_CON_UFS_CARD_QCH_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UFS_CARD_QCH_FMP, QCH_CON_UFS_CARD_QCH_FMP_ENABLE, QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_CARD_QCH_FMP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UFS_EMBD_QCH, QCH_CON_UFS_EMBD_QCH_ENABLE, QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UFS_EMBD_QCH_FMP, QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, QCH_CON_UFS_EMBD_QCH_FMP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_FSYS1_QCH, QCH_CON_VGEN_LITE_FSYS1_QCH_ENABLE, QCH_CON_VGEN_LITE_FSYS1_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_FSYS1_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_FSYS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASTC_QCH, QCH_CON_ASTC_QCH_ENABLE, QCH_CON_ASTC_QCH_CLOCK_REQ, QCH_CON_ASTC_QCH_EXPIRE_VAL, QCH_CON_ASTC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_G2DD0_QCH, QCH_CON_BTM_G2DD0_QCH_ENABLE, QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_G2DD1_QCH, QCH_CON_BTM_G2DD1_QCH_ENABLE, QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_G2DD2_QCH, QCH_CON_BTM_G2DD2_QCH_ENABLE, QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL, QCH_CON_BTM_G2DD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_G2D_QCH, QCH_CON_D_TZPC_G2D_QCH_ENABLE, QCH_CON_D_TZPC_G2D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G2D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(G2D_QCH, QCH_CON_G2D_QCH_ENABLE, QCH_CON_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(G2D_CMU_G2D_QCH, QCH_CON_G2D_CMU_G2D_QCH_ENABLE, QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, QCH_CON_G2D_CMU_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(JPEG_QCH, QCH_CON_JPEG_QCH_ENABLE, QCH_CON_JPEG_QCH_CLOCK_REQ, QCH_CON_JPEG_QCH_EXPIRE_VAL, QCH_CON_JPEG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(JSQZ_QCH, QCH_CON_JSQZ_QCH_ENABLE, QCH_CON_JSQZ_QCH_CLOCK_REQ, QCH_CON_JSQZ_QCH_EXPIRE_VAL, QCH_CON_JSQZ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_G2D_QCH, QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D0_G2D_QCH, QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D0_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D1_G2D_QCH, QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D1_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D2_G2D_QCH, QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D2_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MSCL_QCH, QCH_CON_MSCL_QCH_ENABLE, QCH_CON_MSCL_QCH_CLOCK_REQ, QCH_CON_MSCL_QCH_EXPIRE_VAL, QCH_CON_MSCL_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_G2DD0_QCH, QCH_CON_PPMU_G2DD0_QCH_ENABLE, QCH_CON_PPMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_G2DD1_QCH, QCH_CON_PPMU_G2DD1_QCH_ENABLE, QCH_CON_PPMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_G2DD2_QCH, QCH_CON_PPMU_G2DD2_QCH_ENABLE, QCH_CON_PPMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_PPMU_G2DD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_G2DD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_ASTC_QCH, QCH_CON_QE_ASTC_QCH_ENABLE, QCH_CON_QE_ASTC_QCH_CLOCK_REQ, QCH_CON_QE_ASTC_QCH_EXPIRE_VAL, QCH_CON_QE_ASTC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_JPEG_QCH, QCH_CON_QE_JPEG_QCH_ENABLE, QCH_CON_QE_JPEG_QCH_CLOCK_REQ, QCH_CON_QE_JPEG_QCH_EXPIRE_VAL, QCH_CON_QE_JPEG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_JSQZ_QCH, QCH_CON_QE_JSQZ_QCH_ENABLE, QCH_CON_QE_JSQZ_QCH_CLOCK_REQ, QCH_CON_QE_JSQZ_QCH_EXPIRE_VAL, QCH_CON_QE_JSQZ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_MSCL_QCH, QCH_CON_QE_MSCL_QCH_ENABLE, QCH_CON_QE_MSCL_QCH_CLOCK_REQ, QCH_CON_QE_MSCL_QCH_EXPIRE_VAL, QCH_CON_QE_MSCL_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_G2DD0_QCH, QCH_CON_SYSMMU_G2DD0_QCH_ENABLE, QCH_CON_SYSMMU_G2DD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_G2DD1_QCH, QCH_CON_SYSMMU_G2DD1_QCH_ENABLE, QCH_CON_SYSMMU_G2DD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_G2DD2_QCH, QCH_CON_SYSMMU_G2DD2_QCH_ENABLE, QCH_CON_SYSMMU_G2DD2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_G2DD2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_G2DD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_G2D_QCH, QCH_CON_SYSREG_G2D_QCH_ENABLE, QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_G2D_QCH, QCH_CON_VGEN_LITE_G2D_QCH_ENABLE, QCH_CON_VGEN_LITE_G2D_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_G2D_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_G2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_PPMU_G3D0, QCH_CON_ASB_G3D_QCH_PPMU_G3D0_ENABLE, QCH_CON_ASB_G3D_QCH_PPMU_G3D0_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_PPMU_G3D0_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_PPMU_G3D0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_PPMU_G3D1, QCH_CON_ASB_G3D_QCH_PPMU_G3D1_ENABLE, QCH_CON_ASB_G3D_QCH_PPMU_G3D1_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_PPMU_G3D1_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_PPMU_G3D1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_PPMU_G3D2, QCH_CON_ASB_G3D_QCH_PPMU_G3D2_ENABLE, QCH_CON_ASB_G3D_QCH_PPMU_G3D2_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_PPMU_G3D2_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_PPMU_G3D2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_PPMU_G3D3, QCH_CON_ASB_G3D_QCH_PPMU_G3D3_ENABLE, QCH_CON_ASB_G3D_QCH_PPMU_G3D3_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_PPMU_G3D3_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_PPMU_G3D3_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_QE_G3D0, QCH_CON_ASB_G3D_QCH_QE_G3D0_ENABLE, QCH_CON_ASB_G3D_QCH_QE_G3D0_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_QE_G3D0_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_QE_G3D0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_QE_G3D1, QCH_CON_ASB_G3D_QCH_QE_G3D1_ENABLE, QCH_CON_ASB_G3D_QCH_QE_G3D1_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_QE_G3D1_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_QE_G3D1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_QE_G3D2, QCH_CON_ASB_G3D_QCH_QE_G3D2_ENABLE, QCH_CON_ASB_G3D_QCH_QE_G3D2_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_QE_G3D2_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_QE_G3D2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ASB_G3D_QCH_QE_G3D3, QCH_CON_ASB_G3D_QCH_QE_G3D3_ENABLE, QCH_CON_ASB_G3D_QCH_QE_G3D3_CLOCK_REQ, QCH_CON_ASB_G3D_QCH_QE_G3D3_EXPIRE_VAL, QCH_CON_ASB_G3D_QCH_QE_G3D3_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMG3D_QCH, QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMG3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_G3D_QCH, QCH_CON_D_TZPC_G3D_QCH_ENABLE, QCH_CON_D_TZPC_G3D_QCH_CLOCK_REQ, QCH_CON_D_TZPC_G3D_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(G3D_CMU_G3D_QCH, QCH_CON_G3D_CMU_G3D_QCH_ENABLE, QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, QCH_CON_G3D_CMU_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPU_QCH, QCH_CON_GPU_QCH_ENABLE, QCH_CON_GPU_QCH_CLOCK_REQ, QCH_CON_GPU_QCH_EXPIRE_VAL, QCH_CON_GPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_G3DSFR_QCH, QCH_CON_LHM_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHM_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_G3D_QCH, QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D0_G3D_QCH, QCH_CON_LHS_ACE_D0_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D0_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D0_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D0_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D1_G3D_QCH, QCH_CON_LHS_ACE_D1_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D1_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D1_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D1_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D2_G3D_QCH, QCH_CON_LHS_ACE_D2_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D2_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D2_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D2_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACE_D3_G3D_QCH, QCH_CON_LHS_ACE_D3_G3D_QCH_ENABLE, QCH_CON_LHS_ACE_D3_G3D_QCH_CLOCK_REQ, QCH_CON_LHS_ACE_D3_G3D_QCH_EXPIRE_VAL, QCH_CON_LHS_ACE_D3_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_G3DSFR_QCH, QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_G3DSFR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_G3D_QCH, QCH_CON_SYSREG_G3D_QCH_ENABLE, QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, QCH_CON_SYSREG_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_G3D_QCH, QCH_CON_VGEN_LITE_G3D_QCH_ENABLE, QCH_CON_VGEN_LITE_G3D_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_G3D_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_G3D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_ISPHQ_QCH, QCH_CON_BTM_ISPHQ_QCH_ENABLE, QCH_CON_BTM_ISPHQ_QCH_CLOCK_REQ, QCH_CON_BTM_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_ISPHQ_QCH, QCH_CON_D_TZPC_ISPHQ_QCH_ENABLE, QCH_CON_D_TZPC_ISPHQ_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ISPHQ_CMU_ISPHQ_QCH, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_ISPHQ_CMU_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPHQ_QCH_ISPHQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_ISPHQ_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPHQ_QCH_SYSMMU_ISPHQ, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_SYSMMU_ISPHQ_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPHQ_QCH_PPMU_ISPHQ, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_PPMU_ISPHQ_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPHQ_QCH_VGEN_LITE_ISPHQ, QCH_CON_IS_ISPHQ_QCH_VGEN_LITE_ISPHQ_ENABLE, QCH_CON_IS_ISPHQ_QCH_VGEN_LITE_ISPHQ_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_VGEN_LITE_ISPHQ_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_VGEN_LITE_ISPHQ_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPHQ_QCH_ISPHQ_C2COM, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_ENABLE, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_CLOCK_REQ, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_EXPIRE_VAL, QCH_CON_IS_ISPHQ_QCH_ISPHQ_C2COM_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_ISPPREISPHQ_QCH, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_ENABLE, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_VO_ISPLPISPHQ_QCH, QCH_CON_LHM_ATB_VO_ISPLPISPHQ_QCH_ENABLE, QCH_CON_LHM_ATB_VO_ISPLPISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_VO_ISPLPISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_VO_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_ISPHQ_QCH, QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_ISPHQDSPM_QCH, QCH_CON_LHS_AST_ISPHQDSPM_QCH_ENABLE, QCH_CON_LHS_AST_ISPHQDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ISPHQDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ISPHQDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_VO_ISPHQISPPRE_QCH, QCH_CON_LHS_AST_VO_ISPHQISPPRE_QCH_ENABLE, QCH_CON_LHS_AST_VO_ISPHQISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AST_VO_ISPHQISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_VO_ISPHQISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_ISPHQISPLP_QCH, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_ISPHQ_QCH, QCH_CON_LHS_AXI_D_ISPHQ_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_ISPHQ_QCH, QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_ISPLP0_QCH, QCH_CON_BTM_ISPLP0_QCH_ENABLE, QCH_CON_BTM_ISPLP0_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP0_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPLP0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_ISPLP1_QCH, QCH_CON_BTM_ISPLP1_QCH_ENABLE, QCH_CON_BTM_ISPLP1_QCH_CLOCK_REQ, QCH_CON_BTM_ISPLP1_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPLP1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_ISPLP_QCH, QCH_CON_D_TZPC_ISPLP_QCH_ENABLE, QCH_CON_D_TZPC_ISPLP_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISPLP_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ISPLP_CMU_ISPLP_QCH, QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL, QCH_CON_ISPLP_CMU_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_MC_SCALER, QCH_CON_IS_ISPLP_QCH_MC_SCALER_ENABLE, QCH_CON_IS_ISPLP_QCH_MC_SCALER_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_MC_SCALER_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_MC_SCALER_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_ISPLP, QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_ISPLP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_QE_ISPLP, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_ISPLP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_SYSMMU_ISPLP0, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_ENABLE, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_PPMU_ISPLP0, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_ENABLE, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_SYSMMU_ISPLP1, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_ENABLE, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_SYSMMU_ISPLP1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_PPMU_ISPLP1, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_ENABLE, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_PPMU_ISPLP1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_GDC, QCH_CON_IS_ISPLP_QCH_GDC_ENABLE, QCH_CON_IS_ISPLP_QCH_GDC_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_GDC_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_GDC_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_VGEN_LITE, QCH_CON_IS_ISPLP_QCH_VGEN_LITE_ENABLE, QCH_CON_IS_ISPLP_QCH_VGEN_LITE_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_VGEN_LITE_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_VGEN_LITE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_QE_GDC, QCH_CON_IS_ISPLP_QCH_QE_GDC_ENABLE, QCH_CON_IS_ISPLP_QCH_QE_GDC_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_QE_GDC_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_QE_GDC_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPLP_QCH_ISPLP_C2, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_ENABLE, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_CLOCK_REQ, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_EXPIRE_VAL, QCH_CON_IS_ISPLP_QCH_ISPLP_C2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_DSPMISPLP_QCH, QCH_CON_LHM_AST_DSPMISPLP_QCH_ENABLE, QCH_CON_LHM_AST_DSPMISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_DSPMISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_DSPMISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_VO_ISPPREISPLP_QCH, QCH_CON_LHM_AST_VO_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHM_AST_VO_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AST_VO_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_VO_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_ISPHQISPLP_QCH, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPHQISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_ATB_ISPPREISPLP_QCH, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_VRA2ISPLP_QCH, QCH_CON_LHM_AXI_D_VRA2ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_D_VRA2ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_VRA2ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_VRA2ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_ISPLP_QCH, QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_ISPLPDSPM_QCH, QCH_CON_LHS_AST_ISPLPDSPM_QCH_ENABLE, QCH_CON_LHS_AST_ISPLPDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ISPLPDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ISPLPDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_VO_ISPLPISPHQ_QCH, QCH_CON_LHS_ATB_VO_ISPLPISPHQ_QCH_ENABLE, QCH_CON_LHS_ATB_VO_ISPLPISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_VO_ISPLPISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_VO_ISPLPISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D0_ISPLP_QCH, QCH_CON_LHS_AXI_D0_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D0_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D1_ISPLP_QCH, QCH_CON_LHS_AXI_D1_ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D1_ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_ISPLPVRA2_QCH, QCH_CON_LHS_AXI_P_ISPLPVRA2_QCH_ENABLE, QCH_CON_LHS_AXI_P_ISPLPVRA2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_ISPLPVRA2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_ISPLPVRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_ISPLP_QCH, QCH_CON_SYSREG_ISPLP_QCH_ENABLE, QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL, QCH_CON_SYSREG_ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_ISPPRE_QCH, QCH_CON_BTM_ISPPRE_QCH_ENABLE, QCH_CON_BTM_ISPPRE_QCH_CLOCK_REQ, QCH_CON_BTM_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_BTM_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMISPPRE_QCH, QCH_CON_BUSIF_HPMISPPRE_QCH_ENABLE, QCH_CON_BUSIF_HPMISPPRE_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMISPPRE_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_ISPPRE_QCH, QCH_CON_D_TZPC_ISPPRE_QCH_ENABLE, QCH_CON_D_TZPC_ISPPRE_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_ISPPRE1_QCH, QCH_CON_D_TZPC_ISPPRE1_QCH_ENABLE, QCH_CON_D_TZPC_ISPPRE1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_ISPPRE1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_ISPPRE1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ISPPRE_CMU_ISPPRE_QCH, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_ENABLE, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_CLOCK_REQ, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_ISPPRE_CMU_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_CSIS0, QCH_CON_IS_ISPPRE_QCH_CSIS0_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_CSIS1, QCH_CON_IS_ISPPRE_QCH_CSIS1_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_CSIS2, QCH_CON_IS_ISPPRE_QCH_CSIS2_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS2_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS2_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_CSIS3, QCH_CON_IS_ISPPRE_QCH_CSIS3_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSIS3_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSIS3_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSIS3_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_PPMU_ISPPRE, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_ENABLE, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PPMU_ISPPRE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_PDP_TOP_DMA, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_DMA_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_DMA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_DMA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_DMA_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_SYSMMU_ISPPRE, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_ENABLE, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_SYSMMU_ISPPRE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QE_PDP_TOP, QCH_CON_IS_ISPPRE_QCH_QE_PDP_TOP_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_PDP_TOP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_PDP_TOP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_PDP_TOP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QE_3AA0, QCH_CON_IS_ISPPRE_QCH_QE_3AA0_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_3AA0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_3AA0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_3AA0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QE_3AA1, QCH_CON_IS_ISPPRE_QCH_QE_3AA1_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_3AA1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_3AA1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_3AA1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_3AA0, QCH_CON_IS_ISPPRE_QCH_3AA0_ENABLE, QCH_CON_IS_ISPPRE_QCH_3AA0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_3AA0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_3AA0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_3AA1, QCH_CON_IS_ISPPRE_QCH_3AA1_ENABLE, QCH_CON_IS_ISPPRE_QCH_3AA1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_3AA1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_3AA1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_PDP_TOP_CORE_TOP, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_CORE_TOP_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_CORE_TOP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_CORE_TOP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_CORE_TOP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_VGEN_LITE, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE_ENABLE, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QE_CSISX4_PDP, QCH_CON_IS_ISPPRE_QCH_QE_CSISX4_PDP_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_CSISX4_PDP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_CSISX4_PDP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_CSISX4_PDP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_VGEN_LITE1, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE1_ENABLE, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QSIS3_1, QCH_CON_IS_ISPPRE_QCH_QSIS3_1_ENABLE, QCH_CON_IS_ISPPRE_QCH_QSIS3_1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QSIS3_1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QSIS3_1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_CSISX4_PDP_DMA, QCH_CON_IS_ISPPRE_QCH_CSISX4_PDP_DMA_ENABLE, QCH_CON_IS_ISPPRE_QCH_CSISX4_PDP_DMA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_CSISX4_PDP_DMA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_CSISX4_PDP_DMA_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_VGEN_LITE2, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE2_ENABLE, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE2_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE2_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_VGEN_LITE2_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_VPP, QCH_CON_IS_ISPPRE_QCH_VPP_ENABLE, QCH_CON_IS_ISPPRE_QCH_VPP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_VPP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_VPP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_C2_CSISX4_PDP, QCH_CON_IS_ISPPRE_QCH_C2_CSISX4_PDP_ENABLE, QCH_CON_IS_ISPPRE_QCH_C2_CSISX4_PDP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_C2_CSISX4_PDP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_C2_CSISX4_PDP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_C2_3AA0, QCH_CON_IS_ISPPRE_QCH_C2_3AA0_ENABLE, QCH_CON_IS_ISPPRE_QCH_C2_3AA0_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_C2_3AA0_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_C2_3AA0_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_C2_3AA1, QCH_CON_IS_ISPPRE_QCH_C2_3AA1_ENABLE, QCH_CON_IS_ISPPRE_QCH_C2_3AA1_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_C2_3AA1_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_C2_3AA1_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_C2_AGENT, QCH_CON_IS_ISPPRE_QCH_C2_AGENT_ENABLE, QCH_CON_IS_ISPPRE_QCH_C2_AGENT_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_C2_AGENT_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_C2_AGENT_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_QE_VPP, QCH_CON_IS_ISPPRE_QCH_QE_VPP_ENABLE, QCH_CON_IS_ISPPRE_QCH_QE_VPP_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_QE_VPP_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_QE_VPP_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IS_ISPPRE_QCH_PDP_TOP_RDMA, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_RDMA_ENABLE, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_RDMA_CLOCK_REQ, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_RDMA_EXPIRE_VAL, QCH_CON_IS_ISPPRE_QCH_PDP_TOP_RDMA_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_DSPMISPPRE_QCH, QCH_CON_LHM_AST_DSPMISPPRE_QCH_ENABLE, QCH_CON_LHM_AST_DSPMISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AST_DSPMISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_DSPMISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_VO_ISPHQISPPRE_QCH, QCH_CON_LHM_AST_VO_ISPHQISPPRE_QCH_ENABLE, QCH_CON_LHM_AST_VO_ISPHQISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AST_VO_ISPHQISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_VO_ISPHQISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_ISPPRE_QCH, QCH_CON_LHM_AXI_P_ISPPRE_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_ISPPREDSPM_QCH, QCH_CON_LHS_AST_ISPPREDSPM_QCH_ENABLE, QCH_CON_LHS_AST_ISPPREDSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AST_ISPPREDSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_ISPPREDSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_VO_ISPPREISPLP_QCH, QCH_CON_LHS_AST_VO_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHS_AST_VO_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AST_VO_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_VO_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_ISPPREISPHQ_QCH, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_ENABLE, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPPREISPHQ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ATB_ISPPREISPLP_QCH, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_ENABLE, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_ATB_ISPPREISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_ISPPRE_QCH, QCH_CON_LHS_AXI_D_ISPPRE_QCH_ENABLE, QCH_CON_LHS_AXI_D_ISPPRE_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_ISPPRE_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_ISPPRE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_ISPPRE_QCH_SYSREG, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_ENABLE, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_CLOCK_REQ, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_EXPIRE_VAL, QCH_CON_SYSREG_ISPPRE_QCH_SYSREG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(ADM_DAP_IVA_QCH, DMYQCH_CON_ADM_DAP_IVA_QCH_ENABLE, DMYQCH_CON_ADM_DAP_IVA_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_ADM_DAP_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_IVA_QCH, QCH_CON_BTM_IVA_QCH_ENABLE, QCH_CON_BTM_IVA_QCH_CLOCK_REQ, QCH_CON_BTM_IVA_QCH_EXPIRE_VAL, QCH_CON_BTM_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_IVA_QCH, QCH_CON_D_TZPC_IVA_QCH_ENABLE, QCH_CON_D_TZPC_IVA_QCH_CLOCK_REQ, QCH_CON_D_TZPC_IVA_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IVA_QCH_IVA, QCH_CON_IVA_QCH_IVA_ENABLE, QCH_CON_IVA_QCH_IVA_CLOCK_REQ, QCH_CON_IVA_QCH_IVA_EXPIRE_VAL, QCH_CON_IVA_QCH_IVA_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IVA_QCH_IVA_DEBUG, QCH_CON_IVA_QCH_IVA_DEBUG_ENABLE, QCH_CON_IVA_QCH_IVA_DEBUG_CLOCK_REQ, QCH_CON_IVA_QCH_IVA_DEBUG_EXPIRE_VAL, QCH_CON_IVA_QCH_IVA_DEBUG_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IVA_CMU_IVA_QCH, QCH_CON_IVA_CMU_IVA_QCH_ENABLE, QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL, QCH_CON_IVA_CMU_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(IVA_INTMEM_QCH, QCH_CON_IVA_INTMEM_QCH_ENABLE, QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL, QCH_CON_IVA_INTMEM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_DSPSIVA_QCH, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_ENABLE, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DSPSIVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_IVASC_QCH, QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IVASC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_DSPMIVA_QCH, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_DSPMIVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_IVA_QCH, QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D_IVA_QCH, QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_IVADSPS_QCH, QCH_CON_LHS_AXI_D_IVADSPS_QCH_ENABLE, QCH_CON_LHS_AXI_D_IVADSPS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IVADSPS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IVADSPS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_IVADSPM_QCH, QCH_CON_LHS_AXI_P_IVADSPM_QCH_ENABLE, QCH_CON_LHS_AXI_P_IVADSPM_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_IVADSPM_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_IVADSPM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_IVA_QCH, QCH_CON_PPMU_IVA_QCH_ENABLE, QCH_CON_PPMU_IVA_QCH_CLOCK_REQ, QCH_CON_PPMU_IVA_QCH_EXPIRE_VAL, QCH_CON_PPMU_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_IVA_QCH, QCH_CON_QE_IVA_QCH_ENABLE, QCH_CON_QE_IVA_QCH_CLOCK_REQ, QCH_CON_QE_IVA_QCH_EXPIRE_VAL, QCH_CON_QE_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_IVA_QCH, QCH_CON_SYSMMU_IVA_QCH_ENABLE, QCH_CON_SYSMMU_IVA_QCH_CLOCK_REQ, QCH_CON_SYSMMU_IVA_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_IVA_QCH, QCH_CON_SYSREG_IVA_QCH_ENABLE, QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL, QCH_CON_SYSREG_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TREX_RB1_IVA_QCH, QCH_CON_TREX_RB1_IVA_QCH_ENABLE, QCH_CON_TREX_RB1_IVA_QCH_CLOCK_REQ, QCH_CON_TREX_RB1_IVA_QCH_EXPIRE_VAL, QCH_CON_TREX_RB1_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_IVA_QCH, QCH_CON_VGEN_LITE_IVA_QCH_ENABLE, QCH_CON_VGEN_LITE_IVA_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_IVA_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_IVA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_MFCD0_QCH, QCH_CON_BTM_MFCD0_QCH_ENABLE, QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_MFCD1_QCH, QCH_CON_BTM_MFCD1_QCH_ENABLE, QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, QCH_CON_BTM_MFCD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_MFC_QCH, QCH_CON_D_TZPC_MFC_QCH_ENABLE, QCH_CON_D_TZPC_MFC_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MFC_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_MFC_QCH, QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D0_MFC_QCH, QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D0_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D1_MFC_QCH, QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D1_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LH_ATB_MFC_QCH_MI, QCH_CON_LH_ATB_MFC_QCH_MI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_MI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_MI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_MI_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LH_ATB_MFC_QCH_SI, QCH_CON_LH_ATB_MFC_QCH_SI_ENABLE, QCH_CON_LH_ATB_MFC_QCH_SI_CLOCK_REQ, QCH_CON_LH_ATB_MFC_QCH_SI_EXPIRE_VAL, QCH_CON_LH_ATB_MFC_QCH_SI_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MFC_QCH, QCH_CON_MFC_QCH_ENABLE, QCH_CON_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MFC_CMU_MFC_QCH, QCH_CON_MFC_CMU_MFC_QCH_ENABLE, QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, QCH_CON_MFC_CMU_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_MFCD0_QCH, QCH_CON_PPMU_MFCD0_QCH_ENABLE, QCH_CON_PPMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_MFCD1_QCH, QCH_CON_PPMU_MFCD1_QCH_ENABLE, QCH_CON_PPMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_MFCD2_QCH, QCH_CON_PPMU_MFCD2_QCH_ENABLE, QCH_CON_PPMU_MFCD2_QCH_CLOCK_REQ, QCH_CON_PPMU_MFCD2_QCH_EXPIRE_VAL, QCH_CON_PPMU_MFCD2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_ENABLE, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_CLOCK_REQ, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_EXPIRE_VAL, QCH_CON_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_MFCD0_QCH, QCH_CON_SYSMMU_MFCD0_QCH_ENABLE, QCH_CON_SYSMMU_MFCD0_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD0_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_MFCD1_QCH, QCH_CON_SYSMMU_MFCD1_QCH_ENABLE, QCH_CON_SYSMMU_MFCD1_QCH_CLOCK_REQ, QCH_CON_SYSMMU_MFCD1_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_MFCD1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_MFC_QCH, QCH_CON_SYSREG_MFC_QCH_ENABLE, QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_MFC_QCH, QCH_CON_VGEN_MFC_QCH_ENABLE, QCH_CON_VGEN_MFC_QCH_CLOCK_REQ, QCH_CON_VGEN_MFC_QCH_EXPIRE_VAL, QCH_CON_VGEN_MFC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WFD_QCH, QCH_CON_WFD_QCH_ENABLE, QCH_CON_WFD_QCH_CLOCK_REQ, QCH_CON_WFD_QCH_EXPIRE_VAL, QCH_CON_WFD_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DDRPHY_QCH, QCH_CON_APBBR_DDRPHY_QCH_ENABLE, QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMC_QCH, QCH_CON_APBBR_DMC_QCH_ENABLE, QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMCTZ_QCH, QCH_CON_APBBR_DMCTZ_QCH_ENABLE, QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMMIF_QCH, QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_MIF_CMUREF_QCH, DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMC_QCH, QCH_CON_DMC_QCH_ENABLE, QCH_CON_DMC_QCH_CLOCK_REQ, QCH_CON_DMC_QCH_EXPIRE_VAL, QCH_CON_DMC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_MIF_QCH, QCH_CON_D_TZPC_MIF_QCH_ENABLE, QCH_CON_D_TZPC_MIF_QCH_CLOCK_REQ, QCH_CON_D_TZPC_MIF_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_MIF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_MIF_QCH, QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MIF_CMU_MIF_QCH, QCH_CON_MIF_CMU_MIF_QCH_ENABLE, QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, QCH_CON_MIF_CMU_MIF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPC_DEBUG_QCH, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPC_DEBUG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPC_DVFS_QCH, QCH_CON_QCH_ADAPTER_PPC_DVFS_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPC_DVFS_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPC_DVFS_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPC_DVFS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_MIF_QCH, QCH_CON_SYSREG_MIF_QCH_ENABLE, QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DDRPHY1_QCH, QCH_CON_APBBR_DDRPHY1_QCH_ENABLE, QCH_CON_APBBR_DDRPHY1_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY1_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMC1_QCH, QCH_CON_APBBR_DMC1_QCH_ENABLE, QCH_CON_APBBR_DMC1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC1_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMCTZ1_QCH, QCH_CON_APBBR_DMCTZ1_QCH_ENABLE, QCH_CON_APBBR_DMCTZ1_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ1_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMMIF1_QCH, QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_MIF1_CMUREF_QCH, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF1_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMC1_QCH, QCH_CON_DMC1_QCH_ENABLE, QCH_CON_DMC1_QCH_CLOCK_REQ, QCH_CON_DMC1_QCH_EXPIRE_VAL, QCH_CON_DMC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_MIF1_QCH, QCH_CON_LHM_AXI_P_MIF1_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MIF1_CMU_MIF1_QCH, QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, QCH_CON_MIF1_CMU_MIF1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DEBUG1_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG1_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG1_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG1_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DVFS1_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS1_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS1_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS1_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_MIF1_QCH, QCH_CON_SYSREG_MIF1_QCH_ENABLE, QCH_CON_SYSREG_MIF1_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DDRPHY2_QCH, QCH_CON_APBBR_DDRPHY2_QCH_ENABLE, QCH_CON_APBBR_DDRPHY2_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY2_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMC2_QCH, QCH_CON_APBBR_DMC2_QCH_ENABLE, QCH_CON_APBBR_DMC2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC2_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMCTZ2_QCH, QCH_CON_APBBR_DMCTZ2_QCH_ENABLE, QCH_CON_APBBR_DMCTZ2_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ2_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMMIF2_QCH, QCH_CON_BUSIF_HPMMIF2_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF2_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF2_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_MIF2_CMUREF_QCH, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF2_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMC2_QCH, QCH_CON_DMC2_QCH_ENABLE, QCH_CON_DMC2_QCH_CLOCK_REQ, QCH_CON_DMC2_QCH_EXPIRE_VAL, QCH_CON_DMC2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_MIF2_QCH, QCH_CON_LHM_AXI_P_MIF2_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MIF2_CMU_MIF2_QCH, QCH_CON_MIF2_CMU_MIF2_QCH_ENABLE, QCH_CON_MIF2_CMU_MIF2_QCH_CLOCK_REQ, QCH_CON_MIF2_CMU_MIF2_QCH_EXPIRE_VAL, QCH_CON_MIF2_CMU_MIF2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DEBUG2_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG2_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG2_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG2_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DVFS2_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS2_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS2_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS2_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_MIF2_QCH, QCH_CON_SYSREG_MIF2_QCH_ENABLE, QCH_CON_SYSREG_MIF2_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DDRPHY3_QCH, QCH_CON_APBBR_DDRPHY3_QCH_ENABLE, QCH_CON_APBBR_DDRPHY3_QCH_CLOCK_REQ, QCH_CON_APBBR_DDRPHY3_QCH_EXPIRE_VAL, QCH_CON_APBBR_DDRPHY3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMC3_QCH, QCH_CON_APBBR_DMC3_QCH_ENABLE, QCH_CON_APBBR_DMC3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMC3_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMC3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(APBBR_DMCTZ3_QCH, QCH_CON_APBBR_DMCTZ3_QCH_ENABLE, QCH_CON_APBBR_DMCTZ3_QCH_CLOCK_REQ, QCH_CON_APBBR_DMCTZ3_QCH_EXPIRE_VAL, QCH_CON_APBBR_DMCTZ3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BUSIF_HPMMIF3_QCH, QCH_CON_BUSIF_HPMMIF3_QCH_ENABLE, QCH_CON_BUSIF_HPMMIF3_QCH_CLOCK_REQ, QCH_CON_BUSIF_HPMMIF3_QCH_EXPIRE_VAL, QCH_CON_BUSIF_HPMMIF3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CMU_MIF3_CMUREF_QCH, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_ENABLE, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_CMU_MIF3_CMUREF_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMC3_QCH, QCH_CON_DMC3_QCH_ENABLE, QCH_CON_DMC3_QCH_CLOCK_REQ, QCH_CON_DMC3_QCH_EXPIRE_VAL, QCH_CON_DMC3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_MIF3_QCH, QCH_CON_LHM_AXI_P_MIF3_QCH_ENABLE, QCH_CON_LHM_AXI_P_MIF3_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_MIF3_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_MIF3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MIF3_CMU_MIF3_QCH, QCH_CON_MIF3_CMU_MIF3_QCH_ENABLE, QCH_CON_MIF3_CMU_MIF3_QCH_CLOCK_REQ, QCH_CON_MIF3_CMU_MIF3_QCH_EXPIRE_VAL, QCH_CON_MIF3_CMU_MIF3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DEBUG3_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG3_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG3_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG3_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DEBUG3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QCH_ADAPTER_PPMUPPC_DVFS3_QCH, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS3_QCH_ENABLE, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS3_QCH_CLOCK_REQ, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS3_QCH_EXPIRE_VAL, QCH_CON_QCH_ADAPTER_PPMUPPC_DVFS3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_MIF3_QCH, QCH_CON_SYSREG_MIF3_QCH_ENABLE, QCH_CON_SYSREG_MIF3_QCH_CLOCK_REQ, QCH_CON_SYSREG_MIF3_QCH_EXPIRE_VAL, QCH_CON_SYSREG_MIF3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_NPU0_QCH, QCH_CON_BTM_NPU0_QCH_ENABLE, QCH_CON_BTM_NPU0_QCH_CLOCK_REQ, QCH_CON_BTM_NPU0_QCH_EXPIRE_VAL, QCH_CON_BTM_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_NPU0_QCH, QCH_CON_D_TZPC_NPU0_QCH_ENABLE, QCH_CON_D_TZPC_NPU0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_0_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_0_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_1_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_1_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_2_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_2_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_2_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_2_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_3_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_3_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_3_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_3_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_4_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_4_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_4_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_4_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_4_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_5_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_5_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_5_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_5_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_5_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_6_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_6_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_6_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_6_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_6_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD1_D1_7_QCH, QCH_CON_LHM_AST_D_NPUD1_D1_7_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD1_D1_7_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD1_D1_7_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD1_D1_7_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_P_NPU1_DONE_QCH, QCH_CON_LHM_AST_P_NPU1_DONE_QCH_ENABLE, QCH_CON_LHM_AST_P_NPU1_DONE_QCH_CLOCK_REQ, QCH_CON_LHM_AST_P_NPU1_DONE_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_P_NPU1_DONE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_DSPMNPU0_QCH, QCH_CON_LHM_AXI_D_DSPMNPU0_QCH_ENABLE, QCH_CON_LHM_AXI_D_DSPMNPU0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_DSPMNPU0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_DSPMNPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_NPU_QCH, QCH_CON_LHM_AXI_P_NPU_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPU_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPU_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_ACEL_D_NPU_QCH, QCH_CON_LHS_ACEL_D_NPU_QCH_ENABLE, QCH_CON_LHS_ACEL_D_NPU_QCH_CLOCK_REQ, QCH_CON_LHS_ACEL_D_NPU_QCH_EXPIRE_VAL, QCH_CON_LHS_ACEL_D_NPU_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_0_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_0_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_1_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_1_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_2_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_2_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_2_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_2_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_3_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_3_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_3_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_3_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_4_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_4_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_4_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_4_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_4_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_5_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_5_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_5_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_5_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_5_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_6_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_6_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_6_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_6_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_6_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD0_D1_7_QCH, QCH_CON_LHS_AST_D_NPUD0_D1_7_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD0_D1_7_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD0_D1_7_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD0_D1_7_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_P_NPUD1_SETREG_QCH, QCH_CON_LHS_AST_P_NPUD1_SETREG_QCH_ENABLE, QCH_CON_LHS_AST_P_NPUD1_SETREG_QCH_CLOCK_REQ, QCH_CON_LHS_AST_P_NPUD1_SETREG_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_P_NPUD1_SETREG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_IDPSRAM1_QCH, QCH_CON_LHS_AXI_D_IDPSRAM1_QCH_ENABLE, QCH_CON_LHS_AXI_D_IDPSRAM1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IDPSRAM1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IDPSRAM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_IDPSRAM3_QCH, QCH_CON_LHS_AXI_D_IDPSRAM3_QCH_ENABLE, QCH_CON_LHS_AXI_D_IDPSRAM3_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_IDPSRAM3_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_IDPSRAM3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_P_NPU1_QCH, QCH_CON_LHS_AXI_P_NPU1_QCH_ENABLE, QCH_CON_LHS_AXI_P_NPU1_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_P_NPU1_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_P_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(NPU0_CMU_NPU0_QCH, QCH_CON_NPU0_CMU_NPU0_QCH_ENABLE, QCH_CON_NPU0_CMU_NPU0_QCH_CLOCK_REQ, QCH_CON_NPU0_CMU_NPU0_QCH_EXPIRE_VAL, QCH_CON_NPU0_CMU_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(NPUC_QCH, DMYQCH_CON_NPUC_QCH_ENABLE, DMYQCH_CON_NPUC_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_NPUC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(NPUD_UNIT0_QCH, DMYQCH_CON_NPUD_UNIT0_QCH_ENABLE, DMYQCH_CON_NPUD_UNIT0_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_NPUD_UNIT0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_CPUDMA_QCH, QCH_CON_PPMU_CPUDMA_QCH_ENABLE, QCH_CON_PPMU_CPUDMA_QCH_CLOCK_REQ, QCH_CON_PPMU_CPUDMA_QCH_EXPIRE_VAL, QCH_CON_PPMU_CPUDMA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_NPU0_QCH, QCH_CON_PPMU_NPU0_QCH_ENABLE, QCH_CON_PPMU_NPU0_QCH_CLOCK_REQ, QCH_CON_PPMU_NPU0_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_RFM_QCH, QCH_CON_PPMU_RFM_QCH_ENABLE, QCH_CON_PPMU_RFM_QCH_CLOCK_REQ, QCH_CON_PPMU_RFM_QCH_EXPIRE_VAL, QCH_CON_PPMU_RFM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_CPUDMA_QCH, QCH_CON_QE_CPUDMA_QCH_ENABLE, QCH_CON_QE_CPUDMA_QCH_CLOCK_REQ, QCH_CON_QE_CPUDMA_QCH_EXPIRE_VAL, QCH_CON_QE_CPUDMA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_RFM_QCH, QCH_CON_QE_RFM_QCH_ENABLE, QCH_CON_QE_RFM_QCH_CLOCK_REQ, QCH_CON_QE_RFM_QCH_EXPIRE_VAL, QCH_CON_QE_RFM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SMMU_NPU0_QCH, QCH_CON_SMMU_NPU0_QCH_ENABLE, QCH_CON_SMMU_NPU0_QCH_CLOCK_REQ, QCH_CON_SMMU_NPU0_QCH_EXPIRE_VAL, QCH_CON_SMMU_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_NPU0_QCH, QCH_CON_SYSREG_NPU0_QCH_ENABLE, QCH_CON_SYSREG_NPU0_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_NPU0_QCH, QCH_CON_VGEN_LITE_NPU0_QCH_ENABLE, QCH_CON_VGEN_LITE_NPU0_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_NPU0_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_NPU0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_NPU1_QCH, QCH_CON_D_TZPC_NPU1_QCH_ENABLE, QCH_CON_D_TZPC_NPU1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_NPU1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_0_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_0_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_0_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_0_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_1_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_1_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_1_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_1_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_2_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_2_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_2_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_2_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_3_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_3_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_3_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_3_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_4_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_4_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_4_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_4_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_4_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_5_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_5_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_5_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_5_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_5_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_6_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_6_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_6_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_6_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_6_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_D_NPUD0_D1_7_QCH, QCH_CON_LHM_AST_D_NPUD0_D1_7_QCH_ENABLE, QCH_CON_LHM_AST_D_NPUD0_D1_7_QCH_CLOCK_REQ, QCH_CON_LHM_AST_D_NPUD0_D1_7_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_D_NPUD0_D1_7_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AST_P_NPUD1_SETREG_QCH, QCH_CON_LHM_AST_P_NPUD1_SETREG_QCH_ENABLE, QCH_CON_LHM_AST_P_NPUD1_SETREG_QCH_CLOCK_REQ, QCH_CON_LHM_AST_P_NPUD1_SETREG_QCH_EXPIRE_VAL, QCH_CON_LHM_AST_P_NPUD1_SETREG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_IDPSRAM1_QCH, QCH_CON_LHM_AXI_D_IDPSRAM1_QCH_ENABLE, QCH_CON_LHM_AXI_D_IDPSRAM1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IDPSRAM1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IDPSRAM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_D_IDPSRAM3_QCH, QCH_CON_LHM_AXI_D_IDPSRAM3_QCH_ENABLE, QCH_CON_LHM_AXI_D_IDPSRAM3_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_D_IDPSRAM3_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_D_IDPSRAM3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_NPU1_QCH, QCH_CON_LHM_AXI_P_NPU1_QCH_ENABLE, QCH_CON_LHM_AXI_P_NPU1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_NPU1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_0_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_0_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_0_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_0_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_1_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_1_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_1_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_1_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_2_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_2_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_2_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_2_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_3_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_3_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_3_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_3_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_4_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_4_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_4_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_4_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_4_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_5_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_5_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_5_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_5_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_5_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_6_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_6_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_6_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_6_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_6_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_D_NPUD1_D1_7_QCH, QCH_CON_LHS_AST_D_NPUD1_D1_7_QCH_ENABLE, QCH_CON_LHS_AST_D_NPUD1_D1_7_QCH_CLOCK_REQ, QCH_CON_LHS_AST_D_NPUD1_D1_7_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_D_NPUD1_D1_7_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AST_P_NPU1_DONE_QCH, QCH_CON_LHS_AST_P_NPU1_DONE_QCH_ENABLE, QCH_CON_LHS_AST_P_NPU1_DONE_QCH_CLOCK_REQ, QCH_CON_LHS_AST_P_NPU1_DONE_QCH_EXPIRE_VAL, QCH_CON_LHS_AST_P_NPU1_DONE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(NPU1_CMU_NPU1_QCH, QCH_CON_NPU1_CMU_NPU1_QCH_ENABLE, QCH_CON_NPU1_CMU_NPU1_QCH_CLOCK_REQ, QCH_CON_NPU1_CMU_NPU1_QCH_EXPIRE_VAL, QCH_CON_NPU1_CMU_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(NPUD_UNIT1_QCH, DMYQCH_CON_NPUD_UNIT1_QCH_ENABLE, DMYQCH_CON_NPUD_UNIT1_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_NPUD_UNIT1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_NPU1_QCH, QCH_CON_PPMU_NPU1_QCH_ENABLE, QCH_CON_PPMU_NPU1_QCH_CLOCK_REQ, QCH_CON_PPMU_NPU1_QCH_EXPIRE_VAL, QCH_CON_PPMU_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_NPU1_QCH, QCH_CON_SYSREG_NPU1_QCH_ENABLE, QCH_CON_SYSREG_NPU1_QCH_CLOCK_REQ, QCH_CON_SYSREG_NPU1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_NPU1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_PERIC0_QCH, QCH_CON_D_TZPC_PERIC0_QCH_ENABLE, QCH_CON_D_TZPC_PERIC0_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC0_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_PERIC0_QCH, QCH_CON_GPIO_PERIC0_QCH_ENABLE, QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_PERIC0_QCH, QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PERIC0_CMU_PERIC0_QCH, QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, QCH_CON_PERIC0_CMU_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PWM_QCH, QCH_CON_PWM_QCH_ENABLE, QCH_CON_PWM_QCH_CLOCK_REQ, QCH_CON_PWM_QCH_EXPIRE_VAL, QCH_CON_PWM_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_PERIC0_QCH, QCH_CON_SYSREG_PERIC0_QCH_ENABLE, QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UART_DBG_QCH, QCH_CON_UART_DBG_QCH_ENABLE, QCH_CON_UART_DBG_QCH_CLOCK_REQ, QCH_CON_UART_DBG_QCH_EXPIRE_VAL, QCH_CON_UART_DBG_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI00_I2C_QCH, QCH_CON_USI00_I2C_QCH_ENABLE, QCH_CON_USI00_I2C_QCH_CLOCK_REQ, QCH_CON_USI00_I2C_QCH_EXPIRE_VAL, QCH_CON_USI00_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI00_USI_QCH, QCH_CON_USI00_USI_QCH_ENABLE, QCH_CON_USI00_USI_QCH_CLOCK_REQ, QCH_CON_USI00_USI_QCH_EXPIRE_VAL, QCH_CON_USI00_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI01_I2C_QCH, QCH_CON_USI01_I2C_QCH_ENABLE, QCH_CON_USI01_I2C_QCH_CLOCK_REQ, QCH_CON_USI01_I2C_QCH_EXPIRE_VAL, QCH_CON_USI01_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI01_USI_QCH, QCH_CON_USI01_USI_QCH_ENABLE, QCH_CON_USI01_USI_QCH_CLOCK_REQ, QCH_CON_USI01_USI_QCH_EXPIRE_VAL, QCH_CON_USI01_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI02_I2C_QCH, QCH_CON_USI02_I2C_QCH_ENABLE, QCH_CON_USI02_I2C_QCH_CLOCK_REQ, QCH_CON_USI02_I2C_QCH_EXPIRE_VAL, QCH_CON_USI02_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI02_USI_QCH, QCH_CON_USI02_USI_QCH_ENABLE, QCH_CON_USI02_USI_QCH_CLOCK_REQ, QCH_CON_USI02_USI_QCH_EXPIRE_VAL, QCH_CON_USI02_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI03_I2C_QCH, QCH_CON_USI03_I2C_QCH_ENABLE, QCH_CON_USI03_I2C_QCH_CLOCK_REQ, QCH_CON_USI03_I2C_QCH_EXPIRE_VAL, QCH_CON_USI03_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI03_USI_QCH, QCH_CON_USI03_USI_QCH_ENABLE, QCH_CON_USI03_USI_QCH_CLOCK_REQ, QCH_CON_USI03_USI_QCH_EXPIRE_VAL, QCH_CON_USI03_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI04_I2C_QCH, QCH_CON_USI04_I2C_QCH_ENABLE, QCH_CON_USI04_I2C_QCH_CLOCK_REQ, QCH_CON_USI04_I2C_QCH_EXPIRE_VAL, QCH_CON_USI04_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI04_USI_QCH, QCH_CON_USI04_USI_QCH_ENABLE, QCH_CON_USI04_USI_QCH_CLOCK_REQ, QCH_CON_USI04_USI_QCH_EXPIRE_VAL, QCH_CON_USI04_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI05_I2C_QCH, QCH_CON_USI05_I2C_QCH_ENABLE, QCH_CON_USI05_I2C_QCH_CLOCK_REQ, QCH_CON_USI05_I2C_QCH_EXPIRE_VAL, QCH_CON_USI05_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI05_USI_QCH, QCH_CON_USI05_USI_QCH_ENABLE, QCH_CON_USI05_USI_QCH_CLOCK_REQ, QCH_CON_USI05_USI_QCH_EXPIRE_VAL, QCH_CON_USI05_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI12_I2C_QCH, QCH_CON_USI12_I2C_QCH_ENABLE, QCH_CON_USI12_I2C_QCH_CLOCK_REQ, QCH_CON_USI12_I2C_QCH_EXPIRE_VAL, QCH_CON_USI12_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI12_USI_QCH, QCH_CON_USI12_USI_QCH_ENABLE, QCH_CON_USI12_USI_QCH_CLOCK_REQ, QCH_CON_USI12_USI_QCH_EXPIRE_VAL, QCH_CON_USI12_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI13_I2C_QCH, QCH_CON_USI13_I2C_QCH_ENABLE, QCH_CON_USI13_I2C_QCH_CLOCK_REQ, QCH_CON_USI13_I2C_QCH_EXPIRE_VAL, QCH_CON_USI13_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI13_USI_QCH, QCH_CON_USI13_USI_QCH_ENABLE, QCH_CON_USI13_USI_QCH_CLOCK_REQ, QCH_CON_USI13_USI_QCH_EXPIRE_VAL, QCH_CON_USI13_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI14_I2C_QCH, QCH_CON_USI14_I2C_QCH_ENABLE, QCH_CON_USI14_I2C_QCH_CLOCK_REQ, QCH_CON_USI14_I2C_QCH_EXPIRE_VAL, QCH_CON_USI14_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI14_USI_QCH, QCH_CON_USI14_USI_QCH_ENABLE, QCH_CON_USI14_USI_QCH_CLOCK_REQ, QCH_CON_USI14_USI_QCH_EXPIRE_VAL, QCH_CON_USI14_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI15_I2C_QCH, QCH_CON_USI15_I2C_QCH_ENABLE, QCH_CON_USI15_I2C_QCH_CLOCK_REQ, QCH_CON_USI15_I2C_QCH_EXPIRE_VAL, QCH_CON_USI15_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI15_USI_QCH, QCH_CON_USI15_USI_QCH_ENABLE, QCH_CON_USI15_USI_QCH_CLOCK_REQ, QCH_CON_USI15_USI_QCH_EXPIRE_VAL, QCH_CON_USI15_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_PERIC1_QCH, QCH_CON_D_TZPC_PERIC1_QCH_ENABLE, QCH_CON_D_TZPC_PERIC1_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIC1_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_PERIC1_QCH, QCH_CON_GPIO_PERIC1_QCH_ENABLE, QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, QCH_CON_GPIO_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CAM0_QCH, QCH_CON_I2C_CAM0_QCH_ENABLE, QCH_CON_I2C_CAM0_QCH_CLOCK_REQ, QCH_CON_I2C_CAM0_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CAM1_QCH, QCH_CON_I2C_CAM1_QCH_ENABLE, QCH_CON_I2C_CAM1_QCH_CLOCK_REQ, QCH_CON_I2C_CAM1_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CAM2_QCH, QCH_CON_I2C_CAM2_QCH_ENABLE, QCH_CON_I2C_CAM2_QCH_CLOCK_REQ, QCH_CON_I2C_CAM2_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I2C_CAM3_QCH, QCH_CON_I2C_CAM3_QCH_ENABLE, QCH_CON_I2C_CAM3_QCH_CLOCK_REQ, QCH_CON_I2C_CAM3_QCH_EXPIRE_VAL, QCH_CON_I2C_CAM3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I3C_QCH_I3C, QCH_CON_I3C_QCH_I3C_ENABLE, QCH_CON_I3C_QCH_I3C_CLOCK_REQ, QCH_CON_I3C_QCH_I3C_EXPIRE_VAL, QCH_CON_I3C_QCH_I3C_IGNORE_FORCE_PM_EN), |
| CLK_QCH(I3C_QCH_DMY, DMYQCH_CON_I3C_QCH_DMY_ENABLE, DMYQCH_CON_I3C_QCH_DMY_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_I3C_QCH_DMY_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_PERIC1_QCH, QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PERIC1_CMU_PERIC1_QCH, QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, QCH_CON_PERIC1_CMU_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SPI_CAM0_QCH, QCH_CON_SPI_CAM0_QCH_ENABLE, QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL, QCH_CON_SPI_CAM0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_PERIC1_QCH, QCH_CON_SYSREG_PERIC1_QCH_ENABLE, QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(UART_BT_QCH, QCH_CON_UART_BT_QCH_ENABLE, QCH_CON_UART_BT_QCH_CLOCK_REQ, QCH_CON_UART_BT_QCH_EXPIRE_VAL, QCH_CON_UART_BT_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI06_I2C_QCH, QCH_CON_USI06_I2C_QCH_ENABLE, QCH_CON_USI06_I2C_QCH_CLOCK_REQ, QCH_CON_USI06_I2C_QCH_EXPIRE_VAL, QCH_CON_USI06_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI06_USI_QCH, QCH_CON_USI06_USI_QCH_ENABLE, QCH_CON_USI06_USI_QCH_CLOCK_REQ, QCH_CON_USI06_USI_QCH_EXPIRE_VAL, QCH_CON_USI06_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI07_I2C_QCH, QCH_CON_USI07_I2C_QCH_ENABLE, QCH_CON_USI07_I2C_QCH_CLOCK_REQ, QCH_CON_USI07_I2C_QCH_EXPIRE_VAL, QCH_CON_USI07_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI07_USI_QCH, QCH_CON_USI07_USI_QCH_ENABLE, QCH_CON_USI07_USI_QCH_CLOCK_REQ, QCH_CON_USI07_USI_QCH_EXPIRE_VAL, QCH_CON_USI07_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI08_I2C_QCH, QCH_CON_USI08_I2C_QCH_ENABLE, QCH_CON_USI08_I2C_QCH_CLOCK_REQ, QCH_CON_USI08_I2C_QCH_EXPIRE_VAL, QCH_CON_USI08_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI08_USI_QCH, QCH_CON_USI08_USI_QCH_ENABLE, QCH_CON_USI08_USI_QCH_CLOCK_REQ, QCH_CON_USI08_USI_QCH_EXPIRE_VAL, QCH_CON_USI08_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI09_I2C_QCH, QCH_CON_USI09_I2C_QCH_ENABLE, QCH_CON_USI09_I2C_QCH_CLOCK_REQ, QCH_CON_USI09_I2C_QCH_EXPIRE_VAL, QCH_CON_USI09_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI09_USI_QCH, QCH_CON_USI09_USI_QCH_ENABLE, QCH_CON_USI09_USI_QCH_CLOCK_REQ, QCH_CON_USI09_USI_QCH_EXPIRE_VAL, QCH_CON_USI09_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI10_I2C_QCH, QCH_CON_USI10_I2C_QCH_ENABLE, QCH_CON_USI10_I2C_QCH_CLOCK_REQ, QCH_CON_USI10_I2C_QCH_EXPIRE_VAL, QCH_CON_USI10_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI10_USI_QCH, QCH_CON_USI10_USI_QCH_ENABLE, QCH_CON_USI10_USI_QCH_CLOCK_REQ, QCH_CON_USI10_USI_QCH_EXPIRE_VAL, QCH_CON_USI10_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI11_I2C_QCH, QCH_CON_USI11_I2C_QCH_ENABLE, QCH_CON_USI11_I2C_QCH_CLOCK_REQ, QCH_CON_USI11_I2C_QCH_EXPIRE_VAL, QCH_CON_USI11_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI11_USI_QCH, QCH_CON_USI11_USI_QCH_ENABLE, QCH_CON_USI11_USI_QCH_CLOCK_REQ, QCH_CON_USI11_USI_QCH_EXPIRE_VAL, QCH_CON_USI11_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI16_I3C_QCH_DMY, DMYQCH_CON_USI16_I3C_QCH_DMY_ENABLE, DMYQCH_CON_USI16_I3C_QCH_DMY_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_USI16_I3C_QCH_DMY_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI16_I3C_QCH_I3C, QCH_CON_USI16_I3C_QCH_I3C_ENABLE, QCH_CON_USI16_I3C_QCH_I3C_CLOCK_REQ, QCH_CON_USI16_I3C_QCH_I3C_EXPIRE_VAL, QCH_CON_USI16_I3C_QCH_I3C_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI16_USI_QCH, QCH_CON_USI16_USI_QCH_ENABLE, QCH_CON_USI16_USI_QCH_CLOCK_REQ, QCH_CON_USI16_USI_QCH_EXPIRE_VAL, QCH_CON_USI16_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI17_I2C_QCH, QCH_CON_USI17_I2C_QCH_ENABLE, QCH_CON_USI17_I2C_QCH_CLOCK_REQ, QCH_CON_USI17_I2C_QCH_EXPIRE_VAL, QCH_CON_USI17_I2C_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(USI17_USI_QCH, QCH_CON_USI17_USI_QCH_ENABLE, QCH_CON_USI17_USI_QCH_CLOCK_REQ, QCH_CON_USI17_USI_QCH_EXPIRE_VAL, QCH_CON_USI17_USI_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_PERIS_QCH, QCH_CON_D_TZPC_PERIS_QCH_ENABLE, QCH_CON_D_TZPC_PERIS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_PERIS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_PERIS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GIC_QCH, QCH_CON_GIC_QCH_ENABLE, QCH_CON_GIC_QCH_CLOCK_REQ, QCH_CON_GIC_QCH_EXPIRE_VAL, QCH_CON_GIC_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_PERIS_QCH, QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_PERIS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MCT_QCH, QCH_CON_MCT_QCH_ENABLE, QCH_CON_MCT_QCH_CLOCK_REQ, QCH_CON_MCT_QCH_EXPIRE_VAL, QCH_CON_MCT_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(OTP_CON_BIRA_QCH, QCH_CON_OTP_CON_BIRA_QCH_ENABLE, QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BIRA_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(OTP_CON_BISR_QCH, QCH_CON_OTP_CON_BISR_QCH_ENABLE, QCH_CON_OTP_CON_BISR_QCH_CLOCK_REQ, QCH_CON_OTP_CON_BISR_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_BISR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(OTP_CON_TOP_QCH, QCH_CON_OTP_CON_TOP_QCH_ENABLE, QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, QCH_CON_OTP_CON_TOP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PERIS_CMU_PERIS_QCH, QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, QCH_CON_PERIS_CMU_PERIS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_PERIS_QCH, QCH_CON_SYSREG_PERIS_QCH_ENABLE, QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_PERIS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TMU_SUB_QCH, QCH_CON_TMU_SUB_QCH_ENABLE, QCH_CON_TMU_SUB_QCH_CLOCK_REQ, QCH_CON_TMU_SUB_QCH_EXPIRE_VAL, QCH_CON_TMU_SUB_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TMU_TOP_QCH, QCH_CON_TMU_TOP_QCH_ENABLE, QCH_CON_TMU_TOP_QCH_CLOCK_REQ, QCH_CON_TMU_TOP_QCH_EXPIRE_VAL, QCH_CON_TMU_TOP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WDT_CLUSTER0_QCH, QCH_CON_WDT_CLUSTER0_QCH_ENABLE, QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WDT_CLUSTER2_QCH, QCH_CON_WDT_CLUSTER2_QCH_ENABLE, QCH_CON_WDT_CLUSTER2_QCH_CLOCK_REQ, QCH_CON_WDT_CLUSTER2_QCH_EXPIRE_VAL, QCH_CON_WDT_CLUSTER2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(S2D_CMU_S2D_QCH, QCH_CON_S2D_CMU_S2D_QCH_ENABLE, QCH_CON_S2D_CMU_S2D_QCH_CLOCK_REQ, QCH_CON_S2D_CMU_S2D_QCH_EXPIRE_VAL, QCH_CON_S2D_CMU_S2D_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BTM_VRA2_QCH, QCH_CON_BTM_VRA2_QCH_ENABLE, QCH_CON_BTM_VRA2_QCH_CLOCK_REQ, QCH_CON_BTM_VRA2_QCH_EXPIRE_VAL, QCH_CON_BTM_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_VRA2_QCH, QCH_CON_D_TZPC_VRA2_QCH_ENABLE, QCH_CON_D_TZPC_VRA2_QCH_CLOCK_REQ, QCH_CON_D_TZPC_VRA2_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_ISPLPVRA2_QCH, QCH_CON_LHM_AXI_P_ISPLPVRA2_QCH_ENABLE, QCH_CON_LHM_AXI_P_ISPLPVRA2_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_ISPLPVRA2_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_ISPLPVRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_VRA2_QCH, QCH_CON_LHS_AXI_D_VRA2_QCH_ENABLE, QCH_CON_LHS_AXI_D_VRA2_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VRA2_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_VRA2ISPLP_QCH, QCH_CON_LHS_AXI_D_VRA2ISPLP_QCH_ENABLE, QCH_CON_LHS_AXI_D_VRA2ISPLP_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VRA2ISPLP_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VRA2ISPLP_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(PPMU_VRA2_QCH, QCH_CON_PPMU_VRA2_QCH_ENABLE, QCH_CON_PPMU_VRA2_QCH_CLOCK_REQ, QCH_CON_PPMU_VRA2_QCH_EXPIRE_VAL, QCH_CON_PPMU_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(QE_VRA2_QCH, QCH_CON_QE_VRA2_QCH_ENABLE, QCH_CON_QE_VRA2_QCH_CLOCK_REQ, QCH_CON_QE_VRA2_QCH_EXPIRE_VAL, QCH_CON_QE_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(STR_QCH, QCH_CON_STR_QCH_ENABLE, QCH_CON_STR_QCH_CLOCK_REQ, QCH_CON_STR_QCH_EXPIRE_VAL, QCH_CON_STR_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSMMU_VRA2_QCH, QCH_CON_SYSMMU_VRA2_QCH_ENABLE, QCH_CON_SYSMMU_VRA2_QCH_CLOCK_REQ, QCH_CON_SYSMMU_VRA2_QCH_EXPIRE_VAL, QCH_CON_SYSMMU_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_VRA2_QCH, QCH_CON_SYSREG_VRA2_QCH_ENABLE, QCH_CON_SYSREG_VRA2_QCH_CLOCK_REQ, QCH_CON_SYSREG_VRA2_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_VRA2_QCH, QCH_CON_VGEN_LITE_VRA2_QCH_ENABLE, QCH_CON_VGEN_LITE_VRA2_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_VRA2_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VRA2_QCH, QCH_CON_VRA2_QCH_ENABLE, QCH_CON_VRA2_QCH_CLOCK_REQ, QCH_CON_VRA2_QCH_EXPIRE_VAL, QCH_CON_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VRA2_CMU_VRA2_QCH, QCH_CON_VRA2_CMU_VRA2_QCH_ENABLE, QCH_CON_VRA2_CMU_VRA2_QCH_CLOCK_REQ, QCH_CON_VRA2_CMU_VRA2_QCH_EXPIRE_VAL, QCH_CON_VRA2_CMU_VRA2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_C_VTS_QCH, QCH_CON_BAAW_C_VTS_QCH_ENABLE, QCH_CON_BAAW_C_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_C_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_C_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(BAAW_D_VTS_QCH, QCH_CON_BAAW_D_VTS_QCH_ENABLE, QCH_CON_BAAW_D_VTS_QCH_CLOCK_REQ, QCH_CON_BAAW_D_VTS_QCH_EXPIRE_VAL, QCH_CON_BAAW_D_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(CORTEXM4INTEGRATION_QCH_CPU, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_ENABLE, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_CLOCK_REQ, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_EXPIRE_VAL, QCH_CON_CORTEXM4INTEGRATION_QCH_CPU_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_AHB0_QCH_PCLK, QCH_CON_DMIC_AHB0_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB0_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB0_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB0_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_AHB1_QCH_PCLK, QCH_CON_DMIC_AHB1_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB1_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB1_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB1_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_AHB2_QCH_PCLK, QCH_CON_DMIC_AHB2_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB2_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB2_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB2_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_AHB3_QCH_PCLK, QCH_CON_DMIC_AHB3_QCH_PCLK_ENABLE, QCH_CON_DMIC_AHB3_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_AHB3_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_AHB3_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_IF_QCH_PCLK, QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_IF_QCH_DMIC_CLK, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_IF_3RD_QCH_PCLK, QCH_CON_DMIC_IF_3RD_QCH_PCLK_ENABLE, QCH_CON_DMIC_IF_3RD_QCH_PCLK_CLOCK_REQ, QCH_CON_DMIC_IF_3RD_QCH_PCLK_EXPIRE_VAL, QCH_CON_DMIC_IF_3RD_QCH_PCLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(DMIC_IF_3RD_QCH_DMIC_CLK, DMYQCH_CON_DMIC_IF_3RD_QCH_DMIC_CLK_ENABLE, DMYQCH_CON_DMIC_IF_3RD_QCH_DMIC_CLK_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_DMIC_IF_3RD_QCH_DMIC_CLK_IGNORE_FORCE_PM_EN), |
| CLK_QCH(D_TZPC_VTS_QCH, QCH_CON_D_TZPC_VTS_QCH_ENABLE, QCH_CON_D_TZPC_VTS_QCH_CLOCK_REQ, QCH_CON_D_TZPC_VTS_QCH_EXPIRE_VAL, QCH_CON_D_TZPC_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(GPIO_VTS_QCH, QCH_CON_GPIO_VTS_QCH_ENABLE, QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, QCH_CON_GPIO_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(HWACG_SYS_DMIC0_QCH, QCH_CON_HWACG_SYS_DMIC0_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC0_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC0_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC0_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(HWACG_SYS_DMIC1_QCH, QCH_CON_HWACG_SYS_DMIC1_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC1_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC1_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC1_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(HWACG_SYS_DMIC2_QCH, QCH_CON_HWACG_SYS_DMIC2_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC2_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC2_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC2_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(HWACG_SYS_DMIC3_QCH, QCH_CON_HWACG_SYS_DMIC3_QCH_ENABLE, QCH_CON_HWACG_SYS_DMIC3_QCH_CLOCK_REQ, QCH_CON_HWACG_SYS_DMIC3_QCH_EXPIRE_VAL, QCH_CON_HWACG_SYS_DMIC3_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_LP_VTS_QCH, QCH_CON_LHM_AXI_LP_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_LP_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_LP_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_LP_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHM_AXI_P_VTS_QCH, QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL, QCH_CON_LHM_AXI_P_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_C_VTS_QCH, QCH_CON_LHS_AXI_C_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_C_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_C_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_C_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(LHS_AXI_D_VTS_QCH, QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL, QCH_CON_LHS_AXI_D_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_ABOX_VTS_QCH, QCH_CON_MAILBOX_ABOX_VTS_QCH_ENABLE, QCH_CON_MAILBOX_ABOX_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_ABOX_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_ABOX_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(MAILBOX_AP_VTS_QCH, QCH_CON_MAILBOX_AP_VTS_QCH_ENABLE, QCH_CON_MAILBOX_AP_VTS_QCH_CLOCK_REQ, QCH_CON_MAILBOX_AP_VTS_QCH_EXPIRE_VAL, QCH_CON_MAILBOX_AP_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SWEEPER_C_VTS_QCH, QCH_CON_SWEEPER_C_VTS_QCH_ENABLE, QCH_CON_SWEEPER_C_VTS_QCH_CLOCK_REQ, QCH_CON_SWEEPER_C_VTS_QCH_EXPIRE_VAL, QCH_CON_SWEEPER_C_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(SYSREG_VTS_QCH, QCH_CON_SYSREG_VTS_QCH_ENABLE, QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, QCH_CON_SYSREG_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(TIMER_QCH, QCH_CON_TIMER_QCH_ENABLE, QCH_CON_TIMER_QCH_CLOCK_REQ, QCH_CON_TIMER_QCH_EXPIRE_VAL, QCH_CON_TIMER_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VGEN_LITE_QCH, QCH_CON_VGEN_LITE_QCH_ENABLE, QCH_CON_VGEN_LITE_QCH_CLOCK_REQ, QCH_CON_VGEN_LITE_QCH_EXPIRE_VAL, QCH_CON_VGEN_LITE_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(VTS_CMU_VTS_QCH, QCH_CON_VTS_CMU_VTS_QCH_ENABLE, QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, QCH_CON_VTS_CMU_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(WDT_VTS_QCH, QCH_CON_WDT_VTS_QCH_ENABLE, QCH_CON_WDT_VTS_QCH_CLOCK_REQ, QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, QCH_CON_WDT_VTS_QCH_IGNORE_FORCE_PM_EN), |
| CLK_QCH(U_DMIC_CLK_MUX_QCH, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_ENABLE, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_CLOCK_REQ, EMPTY_CAL_ID, DMYQCH_CON_U_DMIC_CLK_MUX_QCH_IGNORE_FORCE_PM_EN), |
| }; |
| |
| unsigned int cmucal_option_size = 37; |
| struct cmucal_option cmucal_option_list[] = { |
| CLK_OPTION(CTRL_OPTION_CMU_APM, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, APM_CMU_APM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_AUD, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, AUD_CMU_AUD_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_BUSC, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, BUSC_CMU_BUSC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CMGP, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMGP_CMU_CMGP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CMU, CMU_CMU_CMU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CMU_CMU_CMU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CORE, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CORE_CMU_CORE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CPUCL0, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_CPUCL0, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL0_EMBEDDED_CMU_CPUCL0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CPUCL1, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL1_CMU_CPUCL1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_CPUCL2, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL2_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_CPUCL2, CPUCL2_EMBEDDED_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, CPUCL2_EMBEDDED_CMU_CPUCL2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_DPU, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DPU_CMU_DPU_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_DSPM, DSPM_CMU_DSPM_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSPM_CMU_DSPM_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_DSPS, DSPS_CMU_DSPS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, DSPS_CMU_DSPS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_FSYS0, FSYS0_CMU_FSYS0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, FSYS0_CMU_FSYS0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_FSYS0A, FSYS0A_CMU_FSYS0A_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, FSYS0A_CMU_FSYS0A_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_FSYS1, FSYS1_CMU_FSYS1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, FSYS1_CMU_FSYS1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_G2D, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G2D_CMU_G2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_G3D, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_EMBEDDED_CMU_G3D, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, G3D_EMBEDDED_CMU_G3D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_ISPHQ, ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISPHQ_CMU_ISPHQ_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_ISPLP, ISPLP_CMU_ISPLP_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISPLP_CMU_ISPLP_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_ISPPRE, ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, ISPPRE_CMU_ISPPRE_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_IVA, IVA_CMU_IVA_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, IVA_CMU_IVA_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_MFC, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MFC_CMU_MFC_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_MIF, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF_CMU_MIF_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_MIF1, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF1_CMU_MIF1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_MIF2, MIF2_CMU_MIF2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF2_CMU_MIF2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_MIF3, MIF3_CMU_MIF3_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, MIF3_CMU_MIF3_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_NPU0, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU0_CMU_NPU0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_NPU1, NPU1_CMU_NPU1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, NPU1_CMU_NPU1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_PERIC0, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC0_CMU_PERIC0_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_PERIC1, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIC1_CMU_PERIC1_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_PERIS, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, PERIS_CMU_PERIS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_S2D, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, S2D_CMU_S2D_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_VRA2, VRA2_CMU_VRA2_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VRA2_CMU_VRA2_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| CLK_OPTION(CTRL_OPTION_CMU_VTS, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_POWER_MANAGEMENT, VTS_CMU_VTS_CONTROLLER_OPTION_ENABLE_AUTOMATIC_CLKGATING), |
| }; |