drivers/soc/samsung/cal-if/exynos9820/cmucal-node.h

#ifndef __CMUCAL_NODE_H__
#define __CMUCAL_NODE_H__

#include "../cmucal.h"

enum clk_id {
	OSCCLK_RCO_APM = FIXED_RATE_TYPE,
	CLK_DLL_DCO,
	OSCCLK_APM,
	CLK_RCO_APM,
	OSCCLK_AUD,
	CLKIO_AUD_UAIF0,
	CLKIO_AUD_UAIF1,
	CLKIO_AUD_UAIF2,
	CLKIO_AUD_UAIF3,
	CLKIO_AUD_DSIF,
	OSCCLK_BUSC,
	OSCCLK_CMGP,
	OSCCLK_RCO_CMGP,
	OSCCLK_CMU,
	OSCCLK_CORE,
	OSCCLK_CPUCL0,
	OSCCLK_CPUCL1,
	OSCCLK_CPUCL2,
	OSCCLK_DPU,
	OSCCLK_DSPM,
	OSCCLK_DSPS,
	OSCCLK_FSYS0,
	OSCCLK_FSYS0A,
	OSCCLK_FSYS1,
	OSCCLK_G2D,
	OSCCLK_G3D,
	OSCCLK_EMBEDDED_G3D,
	OSCCLK_ISPHQ,
	OSCCLK_ISPLP,
	OSCCLK_ISPPRE,
	OSCCLK_IVA,
	OSCCLK_MFC,
	OSCCLK_MIF,
	OSCCLK_MIF1,
	OSCCLK_MIF2,
	OSCCLK_MIF3,
	OSCCLK_NPU0,
	OSCCLK_NPU1,
	OSCCLK_PERIC0,
	OSCCLK_PERIC1,
	OSCCLK_PERIS,
	OSCCLK_S2D,
	OSCCLK_VRA2,
	OSCCLK_RCO_VTS,
	CLK_RCO_VTS,
	end_of_fixed_rate,
	num_of_fixed_rate = (end_of_fixed_rate - FIXED_RATE_TYPE) & MASK_OF_ID,

	CLKCMU_FSYS1_PCIE = FIXED_FACTOR_TYPE,
	CLKCMU_OTP,
	CLKCMU_FSYS0A_USBDP_DEBUG,
	CLKCMU_FSYS0_PCIE,
	CLK_MIF_BUSD,
	CLK_MIF1_BUSD,
	CLK_MIF2_BUSD,
	CLK_MIF3_BUSD,
	CLK_MIF_BUSD_S2D,
	end_of_fixed_factor,
	num_of_fixed_factor = (end_of_fixed_factor - FIXED_FACTOR_TYPE) & MASK_OF_ID,

	PLL_AUD0 = PLL_TYPE,
	PLL_AUD1,
	PLL_SHARED1,
	PLL_SHARED4,
	PLL_SHARED3,
	PLL_SHARED2,
	PLL_SHARED0,
	APLL_SHARED1,
	PLL_G3D,
	APLL_SHARED0,
	PLL_CPUCL0,
	APLL_CPUCL0,
	PLL_CPUCL1,
	PLL_CPUCL2,
	PLL_MMC,
	PLL_MIF,
	PLL_MIF1,
	PLL_MIF2,
	PLL_MIF3,
	PLL_MIF_S2D,
	end_of_pll,
	num_of_pll = (end_of_pll - PLL_TYPE) & MASK_OF_ID,

	MUX_CLKCMU_CMGP_BUS = MUX_TYPE,
	MUX_CLK_APM_BUS,
	MUX_CLKCMU_VTS_BUS,
	MUX_CLK_AUD_UAIF3,
	MUX_CLK_AUD_UAIF2,
	MUX_CLK_AUD_UAIF1,
	MUX_CLK_AUD_UAIF0,
	MUX_CLK_AUD_CPU,
	MUX_CLK_AUD_DSIF,
	MUX_BUC_CMUREF,
	MUX_CLK_I2C_CMGP0,
	MUX_CLK_USI_CMGP0,
	MUX_CLK_USI_CMGP1,
	MUX_CLK_USI_CMGP2,
	MUX_CLK_USI_CMGP3,
	MUX_CLK_CMGP_ADC,
	MUX_CLK_I2C_CMGP1,
	MUX_CLK_I2C_CMGP2,
	MUX_CLK_I2C_CMGP3,
	MUX_CLKCMU_MFC_MFC,
	MUX_CLKCMU_FSYS0A_USB31DRD,
	MUX_CLKCMU_FSYS1_UFS_EMBD,
	MUX_CLKCMU_BUSC_BUS,
	MUX_CLKCMU_G2D_G2D,
	MUX_CLKCMU_DSPM_BUS,
	MUX_CLKCMU_CPUCL0_SWITCH,
	MUX_CLKCMU_CORE_BUS,
	MUX_CLKCMU_MIF_SWITCH,
	MUX_CLKCMU_ISPPRE_BUS,
	MUX_CLKCMU_ISPLP_BUS,
	MUX_CLKCMU_ISPHQ_BUS,
	MUX_CLKCMU_AUD_CPU,
	MUX_CLKCMU_G2D_MSCL,
	MUX_CLKCMU_HPM,
	MUX_CLKCMU_CPUCL0_DBG_BUS,
	MUX_CLKCMU_FSYS0_BUS,
	MUX_CLKCMU_CIS_CLK0,
	MUX_CLKCMU_CIS_CLK1,
	MUX_CLKCMU_CIS_CLK2,
	MUX_CLKCMU_CIS_CLK3,
	MUX_CLKCMU_IVA_BUS,
	MUX_CLKCMU_FSYS1_UFS_CARD,
	MUX_CMU_CMUREF,
	MUX_CLKCMU_PERIC0_BUS,
	MUX_CLKCMU_PERIC1_BUS,
	MUX_CLKCMU_PERIS_BUS,
	MUX_CLKCMU_FSYS0_DPGTC,
	MUX_CLKCMU_FSYS1_PCIE,
	MUX_CLKCMU_NPU0_BUS,
	MUX_CLKCMU_APM_BUS,
	MUX_CLKCMU_FSYS1_BUS,
	MUX_CLKCMU_CPUCL2_SWITCH,
	MUX_CLKCMU_MFC_WFD,
	MUX_CLKCMU_MIF_BUSP,
	MUX_CLKCMU_PERIC0_IP,
	MUX_CLKCMU_PERIC1_IP,
	MUX_CLKCMU_NPU1_BUS,
	MUX_CLKCMU_FSYS0A_USBDP_DEBUG,
	MUX_CLKCMU_ISPLP_GDC,
	MUX_CLKCMU_DSPS_AUD,
	CLKCMU_DPU_BUS,
	MUX_CLKCMU_DPU_BUS,
	MUX_CLKCMU_CPUCL1_SWITCH,
	MUX_CLKCMU_FSYS0_PCIE,
	MUX_CLKCMU_FSYS0A_BUS,
	MUX_PLL_SHARED1,
	MUX_CLKCMU_DSPM_BUS_OTF,
	MUX_CLK_CMU_CMUREF,
	MUX_CLKCMU_VRA2_BUS,
	MUX_CLKCMU_CIS_CLK4,
	MUX_CLKCMU_DPU,
	MUX_CLKCMU_FSYS1_MMC_CARD,
	MUX_CLKCMU_NPU0_CPU,
	MUX_CLKCMU_CMU_BOOST,
	MUX_PLL_SHARED0,
	MUX_CLKCMU_VRA2_STR,
	MUX_CORE_CMUREF,
	MUX_CLK_CPUCL0_PLL,
	MUX_CPUCL0_CMUREF,
	MUX_PLL_CPUCL0,
	MUX_CLK_CPUCL1_PLL,
	MUX_CPUCL1_CMUREF,
	MUX_CLK_CPUCL2_PLL,
	MUX_CPUCL2_CMUREF,
	MUX_CLK_DSPS_BUS,
	MUX_CLK_FSYS1_MMC_CARD,
	MUX_CLK_FSYS1_BUS,
	MUX_CLK_G3D_BUSD,
	MUX_MIF_CMUREF,
	CLKMUX_MIF_DDRPHY2X,
	MUX_MIF1_CMUREF,
	CLKMUX_MIF1_DDRPHY2X,
	MUX_MIF2_CMUREF,
	CLKMUX_MIF2_DDRPHY2X,
	MUX_MIF3_CMUREF,
	CLKMUX_MIF3_DDRPHY2X,
	CLKCMU_MIF_DDRPHY2X_S2D,
	MUX_CLK_S2D_CORE,
	MUX_CLK_VTS_BUS,
	APM_CMU_APM_CLKOUT0,
	APM_CMU_APM_CLKOUT1,
	AUD_CMU_AUD_CLKOUT0,
	AUD_CMU_AUD_CLKOUT1,
	BUSC_CMU_BUSC_CLKOUT0,
	BUSC_CMU_BUSC_CLKOUT1,
	CMGP_CMU_CMGP_CLKOUT0,
	CMGP_CMU_CMGP_CLKOUT1,
	CMU_CMU_CMU_CLKOUT0,
	CMU_CMU_CMU_CLKOUT1,
	CORE_CMU_CORE_CLKOUT0,
	CORE_CMU_CORE_CLKOUT1,
	CPUCL0_CMU_CPUCL0_CLKOUT0,
	CPUCL0_CMU_CPUCL0_CLKOUT1,
	CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT0,
	CPUCL0_EMBEDDED_CMU_CPUCL0_CLKOUT1,
	CPUCL1_CMU_CPUCL1_CLKOUT0,
	CPUCL1_CMU_CPUCL1_CLKOUT1,
	CPUCL2_CMU_CPUCL2_CLKOUT0,
	CPUCL2_CMU_CPUCL2_CLKOUT1,
	CPUCL2_EMBEDDED_CMU_CPUCL2_CLKOUT0,
	CPUCL2_EMBEDDED_CMU_CPUCL2_CLKOUT1,
	DPU_CMU_DPU_CLKOUT0,
	DPU_CMU_DPU_CLKOUT1,
	DSPM_CMU_DSPM_CLKOUT0,
	DSPM_CMU_DSPM_CLKOUT1,
	DSPS_CMU_DSPS_CLKOUT0,
	DSPS_CMU_DSPS_CLKOUT1,
	FSYS0_CMU_FSYS0_CLKOUT0,
	FSYS0_CMU_FSYS0_CLKOUT1,
	FSYS0A_CMU_FSYS0A_CLKOUT0,
	FSYS0A_CMU_FSYS0A_CLKOUT1,
	FSYS1_CMU_FSYS1_CLKOUT0,
	FSYS1_CMU_FSYS1_CLKOUT1,
	G2D_CMU_G2D_CLKOUT0,
	G2D_CMU_G2D_CLKOUT1,
	G3D_CMU_G3D_CLKOUT0,
	G3D_CMU_G3D_CLKOUT1,
	G3D_EMBEDDED_CMU_G3D_CLKOUT0,
	G3D_EMBEDDED_CMU_G3D_CLKOUT1,
	ISPHQ_CMU_ISPHQ_CLKOUT0,
	ISPHQ_CMU_ISPHQ_CLKOUT1,
	ISPLP_CMU_ISPLP_CLKOUT0,
	ISPLP_CMU_ISPLP_CLKOUT1,
	ISPPRE_CMU_ISPPRE_CLKOUT0,
	ISPPRE_CMU_ISPPRE_CLKOUT1,
	IVA_CMU_IVA_CLKOUT0,
	IVA_CMU_IVA_CLKOUT1,
	MFC_CMU_MFC_CLKOUT0,
	MFC_CMU_MFC_CLKOUT1,
	MIF_CMU_MIF_CLKOUT0,
	MIF_CMU_MIF_CLKOUT1,
	MIF1_CMU_MIF1_CLKOUT0,
	MIF1_CMU_MIF1_CLKOUT1,
	MIF2_CMU_MIF2_CLKOUT0,
	MIF2_CMU_MIF2_CLKOUT1,
	MIF3_CMU_MIF3_CLKOUT0,
	MIF3_CMU_MIF3_CLKOUT1,
	NPU0_CMU_NPU0_CLKOUT0,
	NPU0_CMU_NPU0_CLKOUT1,
	NPU1_CMU_NPU1_CLKOUT0,
	NPU1_CMU_NPU1_CLKOUT1,
	PERIC0_CMU_PERIC0_CLKOUT0,
	PERIC0_CMU_PERIC0_CLKOUT1,
	PERIC1_CMU_PERIC1_CLKOUT0,
	PERIC1_CMU_PERIC1_CLKOUT1,
	PERIS_CMU_PERIS_CLKOUT0,
	PERIS_CMU_PERIS_CLKOUT1,
	VRA2_CMU_VRA2_CLKOUT0,
	VRA2_CMU_VRA2_CLKOUT1,
	VTS_CMU_VTS_CLKOUT0,
	VTS_CMU_VTS_CLKOUT1,
	MUX_CLKCMU_APM_BUS_USER = ((MASK_OF_ID & VTS_CMU_VTS_CLKOUT1) | USER_MUX_TYPE) + 1,
	MUX_DLL_USER,
	MUX_CLKMUX_APM_RCO_USER,
	MUX_CLKCMU_AUD_CPU_USER,
	MUX_CLKCMU_BUSC_BUS_USER,
	MUX_CLKCMU_CMGP_BUS_USER,
	MUX_CLKCMU_CORE_BUS_USER,
	MUX_CLKCMU_CPUCL0_SWITCH_USER,
	MUX_CLKCMU_CPUCL0_DBG_BUS_USER,
	MUX_CLKCMU_CPUCL1_SWITCH_USER,
	MUX_CLKCMU_CPUCL2_SWITCH_USER,
	MUX_CLKCMU_DPU_BUS_USER,
	MUX_CLKCMU_DSPM_BUS_USER,
	MUX_CLKCMU_DSPM_BUS_OTF_USER,
	MUX_CLKCMU_DSPS_BUS_USER,
	MUX_CLKCMU_DSPS_AUD_USER,
	MUX_CLKCMU_FSYS0_BUS_USER,
	MUX_CLKCMU_FSYS0_DPGTC_USER,
	MUX_CLKCMU_FSYS0_PCIE_USER,
	MUX_CLKCMU_FSYS0A_BUS_USER,
	MUX_CLKCMU_FSYS0A_USB31DRD_USER,
	MUX_CLKCMU_FSYS0A_USBDP_DEBUG_USER,
	MUX_CLKCMU_FSYS1_BUS_USER,
	MUX_CLKCMU_FSYS1_MMC_CARD_USER,
	MUX_CLKCMU_FSYS1_PCIE_USER,
	MUX_CLKCMU_FSYS1_UFS_CARD_USER,
	MUX_CLKCMU_FSYS1_UFS_EMBD_USER,
	MUX_CLKCMU_G2D_G2D_USER,
	MUX_CLKCMU_G2D_MSCL_USER,
	MUX_CLKCMU_G3D_SWITCH_USER,
	MUX_CLKCMU_EMBEDDED_G3D_USER,
	MUX_CLKCMU_G3D_BUS_USER,
	MUX_CLKCMU_ISPHQ_BUS_USER,
	MUX_CLKCMU_ISPLP_BUS_USER,
	MUX_CLKCMU_ISPLP_GDC_USER,
	MUX_CLKCMU_ISPPRE_BUS_USER,
	MUX_CLKCMU_IVA_BUS_USER,
	MUX_CLKCMU_MFC_MFC_USER,
	MUX_CLKCMU_MFC_WFD_USER,
	MUX_CLKCMU_MIF_BUSP_USER,
	MUX_CLKCMU_MIF1_BUSP_USER,
	MUX_CLKCMU_MIF2_BUSP_USER,
	MUX_CLKCMU_MIF3_BUSP_USER,
	MUX_CLKCMU_NPU0_BUS_USER,
	MUX_CLKCMU_NPU0_CPU_USER,
	MUX_CLKCMU_NPU1_BUS_USER,
	MUX_CLKCMU_PERIC0_BUS_USER,
	MUX_CLKCMU_PERIC0_USI00_USI_USER,
	MUX_CLKCMU_PERIC0_USI01_USI_USER,
	MUX_CLKCMU_PERIC0_USI02_USI_USER,
	MUX_CLKCMU_PERIC0_USI03_USI_USER,
	MUX_CLKCMU_PERIC0_USI04_USI_USER,
	MUX_CLKCMU_PERIC0_USI05_USI_USER,
	MUX_CLKCMU_PERIC0_USI_I2C_USER,
	MUX_CLKCMU_PERIC0_UART_DBG,
	MUX_CLKCMU_PERIC0_USI12_USI_USER,
	MUX_CLKCMU_PERIC0_USE13_USI_USER,
	MUX_CLKCMU_PERIC0_USI14_USI_USER,
	MUX_CLKCMU_PERIC0_USI15_USI_USER,
	MUX_CLKCMU_PERIC1_BUS_USER,
	MUX_CLKCMU_PERIC1_UART_BT_USER,
	MUX_CLKCMU_PERIC1_USI_I2C_USER,
	MUX_CLKCMU_PERIC1_USI06_USI_USER,
	MUX_CLKCMU_PERIC1_USI07_USI_USER,
	MUX_CLKCMU_PERIC1_USI08_USI_USER,
	MUX_CLKCMU_PERIC1_USI09_USI_USER,
	MUX_CLKCMU_PERIC1_USI10_USI_USER,
	MUX_CLKCMU_PERIC1_USI11_USI_USER,
	MUX_CLKCMU_PERIC1_SPI_CAM0_USER,
	MUX_CLKCMU_PERIC1_I2C_CAM0_USER,
	MUX_CLKCMU_PERIC1_I2C_CAM1_USER,
	MUX_CLKCMU_PERIC1_I2C_CAM2_USER,
	MUX_CLKCMU_PERIC1_I2C_CAM3_USER,
	MUX_CLKCMU_PERIC1_USI16_USI_USER,
	MUX_CLKCMU_PERIC1_USI17_USI_USER,
	MUX_CLKCMU_PERIS_BUS_USER,
	MUX_CLKCMU_VRA2_BUS_USER,
	MUX_CLKCMU_VRA2_STR_USER,
	MUX_CLKCMU_VTS_BUS_USER,
	MUX_CLKCMU_VTS_RCO_USER,
	MUX_HCHGEN_CLK_AUD_CPU = ((MASK_OF_ID & MUX_CLKCMU_VTS_RCO_USER) | CONST_MUX_TYPE) + 1,
	MUX_CLK_PERIS_GIC,
	end_of_mux,
	num_of_mux = (end_of_mux - MUX_TYPE) & MASK_OF_ID,

	CLKCMU_VTS_BUS = DIV_TYPE,
	DIV_CLK_APM_BUS,
	CLKCMU_CMGP_BUS,
	DIV_CLK_AUD_PLL,
	DIV_CLK_AUD_AUDIF,
	DIV_CLK_AUD_CPU_ATCLK,
	DIV_CLK_AUD_CPU_PCLKDBG,
	DIV_CLK_AUD_DSIF,
	DIV_CLK_AUD_UAIF0,
	DIV_CLK_AUD_UAIF1,
	DIV_CLK_AUD_UAIF2,
	DIV_CLK_AUD_UAIF3,
	DIV_CLK_AUD_CPU_ACLK,
	DIV_CLK_AUD_BUS,
	DIV_CLK_AUD_BUSP,
	DIV_CLK_AUD_DMIC,
	DIV_CLK_AUD_CNT,
	DIV_CLK_AUD_MCLK,
	DIV_CLK_BUSC_BUSP,
	DIV_CLK_I2C_CMGP0,
	DIV_CLK_USI_CMGP1,
	DIV_CLK_USI_CMGP0,
	DIV_CLK_USI_CMGP2,
	DIV_CLK_USI_CMGP3,
	DIV_CLK_CMGP_ADC,
	DIV_CLK_I2C_CMGP1,
	DIV_CLK_I2C_CMGP2,
	DIV_CLK_I2C_CMGP3,
	DIV_CLK_CMGP_BUS,
	CLKCMU_APM_BUS,
	PLL_SHARED0_DIV2,
	CLKCMU_G3D_SWITCH,
	CLKCMU_PERIC0_BUS,
	CLKCMU_PERIS_BUS,
	CLKCMU_FSYS0_BUS,
	DIV_CLKCMU_DPU_BUS,
	PLL_SHARED1_DIV2,
	PLL_SHARED2_DIV2,
	PLL_SHARED3_DIV2,
	PLL_SHARED4_DIV2,
	PLL_SHARED0_DIV4,
	CLKCMU_MFC_MFC,
	CLKCMU_G2D_G2D,
	CLKCMU_FSYS0A_USB31DRD,
	CLKCMU_FSYS1_UFS_EMBD,
	CLKCMU_DSPM_BUS,
	CLKCMU_PERIC1_BUS,
	CLKCMU_BUSC_BUS,
	CLKCMU_CPUCL2_SWITCH,
	CLKCMU_CPUCL0_SWITCH,
	CLKCMU_CORE_BUS,
	CLKCMU_ISPPRE_BUS,
	CLKCMU_ISPLP_BUS,
	CLKCMU_ISPHQ_BUS,
	CLKCMU_AUD_CPU,
	CLKCMU_G2D_MSCL,
	CLKCMU_HPM,
	CLKCMU_CPUCL0_DBG_BUS,
	CLKCMU_CIS_CLK0,
	CLKCMU_CIS_CLK1,
	CLKCMU_CIS_CLK2,
	CLKCMU_CIS_CLK3,
	CLKCMU_IVA_BUS,
	CLKCMU_FSYS1_UFS_CARD,
	PLL_SHARED1_DIV4,
	CLKCMU_FSYS0_DPGTC,
	DIV_CLK_CMU_CMUREF,
	CLKCMU_NPU0_BUS,
	CLKCMU_MFC_WFD,
	CLKCMU_MIF_BUSP,
	CLKCMU_PERIC0_IP,
	CLKCMU_PERIC1_IP,
	CLKCMU_NPU1_BUS,
	CLKCMU_ISPLP_GDC,
	CLKCMU_DSPS_AUD,
	PLL_SHARED1_DIV3,
	PLL_SHARED0_DIV3,
	DIV_CLKCMU_DPU,
	CLKCMU_CPUCL1_SWITCH,
	CLKCMU_FSYS0A_BUS,
	CLKCMU_DSPM_BUS_OTF,
	CLKCMU_VRA2_BUS,
	CLKCMU_CIS_CLK4,
	CLKCMU_CMU_BOOST,
	CLKCMU_VRA2_STR,
	DIV_CLK_CORE_BUSP,
	DIV_CLK_CPUCL0_CMUREF,
	DIV_CLK_CLUSTER0_ACLK,
	DIV_CLK_CLUSTER0_ATCLK,
	DIV_CLK_CLUSTER0_PCLKDBG,
	DIV_CLK_CLUSTER0_PERIPHCLK,
	DIV_CLK_CPUCL0_DBG_PCLKDBG,
	DIV_CLK_CPUCL0_PCLK,
	DIV_CLK_CPUCL0_DBG_BUS,
	DIV_CLK_CPUCL1_CMUREF,
	DIV_CLK_CPUCL2_CMUREF,
	DIV_CLK_CPUCL2_PCLK,
	DIV_CLK_CLUSTER2_ACLK,
	DIV_CLK_CLUSTER2_ATCLK,
	DIV_CLK_CPUCL2_PCLKDBG,
	DIV_CLK_CLUSTER2_AMCLK,
	DIV_CLK_DPU_BUSP,
	DIV_CLK_DSPM_BUSP,
	DIV_CLK_DSPS_BUSP,
	DIV_CLK_FSYS1_MMC_CARD,
	DIV_CLK_FSYS1_BUS,
	DIV_CLK_G2D_BUSP,
	DIV_CLK_G3D_BUSP,
	DIV_CLK_ISPHQ_BUSP,
	DIV_CLK_ISPLP_BUSP,
	DIV_CLK_ISPPRE_BUSP,
	DIV_CLK_IVA_BUSP,
	DIV_CLK_IVA_DEBUG,
	DIV_CLK_MFC_BUSP,
	DIV_CLK_MIF_PRE,
	DIV_CLK_MIF1_PRE,
	DIV_CLK_MIF2_PRE,
	DIV_CLK_MIF3_PRE,
	DIV_CLK_NPU0_BUSP,
	DIV_CLK_NPU0_CPU,
	DIV_CLK_NPU1_BUSP,
	DIV_CLK_PERIC0_USI00_USI,
	DIV_CLK_PERIC0_USI01_USI,
	DIV_CLK_PERIC0_USI02_USI,
	DIV_CLK_PERIC0_USI03_USI,
	DIV_CLK_PERIC0_USI04_USI,
	DIV_CLK_PERIC0_USI05_USI,
	DIV_CLK_PERIC0_USI_I2C,
	DIV_CLK_PERIC0_UART_DBG,
	DIV_CLK_PERIC0_USI12_USI,
	DIV_CLK_PERIC0_USI13_USI,
	DIV_CLK_PERIC0_USI14_USI,
	DIV_CLK_PERIC0_USI15_USI,
	DIV_CLK_PERIC1_UART_BT,
	DIV_CLK_PERIC1_USI_I2C,
	DIV_CLK_PERIC1_USI06_USI,
	DIV_CLK_PERIC1_USI07_USI,
	DIV_CLK_PERIC1_USI08_USI,
	DIV_CLK_PERIC1_I2C_CAM0,
	DIV_CLK_PERIC1_I2C_CAM1,
	DIV_CLK_PERIC1_I2C_CAM2,
	DIV_CLK_PERIC1_I2C_CAM3,
	DIV_CLK_PERIC1_SPI_CAM0,
	DIV_CLK_PERIC1_USI09_USI,
	DIV_CLK_PERIC1_USI10_USI,
	DIV_CLK_PERIC1_USI11_USI,
	DIV_CLK_PERIC1_USI16_USI,
	DIV_CLK_PERIC1_USI17_USI,
	DIV_CLK_VRA2_BUSP,
	DIV_CLK_VTS_DMIC_IF,
	DIV_CLK_VTS_DMIC,
	DIV_CLK_VTS_DMIC_DIV2,
	DIV_CLK_VTS_BUS,
	DIV_CLK_CPUCL0_CPU = ((MASK_OF_ID & DIV_CLK_VTS_BUS) | CONST_DIV_TYPE) + 1,
	DIV_CLK_CPUCL1_CPU,
	DIV_CLK_CPUCL2_CPU,
	DIV_CLK_G3D_BUSD,
	end_of_div,
	num_of_div = (end_of_div - DIV_TYPE) & MASK_OF_ID,

	GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK = GATE_TYPE,
	GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
	CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_RCO_IPCLKPORT_CLK,
	GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
	GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
	GATE_CLKCMU_VTS_BUS,
	GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
	GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_LHM_AXI_C_MODEM_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_PEM_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
	CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_VGEN_LITE_APM_IPCLKPORT_CLK,
	CLK_BLK_APM_UID_RSTNSYNC_CLK_APM_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
	GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_APBIF_TOP_RTC_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_MAILBOX_AP_CP_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_MAILBOX_AP_CP_S_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_GREBEINTEGRATION_DBGCORE_IPCLKPORT_HCLK,
	GOUT_BLK_APM_UID_DTZPC_APM_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_LHM_AXI_C_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_MAILBOX_APM_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_LHS_AXI_LP_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_MAILBOX_APM_CP_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
	GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
	GOUT_BLK_APM_UID_LHS_AXI_C_CMGP_IPCLKPORT_I_CLK,
	GATE_CLKCMU_CMGP_BUS,
	GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
	CLK_BLK_AUD_UID_AUD_CMU_AUD_IPCLKPORT_PCLK,
	GOUT_BLK_AUD_UID_LHS_AXI_D_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_ACLK,
	GOUT_BLK_AUD_UID_PPMU_AUD_IPCLKPORT_PCLK,
	GOUT_BLK_AUD_UID_SYSREG_AUD_IPCLKPORT_PCLK,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF0,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF1,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF3,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_DSIF,
	GOUT_BLK_AUD_UID_LHS_ATB_T0_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_AUD_UID_GPIO_AUD_IPCLKPORT_PCLK,
	GOUT_BLK_AUD_UID_AXI_US_32TO128_IPCLKPORT_ACLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUS_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ATCLK_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_PCLKDBG_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_DSIF_IPCLKPORT_CLK,
	CLK_BLK_AUD_UID_RSTNSYNC_CLK_AUD_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF0_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF1_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF2_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_UAIF3_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_BTM_AUD_IPCLKPORT_I_ACLK,
	GOUT_BLK_AUD_UID_BTM_AUD_IPCLKPORT_I_PCLK,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_ASB,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_ACLK_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_UAIF2,
	GOUT_BLK_AUD_UID_LHM_AXI_P_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_PERI_AXI_ASB_IPCLKPORT_PCLK,
	GOUT_BLK_AUD_UID_WDT_AUD_IPCLKPORT_PCLK,
	CLK_BLK_AUD_UID_DMIC_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_TREX_AUD_IPCLKPORT_CLK,
	CLK_BLK_AUD_UID_DFTMUX_AUD_IPCLKPORT_AUD_CODEC_MCLK,
	GOUT_BLK_AUD_UID_SMMU_AUD_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_WRAP2_CONV_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CPU_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_XIU_P_AUD_IPCLKPORT_ACLK,
	GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKS,
	GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_IPCLKPORT_PCLKM,
	GOUT_BLK_AUD_UID_AXI2APB_AUD_IPCLKPORT_ACLK,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_CA32,
	GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKS,
	GOUT_BLK_AUD_UID_AD_APB_SMMU_AUD_S_IPCLKPORT_PCLKM,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_CCLK_DAP,
	GOUT_BLK_AUD_UID_LHS_ATB_T1_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_AUD_UID_VGEN_LITE_AUD_IPCLKPORT_CLK,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_ACLK_IRQ,
	GOUT_BLK_AUD_UID_ABOX_IPCLKPORT_BCLK_CNT,
	GOUT_BLK_AUD_UID_RSTNSYNC_CLK_AUD_CNT_IPCLKPORT_CLK,
	CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_TREX_D0_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK,
	GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D_NPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D0_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_APM_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D1_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_SIREX_IPCLKPORT_I_PCLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D0_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_ACEL_D1_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_TREX_RB_BUSC_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_TREX_RB_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_PPFW_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_WRAP2_CONV_BUSC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_VGEN_PDMA0_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_VGEN_LITE_BUSC_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_TREX_D0_BUSC_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC,
	GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC,
	CLK_BLK_BUSC_UID_HPM_BUSC_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_BUSC_UID_BUSIF_HPMBUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_SBIC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_SIREX_IPCLKPORT_I_ACLK,
	GOUT_BLK_BUSC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
	GOUT_BLK_BUSC_UID_AD_APB_DIT_IPCLKPORT_PCLKS,
	GOUT_BLK_BUSC_UID_DIT_IPCLKPORT_ICLKL2A,
	GOUT_BLK_BUSC_UID_D_TZPC_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_NPU_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_MMCACHE_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_MMCACHE_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_MMCACHE_IPCLKPORT_PCLK_SECURE,
	GOUT_BLK_BUSC_UID_MMCACHE_IPCLKPORT_PCLK_PPFW,
	GOUT_BLK_BUSC_UID_TREX_D1_BUSC_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_TREX_D1_BUSC_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_DBG_G_BUSC_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_BUSC_UID_QE_SPDMA_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_QE_SPDMA_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_QE_PDMA0_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_QE_PDMA0_IPCLKPORT_PCLK,
	GOUT_BLK_BUSC_UID_XIU_D_BUSC_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_BAAW_P_VTS_IPCLKPORT_I_PCLK,
	GOUT_BLK_BUSC_UID_AXI_US_64TO128_IPCLKPORT_ACLK,
	GOUT_BLK_BUSC_UID_BAAW_P_NPU_IPCLKPORT_I_PCLK,
	GOUT_BLK_BUSC_UID_LHM_AXI_D_VRA2_IPCLKPORT_I_CLK,
	CLK_BLK_CMGP_UID_CMGP_CMU_CMGP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S0,
	GOUT_BLK_CMGP_UID_ADC_CMGP_IPCLKPORT_PCLK_S1,
	GOUT_BLK_CMGP_UID_GPIO_CMGP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_SYSREG_CMGP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_OSCCLK_RCO_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C0_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_BUS_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI0_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI1_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI2_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_USI3_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_SYSREG_CMGP2CP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP0_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP0_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP2_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP3_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_USI_CMGP1_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_SYSREG_CMGP2PMU_AP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_DTZPC_CMGP_IPCLKPORT_PCLK,
	GOUT_BLK_CMGP_UID_LHM_AXI_C_CMGP_IPCLKPORT_I_CLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP1_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP3_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_I2C_CMGP2_IPCLKPORT_IPCLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C1_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C2_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_RSTNSYNC_CLK_CMGP_I2C3_IPCLKPORT_CLK,
	GOUT_BLK_CMGP_UID_SYSREG_CMGP2APM_IPCLKPORT_PCLK,
	GATE_CLKCMU_APM_BUS,
	GATE_CLKCMU_FSYS0_BUS,
	CLKCMU_MIF_SWITCH,
	GATE_CLKCMU_MFC_MFC,
	GATE_CLKCMU_G2D_G2D,
	GATE_CLKCMU_FSYS0A_USB31DRD,
	GATE_CLKCMU_FSYS1_UFS_EMBD,
	CLKCMU_FSYS1_BUS,
	CLKCMU_FSYS1_MMC_CARD,
	GATE_CLKCMU_DPU_BUS,
	GATE_CLKCMU_G3D_SWITCH,
	GATE_CLKCMU_PERIS_BUS,
	GATE_CLKCMU_DSPM_BUS,
	GATE_CLKCMU_PERIC0_BUS,
	GATE_CLKCMU_PERIC1_BUS,
	GATE_CLKCMU_BUSC_BUS,
	GATE_CLKCMU_CPUCL2_SWITCH,
	GATE_CLKCMU_CPUCL0_SWITCH,
	GATE_CLKCMU_CORE_BUS,
	GATE_CLKCMU_ISPPRE_BUS,
	GATE_CLKCMU_ISPLP_BUS,
	GATE_CLKCMU_ISPHQ_BUS,
	GATE_CLKCMU_AUD_CPU,
	GATE_CLKCMU_G2D_MSCL,
	GATE_CLKCMU_HPM,
	GATE_CLKCMU_FSYS1_PCIE,
	GATE_CLKCMU_CPUCL0_DBG_BUS,
	GATE_CLKCMU_CIS_CLK0,
	GATE_CLKCMU_CIS_CLK1,
	GATE_CLKCMU_CIS_CLK3,
	GATE_CLKCMU_CIS_CLK2,
	GATE_CLKCMU_IVA_BUS,
	GATE_CLKCMU_FSYS1_UFS_CARD,
	GATE_CLKCMU_FSYS0_DPGTC,
	CLKCMU_MODEM_SHARED0,
	CLKCMU_MODEM_SHARED1,
	GATE_CLKCMU_NPU0_BUS,
	GATE_CLKCMU_MFC_WFD,
	GATE_CLKCMU_MIF_BUSP,
	GATE_CLKCMU_PERIC0_IP,
	GATE_CLKCMU_PERIC1_IP,
	GATE_CLKCMU_NPU1_BUS,
	GATE_CLKCMU_FSYS0A_USBDP_DEBUG,
	GATE_CLKCMU_ISPLP_GDC,
	GATE_CLKCMU_DSPS_AUD,
	GATE_CLKCMU_DPU,
	GATE_CLKCMU_CPUCL1_SWITCH,
	GATE_CLKCMU_FSYS0_PCIE,
	GATE_CLKCMU_FSYS0A_BUS,
	GATE_CLKCMU_BUS_OTF,
	GATE_CLKCMU_VRA2_BUS,
	GATE_CLKCMU_CIS_CLK4,
	CLKCMU_NPU0_CPU,
	GATE_CLKCMU_VRA2_STR,
	CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_AXI2APB_CORE_0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_DEBUG_CCI_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE,
	GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL2_0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL2_0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK,
	CLK_BLK_CORE_UID_RSTNSYNC_CLK_CORE_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM,
	GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK,
	GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPFW_G3D_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL2_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_AXI_D0_CP_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK,
	CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_BPS_D0_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_BPS_D1_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_BPS_D2_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_BPS_D3_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_LHS_AXI_P_CP_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKS,
	GOUT_BLK_CORE_UID_APB_ASYNC_PPFW_G3D_IPCLKPORT_PCLKM,
	GOUT_BLK_CORE_UID_BAAW_CP_IPCLKPORT_I_PCLK,
	GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE,
	GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE,
	GOUT_BLK_CORE_UID_BPS_P_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHS_AXI_P_APM_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL2_1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL2_1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_D_TZPC_CORE_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_AXI2APB_CORE_1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_XIU_P_CORE_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL2_0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL2_0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL2_1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL2_1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_G3D0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_G3D1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_G3D2_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_G3D3_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_IRPS0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_IRPS1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_LHM_AXI_D1_CP_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHS_AXI_L_CORE_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_1_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_1_IPCLKPORT_CLK,
	GOUT_BLK_CORE_UID_AXI2APB_CORE_2_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_LHM_AXI_L_CORE_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_LHM_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL0_0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPC_CPUCL0_1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL0_0_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_ACLK,
	GOUT_BLK_CORE_UID_PPMU_CPUCL0_1_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_LHM_DBG_G_BUSC_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_MPACE_ASB_D0_MIF_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_MPACE_ASB_D1_MIF_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_MPACE_ASB_D2_MIF_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_MPACE_ASB_D3_MIF_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_PCLK,
	GOUT_BLK_CORE_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK,
	GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKM,
	GOUT_BLK_CORE_UID_AXI_ASB_CSSYS_IPCLKPORT_ACLKS,
	CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK,
	CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK,
	GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK,
	GATE_CLK_CPUCL0_CPU,
	CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_PCLKDBG,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T0_CLUSTER2_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_CLUSTER2_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_SECJTAG_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK,
	CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_PCLKDBG_IPCLKPORT_CLK,
	CLK_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_ATCLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ACE_D0_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_ADM_APB_G_CLUSTER0_IPCLKPORT_PCLKM,
	GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ACLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_ATCLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CLUSTER0_PCLKDBG_IPCLKPORT_CLK,
	CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK,
	CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_PERIPHCLK,
	GOUT_BLK_CPUCL0_UID_CSSYS_IPCLKPORT_ATCLK,
	CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_SCLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ACE_D1_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T4_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_ATB_T5_CLUSTER0_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_D_TZPC_CPUCL0_IPCLKPORT_PCLK,
	GOUT_BLK_CPUCL0_UID_LHM_ATB_T1_AUD_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_AXI_G_INT_CSSYS_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHS_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_AXI_G_INT_DBGCORE_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_XIU_P_CPUCL0_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL0_UID_XIU_DP_CSSYS_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL0_UID_TREX_CPUCL0_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_AXI_US_32TO64_G_DBGCORE_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL0_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_DBG_BUS_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL0_UID_TREX_CPUCL0_IPCLKPORT_PCLK,
	CLK_BLK_CPUCL0_UID_HPM_CPUCL0_1_IPCLKPORT_HPM_TARGETCLK_C,
	CLK_BLK_CPUCL0_UID_HPM_CPUCL0_0_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKS,
	GOUT_BLK_CPUCL0_UID_APB_ASYNC_P_CSSYS_0_IPCLKPORT_PCLKM,
	GOUT_BLK_CPUCL0_UID_LHS_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_LHM_AXI_G_INT_ETR_IPCLKPORT_I_CLK,
	GOUT_BLK_CPUCL0_UID_AXI2APB_P_CSSYS_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL0_UID_BPS_CPUCL0_IPCLKPORT_I_CLK,
	CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_PCLK,
	CLK_BLK_CPUCL0_UID_CPUCL0_IPCLKPORT_ATCLK,
	GATE_CLK_CPUCL1_CPU,
	CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK,
	CLK_BLK_CPUCL1_UID_CPUCL1_IPCLKPORT_SCLK,
	CLK_BLK_CPUCL2_UID_CPUCL2_CMU_CPUCL2_IPCLKPORT_PCLK,
	GOUT_BLK_CPUCL2_UID_SYSREG_CPUCL2_IPCLKPORT_PCLK,
	GOUT_BLK_CPUCL2_UID_BUSIF_HPMCPUCL2_IPCLKPORT_PCLK,
	CLK_BLK_CPUCL2_UID_HPM_CPUCL2_0_IPCLKPORT_HPM_TARGETCLK_C,
	GATE_CLK_CPUCL2_CPU,
	CLK_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_CPUCL2_UID_RSTNSYNC_CLK_CPUCL2_PCLK_IPCLKPORT_CLK,
	CLK_BLK_CPUCL2_UID_CLUSTER2_IPCLKPORT_PCLKDBG,
	GOUT_BLK_CPUCL2_UID_AXI2APB_CPUCL2_IPCLKPORT_ACLK,
	GOUT_BLK_CPUCL2_UID_LHM_AXI_P_CPUCL2_IPCLKPORT_I_CLK,
	CLK_BLK_CPUCL2_UID_HPM_CPUCL2_1_IPCLKPORT_HPM_TARGETCLK_C,
	CLK_BLK_CPUCL2_UID_HPM_CPUCL2_2_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_CPUCL2_UID_D_TZPC_CPUCL2_IPCLKPORT_PCLK,
	CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_ACLK,
	GOUT_BLK_DPU_UID_BTM_DPUD0_IPCLKPORT_I_PCLK,
	GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_ACLK,
	GOUT_BLK_DPU_UID_BTM_DPUD1_IPCLKPORT_I_PCLK,
	GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_AXI2APB_DPUP1_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_AXI2APB_DPUP0_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK,
	GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_DPU_UID_XIU_P_DPU_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DECON0_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DECON1_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DPP_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_ACLK,
	GOUT_BLK_DPU_UID_BTM_DPUD2_IPCLKPORT_I_PCLK,
	GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK,
	GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK,
	GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
	CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_DPU_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DECON2_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD0_S_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD1_S_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_SYSMMU_DPUD2_S_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPU_WB_MUX,
	GOUT_BLK_DPU_UID_WRAPPER_FOR_S5I6280_HSI_DCPHY_COMBO_TOP_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_PGEN_IPCLKPORT_PCLKM,
	GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
	GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DECON,
	GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DMA,
	GOUT_BLK_DPU_UID_DPU_IPCLKPORT_ACLK_DPP,
	GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK,
	GOUT_BLK_DPU_UID_AD_APB_MCD_IPCLKPORT_PCLKS,
	GOUT_BLK_DPU_UID_AD_APB_MCD_IPCLKPORT_PCLKM,
	CLK_BLK_DSPM_UID_DSPM_CMU_DSPM_IPCLKPORT_PCLK,
	GOUT_BLK_DSPM_UID_SYSREG_DSPM_IPCLKPORT_PCLK,
	GOUT_BLK_DSPM_UID_AXI2APB_DSPM_IPCLKPORT_ACLK,
	GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_ACLK,
	GOUT_BLK_DSPM_UID_PPMU_DSPM0_IPCLKPORT_PCLK,
	GOUT_BLK_DSPM_UID_SYSMMU_DSPM0_IPCLKPORT_CLK,
	GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_ACLK,
	GOUT_BLK_DSPM_UID_LHM_AXI_P_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_BTM_DSPM0_IPCLKPORT_I_PCLK,
	GOUT_BLK_DSPM_UID_LHS_ACEL_D0_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_DSPM_UID_LHM_AXI_P_IVADSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMIVA_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_WRAP2_CONV_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKM,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM0_IPCLKPORT_PCLKS,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKM,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM1_IPCLKPORT_PCLKS,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKS,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM3_IPCLKPORT_PCLKM,
	GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKS,
	GOUT_BLK_DSPM_UID_AD_AXI_DSPM0_IPCLKPORT_ACLKM,
	GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_ACLK,
	GOUT_BLK_DSPM_UID_BTM_DSPM1_IPCLKPORT_I_PCLK,
	GOUT_BLK_DSPM_UID_LHS_ACEL_D1_DSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHS_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_ACLK,
	GOUT_BLK_DSPM_UID_PPMU_DSPM1_IPCLKPORT_PCLK,
	GOUT_BLK_DSPM_UID_SYSMMU_DSPM1_IPCLKPORT_CLK,
	CLKCMU_DSPS_BUS,
	GOUT_BLK_DSPM_UID_ADM_APB_DSPM_IPCLKPORT_PCLKM,
	GOUT_BLK_DSPM_UID_LHM_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_XIU_P_DSPM_IPCLKPORT_ACLK,
	GOUT_BLK_DSPM_UID_VGEN_LITE_DSPM_IPCLKPORT_CLK,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKM,
	GOUT_BLK_DSPM_UID_AD_APB_DSPM2_IPCLKPORT_PCLKS,
	GOUT_BLK_DSPM_UID_SCORE_TS_II_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_D_TZPC_DSPM_IPCLKPORT_PCLK,
	GOUT_BLK_DSPM_UID_LHM_AST_ISPPREDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHM_AST_ISPLPDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHM_AST_ISPHQDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHS_AST_DSPMISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_LHS_AST_DSPMISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPM_UID_RSTNSYNC_CLK_DSPM_BUSD_OTF_IPCLKPORT_CLK,
	GOUT_BLK_DSPM_UID_XIU_D_DSPM_IPCLKPORT_ACLK,
	GOUT_BLK_DSPM_UID_BAAW_DSPM_IPCLKPORT_I_PCLK,
	GOUT_BLK_DSPM_UID_LHS_AXI_D_DSPMNPU0_IPCLKPORT_I_CLK,
	CLK_BLK_DSPS_UID_DSPS_CMU_DSPS_IPCLKPORT_PCLK,
	GOUT_BLK_DSPS_UID_AXI2APB_DSPS_IPCLKPORT_ACLK,
	GOUT_BLK_DSPS_UID_LHM_AXI_P_DSPMDSPS_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPS_UID_SYSREG_DSPS_IPCLKPORT_PCLK,
	GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_DSPS_UID_RSTNSYNC_CLK_DSPS_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_DSPS_UID_LHS_AXI_D_DSPSIVA_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPS_UID_LHS_AXI_D0_DSPSDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPS_UID_SCORE_BARON_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPS_UID_LHM_AXI_D_IVADSPS_IPCLKPORT_I_CLK,
	GOUT_BLK_DSPS_UID_D_TZPC_DSPS_IPCLKPORT_PCLK,
	GOUT_BLK_DSPS_UID_VGEN_LITE_DSPS_IPCLKPORT_CLK,
	CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK,
	GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK,
	CLK_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK,
	GOUT_BLK_FSYS0_UID_VGEN_LITE_FSYS0_IPCLKPORT_CLK,
	GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
	GOUT_BLK_FSYS0_UID_LHM_AXI_D_USB_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_LHS_AXI_P_USB_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_PPMU_FSYS0_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS0_UID_PPMU_FSYS0_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0_UID_SYSMMU_PCIE_GEN3A_IPCLKPORT_CLK,
	GOUT_BLK_FSYS0_UID_SYSMMU_PCIE_GEN3B_IPCLKPORT_CLK,
	GOUT_BLK_FSYS0_UID_XIU_P0_FSYS0_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X2_DWC_PCIE_DM_INST_0_DBI_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X2_DWC_PCIE_DM_INST_0_MSTR_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIE_PHY_TOP_X2_INST_0_I_PLL_REF_CLK_IN_SYSPLL,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_PCIE_SUB_CTRL_INST_1_PHY_REFCLK_IN,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X2_DWC_PCIE_DM_INST_0_SLV_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X1_DWC_PCIE_DM_INST_0_DBI_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X1_DWC_PCIE_DM_INST_0_MSTR_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_MK_G3X1_DWC_PCIE_DM_INST_0_SLV_ACLK_UG,
	GOUT_BLK_FSYS0_UID_PCIE_IA_GEN3A_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_PCIE_IA_GEN3B_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0_UID_D_TZPC_FSYS0_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIE_PHY_TOP_X2_INST_0_I_APB_PCLK_0,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIE_PHY_TOP_X2_INST_0_I_LN0_APB_PCLK_0,
	GOUT_BLK_FSYS0_UID_PCIE_GEN3_IPCLKPORT_IEEE1500_WRAPPER_FOR_QCHANNEL_WRAPPER_FOR_PCIE_PHY_TOP_X2_INST_0_I_LN1_APB_PCLK_0,
	CLK_BLK_FSYS0A_UID_FSYS0A_CMU_FSYS0A_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_ACLK_BUS,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_ACLK_BUS_PHYCTRL,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
	GOUT_BLK_FSYS0A_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
	GOUT_BLK_FSYS0A_UID_LHM_AXI_P_USB_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0A_UID_LHS_AXI_D_USB_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS0A_UID_RSTNSYNC_CLK_FSYS0A_BUS_IPCLKPORT_CLK,
	GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIEG2_PHY_X1_INST_0_I_SCL_APB_PCLK,
	GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK,
	GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK,
	GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS1_UID_PPMU_FSYS1_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK,
	CLK_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PHY_REFCLK_IN,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_SLV_ACLK,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_DBI_ACLK,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_PIPE2_DIGITAL_X1_WRAP_INST_0_I_APB_PCLK_SCL,
	GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK,
	GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO,
	GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
	GOUT_BLK_FSYS1_UID_SYSMMU_FSYS1_IPCLKPORT_CLK,
	GOUT_BLK_FSYS1_UID_VGEN_LITE_FSYS1_IPCLKPORT_CLK,
	GOUT_BLK_FSYS1_UID_PCIE_GEN2_IPCLKPORT_MSTR_ACLK,
	GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK,
	GOUT_BLK_FSYS1_UID_PCIE_IA_GEN2_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS1_UID_D_TZPC_FSYS1_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
	GOUT_BLK_FSYS1_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
	GOUT_BLK_FSYS1_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
	GOUT_BLK_FSYS1_UID_PUF_IPCLKPORT_I_CLK,
	GOUT_BLK_FSYS1_UID_QE_RTIC_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS1_UID_QE_RTIC_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_QE_SSS_IPCLKPORT_ACLK,
	GOUT_BLK_FSYS1_UID_QE_SSS_IPCLKPORT_PCLK,
	GOUT_BLK_FSYS1_UID_BAAW_SSS_IPCLKPORT_I_PCLK,
	GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK,
	CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD0_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD0_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD1_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD1_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_SYSMMU_G2DD0_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_G2D_UID_AS_P_G2D_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_G2D_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK,
	GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK,
	GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK,
	GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK,
	GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK,
	GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK,
	GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_QE_MSCL_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_QE_MSCL_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_SYSMMU_G2DD2_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD2_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_PPMU_G2DD2_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK,
	GOUT_BLK_G2D_UID_AS_P_JPEG_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_JPEG_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_AS_P_MSCL_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_MSCL_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSD_G2D_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSD_MSCL_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_AS_P_ASTC_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_ASTC_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD0_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD0_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD2_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD2_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD0_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD0_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD2_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD2_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_QE_ASTC_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_QE_ASTC_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_VGEN_LITE_G2D_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_G2D_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD1_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_NS_G2DD1_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD1_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_AS_P_SYSMMU_S_G2DD1_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_SYSMMU_G2DD1_IPCLKPORT_CLK,
	GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK,
	GOUT_BLK_G2D_UID_MSCL_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_ASTC_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_AS_P_JSQZ_IPCLKPORT_PCLKM,
	GOUT_BLK_G2D_UID_AS_P_JSQZ_IPCLKPORT_PCLKS,
	GOUT_BLK_G2D_UID_QE_JSQZ_IPCLKPORT_ACLK,
	GOUT_BLK_G2D_UID_QE_JSQZ_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_D_TZPC_G2D_IPCLKPORT_PCLK,
	GOUT_BLK_G2D_UID_JSQZ_IPCLKPORT_I_CLK,
	GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK,
	GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK,
	GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK,
	CLK_BLK_G3D_UID_HPM_G3D0_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK,
	GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK,
	CLK_BLK_G3D_UID_RSTNSYNC_CLK_G3D_OSCCLK_IPCLKPORT_CLK,
	CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK,
	GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK,
	GOUT_BLK_G3D_UID_VGEN_LITE_G3D_IPCLKPORT_CLK,
	CLK_BLK_G3D_UID_GPU_IPCLKPORT_CLK,
	GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK,
	GOUT_BLK_G3D_UID_LHM_AXI_G3DSFR_IPCLKPORT_I_CLK,
	GOUT_BLK_G3D_UID_GRAY2BIN_G3D_IPCLKPORT_CLK,
	GOUT_BLK_G3D_UID_D_TZPC_G3D_IPCLKPORT_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_PPMU_G3D0_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_PPMU_G3D1_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_PPMU_G3D2_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_PPMU_G3D3_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_QE_G3D0_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_QE_G3D1_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_QE_G3D2_PCLK,
	GOUT_BLK_G3D_UID_ASB_G3D_IPCLKPORT_QE_G3D3_PCLK,
	GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_LHS_AXI_D_ISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS,
	GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK,
	CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK,
	GOUT_BLK_ISPHQ_UID_LHM_ATB_ISPPREISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_LHS_ATB_ISPHQISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_BTM_ISPHQ_IPCLKPORT_I_ACLK,
	GOUT_BLK_ISPHQ_UID_BTM_ISPHQ_IPCLKPORT_I_PCLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_SYSMMU_PCLKM_NONSECURE,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_SYSMMU_PCLKM_SECURE,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_SYSMMU_PCLKS_NONSECURE,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_SYSMMU_PCLKS_SECURE,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_SYSMMU_ISPHQ_ACLK,
	CLK_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK,
	CLK_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_PPMU_ISPHQ_ACLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_PPMU_ISPHQ_PCLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_VGEN_LITE_ISPHQ_PCLK,
	GOUT_BLK_ISPHQ_UID_LHM_ATB_VO_ISPLPISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_LHS_AST_VO_ISPHQISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK,
	GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_C2COM_ACLK,
	GOUT_BLK_ISPHQ_UID_D_TZPC_ISPHQ_IPCLKPORT_PCLK,
	GOUT_BLK_ISPHQ_UID_LHS_AST_ISPHQDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHS_AXI_D0_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_BTM_ISPLP0_IPCLKPORT_I_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SYSMMU_ISPLP0_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_PPMU_ISPLP0_ACLK,
	GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_ISPLP_UID_BTM_ISPLP0_IPCLKPORT_I_PCLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_PPMU_ISPLP0_PCLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK,
	GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK,
	CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK,
	GOUT_BLK_ISPLP_UID_BTM_ISPLP1_IPCLKPORT_I_ACLK,
	GOUT_BLK_ISPLP_UID_BTM_ISPLP1_IPCLKPORT_I_PCLK,
	GOUT_BLK_ISPLP_UID_LHS_AXI_D1_ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_ATB_ISPHQISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_AST_VO_ISPPREISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_ATB_ISPPREISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_PPMU_ISPLP1_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_PPMU_ISPLP1_PCLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SYSMMU_ISPLP1_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_P_ISPLP_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_VGEN_LITE_ISPLP_PCLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_GDC_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_GDC_PCLK,
	GOUT_BLK_ISPLP_UID_LHS_ATB_VO_ISPLPISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_C2CLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_MC_SCALER_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_GDC_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_ASYNCM_GDC_ACLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_ASYNCS_GDC_ACLK,
	GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_GDC_IPCLKPORT_CLK,
	GOUT_BLK_ISPLP_UID_D_TZPC_ISPLP_IPCLKPORT_PCLK,
	GOUT_BLK_ISPLP_UID_LHS_AST_ISPLPDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_AST_DSPMISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHS_AXI_P_ISPLPVRA2_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_LHM_AXI_D_VRA2ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_GDC_PCLKM,
	GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_GDC_PCLKS,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_APB_ASYNC_TOP_3AA0_PCLKS,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_PPMU_ISPPRE,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_QE_PDP_TOP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_QE_3AA0,
	GOUT_BLK_ISPPRE_UID_LHS_AXI_D_ISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_BTM_ISPPRE_IPCLKPORT_I_ACLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_QE_PDP_TOP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_QE_3AA0,
	GOUT_BLK_ISPPRE_UID_LHM_AXI_P_ISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_SYSMMU_ISPPRE,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_XIU_D_ISPPRE,
	GOUT_BLK_ISPPRE_UID_SYSREG_ISPPRE_IPCLKPORT_PCLK,
	GOUT_BLK_ISPPRE_UID_RSTNSYNC_CLK_ISPPRE_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_ISPPRE_UID_RSTNSYNC_CLK_ISPPRE_BUSP_IPCLKPORT_CLK,
	CLK_BLK_ISPPRE_UID_ISPPRE_CMU_ISPPRE_IPCLKPORT_PCLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_QE_3AA1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_QE_3AA1,
	GOUT_BLK_ISPPRE_UID_BTM_ISPPRE_IPCLKPORT_I_PCLK,
	GOUT_BLK_ISPPRE_UID_LHS_ATB_ISPPREISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_LHS_ATB_ISPPREISPHQ_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_APB_ASYNC_TOP_3AA0_PCLKM,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_VGEN_LITE_ISPPRE,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_3AA0,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_3AA1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_PDP_TOP_CORE_TOP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_PDP_TOP_DMA,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_QE_CSISX4_PDP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_VGEN_LITE_ISPPRE1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_QE_CSISX4_PDP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSIS0,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSIS1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSIS2,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSIS3,
	GOUT_BLK_ISPPRE_UID_D_TZPC_ISPPRE_IPCLKPORT_PCLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSIS3_1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_CSISX4_PDP_DMA,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_XIU_P_ISPPRE,
	GOUT_BLK_ISPPRE_UID_LHS_AST_ISPPREDSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_LHM_AST_DSPMISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_PPMU_ISPPRE,
	GOUT_BLK_ISPPRE_UID_BUSIF_HPMISPPRE_IPCLKPORT_PCLK,
	GOUT_BLK_ISPPRE_UID_RSTNSYNC_CLK_ISPPRE_OSCCLK_IPCLKPORT_CLK,
	CLK_BLK_ISPPRE_UID_HPM_ISPPRE_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_ISPPRE_UID_D_TZPC_ISPPRE1_IPCLKPORT_PCLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_VGEN_LITE_ISPPRE2,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_VPP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_C2CLK_CSISX4_PDP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_C2CLK_3AA0,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_C2CLK_3AA1,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_C2CLK_AGENT,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_QE_VPP,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_PCLK_QE_VPP,
	GOUT_BLK_ISPPRE_UID_LHS_AST_VO_ISPPREISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_LHM_AST_VO_ISPHQISPPRE_IPCLKPORT_I_CLK,
	GOUT_BLK_ISPPRE_UID_IS_ISPPRE_IPCLKPORT_ACLK_PDP_TOP_RDMA,
	CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSPS_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSPM_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_LHM_AXI_P_DSPMIVA_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK,
	GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK,
	GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_PPMU_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_SYSMMU_IVA_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKS,
	GOUT_BLK_IVA_UID_AD_APB_IVA0_IPCLKPORT_PCLKM,
	GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_ADM_DAP_IVA_IPCLKPORT_DAPCLKM,
	GOUT_BLK_IVA_UID_LHM_AXI_D_DSPSIVA_IPCLKPORT_I_CLK,
	GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_DEBUG_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKS,
	GOUT_BLK_IVA_UID_AD_APB_IVA1_IPCLKPORT_PCLKM,
	GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKM,
	GOUT_BLK_IVA_UID_AD_APB_IVA2_IPCLKPORT_PCLKS,
	GOUT_BLK_IVA_UID_VGEN_LITE_IVA_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A,
	GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_XIU_D0_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_XIU_D1_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_IVA_IPCLKPORT_DAP_CLK,
	GOUT_BLK_IVA_UID_D_TZPC_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_XIU_D2_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_TREX_RB1_IVA_IPCLKPORT_CLK,
	GOUT_BLK_IVA_UID_TREX_RB1_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_QE_IVA_IPCLKPORT_ACLK,
	GOUT_BLK_IVA_UID_QE_IVA_IPCLKPORT_PCLK,
	GOUT_BLK_IVA_UID_WRAP2_CONV_IVA_IPCLKPORT_I_CLK,
	CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK,
	GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_MFC_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK,
	GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK,
	GOUT_BLK_MFC_UID_SYSMMU_MFCD0_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_SYSMMU_MFCD1_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_PPMU_MFCD0_IPCLKPORT_PCLK,
	GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_PPMU_MFCD1_IPCLKPORT_PCLK,
	GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK,
	GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK,
	GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK,
	GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_MFC_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_NS_MFCD0_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_NS_MFCD0_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_NS_MFCD1_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_NS_MFCD1_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_S_MFCD0_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_S_MFCD0_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_S_MFCD1_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AS_APB_SYSMMU_S_MFCD1_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKS,
	GOUT_BLK_MFC_UID_AS_AXI_WFD_IPCLKPORT_ACLKM,
	GOUT_BLK_MFC_UID_PPMU_MFCD2_IPCLKPORT_PCLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_WFD_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_XIU_D_MFC_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_AS_APB_WFD_S_IPCLKPORT_PCLKS,
	GOUT_BLK_MFC_UID_AS_APB_WFD_NS_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_AS_APB_WFD_S_IPCLKPORT_PCLKM,
	GOUT_BLK_MFC_UID_VGEN_MFC_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_MFC_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_WFD_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_MFC_SW_RESET_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_SI_SW_RESET_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_LH_ATB_MFC_MI_SW_RESET_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_WFD_SW_RESET_IPCLKPORT_CLK,
	GOUT_BLK_MFC_UID_PPMU_MFCD2_IPCLKPORT_ACLK,
	GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_MI,
	GOUT_BLK_MFC_UID_LH_ATB_MFC_IPCLKPORT_I_CLK_SI,
	GOUT_BLK_MFC_UID_D_TZPC_MFC_IPCLKPORT_PCLK,
	CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK,
	GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK,
	GOUT_BLK_MIF_UID_PPC_DVFS_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK,
	CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1,
	GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2,
	GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK,
	CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DEBUG_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_QCH_ADAPTER_PPC_DVFS_IPCLKPORT_PCLK,
	GOUT_BLK_MIF_UID_D_TZPC_MIF_IPCLKPORT_PCLK,
	CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK,
	CLK_BLK_MIF_UID_PPC_DEBUG_IPCLKPORT_ACLK,
	CLK_BLK_MIF_UID_PPC_DVFS_IPCLKPORT_CLK,
	CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK,
	CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C,
	CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK,
	GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1,
	GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2,
	GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK,
	GOUT_BLK_MIF1_UID_PPMUPPC_DEBUG1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_PPMUPPC_DVFS1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK,
	CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_OSCCLK1_IPCLKPORT_CLK,
	CLK_BLK_MIF1_UID_PPMUPPC_DVFS1_IPCLKPORT_CLK,
	GOUT_BLK_MIF1_UID_QCH_ADAPTER_PPMUPPC_DEBUG1_IPCLKPORT_PCLK,
	GOUT_BLK_MIF1_UID_QCH_ADAPTER_PPMUPPC_DVFS1_IPCLKPORT_PCLK,
	CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK,
	CLK_BLK_MIF1_UID_PPMUPPC_DEBUG1_IPCLKPORT_ACLK,
	CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK,
	CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_MPACE_CLK,
	CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK,
	GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1,
	GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2,
	GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK,
	GOUT_BLK_MIF2_UID_PPMUPPC_DEBUG2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_PPMUPPC_DVFS2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK,
	CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_OSCCLK2_IPCLKPORT_CLK,
	GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK,
	CLK_BLK_MIF2_UID_PPMUPPC_DEBUG2_IPCLKPORT_ACLK,
	CLK_BLK_MIF2_UID_PPMUPPC_DVFS2_IPCLKPORT_CLK,
	CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK,
	GOUT_BLK_MIF2_UID_QCH_ADAPTER_PPMUPPC_DEBUG2_IPCLKPORT_PCLK,
	GOUT_BLK_MIF2_UID_QCH_ADAPTER_PPMUPPC_DVFS2_IPCLKPORT_PCLK,
	CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK,
	CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK,
	CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_MPACE_CLK,
	CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C,
	GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK,
	GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1,
	GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK,
	GOUT_BLK_MIF3_UID_PPMUPPC_DEBUG3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_PPMUPPC_DVFS3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK,
	CLK_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_OSCCLK3_IPCLKPORT_CLK,
	GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2,
	CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_QCH_ADAPTER_PPMUPPC_DEBUG3_IPCLKPORT_PCLK,
	GOUT_BLK_MIF3_UID_QCH_ADAPTER_PPMUPPC_DVFS3_IPCLKPORT_PCLK,
	CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK,
	CLK_BLK_MIF3_UID_PPMUPPC_DEBUG3_IPCLKPORT_ACLK,
	CLK_BLK_MIF3_UID_PPMUPPC_DVFS3_IPCLKPORT_CLK,
	CLK_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK,
	CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_MPACE_CLK,
	GOUT_BLK_NPU0_UID_LHS_ACEL_D_NPU_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AXI_P_NPU1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_BUSP_IPCLKPORT_CLK,
	CLK_BLK_NPU0_UID_NPU0_CMU_NPU0_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_APB_ASYNC_SI0_IPCLKPORT_PCLKS,
	GOUT_BLK_NPU0_UID_APB_ASYNC_SMMU_NS_IPCLKPORT_PCLKS,
	GOUT_BLK_NPU0_UID_APB_ASYNC_SMMU_NS_IPCLKPORT_PCLKM,
	GOUT_BLK_NPU0_UID_AXI2APB_NPU0_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_BTM_NPU0_IPCLKPORT_I_ACLK,
	GOUT_BLK_NPU0_UID_BTM_NPU0_IPCLKPORT_I_PCLK,
	GOUT_BLK_NPU0_UID_D_TZPC_NPU0_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_2_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_4_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_5_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_6_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_D_NPUD1_D1_7_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AST_P_NPU1_DONE_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AXI_D_DSPMNPU0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHM_AXI_P_NPU_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_2_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_4_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_5_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_6_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_D_NPUD0_D1_7_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AST_P_NPUD1_SETREG_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AXI_D_IDPSRAM1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_LHS_AXI_D_IDPSRAM3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_NPUC_IPCLKPORT_I_PCLK,
	GOUT_BLK_NPU0_UID_NPUD_UNIT0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU0_UID_PPMU_CPUDMA_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_PPMU_CPUDMA_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_PPMU_RFM_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_PPMU_RFM_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_QE_CPUDMA_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_QE_CPUDMA_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_QE_RFM_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_QE_RFM_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_SMMU_NPU0_IPCLKPORT_CLK,
	GOUT_BLK_NPU0_UID_SYSREG_NPU0_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_XIU_D_NPU0_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_RSTNSYNC_CLK_NPU0_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_NPU0_UID_NPUC_IPCLKPORT_I_CM7_CLKIN,
	GOUT_BLK_NPU0_UID_NPUC_IPCLKPORT_I_ACLK,
	GOUT_BLK_NPU0_UID_APB_ASYNC_SMMU_S_IPCLKPORT_PCLKM,
	GOUT_BLK_NPU0_UID_APB_ASYNC_SMMU_S_IPCLKPORT_PCLKS,
	GOUT_BLK_NPU0_UID_VGEN_LITE_NPU0_IPCLKPORT_CLK,
	GOUT_BLK_NPU0_UID_PPMU_NPU0_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_PPMU_NPU0_IPCLKPORT_PCLK,
	GOUT_BLK_NPU0_UID_NPU0_PPC_WRAPPER_IPCLKPORT_ACLK,
	GOUT_BLK_NPU0_UID_NPU0_PPC_WRAPPER_IPCLKPORT_PCLK,
	CLK_BLK_NPU1_UID_NPU1_CMU_NPU1_IPCLKPORT_PCLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_RSTNSYNC_CLK_NPU1_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_NPU1_UID_RSTNSYNC_CLK_NPU1_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_NPU1_UID_LHM_AXI_P_NPU1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_APB_ASYNC_SI1_IPCLKPORT_PCLKS,
	GOUT_BLK_NPU1_UID_AXI2APB_NPU1_IPCLKPORT_ACLK,
	GOUT_BLK_NPU1_UID_D_TZPC_NPU1_IPCLKPORT_PCLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_2_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_4_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_5_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_6_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_D_NPUD0_D1_7_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AST_P_NPUD1_SETREG_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AXI_D_IDPSRAM1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHM_AXI_D_IDPSRAM3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_0_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_2_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_3_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_4_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_5_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_6_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_LHS_AST_D_NPUD1_D1_7_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_SYSREG_NPU1_IPCLKPORT_PCLK,
	GOUT_BLK_NPU1_UID_LHS_AST_P_NPU1_DONE_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_NPUD_UNIT1_IPCLKPORT_I_CLK,
	GOUT_BLK_NPU1_UID_PPMU_NPU1_IPCLKPORT_ACLK,
	GOUT_BLK_NPU1_UID_PPMU_NPU1_IPCLKPORT_PCLK,
	GOUT_BLK_NPU1_UID_NPU1_PPC_WRAPPER_IPCLKPORT_ACLK,
	GOUT_BLK_NPU1_UID_NPU1_PPC_WRAPPER_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0,
	GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P0_IPCLKPORT_ACLK,
	CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
	CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0P1_IPCLKPORT_ACLK,
	GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI00_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI_I2C_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI01_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI02_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI03_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI04_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI05_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_UART_DBG_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_XIU_P_PERIC0_IPCLKPORT_ACLK,
	GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI00_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI01_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI01_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI02_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI02_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI03_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI03_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI04_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI04_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI05_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI05_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
	GOUT_BLK_PERIC0_UID_USI00_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI12_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI13_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI12_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI12_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI13_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI13_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI14_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI14_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI15_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI15_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_USI15_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC0_UID_USI15_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI15_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK,
	GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK,
	GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK,
	CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI06_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI07_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI08_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI09_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI_I2C_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_UART_BT_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPI_CAM0_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM0_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM1_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM2_IPCLKPORT_CLK,
	CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I2C_CAM3_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM0_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM1_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM2_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_I2C_CAM3_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
	GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI06_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI06_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI07_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI07_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI08_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI08_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI09_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI09_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI10_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI10_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI11_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI11_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_I3C_IPCLKPORT_I_PCLK,
	GOUT_BLK_PERIC1_UID_I3C_IPCLKPORT_I_SCLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI16_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI17_USI_IPCLKPORT_CLK,
	GOUT_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI16_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI17_USI_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI17_USI_IPCLKPORT_PCLK,
	GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_SCLK,
	GOUT_BLK_PERIC1_UID_USI16_I3C_IPCLKPORT_I_PCLK,
	GOUT_BLK_PERIC1_UID_USI17_I2C_IPCLKPORT_IPCLK,
	GOUT_BLK_PERIC1_UID_USI17_I2C_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_AXI2APB_PERISP_IPCLKPORT_ACLK,
	GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK,
	GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_WDT_CLUSTER2_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
	CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK,
	CLK_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_OSCCLK_IPCLKPORT_CLK,
	GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK,
	GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS,
	GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM,
	GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK,
	GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK,
	GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_D_TZPC_PERIS_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_TMU_SUB_IPCLKPORT_PCLK,
	GOUT_BLK_PERIS_UID_TMU_TOP_IPCLKPORT_PCLK,
	CLK_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
	CLK_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
	CLK_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
	GOUT_BLK_PERIS_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
	CLK_BLK_S2D_UID_S2D_CMU_S2D_IPCLKPORT_PCLK,
	GOUT_BLK_S2D_UID_RSTNSYNC_CLK_S2D_CORE_IPCLKPORT_CLK,
	CLK_BLK_VRA2_UID_VRA2_CMU_VRA2_IPCLKPORT_PCLK,
	GOUT_BLK_VRA2_UID_AS_APB_VRA2_IPCLKPORT_PCLKS,
	GOUT_BLK_VRA2_UID_AS_APB_VRA2_IPCLKPORT_PCLKM,
	GOUT_BLK_VRA2_UID_AXI2APB_VRA2_IPCLKPORT_ACLK,
	GOUT_BLK_VRA2_UID_D_TZPC_VRA2_IPCLKPORT_PCLK,
	GOUT_BLK_VRA2_UID_LHM_AXI_P_ISPLPVRA2_IPCLKPORT_I_CLK,
	GOUT_BLK_VRA2_UID_LHS_AXI_D_VRA2ISPLP_IPCLKPORT_I_CLK,
	GOUT_BLK_VRA2_UID_QE_VRA2_IPCLKPORT_ACLK,
	GOUT_BLK_VRA2_UID_SYSREG_VRA2_IPCLKPORT_PCLK,
	GOUT_BLK_VRA2_UID_VGEN_LITE_VRA2_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_VRA2_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_RSTNSYNC_CLK_VRA2_BUSD_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_RSTNSYNC_CLK_VRA2_BUSP_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_AS_APB_STR_IPCLKPORT_PCLKS,
	GOUT_BLK_VRA2_UID_AS_APB_STR_IPCLKPORT_PCLKM,
	GOUT_BLK_VRA2_UID_BTM_VRA2_IPCLKPORT_I_ACLK,
	GOUT_BLK_VRA2_UID_BTM_VRA2_IPCLKPORT_I_PCLK,
	GOUT_BLK_VRA2_UID_PPMU_VRA2_IPCLKPORT_ACLK,
	GOUT_BLK_VRA2_UID_PPMU_VRA2_IPCLKPORT_PCLK,
	GOUT_BLK_VRA2_UID_SYSMMU_VRA2_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_STR_IPCLKPORT_I_STR_CLK,
	GOUT_BLK_VRA2_UID_LHS_AXI_D_VRA2_IPCLKPORT_I_CLK,
	GOUT_BLK_VRA2_UID_RSTNSYNC_CLK_VRA2_STR_IPCLKPORT_CLK,
	GOUT_BLK_VRA2_UID_QE_VRA2_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IF_IPCLKPORT_CLK,
	CLK_BLK_VTS_UID_RSTNSYNC_CLK_VTS_OSCCLK_RCO_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_CLK,
	CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_IF_DIV2_CLK,
	GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK,
	CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_AHB_BUSMATRIX_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB0_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB1_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_LHS_AXI_C_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_ASYNCINTERRUPT_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK_BUS,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK_BUS,
	GOUT_BLK_VTS_UID_SS_VTS_GLUE_IPCLKPORT_ACLK_CPU,
	GOUT_BLK_VTS_UID_CORTEXM4INTEGRATION_IPCLKPORT_FCLK,
	CLK_BLK_VTS_UID_U_DMIC_CLK_MUX_IPCLKPORT_D0,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC0_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC1_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_LHM_AXI_LP_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_BAAW_C_VTS_IPCLKPORT_I_PCLK,
	GOUT_BLK_VTS_UID_D_TZPC_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMIC_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_VGEN_LITE_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_BPS_LP_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_BPS_P_VTS_IPCLKPORT_I_CLK,
	GOUT_BLK_VTS_UID_XHB_LP_VTS_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_XHB_P_VTS_IPCLKPORT_CLK,
	GOUT_BLK_VTS_UID_SWEEPER_C_VTS_IPCLKPORT_ACLK,
	GOUT_BLK_VTS_UID_SWEEPER_D_VTS_IPCLKPORT_ACLK,
	GOUT_BLK_VTS_UID_BAAW_D_VTS_IPCLKPORT_I_PCLK,
	GOUT_BLK_VTS_UID_MAILBOX_ABOX_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB2_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_AHB3_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC2_IPCLKPORT_HCLK_BUS,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK,
	GOUT_BLK_VTS_UID_HWACG_SYS_DMIC3_IPCLKPORT_HCLK_BUS,
	GOUT_BLK_VTS_UID_DMIC_IF_3RD_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_DMIC_IF_3RD_IPCLKPORT_DMIC_IF_CLK,
	GOUT_BLK_VTS_UID_DMIC_IF_3RD_IPCLKPORT_DMIC_IF_DIV2_CLK,
	GOUT_BLK_VTS_UID_MAILBOX_AP_VTS_IPCLKPORT_PCLK,
	GOUT_BLK_VTS_UID_TIMER_IPCLKPORT_PCLK,
	end_of_gate,
	num_of_gate = (end_of_gate - GATE_TYPE) & MASK_OF_ID,

};
#endif