| #include "../cmucal.h" |
| #include "cmucal-sfr.h" |
| |
| /*=================CMUCAL version: S5E8895================================*/ |
| |
| /*====================The section of SFR Block instance===================*/ |
| struct sfr_block cmucal_sfr_block_list[] __initdata = { |
| SFR_BLOCK(ABOX, 0x13e00000, 0x8000), |
| SFR_BLOCK(APM, 0x16400000, 0x8000), |
| SFR_BLOCK(BUS1, 0x15c00000, 0x8000), |
| SFR_BLOCK(BUSC, 0x15a00000, 0x8000), |
| SFR_BLOCK(CAM, 0x12c00000, 0x8000), |
| SFR_BLOCK(CMU, 0x15a80000, 0x8000), |
| SFR_BLOCK(CORE, 0x15810000, 0x8000), |
| SFR_BLOCK(CPUCL0, 0x16800000, 0x8000), |
| SFR_BLOCK(CPUCL1, 0x16900000, 0x8000), |
| SFR_BLOCK(DBG, 0x17c00000, 0x8000), |
| SFR_BLOCK(DCAM, 0x12e00000, 0x8000), |
| SFR_BLOCK(DPU0, 0x12800000, 0x8000), |
| SFR_BLOCK(DPU1, 0x12a00000, 0x8000), |
| SFR_BLOCK(DSP, 0x13400000, 0x8000), |
| SFR_BLOCK(FSYS0, 0x11000000, 0x8000), |
| SFR_BLOCK(FSYS1, 0x11400000, 0x8000), |
| SFR_BLOCK(G2D, 0x13a00000, 0x8000), |
| SFR_BLOCK(G3D, 0x13800000, 0x8000), |
| SFR_BLOCK(IMEM, 0x15e00000, 0x8000), |
| SFR_BLOCK(ISPHQ, 0x13100000, 0x8000), |
| SFR_BLOCK(ISPLP, 0x13000000, 0x8000), |
| SFR_BLOCK(IVA, 0x13500000, 0x8000), |
| SFR_BLOCK(MFC, 0x13c00000, 0x8000), |
| SFR_BLOCK(MIF, 0x16000000, 0x8000), |
| SFR_BLOCK(MIF1, 0x16100000, 0x8000), |
| SFR_BLOCK(MIF2, 0x16200000, 0x8000), |
| SFR_BLOCK(MIF3, 0x16300000, 0x8000), |
| SFR_BLOCK(PERIC0, 0x10400000, 0x8000), |
| SFR_BLOCK(PERIC1, 0x10800000, 0x8000), |
| SFR_BLOCK(PERIS, 0x10010000, 0x8000), |
| SFR_BLOCK(SRDZ, 0x14200000, 0x8000), |
| SFR_BLOCK(VPU, 0x13200000, 0x8000), |
| SFR_BLOCK(VTS, 0x14000000, 0x8000), |
| }; |
| |
| unsigned int cmucal_sfr_block_size = 33; |
| |
| /*====================The section of SFR instance===================*/ |
| struct sfr cmucal_sfr_list[] __initdata = { |
| SFR(PLL_CON0_PLL_AUD, 0x0120, ABOX), |
| SFR(PLL_CON3_PLL_AUD, 0x012c, ABOX), |
| SFR(PLL_LOCKTIME_PLL_AUD, 0x0000, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_PLL, 0x1820, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_AUDIF, 0x1800, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK, 0x1810, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG, 0x1814, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_DSIF, 0x181c, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_UAIF0, 0x1828, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_UAIF1, 0x182c, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_UAIF2, 0x1830, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_UAIF3, 0x1834, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_UAIF3, 0x1010, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_UAIF2, 0x100c, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_UAIF1, 0x1008, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_UAIF0, 0x1004, ABOX), |
| SFR(CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK, 0x2000, ABOX), |
| SFR(PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER, 0x0100, ABOX), |
| SFR(PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER, 0x0108, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_CPU, 0x1000, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x2064, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK, 0x2074, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK, 0x2078, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK, 0x207c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK, 0x20b0, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK, 0x20b4, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK, 0x20b8, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0, 0x2024, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1, 0x2028, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3, 0x2030, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF, 0x2020, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK, 0x2060, ABOX), |
| SFR(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0, 0x0810, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK, 0x201c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK, 0x2058, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK, 0x2048, ABOX), |
| SFR(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1, 0x0814, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK, 0x2084, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK, 0x208c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK, 0x2094, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK, 0x2098, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK, 0x209c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK, 0x20a0, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK, 0x20a4, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK, 0x20a8, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK, 0x180c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK, 0x204c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK, 0x2050, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB, 0x2038, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_BUS, 0x1804, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK, 0x2088, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7, 0x2040, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK, 0x2090, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM, 0x2068, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2, 0x202c, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_BUSP, 0x1808, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK, 0x205c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS, 0x206c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK, 0x2080, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK, 0x2070, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK, 0x20c0, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_DMIC, 0x1818, ABOX), |
| SFR(CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK, 0x2008, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB, 0x203c, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK, 0x2018, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK, 0x20bc, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK, 0x20c4, ABOX), |
| SFR(CLK_CON_DIV_DIV_CLK_ABOX_UAIF4, 0x1838, ABOX), |
| SFR(CLK_CON_MUX_MUX_CLK_ABOX_UAIF4, 0x1014, ABOX), |
| SFR(CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK, 0x2004, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK, 0x20ac, ABOX), |
| SFR(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4, 0x2034, ABOX), |
| SFR(QCH_CON_ABOX_CMU_ABOX_QCH, 0x300c, ABOX), |
| SFR(DMYQCH_CON_ABOX_TOP_QCH, 0x3000, ABOX), |
| SFR(QCH_CON_BTM_ABOX_QCH, 0x3010, ABOX), |
| SFR(DMYQCH_CON_DMIC_QCH, 0x3004, ABOX), |
| SFR(QCH_CON_GPIO_ABOX_QCH, 0x3014, ABOX), |
| SFR(QCH_CON_LHM_AXI_P_ABOX_QCH, 0x3018, ABOX), |
| SFR(QCH_CON_LHS_ATB_ABOX_QCH, 0x301c, ABOX), |
| SFR(QCH_CON_LHS_AXI_D_ABOX_QCH, 0x3020, ABOX), |
| SFR(QCH_CON_PMU_ABOX_QCH, 0x3024, ABOX), |
| SFR(QCH_CON_BCM_ABOX_QCH, 0x3028, ABOX), |
| SFR(QCH_CON_SMMU_ABOX_QCH, 0x302c, ABOX), |
| SFR(QCH_CON_SYSREG_ABOX_QCH, 0x3030, ABOX), |
| SFR(QCH_CON_TREX_ABOX_QCH, 0x3034, ABOX), |
| SFR(QCH_CON_WDT_ABOXCPU_QCH, 0x3038, ABOX), |
| SFR(PLL_CON0_MUX_CLKCMU_APM_BUS_USER, 0x0100, APM), |
| SFR(PLL_CON2_MUX_CLKCMU_APM_BUS_USER, 0x0108, APM), |
| SFR(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 0x2000, APM), |
| SFR(CLKOUT_CON_BLK_APM_CMU_CLKOUT0, 0x0810, APM), |
| SFR(CLKOUT_CON_BLK_APM_CMU_CLKOUT1, 0x0814, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK, 0x2030, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK, 0x202c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU, 0x2018, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS, 0x201c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE, 0x2020, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK, 0x2044, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 0x2050, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 0x204c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK, 0x2048, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK, 0x2038, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK, 0x203c, APM), |
| SFR(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK, 0x2040, APM), |
| SFR(QCH_CON_APM_QCH_SYS, 0x300c, APM), |
| SFR(QCH_CON_APM_QCH_CPU, 0x3008, APM), |
| SFR(DMYQCH_CON_APM_QCH_OSCCLK, 0x3000, APM), |
| SFR(QCH_CON_APM_CMU_APM_QCH, 0x3004, APM), |
| SFR(QCH_CON_LHM_AXI_P_ALIVE_QCH, 0x3014, APM), |
| SFR(QCH_CON_LHS_AXI_D_ALIVE_QCH, 0x3018, APM), |
| SFR(QCH_CON_MAILBOX_APM2AP_QCH, 0x3020, APM), |
| SFR(QCH_CON_MAILBOX_APM2CP_QCH, 0x3024, APM), |
| SFR(QCH_CON_MAILBOX_APM2GNSS_QCH, 0x3028, APM), |
| SFR(QCH_CON_SCAN2AXI_QCH, 0x302c, APM), |
| SFR(QCH_CON_SYSREG_APM_QCH, 0x3030, APM), |
| SFR(QCH_CON_WDT_APM_QCH, 0x3034, APM), |
| SFR(CLK_CON_DIV_DIV_CLK_BUS1_BUSP, 0x1800, BUS1), |
| SFR(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER, 0x0100, BUS1), |
| SFR(PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER, 0x0108, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK, 0x2014, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK, 0x2018, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK, 0x2020, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK, 0x2028, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK, 0x2040, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK, 0x203c, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1, 0x2048, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK, 0x2044, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK, 0x200c, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK, 0x2010, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK, 0x202c, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK, 0x2038, BUS1), |
| SFR(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0, 0x0810, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK, 0x201c, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK, 0x2024, BUS1), |
| SFR(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1, 0x0814, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK, 0x2030, BUS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK, 0x2034, BUS1), |
| SFR(QCH_CON_BUS1_CMU_BUS1_QCH, 0x3008, BUS1), |
| SFR(QCH_CON_LHM_ACEL_D_FSYS1_QCH, 0x301c, BUS1), |
| SFR(QCH_CON_LHM_AXI_D_ALIVE_QCH, 0x3028, BUS1), |
| SFR(QCH_CON_LHM_AXI_D_GNSS_QCH, 0x3030, BUS1), |
| SFR(QCH_CON_LHS_AXI_P_ALIVE_QCH, 0x3034, BUS1), |
| SFR(QCH_CON_LHS_AXI_P_FSYS1_QCH, 0x3040, BUS1), |
| SFR(QCH_CON_PMU_BUS1_QCH, 0x3050, BUS1), |
| SFR(QCH_CON_SYSREG_BUS1_QCH, 0x3054, BUS1), |
| SFR(QCH_CON_TREX_D_BUS1_QCH, 0x3058, BUS1), |
| SFR(QCH_CON_TREX_P_BUS1_QCH, 0x305c, BUS1), |
| SFR(CLK_CON_DIV_DIV_CLK_BUSC_BUSP, 0x1800, BUSC), |
| SFR(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK, 0x2000, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK, 0x2038, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK, 0x203c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK, 0x2040, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK, 0x204c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK, 0x2128, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK, 0x2044, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK, 0x2100, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK, 0x2110, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK, 0x20f8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0, 0x2010, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1, 0x2014, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK, 0x212c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK, 0x2130, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK, 0x2138, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC, 0x213c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x209c, BUSC), |
| SFR(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER, 0x0140, BUSC), |
| SFR(PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER, 0x0148, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK, 0x20d0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK, 0x20d4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK, 0x20d8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK, 0x20dc, BUSC), |
| SFR(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0, 0x0810, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK, 0x20e8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK, 0x20e0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK, 0x20e4, BUSC), |
| SFR(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1, 0x0814, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK, 0x2034, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK, 0x2104, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK, 0x210c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK, 0x2048, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK, 0x2124, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY, 0x2120, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP, 0x2118, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP, 0x211c, BUSC), |
| SFR(PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER, 0x0120, BUSC), |
| SFR(PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER, 0x0128, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK, 0x2050, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS, 0x201c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM, 0x2018, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK, 0x2108, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK, 0x2030, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK, 0x20a0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK, 0x20fc, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK, 0x2114, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS, 0x2024, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM, 0x2020, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS, 0x202c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM, 0x2028, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK, 0x2054, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK, 0x2058, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK, 0x205c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK, 0x2060, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK, 0x2064, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK, 0x2068, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK, 0x206c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK, 0x2070, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK, 0x2074, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK, 0x2078, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK, 0x207c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK, 0x2080, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK, 0x2084, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK, 0x2088, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK, 0x208c, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK, 0x2094, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK, 0x2090, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK, 0x2098, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK, 0x20a4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK, 0x20a8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK, 0x20ac, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK, 0x20b0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK, 0x20ec, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK, 0x20b4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK, 0x20b8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK, 0x20bc, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK, 0x20c0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK, 0x20c4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK, 0x20c8, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK, 0x20cc, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK, 0x20f0, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK, 0x20f4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC, 0x2134, BUSC), |
| SFR(QCH_CON_ADCIF_BUSC_QCH_S0, 0x3008, BUSC), |
| SFR(QCH_CON_ADCIF_BUSC_QCH_S1, 0x300c, BUSC), |
| SFR(QCH_CON_BUSC_CMU_BUSC_QCH, 0x3010, BUSC), |
| SFR(QCH_CON_BUSIF_CMUTOPC_QCH, 0x3014, BUSC), |
| SFR(QCH_CON_GNSSMBOX_QCH, 0x3018, BUSC), |
| SFR(QCH_CON_GPIO_BUSC_QCH, 0x301c, BUSC), |
| SFR(QCH_CON_HSI2CDF_QCH, 0x3020, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D0_G2D_QCH, 0x3024, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D1_G2D_QCH, 0x3028, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D2_G2D_QCH, 0x302c, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D_DSP_QCH, 0x3030, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D_FSYS0_QCH, 0x3034, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D_IVA_QCH, 0x3038, BUSC), |
| SFR(QCH_CON_LHM_ACEL_D_VPU_QCH, 0x303c, BUSC), |
| SFR(QCH_CON_LHM_AXI_D0_CAM_QCH, 0x3040, BUSC), |
| SFR(QCH_CON_LHM_AXI_D0_DPU_QCH, 0x3044, BUSC), |
| SFR(QCH_CON_LHM_AXI_D0_MFC_QCH, 0x3048, BUSC), |
| SFR(QCH_CON_LHM_AXI_D1_CAM_QCH, 0x304c, BUSC), |
| SFR(QCH_CON_LHM_AXI_D1_DPU_QCH, 0x3050, BUSC), |
| SFR(QCH_CON_LHM_AXI_D1_MFC_QCH, 0x3054, BUSC), |
| SFR(QCH_CON_LHM_AXI_D2_DPU_QCH, 0x3058, BUSC), |
| SFR(QCH_CON_LHM_AXI_D_ABOX_QCH, 0x305c, BUSC), |
| SFR(QCH_CON_LHM_AXI_D_ISPLP_QCH, 0x3060, BUSC), |
| SFR(QCH_CON_LHM_AXI_D_SRDZ_QCH, 0x3064, BUSC), |
| SFR(QCH_CON_LHM_AXI_D_VTS_QCH, 0x3068, BUSC), |
| SFR(QCH_CON_LHM_AXI_G_CSSYS_QCH, 0x306c, BUSC), |
| SFR(QCH_CON_LHS_AXI_D_IVASC_QCH, 0x3070, BUSC), |
| SFR(QCH_CON_LHS_AXI_P0_DPU_QCH, 0x3074, BUSC), |
| SFR(QCH_CON_LHS_AXI_P1_DPU_QCH, 0x3078, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_ABOX_QCH, 0x307c, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_CAM_QCH, 0x3080, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_DSP_QCH, 0x3084, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_FSYS0_QCH, 0x3088, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_G2D_QCH, 0x308c, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_ISPHQ_QCH, 0x3090, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_ISPLP_QCH, 0x3094, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_IVA_QCH, 0x3098, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_MFC_QCH, 0x309c, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_MIF0_QCH, 0x30a0, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_MIF1_QCH, 0x30a4, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_MIF2_QCH, 0x30a8, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_MIF3_QCH, 0x30ac, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_PERIC0_QCH, 0x30b0, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_PERIC1_QCH, 0x30b4, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_PERIS_QCH, 0x30b8, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_SRDZ_QCH, 0x30bc, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_VPU_QCH, 0x30c0, BUSC), |
| SFR(QCH_CON_LHS_AXI_P_VTS_QCH, 0x30c4, BUSC), |
| SFR(QCH_CON_MBOX_QCH, 0x30c8, BUSC), |
| SFR(QCH_CON_PDMA0_QCH, 0x30cc, BUSC), |
| SFR(QCH_CON_PMU_BUSC_QCH, 0x30d0, BUSC), |
| SFR(QCH_CON_SECMBOX_QCH, 0x30d4, BUSC), |
| SFR(QCH_CON_SPDMA_QCH, 0x30d8, BUSC), |
| SFR(QCH_CON_SPEEDY_QCH, 0x30e8, BUSC), |
| SFR(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY, 0x30e4, BUSC), |
| SFR(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP, 0x30e0, BUSC), |
| SFR(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP, 0x30dc, BUSC), |
| SFR(QCH_CON_SYSREG_BUSC_QCH, 0x30ec, BUSC), |
| SFR(QCH_CON_TREX_D_BUSC_QCH, 0x30f0, BUSC), |
| SFR(QCH_CON_TREX_P_BUSC_QCH, 0x30f4, BUSC), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS, 0x2104, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA, 0x2118, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER, 0x211c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0, 0x2120, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA, 0x2128, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM, 0x212c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0, 0x2130, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1, 0x2134, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4, 0x2138, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0, 0x213c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA, 0x2144, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0, 0x2148, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1, 0x214c, CAM), |
| SFR(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER, 0x0100, CAM), |
| SFR(PLL_CON2_MUX_CLKCMU_CAM_BUS_USER, 0x0108, CAM), |
| SFR(CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2, 0x1800, CAM), |
| SFR(PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER, 0x0120, CAM), |
| SFR(PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER, 0x0128, CAM), |
| SFR(PLL_CON0_MUX_CLKCMU_CAM_VRA_USER, 0x0160, CAM), |
| SFR(PLL_CON2_MUX_CLKCMU_CAM_VRA_USER, 0x0168, CAM), |
| SFR(CLK_CON_DIV_DIV_CLK_CAM_BUSP, 0x1804, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK, 0x2158, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK, 0x215c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK, 0x2010, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0, 0x2058, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1, 0x2060, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2, 0x2068, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3, 0x2070, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER, 0x207c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0, 0x20d0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0, 0x2080, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1, 0x2084, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4, 0x20c0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0, 0x20c4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA, 0x20cc, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC, 0x20b8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0, 0x2098, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP, 0x2094, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ, 0x2090, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0, 0x20d8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0, 0x20a4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC, 0x2088, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA, 0x20e0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA, 0x20ac, CAM), |
| SFR(CLKOUT_CON_BLK_CAM_CMU_CLKOUT0, 0x0810, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK, 0x2154, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2, 0x205c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2, 0x2064, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2, 0x206c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2, 0x2074, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0, 0x2040, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA, 0x2048, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0, 0x204c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1, 0x2050, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1, 0x20d4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0, 0x20e4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA, 0x20ec, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1, 0x20fc, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2, 0x2100, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER, 0x203c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA, 0x2038, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA, 0x20a0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM, 0x20b4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM, 0x20b0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK, 0x217c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0, 0x20f0, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA, 0x20f8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK, 0x2018, CAM), |
| SFR(CLKOUT_CON_BLK_CAM_CMU_CLKOUT1, 0x0814, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS, 0x2054, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS, 0x2024, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK, 0x2168, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK, 0x2164, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK, 0x216c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK, 0x2170, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK, 0x2178, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA, 0x2078, CAM), |
| SFR(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK, 0x2000, CAM), |
| SFR(PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER, 0x0140, CAM), |
| SFR(PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER, 0x0148, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1, 0x20c8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1, 0x2140, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1, 0x20e8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1, 0x209c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC, 0x20bc, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1, 0x2124, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1, 0x20dc, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1, 0x20a8, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC, 0x208c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1, 0x20f4, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1, 0x2044, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK, 0x2014, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK, 0x201c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK, 0x2174, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0, 0x2108, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1, 0x210c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3, 0x2114, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2, 0x2110, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0, 0x2028, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1, 0x202c, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2, 0x2030, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3, 0x2034, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK, 0x2160, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK, 0x2150, CAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK, 0x2020, CAM), |
| SFR(QCH_CON_BTM_CAMD0_QCH, 0x3004, CAM), |
| SFR(QCH_CON_BTM_CAMD1_QCH, 0x3008, CAM), |
| SFR(QCH_CON_CAM_CMU_CAM_QCH, 0x300c, CAM), |
| SFR(QCH_CON_ISP_EWGEN_CAM_QCH, 0x3010, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_CSIS0, 0x3018, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_CSIS1, 0x301c, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_CSIS2, 0x3020, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_CSIS3, 0x3024, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_MC_SCALER, 0x302c, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_CSISX4_DMA, 0x3028, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_SYSMMU_CAM0, 0x3048, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_SYSMMU_CAM1, 0x304c, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_BCM_CAM0, 0x3030, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_BCM_CAM1, 0x3034, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_TPU0, 0x3050, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_VRA, 0x3058, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_QE_TPU0, 0x303c, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_QE_VRA, 0x3044, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_BNS, 0x3014, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_QE_CSISX4, 0x3038, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_QE_TPU1, 0x3040, CAM), |
| SFR(QCH_CON_IS_CAM_QCH_TPU1, 0x3054, CAM), |
| SFR(QCH_CON_LHM_ATB_SRDZCAM_QCH, 0x305c, CAM), |
| SFR(QCH_CON_LHM_AXI_P_CAM_QCH, 0x3060, CAM), |
| SFR(QCH_CON_LHS_AXI_D0_CAM_QCH, 0x3064, CAM), |
| SFR(QCH_CON_LHS_AXI_D1_CAM_QCH, 0x3068, CAM), |
| SFR(QCH_CON_PMU_CAM_QCH, 0x306c, CAM), |
| SFR(QCH_CON_SYSREG_CAM_QCH, 0x3070, CAM), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 0x200c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_APM_BUS, 0x1804, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2, 0x1914, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0x1880, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0x18a8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIS_BUS, 0x18fc, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0x1854, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS, 0x205c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0x104c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DPU_BUS, 0x184c, CMU), |
| SFR(PLL_CON0_PLL_SHARED1, 0x0140, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED1, 0x0004, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2, 0x191c, CMU), |
| SFR(CLK_CON_GAT_CLKCMU_MIF_SWITCH, 0x2004, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_BUS1_BUS, 0x1808, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0x1008, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_USI00, 0x18b0, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG, 0x18ac, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_USI01, 0x18b4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_USI02, 0x18b8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC0_USI03, 0x18bc, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2, 0x1924, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2, 0x1928, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2, 0x192c, CMU), |
| SFR(PLL_CON0_PLL_SHARED4, 0x01a0, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED4, 0x0010, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4, 0x1918, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS, 0x1098, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MFC_BUS, 0x1898, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS, 0x20a0, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 0x2080, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_G2D_G2D, 0x1878, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30, 0x1068, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30, 0x206c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30, 0x1864, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD, 0x2064, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD, 0x185c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD, 0x1860, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD, 0x2068, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD, 0x1064, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD, 0x186c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0x1868, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS, 0x2070, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 0x2074, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 0x2054, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 0x2088, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS, 0x2100, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_VPU_BUS, 0x210c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_VPU_BUS, 0x1908, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_VPU_BUS, 0x1100, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DSP_BUS, 0x2058, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DSP_BUS, 0x1850, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS, 0x20ac, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG, 0x10a4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG, 0x20b0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00, 0x10a8, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00, 0x20b4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01, 0x20b8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02, 0x10b0, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02, 0x20bc, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03, 0x10b4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05, 0x20dc, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT, 0x20d4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0x18c0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04, 0x10cc, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04, 0x20d8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05, 0x10d0, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS, 0x20c4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_UART_BT, 0x18d0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT, 0x10c8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI05, 0x18d8, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06, 0x20e0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06, 0x10d4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI06, 0x18dc, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07, 0x10d8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI07, 0x18e0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08, 0x10dc, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI08, 0x18e4, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09, 0x10e0, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI09, 0x18e8, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10, 0x20f0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10, 0x10e4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI10, 0x18ec, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11, 0x20f4, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11, 0x10e8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI11, 0x18f0, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12, 0x20f8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12, 0x10ec, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI12, 0x18f4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13, 0x20fc, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13, 0x10f0, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI13, 0x18f8, CMU), |
| SFR(PLL_CON0_PLL_SHARED3, 0x0180, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED3, 0x000c, CMU), |
| SFR(PLL_CON0_MUX_CP2AP_MIF_CLK_USER, 0x0100, CMU), |
| SFR(PLL_CON2_MUX_CP2AP_MIF_CLK_USER, 0x0108, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS, 0x2014, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0x100c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_BUSC_BUS, 0x180c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0x107c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08, 0x20e8, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07, 0x20e4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_USI04, 0x18d4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03, 0x20c0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01, 0x10ac, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 0x2010, CMU), |
| SFR(PLL_CON0_PLL_SHARED2, 0x0160, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED2, 0x0008, CMU), |
| SFR(PLL_CON0_PLL_SHARED0, 0x0120, CMU), |
| SFR(PLL_LOCKTIME_PLL_SHARED0, 0x0000, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09, 0x20ec, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0x1070, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0x1054, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD, 0x1060, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0x183c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 0x2044, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 0x2040, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH, 0x1038, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0x1838, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CORE_BUS, 0x1834, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 0x203c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0x1034, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0x109c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS, 0x1014, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0, 0x1018, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1, 0x101c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS, 0x201c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CAM_BUS, 0x1814, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0, 0x2020, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CAM_TPU0, 0x1818, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1, 0x2024, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CAM_TPU1, 0x181c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS, 0x1090, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_ISPLP_BUS, 0x1890, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS, 0x2098, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_ISPHQ_BUS, 0x188c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS, 0x108c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS, 0x2094, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX, 0x2008, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX, 0x1000, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_ABOX_CPUABOX, 0x1800, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG, 0x2084, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_G2D_JPEG, 0x187c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG, 0x1080, CMU), |
| SFR(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0, 0x0810, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_HPM, 0x1084, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_HPM, 0x1884, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_HPM, 0x208c, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE, 0x2078, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS1_PCIE, 0x1870, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DBG_BUS, 0x1040, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DBG_BUS, 0x2048, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DBG_BUS, 0x1840, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0, 0x10c0, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0, 0x20cc, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0, 0x18c8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1, 0x10c4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1, 0x20d0, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1, 0x18cc, CMU), |
| SFR(CLK_CON_GAT_CLKCMU_DROOPDETECTOR, 0x2000, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR, 0x1050, CMU), |
| SFR(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1, 0x0814, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0x1058, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0x1024, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 0x202c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK0, 0x1824, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 0x2030, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 0x2038, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 0x2034, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK1, 0x1828, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK2, 0x182c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CIS_CLK3, 0x1830, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0x1028, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0x102c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0x1030, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_OTP, 0x18a4, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS, 0x1094, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS, 0x209c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IVA_BUS, 0x1894, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD, 0x1078, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD, 0x207c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD, 0x1874, CMU), |
| SFR(CLK_CON_MUX_MUX_CMU_CMUREF, 0x1108, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C, 0x1010, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C, 0x2018, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C, 0x1810, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_CAM_VRA, 0x1820, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_CAM_VRA, 0x2028, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CAM_VRA, 0x1020, CMU), |
| SFR(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4, 0x1920, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2, 0x18c4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2, 0x20c8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0x10a0, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0x10b8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0x10f4, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC, 0x1858, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC, 0x2060, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0, 0x20a4, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1, 0x20a8, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MODEM_SHARED0, 0x189c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_MODEM_SHARED1, 0x18a0, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DCAM_BUS, 0x1844, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS, 0x204c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS, 0x1044, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS, 0x2090, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_IMEM_BUS, 0x1888, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS, 0x1088, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC, 0x105c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE, 0x1074, CMU), |
| SFR(CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0x190c, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_SRDZ_IMGD, 0x1904, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD, 0x2108, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS, 0x10f8, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD, 0x10fc, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_SRDZ_BUS, 0x1900, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS, 0x2104, CMU), |
| SFR(CLK_CON_DIV_CLKCMU_DCAM_IMGD, 0x1848, CMU), |
| SFR(CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD, 0x2050, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD, 0x1048, CMU), |
| SFR(CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2, 0x1910, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2, 0x10bc, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0x1004, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0x106c, CMU), |
| SFR(CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0x1104, CMU), |
| SFR(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH, 0x103c, CMU), |
| SFR(DMYQCH_CON_CMU_CMU_CMUREF_QCH, 0x3000, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0, 0x3004, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1, 0x3008, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2, 0x300c, CMU), |
| SFR(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3, 0x3010, CMU), |
| SFR(CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0x1800, CORE), |
| SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK, 0x2000, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK, 0x209c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK, 0x20e8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK, 0x2020, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK, 0x2094, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK, 0x2098, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK, 0x20a8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK, 0x20ac, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE, 0x20fc, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE, 0x20f4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK, 0x20f8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK, 0x2034, CORE), |
| SFR(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER, 0x0100, CORE), |
| SFR(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER, 0x0108, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK, 0x204c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK, 0x2058, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK, 0x2084, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK, 0x2088, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK, 0x208c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK, 0x2090, CORE), |
| SFR(CLKOUT_CON_BLK_CORE_CMU_CLKOUT0, 0x0810, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK, 0x2038, CORE), |
| SFR(CLKOUT_CON_BLK_CORE_CMU_CLKOUT1, 0x0814, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK, 0x20b0, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK, 0x20b4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK, 0x20b8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK, 0x20bc, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK, 0x20e0, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK, 0x20e4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK, 0x205c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK, 0x2060, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK, 0x2064, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK, 0x2068, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK, 0x206c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM, 0x2018, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK, 0x2028, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK, 0x202c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK, 0x201c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK, 0x2100, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE, 0x2104, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK, 0x2024, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK, 0x20c0, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK, 0x20c4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK, 0x20c8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK, 0x20cc, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK, 0x20d0, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK, 0x20d4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK, 0x20d8, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK, 0x20dc, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK, 0x20a0, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK, 0x20a4, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK, 0x2078, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK, 0x207c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK, 0x2080, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2070, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x2074, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK, 0x2054, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK, 0x2050, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK, 0x203c, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK, 0x2040, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK, 0x2044, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK, 0x2048, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK, 0x20f0, CORE), |
| SFR(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK, 0x2030, CORE), |
| SFR(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK, 0x20ec, CORE), |
| SFR(QCH_CON_APBBR_CCI_QCH, 0x3024, CORE), |
| SFR(QCH_CON_BDU_QCH, 0x3028, CORE), |
| SFR(QCH_CON_BUSIF_HPMCORE_QCH, 0x302c, CORE), |
| SFR(DMYQCH_CON_CCI_QCH, 0x3000, CORE), |
| SFR(QCH_CON_CORE_CMU_CORE_QCH, 0x3030, CORE), |
| SFR(QCH_CON_LHM_ACE_D0_G3D_QCH, 0x3034, CORE), |
| SFR(QCH_CON_LHM_ACE_D1_G3D_QCH, 0x3038, CORE), |
| SFR(QCH_CON_LHM_ACE_D2_G3D_QCH, 0x303c, CORE), |
| SFR(QCH_CON_LHM_ACE_D3_G3D_QCH, 0x3040, CORE), |
| SFR(QCH_CON_LHM_ACE_D_CPUCL1_QCH, 0x3044, CORE), |
| SFR(QCH_CON_LHM_AXI_D_CP_QCH, 0x3048, CORE), |
| SFR(QCH_CON_LHM_AXI_P_CP_QCH, 0x304c, CORE), |
| SFR(QCH_CON_LHS_ATB_T_BDU_QCH, 0x3050, CORE), |
| SFR(QCH_CON_LHS_AXI_P_CPUCL0_QCH, 0x3054, CORE), |
| SFR(QCH_CON_LHS_AXI_P_CPUCL1_QCH, 0x3058, CORE), |
| SFR(QCH_CON_LHS_AXI_P_DBG_QCH, 0x305c, CORE), |
| SFR(QCH_CON_LHS_AXI_P_G3D_QCH, 0x3060, CORE), |
| SFR(QCH_CON_LHS_AXI_P_IMEM_QCH, 0x3064, CORE), |
| SFR(QCH_CON_PMU_CORE_QCH, 0x3068, CORE), |
| SFR(QCH_CON_PPCFW_G3D_QCH, 0x306c, CORE), |
| SFR(QCH_CON_BCM_CPUCL0_QCH, 0x3070, CORE), |
| SFR(QCH_CON_BCM_CPUCL1_QCH, 0x3074, CORE), |
| SFR(QCH_CON_BCM_G3D0_QCH, 0x3078, CORE), |
| SFR(QCH_CON_BCM_G3D1_QCH, 0x307c, CORE), |
| SFR(QCH_CON_BCM_G3D2_QCH, 0x3080, CORE), |
| SFR(QCH_CON_BCM_G3D3_QCH, 0x3084, CORE), |
| SFR(QCH_CON_SYSREG_CORE_QCH, 0x3088, CORE), |
| SFR(QCH_CON_TREX_D_CORE_QCH, 0x308c, CORE), |
| SFR(QCH_CON_TREX_P0_CORE_QCH, 0x3090, CORE), |
| SFR(QCH_CON_TREX_P1_CORE_QCH, 0x3094, CORE), |
| SFR(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL, 0x1000, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF, 0x1808, CPUCL0), |
| SFR(PLL_CON0_PLL_CPUCL0, 0x0120, CPUCL0), |
| SFR(PLL_LOCKTIME_PLL_CPUCL0, 0x0000, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK, 0x1810, CPUCL0), |
| SFR(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0100, CPUCL0), |
| SFR(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER, 0x0108, CPUCL0), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK, 0x2000, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK, 0x2024, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK, 0x2040, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK, 0x2028, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK, 0x2034, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0, 0x0810, CPUCL0), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C, 0x200c, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK, 0x1800, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK, 0x1804, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK, 0x202c, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK, 0x2038, CPUCL0), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN, 0x2004, CPUCL0), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN, 0x2008, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1, 0x0814, CPUCL0), |
| SFR(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU, 0x2020, CPUCL0), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK, 0x203c, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG, 0x1814, CPUCL0), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU, 0x180c, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0, 0x0818, CPUCL0), |
| SFR(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1, 0x081c, CPUCL0), |
| SFR(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH, 0x3014, CPUCL0), |
| SFR(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0, 0x3018, CPUCL0), |
| SFR(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1, 0x301c, CPUCL0), |
| SFR(QCH_CON_BUSIF_HPMCPUCL0_QCH, 0x3020, CPUCL0), |
| SFR(DMYQCH_CON_CLUSTER0_QCH, 0x3000, CPUCL0), |
| SFR(QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0, 0x3024, CPUCL0), |
| SFR(QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0, 0x3028, CPUCL0), |
| SFR(QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0, 0x302c, CPUCL0), |
| SFR(QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0, 0x3030, CPUCL0), |
| SFR(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH, 0x3034, CPUCL0), |
| SFR(QCH_CON_CPUCL0_CMU_CPUCL0_QCH, 0x3038, CPUCL0), |
| SFR(QCH_CON_LHM_AXI_P_CPUCL0_QCH, 0x303c, CPUCL0), |
| SFR(QCH_CON_PMU_CPUCL0_QCH, 0x3040, CPUCL0), |
| SFR(QCH_CON_SYSREG_CPUCL0_QCH, 0x3044, CPUCL0), |
| SFR(PLL_CON0_PLL_CPUCL1, 0x0120, CPUCL1), |
| SFR(PLL_LOCKTIME_PLL_CPUCL1, 0x0000, CPUCL1), |
| SFR(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0100, CPUCL1), |
| SFR(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER, 0x0108, CPUCL1), |
| SFR(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL, 0x1000, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF, 0x1810, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK, 0x1818, CPUCL1), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK, 0x2000, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK, 0x201c, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK, 0x2028, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK, 0x2034, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK, 0x202c, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK, 0x2020, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0, 0x0810, CPUCL1), |
| SFR(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C, 0x2004, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1, 0x0814, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG, 0x180c, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK, 0x1808, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK, 0x1800, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK, 0x1804, CPUCL1), |
| SFR(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU, 0x2018, CPUCL1), |
| SFR(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK, 0x2030, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU, 0x1814, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0, 0x0818, CPUCL1), |
| SFR(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1, 0x081c, CPUCL1), |
| SFR(QCH_CON_BUSIF_HPMCPUCL1_QCH, 0x301c, CPUCL1), |
| SFR(DMYQCH_CON_CLUSTER1_QCH_CPU, 0x3000, CPUCL1), |
| SFR(DMYQCH_CON_CLUSTER1_QCH_DBG, 0x3004, CPUCL1), |
| SFR(QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1, 0x3020, CPUCL1), |
| SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1, 0x3024, CPUCL1), |
| SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1, 0x3028, CPUCL1), |
| SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1, 0x302c, CPUCL1), |
| SFR(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1, 0x3030, CPUCL1), |
| SFR(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH, 0x3034, CPUCL1), |
| SFR(QCH_CON_CPUCL1_CMU_CPUCL1_QCH, 0x3038, CPUCL1), |
| SFR(QCH_CON_LHM_AXI_P_CPUCL1_QCH, 0x303c, CPUCL1), |
| SFR(QCH_CON_PMU_CPUCL1_QCH, 0x3040, CPUCL1), |
| SFR(QCH_CON_SYSREG_CPUCL1_QCH, 0x3044, CPUCL1), |
| SFR(CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG, 0x1804, DBG), |
| SFR(CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK, 0x2004, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK, 0x2074, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK, 0x204c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK, 0x2050, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK, 0x2054, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK, 0x2058, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK, 0x205c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK, 0x2060, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK, 0x2064, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK, 0x2068, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK, 0x206c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK, 0x2030, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK, 0x2070, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK, 0x2098, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK, 0x2094, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK, 0x2034, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG, 0x2038, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK, 0x2090, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK, 0x207c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK, 0x2084, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK, 0x209c, DBG), |
| SFR(CLKOUT_CON_BLK_DBG_CMU_CLKOUT0, 0x0810, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK, 0x2078, DBG), |
| SFR(CLKOUT_CON_BLK_DBG_CMU_CLKOUT1, 0x0814, DBG), |
| SFR(PLL_CON0_MUX_CLKCMU_DBG_BUS_USER, 0x0100, DBG), |
| SFR(PLL_CON2_MUX_CLKCMU_DBG_BUS_USER, 0x0108, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK, 0x2088, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK, 0x208c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK, 0x203c, DBG), |
| SFR(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK, 0x2044, DBG), |
| SFR(QCH_CON_CSSYS_QCH, 0x3030, DBG), |
| SFR(QCH_CON_DBG_CMU_DBG_QCH, 0x3034, DBG), |
| SFR(QCH_CON_DUMPPC_CPUCL0_QCH, 0x3038, DBG), |
| SFR(QCH_CON_DUMPPC_CPUCL1_QCH, 0x303c, DBG), |
| SFR(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH, 0x3040, DBG), |
| SFR(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH, 0x3044, DBG), |
| SFR(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH, 0x3048, DBG), |
| SFR(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH, 0x304c, DBG), |
| SFR(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH, 0x3050, DBG), |
| SFR(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH, 0x3054, DBG), |
| SFR(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH, 0x3058, DBG), |
| SFR(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH, 0x305c, DBG), |
| SFR(QCH_CON_LHM_ATB_T_AUD_QCH, 0x3060, DBG), |
| SFR(QCH_CON_LHM_ATB_T_BDU_QCH, 0x3064, DBG), |
| SFR(QCH_CON_LHM_AXI_P_DBG_QCH, 0x3068, DBG), |
| SFR(QCH_CON_LHS_AXI_G_CSSYS_QCH, 0x306c, DBG), |
| SFR(QCH_CON_LHS_AXI_G_ETR_QCH, 0x3070, DBG), |
| SFR(QCH_CON_PMU_DBG_QCH, 0x3074, DBG), |
| SFR(QCH_CON_SECJTAG_QCH, 0x3078, DBG), |
| SFR(QCH_CON_STM_TXACTOR_QCH, 0x307c, DBG), |
| SFR(QCH_CON_SYSREG_DBG_QCH, 0x3080, DBG), |
| SFR(CLK_CON_DIV_DIV_CLK_DCAM_BUSP, 0x1800, DCAM), |
| SFR(PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER, 0x0100, DCAM), |
| SFR(PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER, 0x0108, DCAM), |
| SFR(CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK, 0x2000, DCAM), |
| SFR(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0, 0x0810, DCAM), |
| SFR(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1, 0x0814, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK, 0x2028, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK, 0x2038, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK, 0x2058, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK, 0x2018, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK, 0x201c, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS, 0x2014, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM, 0x2010, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK, 0x205c, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK, 0x203c, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK, 0x2040, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, 0x202c, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, 0x2034, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK, 0x2044, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK, 0x204c, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK, 0x2050, DCAM), |
| SFR(PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER, 0x0120, DCAM), |
| SFR(PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER, 0x0128, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK, 0x2048, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, 0x2030, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK, 0x2054, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK, 0x2020, DCAM), |
| SFR(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK, 0x2024, DCAM), |
| SFR(QCH_CON_BTM_DCAM_QCH, 0x3004, DCAM), |
| SFR(QCH_CON_DCAM_CMU_DCAM_QCH, 0x3008, DCAM), |
| SFR(QCH_CON_DCP_QCH, 0x300c, DCAM), |
| SFR(QCH_CON_LHM_AXI_P_SRDZDCAM_QCH, 0x3010, DCAM), |
| SFR(QCH_CON_LHS_ATB_DCAMSRDZ_QCH, 0x3014, DCAM), |
| SFR(QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH, 0x3018, DCAM), |
| SFR(QCH_CON_PMU_DCAM_QCH, 0x301c, DCAM), |
| SFR(QCH_CON_BCM_DCAM_QCH, 0x3020, DCAM), |
| SFR(QCH_CON_SYSREG_DCAM_QCH, 0x3024, DCAM), |
| SFR(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 0x0100, DPU0), |
| SFR(PLL_CON2_MUX_CLKCMU_DPU_BUS_USER, 0x0108, DPU0), |
| SFR(CLK_CON_GAT_CLKCMU_DPU1_BUSD, 0x2000, DPU0), |
| SFR(CLK_CON_DIV_DIV_CLK_DPU0_BUSP, 0x1808, DPU0), |
| SFR(CLK_CON_GAT_CLKCMU_DPU1_BUSP, 0x2004, DPU0), |
| SFR(CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK, 0x2008, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK, 0x207c, DPU0), |
| SFR(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0, 0x0810, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK, 0x205c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK, 0x2060, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK, 0x2064, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK, 0x2068, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK, 0x20bc, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK, 0x2108, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK, 0x2058, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK, 0x2054, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE, 0x20e8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE, 0x20e4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK, 0x20e0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE, 0x20f4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE, 0x20f0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK, 0x20a8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK, 0x20ac, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK, 0x20b0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK, 0x210c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS, 0x2018, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM, 0x2014, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS, 0x2020, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM, 0x201c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS, 0x204c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS, 0x2050, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS, 0x2028, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM, 0x2024, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS, 0x2030, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM, 0x202c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK, 0x2088, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK, 0x2080, DPU0), |
| SFR(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1, 0x0814, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK, 0x2084, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK, 0x20a4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0, 0x208c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1, 0x2090, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2, 0x2094, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB, 0x20a0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF, 0x2098, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR, 0x209c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK, 0x20b4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK, 0x20b8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK, 0x206c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK, 0x2070, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK, 0x20f8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE, 0x2100, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE, 0x20fc, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM, 0x203c, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS, 0x2040, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM, 0x2034, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS, 0x2038, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM, 0x2044, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS, 0x2048, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK, 0x20ec, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK, 0x20c0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK, 0x20c4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK, 0x20c8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK, 0x20cc, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK, 0x20d0, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK, 0x20d4, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK, 0x20d8, DPU0), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK, 0x20dc, DPU0), |
| SFR(QCH_CON_BTM_DPUD0_QCH, 0x3004, DPU0), |
| SFR(QCH_CON_BTM_DPUD1_QCH, 0x3008, DPU0), |
| SFR(QCH_CON_BTM_DPUD2_QCH, 0x300c, DPU0), |
| SFR(QCH_CON_DECON0_QCH, 0x3014, DPU0), |
| SFR(QCH_CON_DPP_QCH_DPP_G0, 0x3018, DPU0), |
| SFR(QCH_CON_DPP_QCH_DPP_G1, 0x301c, DPU0), |
| SFR(QCH_CON_DPP_QCH_DPP_VGR, 0x3020, DPU0), |
| SFR(QCH_CON_DPU0_CMU_DPU0_QCH, 0x3024, DPU0), |
| SFR(QCH_CON_DPU_DMA_QCH, 0x3028, DPU0), |
| SFR(QCH_CON_DPU_WB_MUX_QCH, 0x302c, DPU0), |
| SFR(QCH_CON_LHM_AXI_P0_DPU_QCH, 0x3030, DPU0), |
| SFR(QCH_CON_LHS_AXI_D0_DPU_QCH, 0x3034, DPU0), |
| SFR(QCH_CON_LHS_AXI_D1_DPU_QCH, 0x3038, DPU0), |
| SFR(QCH_CON_LHS_AXI_D2_DPU_QCH, 0x303c, DPU0), |
| SFR(QCH_CON_LHS_AXI_D_USBTV_QCH, 0x3040, DPU0), |
| SFR(QCH_CON_PMU_DPU0_QCH, 0x304c, DPU0), |
| SFR(QCH_CON_BCM_DPUD0_QCH, 0x3050, DPU0), |
| SFR(QCH_CON_BCM_DPUD1_QCH, 0x3054, DPU0), |
| SFR(QCH_CON_BCM_DPUD2_QCH, 0x3058, DPU0), |
| SFR(QCH_CON_SYSMMU_DPUD0_QCH, 0x305c, DPU0), |
| SFR(QCH_CON_SYSMMU_DPUD1_QCH, 0x3060, DPU0), |
| SFR(QCH_CON_SYSMMU_DPUD2_QCH, 0x3064, DPU0), |
| SFR(QCH_CON_SYSREG_DPU0_QCH, 0x3068, DPU0), |
| SFR(PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER, 0x0100, DPU1), |
| SFR(PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER, 0x0108, DPU1), |
| SFR(PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER, 0x0120, DPU1), |
| SFR(PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER, 0x0128, DPU1), |
| SFR(CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK, 0x2000, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK, 0x201c, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK, 0x2020, DPU1), |
| SFR(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0, 0x0810, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK, 0x2048, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK, 0x2034, DPU1), |
| SFR(PLL_CON0_PLL_DPU, 0x0140, DPU1), |
| SFR(PLL_LOCKTIME_PLL_DPU, 0x0000, DPU1), |
| SFR(CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2, 0x1800, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK, 0x2018, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK, 0x202c, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS, 0x200c, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM, 0x2008, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS, 0x2014, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM, 0x2010, DPU1), |
| SFR(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1, 0x0814, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK, 0x2038, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK, 0x203c, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK, 0x2040, DPU1), |
| SFR(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK, 0x2024, DPU1), |
| SFR(QCH_CON_DECON1_QCH, 0x3004, DPU1), |
| SFR(QCH_CON_DECON2_QCH_ACLK, 0x3008, DPU1), |
| SFR(QCH_CON_DECON2_QCH_VCLK, 0x300c, DPU1), |
| SFR(QCH_CON_DPU1_CMU_DPU1_QCH, 0x3010, DPU1), |
| SFR(QCH_CON_LHM_AXI_P_DPU1_QCH, 0x3014, DPU1), |
| SFR(QCH_CON_LHS_ATB_DPTX_QCH, 0x3018, DPU1), |
| SFR(QCH_CON_PMU_DPU1_QCH, 0x301c, DPU1), |
| SFR(QCH_CON_SYSREG_DPU1_QCH, 0x3020, DPU1), |
| SFR(CLK_CON_DIV_DIV_CLK_DSP_BUSP, 0x1800, DSP), |
| SFR(PLL_CON0_MUX_CLKCMU_DSP_BUS_USER, 0x0100, DSP), |
| SFR(PLL_CON2_MUX_CLKCMU_DSP_BUS_USER, 0x0108, DSP), |
| SFR(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK, 0x2000, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK, 0x2054, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK, 0x2040, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK, 0x2064, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK, 0x2018, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS, 0x2014, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM, 0x2010, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK, 0x206c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK, 0x2044, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK, 0x2048, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK, 0x2058, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE, 0x205c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK, 0x201c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK, 0x202c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK, 0x2020, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE, 0x2060, DSP), |
| SFR(CLKOUT_CON_BLK_DSP_CMU_CLKOUT0, 0x0810, DSP), |
| SFR(CLKOUT_CON_BLK_DSP_CMU_CLKOUT1, 0x0814, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK, 0x2034, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK, 0x204c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK, 0x2050, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK, 0x2070, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK, 0x2074, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK, 0x2024, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK, 0x2028, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK, 0x2030, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK, 0x2038, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK, 0x203c, DSP), |
| SFR(CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK, 0x2068, DSP), |
| SFR(QCH_CON_BTM_SCORE_QCH, 0x3000, DSP), |
| SFR(QCH_CON_DSP_CMU_DSP_QCH, 0x3004, DSP), |
| SFR(QCH_CON_LHM_AXI_D_IVADSP_QCH, 0x3008, DSP), |
| SFR(QCH_CON_LHM_AXI_D_VPUDSP_QCH, 0x300c, DSP), |
| SFR(QCH_CON_LHM_AXI_P_DSP_QCH, 0x3010, DSP), |
| SFR(QCH_CON_LHM_AXI_P_IVADSP_QCH, 0x3014, DSP), |
| SFR(QCH_CON_LHS_ACEL_D_DSP_QCH, 0x3018, DSP), |
| SFR(QCH_CON_LHS_AXI_P_DSPIVA_QCH, 0x301c, DSP), |
| SFR(QCH_CON_LHS_AXI_P_DSPVPU_QCH, 0x3020, DSP), |
| SFR(QCH_CON_PMU_DSP_QCH, 0x3024, DSP), |
| SFR(QCH_CON_BCM_SCORE_QCH, 0x3028, DSP), |
| SFR(QCH_CON_SCORE_QCH, 0x302c, DSP), |
| SFR(QCH_CON_SMMU_SCORE_QCH, 0x3030, DSP), |
| SFR(QCH_CON_SYSREG_DSP_QCH, 0x3034, DSP), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, 0x0160, FSYS0), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER, 0x0168, FSYS0), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER, 0x0140, FSYS0), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER, 0x0148, FSYS0), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER, 0x0100, FSYS0), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER, 0x0108, FSYS0), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER, 0x0180, FSYS0), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER, 0x0188, FSYS0), |
| SFR(CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK, 0x2000, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK, 0x204c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK, 0x2010, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK, 0x2044, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK, 0x2048, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK, 0x2040, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK, 0x2090, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK, 0x2014, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK, 0x2018, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK, 0x201c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 0x2034, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 0x2038, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK, 0x203c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK, 0x2050, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN, 0x2054, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK, 0x2058, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK, 0x2068, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK, 0x205c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK, 0x2060, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK, 0x206c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO, 0x2070, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK, 0x2094, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK, 0x2098, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK, 0x209c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK, 0x2088, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK, 0x2080, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK, 0x207c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK, 0x2020, FSYS0), |
| SFR(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0, 0x0810, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK, 0x2024, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK, 0x2084, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK, 0x208c, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK, 0x2078, FSYS0), |
| SFR(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1, 0x0814, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK, 0x2064, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK, 0x2074, FSYS0), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER, 0x0120, FSYS0), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER, 0x0128, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK, 0x2030, FSYS0), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK, 0x202c, FSYS0), |
| SFR(QCH_CON_BTM_FSYS0_QCH, 0x3004, FSYS0), |
| SFR(QCH_CON_DP_LINK_QCH, 0x3008, FSYS0), |
| SFR(QCH_CON_ETR_MIU_QCH_PCLK, 0x3010, FSYS0), |
| SFR(QCH_CON_ETR_MIU_QCH_ACLK, 0x300c, FSYS0), |
| SFR(QCH_CON_FSYS0_CMU_FSYS0_QCH, 0x3014, FSYS0), |
| SFR(QCH_CON_GPIO_FSYS0_QCH, 0x3018, FSYS0), |
| SFR(QCH_CON_LHM_AXI_D_USBTV_QCH, 0x301c, FSYS0), |
| SFR(QCH_CON_LHM_AXI_G_ETR_QCH, 0x3020, FSYS0), |
| SFR(QCH_CON_LHM_AXI_P_FSYS0_QCH, 0x3024, FSYS0), |
| SFR(QCH_CON_LHS_ACEL_D_FSYS0_QCH, 0x3028, FSYS0), |
| SFR(QCH_CON_MMC_EMBD_QCH, 0x302c, FSYS0), |
| SFR(QCH_CON_PMU_FSYS0_QCH, 0x3030, FSYS0), |
| SFR(QCH_CON_BCM_FSYS0_QCH, 0x3034, FSYS0), |
| SFR(QCH_CON_SYSREG_FSYS0_QCH, 0x3038, FSYS0), |
| SFR(QCH_CON_UFS_EMBD_QCH, 0x303c, FSYS0), |
| SFR(QCH_CON_UFS_EMBD_QCH_FMP, 0x3040, FSYS0), |
| SFR(QCH_CON_USBTV_QCH_USB30DRD_LINK, 0x3044, FSYS0), |
| SFR(QCH_CON_USBTV_QCH_USBTV_HOST, 0x304c, FSYS0), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER, 0x0100, FSYS1), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER, 0x0108, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK, 0x2024, FSYS1), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER, 0x0120, FSYS1), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER, 0x0128, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK, 0x2034, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN, 0x2038, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK, 0x2044, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK, 0x2094, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK, 0x2098, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK, 0x2084, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK, 0x2088, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK, 0x2080, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK, 0x207c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK, 0x2090, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK, 0x2068, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK, 0x2028, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK, 0x2030, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK, 0x202c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK, 0x20a8, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK, 0x20ac, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK, 0x206c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK, 0x2070, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK, 0x200c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK, 0x2010, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK, 0x2008, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK, 0x2014, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK, 0x2018, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK, 0x201c, FSYS1), |
| SFR(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0, 0x0810, FSYS1), |
| SFR(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN, 0x2000, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0, 0x205c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0, 0x2048, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0, 0x203c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK, 0x2050, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL, 0x2058, FSYS1), |
| SFR(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1, 0x0814, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK, 0x2074, FSYS1), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER, 0x0140, FSYS1), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER, 0x0148, FSYS1), |
| SFR(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER, 0x0160, FSYS1), |
| SFR(PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER, 0x0168, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1, 0x204c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1, 0x2060, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1, 0x2040, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK, 0x2054, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK, 0x209c, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK, 0x20a4, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO, 0x20a0, FSYS1), |
| SFR(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM, 0x2004, FSYS1), |
| SFR(QCH_CON_ADM_AHB_SSS_QCH, 0x3008, FSYS1), |
| SFR(QCH_CON_BTM_FSYS1_QCH, 0x300c, FSYS1), |
| SFR(QCH_CON_FSYS1_CMU_FSYS1_QCH, 0x3010, FSYS1), |
| SFR(QCH_CON_GPIO_FSYS1_QCH, 0x3014, FSYS1), |
| SFR(QCH_CON_LHM_AXI_P_FSYS1_QCH, 0x3018, FSYS1), |
| SFR(QCH_CON_LHS_ACEL_D_FSYS1_QCH, 0x301c, FSYS1), |
| SFR(QCH_CON_MMC_CARD_QCH, 0x3020, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE0_MSTR, 0x302c, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE_PCS, 0x303c, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE_PHY, 0x3040, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE0_DBI, 0x3028, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE0_APB, 0x3024, FSYS1), |
| SFR(DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL, 0x3000, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE1_MSTR, 0x3038, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE1_DBI, 0x3034, FSYS1), |
| SFR(QCH_CON_PCIE_QCH_PCIE1_APB, 0x3030, FSYS1), |
| SFR(QCH_CON_PMU_FSYS1_QCH, 0x3044, FSYS1), |
| SFR(QCH_CON_BCM_FSYS1_QCH, 0x3048, FSYS1), |
| SFR(QCH_CON_RTIC_QCH, 0x304c, FSYS1), |
| SFR(QCH_CON_SSS_QCH, 0x3050, FSYS1), |
| SFR(QCH_CON_SYSREG_FSYS1_QCH, 0x3054, FSYS1), |
| SFR(QCH_CON_TOE_WIFI0_QCH, 0x3058, FSYS1), |
| SFR(QCH_CON_TOE_WIFI1_QCH, 0x305c, FSYS1), |
| SFR(QCH_CON_UFS_CARD_QCH, 0x3060, FSYS1), |
| SFR(QCH_CON_UFS_CARD_QCH_FMP, 0x3064, FSYS1), |
| SFR(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER, 0x0100, G2D), |
| SFR(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER, 0x0108, G2D), |
| SFR(CLK_CON_DIV_DIV_CLK_G2D_BUSP, 0x1804, G2D), |
| SFR(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK, 0x2000, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK, 0x2068, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK, 0x206c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK, 0x2070, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK, 0x2074, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK, 0x209c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE, 0x20a0, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK, 0x20c0, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK, 0x2054, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK, 0x2058, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK, 0x2050, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM, 0x2010, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS, 0x2014, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK, 0x2028, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK, 0x2048, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE, 0x20ac, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK, 0x20a8, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK, 0x2064, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK, 0x2030, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK, 0x2038, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK, 0x20c8, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK, 0x202c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK, 0x2034, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK, 0x203c, G2D), |
| SFR(PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER, 0x0120, G2D), |
| SFR(PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER, 0x0128, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK, 0x204c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK, 0x2060, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK, 0x2040, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK, 0x2044, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK, 0x2080, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK, 0x2084, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK, 0x2088, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK, 0x208c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK, 0x20b4, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE, 0x20b8, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK, 0x2078, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK, 0x207c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK, 0x205c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM, 0x2018, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS, 0x201c, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK, 0x20c4, G2D), |
| SFR(CLKOUT_CON_BLK_G2D_CMU_CLKOUT0, 0x0810, G2D), |
| SFR(CLKOUT_CON_BLK_G2D_CMU_CLKOUT1, 0x0814, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE, 0x20a4, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE, 0x20b0, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE, 0x20bc, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS, 0x2024, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM, 0x2020, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK, 0x2094, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK, 0x2090, G2D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK, 0x2098, G2D), |
| SFR(QCH_CON_BTM_G2DD0_QCH, 0x3000, G2D), |
| SFR(QCH_CON_BTM_G2DD1_QCH, 0x3004, G2D), |
| SFR(QCH_CON_BTM_G2DD2_QCH, 0x3008, G2D), |
| SFR(QCH_CON_G2D_QCH, 0x3010, G2D), |
| SFR(QCH_CON_G2D_CMU_G2D_QCH, 0x300c, G2D), |
| SFR(QCH_CON_JPEG_QCH, 0x3014, G2D), |
| SFR(QCH_CON_LHM_AXI_P_G2D_QCH, 0x3018, G2D), |
| SFR(QCH_CON_LHS_ACEL_D0_G2D_QCH, 0x301c, G2D), |
| SFR(QCH_CON_LHS_ACEL_D1_G2D_QCH, 0x3020, G2D), |
| SFR(QCH_CON_LHS_ACEL_D2_G2D_QCH, 0x3024, G2D), |
| SFR(QCH_CON_M2MSCALER_QCH, 0x3028, G2D), |
| SFR(QCH_CON_PMU_G2D_QCH, 0x302c, G2D), |
| SFR(QCH_CON_BCM_G2DD0_QCH, 0x3030, G2D), |
| SFR(QCH_CON_BCM_G2DD1_QCH, 0x3034, G2D), |
| SFR(QCH_CON_BCM_G2DD2_QCH, 0x3038, G2D), |
| SFR(QCH_CON_QE_JPEG_QCH, 0x303c, G2D), |
| SFR(QCH_CON_QE_M2MSCALER_QCH, 0x3040, G2D), |
| SFR(QCH_CON_SMMU_G2DD0_QCH, 0x3044, G2D), |
| SFR(QCH_CON_SMMU_G2DD1_QCH, 0x3048, G2D), |
| SFR(QCH_CON_SMMU_G2DD2_QCH, 0x304c, G2D), |
| SFR(QCH_CON_SYSREG_G2D_QCH, 0x3050, G2D), |
| SFR(CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0x1804, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK, 0x2020, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK, 0x203c, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK, 0x202c, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK, 0x2028, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0, 0x0810, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK, 0x2024, G3D), |
| SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, G3D), |
| SFR(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 0x0100, G3D), |
| SFR(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER, 0x0108, G3D), |
| SFR(CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0x1000, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1, 0x0814, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK, 0x2030, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK, 0x2038, G3D), |
| SFR(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK, 0x2034, G3D), |
| SFR(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK, 0x2004, G3D), |
| SFR(PLL_CON0_PLL_G3D, 0x0120, G3D), |
| SFR(PLL_LOCKTIME_PLL_G3D, 0x0000, G3D), |
| SFR(CLK_CON_GAT_GATE_CLK_G3D_AGPU, 0x201c, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0, 0x0818, G3D), |
| SFR(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1, 0x081c, G3D), |
| SFR(QCH_CON_AGPU_QCH_G3D, 0x3010, G3D), |
| SFR(QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR, 0x3014, G3D), |
| SFR(QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D, 0x3018, G3D), |
| SFR(QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D, 0x301c, G3D), |
| SFR(QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D, 0x3020, G3D), |
| SFR(QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D, 0x3024, G3D), |
| SFR(QCH_CON_BUSIF_HPMG3D_QCH, 0x3028, G3D), |
| SFR(QCH_CON_G3D_CMU_G3D_QCH, 0x302c, G3D), |
| SFR(QCH_CON_LHM_AXI_P_G3D_QCH, 0x3030, G3D), |
| SFR(QCH_CON_LHS_AXI_G3DSFR_QCH, 0x3034, G3D), |
| SFR(QCH_CON_PMU_G3D_QCH, 0x3038, G3D), |
| SFR(QCH_CON_SYSREG_G3D_QCH, 0x303c, G3D), |
| SFR(PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER, 0x0100, IMEM), |
| SFR(PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER, 0x0108, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK, 0x2018, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK, 0x2020, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK, 0x2010, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK, 0x2028, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK, 0x2024, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK, 0x201c, IMEM), |
| SFR(CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK, 0x2000, IMEM), |
| SFR(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0, 0x0810, IMEM), |
| SFR(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1, 0x0814, IMEM), |
| SFR(CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK, 0x2014, IMEM), |
| SFR(QCH_CON_IMEM_CMU_IMEM_QCH, 0x3000, IMEM), |
| SFR(QCH_CON_INTMEM_QCH, 0x3004, IMEM), |
| SFR(QCH_CON_LHM_AXI_P_IMEM_QCH, 0x3008, IMEM), |
| SFR(QCH_CON_PMU_IMEM_QCH, 0x300c, IMEM), |
| SFR(QCH_CON_SYSREG_IMEM_QCH, 0x3010, IMEM), |
| SFR(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER, 0x0100, ISPHQ), |
| SFR(PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER, 0x0108, ISPHQ), |
| SFR(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP, 0x1800, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK, 0x2040, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK, 0x2048, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, 0x204c, ISPHQ), |
| SFR(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0, 0x0810, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK, 0x202c, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK, 0x2030, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK, 0x2038, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK, 0x2044, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK, 0x2028, ISPHQ), |
| SFR(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1, 0x0814, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK, 0x2054, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK, 0x2058, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM, 0x2018, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM, 0x2020, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS, 0x201c, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS, 0x2024, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK, 0x2034, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK, 0x203c, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK, 0x2050, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK, 0x205c, ISPHQ), |
| SFR(CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK, 0x2004, ISPHQ), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK, 0x2014, ISPHQ), |
| SFR(QCH_CON_ISPHQ_CMU_ISPHQ_QCH, 0x3000, ISPHQ), |
| SFR(QCH_CON_ISP_EWGEN_ISPHQ_QCH, 0x3004, ISPHQ), |
| SFR(QCH_CON_IS_ISPHQ_QCH_3AA, 0x3008, ISPHQ), |
| SFR(QCH_CON_IS_ISPHQ_QCH_ISPHQ, 0x300c, ISPHQ), |
| SFR(QCH_CON_IS_ISPHQ_QCH_QE_3AA, 0x3010, ISPHQ), |
| SFR(QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ, 0x3014, ISPHQ), |
| SFR(QCH_CON_LHM_AXI_P_ISPHQ_QCH, 0x3018, ISPHQ), |
| SFR(QCH_CON_LHS_AXI_LD_ISPHQ_QCH, 0x301c, ISPHQ), |
| SFR(QCH_CON_PMU_ISPHQ_QCH, 0x3020, ISPHQ), |
| SFR(QCH_CON_SYSREG_ISPHQ_QCH, 0x3024, ISPHQ), |
| SFR(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER, 0x0100, ISPLP), |
| SFR(PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER, 0x0108, ISPLP), |
| SFR(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP, 0x1800, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK, 0x2058, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK, 0x2064, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK, 0x2068, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK, 0x2010, ISPLP), |
| SFR(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0, 0x0810, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK, 0x2030, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK, 0x203c, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK, 0x205c, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK, 0x204c, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK, 0x2034, ISPLP), |
| SFR(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1, 0x0814, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK, 0x2070, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK, 0x2074, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM, 0x201c, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM, 0x2024, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK, 0x2014, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS, 0x2020, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS, 0x2028, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK, 0x2038, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK, 0x2040, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK, 0x2048, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE, 0x2050, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE, 0x2054, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK, 0x206c, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK, 0x2078, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK, 0x202c, ISPLP), |
| SFR(CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK, 0x2000, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK, 0x2060, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK, 0x2018, ISPLP), |
| SFR(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK, 0x2044, ISPLP), |
| SFR(QCH_CON_BTM_ISPLP_QCH, 0x3000, ISPLP), |
| SFR(QCH_CON_ISPLP_CMU_ISPLP_QCH, 0x3004, ISPLP), |
| SFR(QCH_CON_ISP_EWGEN_ISPLP_QCH, 0x3008, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_3AAW, 0x300c, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_ISPLP, 0x3010, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_QE_3AAW, 0x3018, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_QE_ISPLP, 0x301c, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP, 0x3020, ISPLP), |
| SFR(QCH_CON_IS_ISPLP_QCH_BCM_ISPLP, 0x3014, ISPLP), |
| SFR(QCH_CON_LHM_AXI_LD_ISPHQ_QCH, 0x3024, ISPLP), |
| SFR(QCH_CON_LHM_AXI_P_ISPLP_QCH, 0x3028, ISPLP), |
| SFR(QCH_CON_LHS_AXI_D_ISPLP_QCH, 0x302c, ISPLP), |
| SFR(QCH_CON_PMU_ISPLP_QCH, 0x3030, ISPLP), |
| SFR(QCH_CON_SYSREG_ISPLP_QCH, 0x3034, ISPLP), |
| SFR(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER, 0x0100, IVA), |
| SFR(PLL_CON2_MUX_CLKCMU_IVA_BUS_USER, 0x0108, IVA), |
| SFR(CLK_CON_DIV_DIV_CLK_IVA_BUSP, 0x1800, IVA), |
| SFR(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK, 0x2000, IVA), |
| SFR(CLKOUT_CON_BLK_IVA_CMU_CLKOUT0, 0x0810, IVA), |
| SFR(CLKOUT_CON_BLK_IVA_CMU_CLKOUT1, 0x0814, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK, 0x203c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK, 0x2040, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK, 0x2044, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK, 0x2034, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK, 0x2038, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK, 0x2020, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK, 0x2024, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK, 0x204c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK, 0x2050, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK, 0x205c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK, 0x2060, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK, 0x2068, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK, 0x206c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS, 0x2014, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM, 0x2010, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK, 0x2018, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK, 0x201c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK, 0x2064, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK, 0x2048, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A, 0x202c, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK, 0x2054, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK, 0x2058, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK, 0x2028, IVA), |
| SFR(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK, 0x2030, IVA), |
| SFR(QCH_CON_BTM_IVA_QCH, 0x3000, IVA), |
| SFR(QCH_CON_IVA_QCH, 0x300c, IVA), |
| SFR(QCH_CON_IVA_CMU_IVA_QCH, 0x3004, IVA), |
| SFR(QCH_CON_IVA_INTMEM_QCH, 0x3008, IVA), |
| SFR(QCH_CON_LHM_AXI_D_IVASC_QCH, 0x3010, IVA), |
| SFR(QCH_CON_LHM_AXI_P_DSPIVA_QCH, 0x3014, IVA), |
| SFR(QCH_CON_LHM_AXI_P_IVA_QCH, 0x3018, IVA), |
| SFR(QCH_CON_LHS_ACEL_D_IVA_QCH, 0x301c, IVA), |
| SFR(QCH_CON_LHS_AXI_D_IVADSP_QCH, 0x3020, IVA), |
| SFR(QCH_CON_LHS_AXI_P_IVADSP_QCH, 0x3024, IVA), |
| SFR(QCH_CON_PMU_IVA_QCH, 0x3028, IVA), |
| SFR(QCH_CON_BCM_IVA_QCH, 0x302c, IVA), |
| SFR(QCH_CON_SMMU_IVA_QCH, 0x3030, IVA), |
| SFR(QCH_CON_SYSREG_IVA_QCH, 0x3034, IVA), |
| SFR(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER, 0x0100, MFC), |
| SFR(PLL_CON2_MUX_CLKCMU_MFC_BUS_USER, 0x0108, MFC), |
| SFR(CLK_CON_DIV_DIV_CLK_MFC_BUSP, 0x1800, MFC), |
| SFR(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK, 0x2000, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK, 0x2038, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS, 0x2014, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM, 0x2010, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK, 0x2018, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK, 0x203c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK, 0x2070, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK, 0x2030, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK, 0x2034, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK, 0x202c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK, 0x2058, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE, 0x2060, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK, 0x2064, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE, 0x206c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK, 0x2040, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK, 0x2044, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK, 0x2048, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK, 0x204c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK, 0x201c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK, 0x2024, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK, 0x2020, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK, 0x2028, MFC), |
| SFR(CLKOUT_CON_BLK_MFC_CMU_CLKOUT0, 0x0810, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE, 0x205c, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE, 0x2068, MFC), |
| SFR(CLKOUT_CON_BLK_MFC_CMU_CLKOUT1, 0x0814, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK, 0x2050, MFC), |
| SFR(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK, 0x2054, MFC), |
| SFR(QCH_CON_BTM_MFCD0_QCH, 0x3000, MFC), |
| SFR(QCH_CON_BTM_MFCD1_QCH, 0x3004, MFC), |
| SFR(QCH_CON_LHM_AXI_P_MFC_QCH, 0x3010, MFC), |
| SFR(QCH_CON_LHS_AXI_D0_MFC_QCH, 0x3014, MFC), |
| SFR(QCH_CON_LHS_AXI_D1_MFC_QCH, 0x3018, MFC), |
| SFR(QCH_CON_MFC_QCH, 0x3020, MFC), |
| SFR(QCH_CON_MFC_CMU_MFC_QCH, 0x301c, MFC), |
| SFR(QCH_CON_PMU_MFC_QCH, 0x3024, MFC), |
| SFR(QCH_CON_BCM_MFCD0_QCH, 0x3028, MFC), |
| SFR(QCH_CON_BCM_MFCD1_QCH, 0x302c, MFC), |
| SFR(QCH_CON_SMMU_MFCD0_QCH, 0x3030, MFC), |
| SFR(QCH_CON_SMMU_MFCD1_QCH, 0x3034, MFC), |
| SFR(QCH_CON_SYSREG_MFC_QCH, 0x3038, MFC), |
| SFR(PLL_CON0_PLL_MIF, 0x0100, MIF), |
| SFR(PLL_LOCKTIME_PLL_MIF, 0x0000, MIF), |
| SFR(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X, 0x1000, MIF), |
| SFR(CLK_CON_DIV_CLK_MIF_BUSD, 0x1800, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_PRE, 0x1810, MIF), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF_BUSP, 0x1804, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK, 0x2010, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK, 0x2044, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK, 0x2064, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK, 0x2054, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK, 0x2040, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK, 0x2050, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK, 0x203c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK, 0x205c, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK, 0x2058, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK, 0x2030, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK, 0x2038, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK, 0x2034, MIF), |
| SFR(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0, 0x0810, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1, 0x2048, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2, 0x204c, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK, 0x2004, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK, 0x200c, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK, 0x2018, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK, 0x201c, MIF), |
| SFR(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1, 0x0814, MIF), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK, 0x2020, MIF), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK, 0x2060, MIF), |
| SFR(CLK_CON_MUX_MUX_MIF_CMUREF, 0x1004, MIF), |
| SFR(QCH_CON_APBBR_DDRPHY_QCH, 0x3004, MIF), |
| SFR(QCH_CON_APBBR_DMC_QCH, 0x300c, MIF), |
| SFR(QCH_CON_APBBR_DMCTZ_QCH, 0x3008, MIF), |
| SFR(QCH_CON_BUSIF_HPMMIF_QCH, 0x3010, MIF), |
| SFR(DMYQCH_CON_CMU_MIF_CMUREF_QCH, 0x3000, MIF), |
| SFR(QCH_CON_DDRPHY_QCH, 0x3014, MIF), |
| SFR(QCH_CON_DMC_QCH, 0x3018, MIF), |
| SFR(QCH_CON_LHM_AXI_P_MIF_QCH, 0x301c, MIF), |
| SFR(QCH_CON_MIF_CMU_MIF_QCH, 0x3020, MIF), |
| SFR(QCH_CON_PMU_MIF_QCH, 0x3024, MIF), |
| SFR(QCH_CON_BCMPPC_DEBUG_QCH, 0x3028, MIF), |
| SFR(QCH_CON_BCMPPC_DVFS_QCH, 0x302c, MIF), |
| SFR(QCH_CON_SYSREG_MIF_QCH, 0x3030, MIF), |
| SFR(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0, 0x0810, MIF1), |
| SFR(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1, 0x0814, MIF1), |
| SFR(CLK_CON_MUX_MUX_MIF1_CMUREF, 0x1004, MIF1), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF1_PRE, 0x1810, MIF1), |
| SFR(CLK_CON_DIV_CLK_MIF1_BUSD, 0x1800, MIF1), |
| SFR(PLL_CON0_PLL_MIF1, 0x0100, MIF1), |
| SFR(PLL_LOCKTIME_PLL_MIF1, 0x0000, MIF1), |
| SFR(CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X, 0x1000, MIF1), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF1_BUSP, 0x1804, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK, 0x2010, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK, 0x2030, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK, 0x2034, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK, 0x2038, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK, 0x203c, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK, 0x2040, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK, 0x2044, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1, 0x2048, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2, 0x204c, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK, 0x2050, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK, 0x2054, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK, 0x2058, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK, 0x205c, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK, 0x2064, MIF1), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK, 0x2060, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK, 0x2004, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK, 0x200c, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK, 0x2018, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK, 0x201c, MIF1), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK, 0x2020, MIF1), |
| SFR(QCH_CON_APBBR_DDRPHY1_QCH, 0x3004, MIF1), |
| SFR(QCH_CON_APBBR_DMC1_QCH, 0x3008, MIF1), |
| SFR(QCH_CON_APBBR_DMCTZ1_QCH, 0x300c, MIF1), |
| SFR(QCH_CON_BUSIF_HPMMIF1_QCH, 0x3010, MIF1), |
| SFR(DMYQCH_CON_CMU_MIF1_CMUREF_QCH, 0x3000, MIF1), |
| SFR(QCH_CON_DDRPHY1_QCH, 0x3014, MIF1), |
| SFR(QCH_CON_DMC1_QCH, 0x3018, MIF1), |
| SFR(QCH_CON_LHM_AXI_P_MIF1_QCH, 0x301c, MIF1), |
| SFR(QCH_CON_MIF1_CMU_MIF1_QCH, 0x3020, MIF1), |
| SFR(QCH_CON_PMU_MIF1_QCH, 0x3024, MIF1), |
| SFR(QCH_CON_BCMPPC_DEBUG1_QCH, 0x3028, MIF1), |
| SFR(QCH_CON_BCMPPC_DVFS1_QCH, 0x302c, MIF1), |
| SFR(QCH_CON_SYSREG_MIF1_QCH, 0x3030, MIF1), |
| SFR(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0, 0x0810, MIF2), |
| SFR(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1, 0x0814, MIF2), |
| SFR(CLK_CON_MUX_MUX_MIF2_CMUREF, 0x1004, MIF2), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF2_PRE, 0x1810, MIF2), |
| SFR(CLK_CON_DIV_CLK_MIF2_BUSD, 0x1800, MIF2), |
| SFR(PLL_CON0_PLL_MIF2, 0x0100, MIF2), |
| SFR(PLL_LOCKTIME_PLL_MIF2, 0x0000, MIF2), |
| SFR(CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X, 0x1000, MIF2), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF2_BUSP, 0x1804, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK, 0x2010, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK, 0x202c, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK, 0x2030, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK, 0x2034, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK, 0x2038, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK, 0x203c, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK, 0x2040, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1, 0x2044, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2, 0x2048, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK, 0x204c, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK, 0x2054, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK, 0x2058, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK, 0x205c, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK, 0x2060, MIF2), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK, 0x2064, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK, 0x2004, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK, 0x200c, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK, 0x2014, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK, 0x2018, MIF2), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK, 0x201c, MIF2), |
| SFR(QCH_CON_APBBR_DDRPHY2_QCH, 0x3004, MIF2), |
| SFR(QCH_CON_APBBR_DMC2_QCH, 0x3008, MIF2), |
| SFR(QCH_CON_APBBR_DMCTZ2_QCH, 0x300c, MIF2), |
| SFR(QCH_CON_BUSIF_HPMMIF2_QCH, 0x3010, MIF2), |
| SFR(DMYQCH_CON_CMU_MIF2_CMUREF_QCH, 0x3000, MIF2), |
| SFR(QCH_CON_DDRPHY2_QCH, 0x3014, MIF2), |
| SFR(QCH_CON_DMC2_QCH, 0x3018, MIF2), |
| SFR(QCH_CON_LHM_AXI_P_MIF2_QCH, 0x301c, MIF2), |
| SFR(QCH_CON_MIF2_CMU_MIF2_QCH, 0x3020, MIF2), |
| SFR(QCH_CON_PMU_MIF2_QCH, 0x3024, MIF2), |
| SFR(QCH_CON_BCMPPC_DEBUG2_QCH, 0x3028, MIF2), |
| SFR(QCH_CON_BCMPPC_DVFS2_QCH, 0x302c, MIF2), |
| SFR(QCH_CON_SYSREG_MIF2_QCH, 0x3030, MIF2), |
| SFR(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0, 0x0810, MIF3), |
| SFR(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1, 0x0814, MIF3), |
| SFR(CLK_CON_MUX_MUX_MIF3_CMUREF, 0x1004, MIF3), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF3_PRE, 0x1810, MIF3), |
| SFR(CLK_CON_DIV_CLK_MIF3_BUSD, 0x1800, MIF3), |
| SFR(PLL_CON0_PLL_MIF3, 0x0100, MIF3), |
| SFR(PLL_LOCKTIME_PLL_MIF3, 0x0000, MIF3), |
| SFR(CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X, 0x1000, MIF3), |
| SFR(CLK_CON_DIV_DIV_CLK_MIF3_BUSP, 0x1804, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C, 0x2008, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK, 0x202c, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK, 0x2030, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK, 0x2034, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK, 0x2038, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK, 0x203c, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK, 0x2040, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1, 0x2044, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK, 0x204c, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK, 0x2050, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK, 0x2054, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK, 0x2058, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK, 0x2060, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK, 0x2064, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2, 0x2048, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK, 0x2010, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK, 0x2004, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK, 0x200c, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK, 0x2018, MIF3), |
| SFR(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK, 0x201c, MIF3), |
| SFR(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK, 0x205c, MIF3), |
| SFR(QCH_CON_APBBR_DDRPHY3_QCH, 0x3004, MIF3), |
| SFR(QCH_CON_APBBR_DMC3_QCH, 0x3008, MIF3), |
| SFR(QCH_CON_APBBR_DMCTZ3_QCH, 0x300c, MIF3), |
| SFR(QCH_CON_BUSIF_HPMMIF3_QCH, 0x3010, MIF3), |
| SFR(DMYQCH_CON_CMU_MIF3_CMUREF_QCH, 0x3000, MIF3), |
| SFR(QCH_CON_DDRPHY3_QCH, 0x3014, MIF3), |
| SFR(QCH_CON_DMC3_QCH, 0x3018, MIF3), |
| SFR(QCH_CON_LHM_AXI_P_MIF3_QCH, 0x301c, MIF3), |
| SFR(QCH_CON_MIF3_CMU_MIF3_QCH, 0x3020, MIF3), |
| SFR(QCH_CON_PMU_MIF3_QCH, 0x3024, MIF3), |
| SFR(QCH_CON_BCMPPC_DEBUG3_QCH, 0x3028, MIF3), |
| SFR(QCH_CON_BCMPPC_DVFS3_QCH, 0x302c, MIF3), |
| SFR(QCH_CON_SYSREG_MIF3_QCH, 0x3030, MIF3), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 0x0100, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER, 0x0108, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK, 0x201c, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK, 0x2018, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK, 0x2020, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0, 0x2028, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK, 0x2034, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK, 0x203c, PERIC0), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER, 0x0120, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER, 0x0128, PERIC0), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER, 0x0140, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER, 0x0148, PERIC0), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER, 0x0160, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER, 0x0168, PERIC0), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER, 0x0180, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER, 0x0188, PERIC0), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER, 0x01a0, PERIC0), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER, 0x01a8, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK, 0x2038, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK, 0x2040, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI, 0x2044, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK, 0x2048, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI, 0x204c, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK, 0x2050, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI, 0x2054, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK, 0x2058, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI, 0x205c, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK, 0x2014, PERIC0), |
| SFR(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK, 0x2000, PERIC0), |
| SFR(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0, 0x0810, PERIC0), |
| SFR(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1, 0x0814, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK, 0x202c, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK, 0x2030, PERIC0), |
| SFR(QCH_CON_GPIO_PERIC0_QCH, 0x3000, PERIC0), |
| SFR(QCH_CON_LHM_AXI_P_PERIC0_QCH, 0x3004, PERIC0), |
| SFR(QCH_CON_PERIC0_CMU_PERIC0_QCH, 0x3008, PERIC0), |
| SFR(QCH_CON_PMU_PERIC0_QCH, 0x300c, PERIC0), |
| SFR(QCH_CON_PWM_QCH, 0x3010, PERIC0), |
| SFR(QCH_CON_SPEEDY2_TSP_QCH, 0x3014, PERIC0), |
| SFR(QCH_CON_SYSREG_PERIC0_QCH, 0x3018, PERIC0), |
| SFR(QCH_CON_UART_DBG_QCH, 0x301c, PERIC0), |
| SFR(QCH_CON_USI00_QCH, 0x3020, PERIC0), |
| SFR(QCH_CON_USI01_QCH, 0x3024, PERIC0), |
| SFR(QCH_CON_USI02_QCH, 0x3028, PERIC0), |
| SFR(QCH_CON_USI03_QCH, 0x302c, PERIC0), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK, 0x2020, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK, 0x203c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK, 0x2028, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK, 0x2040, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK, 0x2078, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK, 0x2080, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK, 0x20b4, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK, 0x20bc, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK, 0x20c4, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK, 0x20cc, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK, 0x208c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK, 0x2094, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK, 0x209c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK, 0x20a4, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK, 0x20ac, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK, 0x20d4, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER, 0x0180, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER, 0x0188, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK, 0x201c, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER, 0x01c0, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER, 0x01c8, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER, 0x01e0, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER, 0x01e8, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER, 0x0200, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER, 0x0208, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER, 0x0220, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER, 0x0228, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER, 0x0240, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER, 0x0248, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER, 0x0260, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER, 0x0268, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER, 0x0280, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER, 0x0288, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER, 0x02a0, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER, 0x02a8, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER, 0x02c0, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER, 0x02c8, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK, 0x207c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI, 0x20b8, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI, 0x20c0, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI, 0x20c8, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI, 0x20d0, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI, 0x2088, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI, 0x2090, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI, 0x2098, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI, 0x20a0, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI, 0x20a8, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI, 0x20b0, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 0x0100, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER, 0x0108, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER, 0x01a0, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER, 0x01a8, PERIC1), |
| SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK, 0x2000, PERIC1), |
| SFR(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0, 0x0810, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK, 0x2034, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK, 0x2038, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK, 0x2068, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK, 0x2070, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER, 0x0140, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER, 0x0148, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER, 0x0160, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER, 0x0168, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK, 0x206c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK, 0x2074, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK, 0x2084, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK, 0x2030, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK, 0x202c, PERIC1), |
| SFR(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1, 0x0814, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK, 0x2044, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK, 0x2058, PERIC1), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER, 0x0120, PERIC1), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER, 0x0128, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK, 0x205c, PERIC1), |
| SFR(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK, 0x200c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK, 0x2048, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK, 0x204c, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK, 0x2050, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK, 0x2054, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK, 0x2060, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK, 0x2064, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK, 0x2024, PERIC1), |
| SFR(QCH_CON_GPIO_PERIC1_QCH, 0x3000, PERIC1), |
| SFR(QCH_CON_HSI2C_CAM0_QCH, 0x3004, PERIC1), |
| SFR(QCH_CON_HSI2C_CAM1_QCH, 0x3008, PERIC1), |
| SFR(QCH_CON_HSI2C_CAM2_QCH, 0x300c, PERIC1), |
| SFR(QCH_CON_HSI2C_CAM3_QCH, 0x3010, PERIC1), |
| SFR(QCH_CON_LHM_AXI_P_PERIC1_QCH, 0x3014, PERIC1), |
| SFR(QCH_CON_PERIC1_CMU_PERIC1_QCH, 0x3018, PERIC1), |
| SFR(QCH_CON_PMU_PERIC1_QCH, 0x301c, PERIC1), |
| SFR(QCH_CON_SPEEDY2_DDI_QCH, 0x3028, PERIC1), |
| SFR(QCH_CON_SPEEDY2_DDI1_QCH, 0x3020, PERIC1), |
| SFR(QCH_CON_SPEEDY2_DDI2_QCH, 0x3024, PERIC1), |
| SFR(QCH_CON_SPEEDY2_TSP1_QCH, 0x302c, PERIC1), |
| SFR(QCH_CON_SPEEDY2_TSP2_QCH, 0x3030, PERIC1), |
| SFR(QCH_CON_SPI_CAM0_QCH, 0x3034, PERIC1), |
| SFR(QCH_CON_SPI_CAM1_QCH, 0x3038, PERIC1), |
| SFR(QCH_CON_SYSREG_PERIC1_QCH, 0x303c, PERIC1), |
| SFR(QCH_CON_UART_BT_QCH, 0x3040, PERIC1), |
| SFR(QCH_CON_USI04_QCH, 0x3044, PERIC1), |
| SFR(QCH_CON_USI05_QCH, 0x3048, PERIC1), |
| SFR(QCH_CON_USI06_QCH, 0x304c, PERIC1), |
| SFR(QCH_CON_USI07_QCH, 0x3050, PERIC1), |
| SFR(QCH_CON_USI08_QCH, 0x3054, PERIC1), |
| SFR(QCH_CON_USI09_QCH, 0x3058, PERIC1), |
| SFR(QCH_CON_USI10_QCH, 0x305c, PERIC1), |
| SFR(QCH_CON_USI11_QCH, 0x3060, PERIC1), |
| SFR(QCH_CON_USI12_QCH, 0x3064, PERIC1), |
| SFR(QCH_CON_USI13_QCH, 0x3068, PERIC1), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK, 0x2018, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK, 0x201c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK, 0x2028, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK, 0x2090, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK, 0x202c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK, 0x2034, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK, 0x2038, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK, 0x2020, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK, 0x2044, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK, 0x2048, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK, 0x204c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK, 0x2070, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK, 0x2074, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK, 0x2078, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK, 0x207c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK, 0x2080, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK, 0x2084, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK, 0x2050, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK, 0x2054, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK, 0x2058, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK, 0x205c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK, 0x2060, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK, 0x2064, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK, 0x2068, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK, 0x206c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK, 0x208c, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK, 0x2088, PERIS), |
| SFR(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK, 0x2000, PERIS), |
| SFR(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 0x0100, PERIS), |
| SFR(PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER, 0x0108, PERIS), |
| SFR(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0, 0x0810, PERIS), |
| SFR(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1, 0x0814, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK, 0x203c, PERIS), |
| SFR(CLK_CON_MUX_MUX_CLK_PERIS_GIC, 0x1000, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK, 0x2040, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS, 0x2014, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM, 0x2010, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK, 0x2030, PERIS), |
| SFR(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK, 0x2024, PERIS), |
| SFR(QCH_CON_BUSIF_TMU_QCH, 0x3000, PERIS), |
| SFR(QCH_CON_GIC_QCH, 0x3004, PERIS), |
| SFR(QCH_CON_LHM_AXI_P_PERIS_QCH, 0x3008, PERIS), |
| SFR(QCH_CON_MCT_QCH, 0x300c, PERIS), |
| SFR(QCH_CON_OTP_CON_BIRA_QCH, 0x3010, PERIS), |
| SFR(QCH_CON_OTP_CON_TOP_QCH, 0x3014, PERIS), |
| SFR(QCH_CON_PERIS_CMU_PERIS_QCH, 0x3018, PERIS), |
| SFR(QCH_CON_PMU_PERIS_QCH, 0x301c, PERIS), |
| SFR(QCH_CON_SYSREG_PERIS_QCH, 0x3020, PERIS), |
| SFR(QCH_CON_TZPC00_QCH, 0x3024, PERIS), |
| SFR(QCH_CON_TZPC01_QCH, 0x3028, PERIS), |
| SFR(QCH_CON_TZPC02_QCH, 0x302c, PERIS), |
| SFR(QCH_CON_TZPC03_QCH, 0x3030, PERIS), |
| SFR(QCH_CON_TZPC04_QCH, 0x3034, PERIS), |
| SFR(QCH_CON_TZPC05_QCH, 0x3038, PERIS), |
| SFR(QCH_CON_TZPC06_QCH, 0x303c, PERIS), |
| SFR(QCH_CON_TZPC07_QCH, 0x3040, PERIS), |
| SFR(QCH_CON_TZPC08_QCH, 0x3044, PERIS), |
| SFR(QCH_CON_TZPC09_QCH, 0x3048, PERIS), |
| SFR(QCH_CON_TZPC10_QCH, 0x304c, PERIS), |
| SFR(QCH_CON_TZPC11_QCH, 0x3050, PERIS), |
| SFR(QCH_CON_TZPC12_QCH, 0x3054, PERIS), |
| SFR(QCH_CON_TZPC13_QCH, 0x3058, PERIS), |
| SFR(QCH_CON_TZPC14_QCH, 0x305c, PERIS), |
| SFR(QCH_CON_TZPC15_QCH, 0x3060, PERIS), |
| SFR(QCH_CON_WDT_CLUSTER0_QCH, 0x3064, PERIS), |
| SFR(QCH_CON_WDT_CLUSTER1_QCH, 0x3068, PERIS), |
| SFR(PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER, 0x0120, SRDZ), |
| SFR(PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER, 0x0128, SRDZ), |
| SFR(CLK_CON_DIV_DIV_CLK_SRDZ_BUSP, 0x1800, SRDZ), |
| SFR(PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER, 0x0100, SRDZ), |
| SFR(PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER, 0x0108, SRDZ), |
| SFR(CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK, 0x2008, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK, 0x2054, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK, 0x2058, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK, 0x205c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK, 0x206c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK, 0x2040, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK, 0x2070, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK, 0x2018, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK, 0x201c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS, 0x2014, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM, 0x2010, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK, 0x2074, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK, 0x2078, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK, 0x2044, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK, 0x2048, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK, 0x2060, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE, 0x2064, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE, 0x2068, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK, 0x2020, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK, 0x2024, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK, 0x2030, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK, 0x2038, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK, 0x203c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK, 0x202c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK, 0x2034, SRDZ), |
| SFR(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0, 0x0810, SRDZ), |
| SFR(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1, 0x0814, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK, 0x2028, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK, 0x204c, SRDZ), |
| SFR(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK, 0x2050, SRDZ), |
| SFR(QCH_CON_BTM_SRDZ_QCH, 0x3008, SRDZ), |
| SFR(QCH_CON_LHM_ATB_DCAMSRDZ_QCH, 0x300c, SRDZ), |
| SFR(QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH, 0x3010, SRDZ), |
| SFR(QCH_CON_LHM_AXI_P_SRDZ_QCH, 0x3014, SRDZ), |
| SFR(QCH_CON_LHS_ATB_SRDZCAM_QCH, 0x3018, SRDZ), |
| SFR(QCH_CON_LHS_AXI_D_SRDZ_QCH, 0x301c, SRDZ), |
| SFR(QCH_CON_LHS_AXI_P_SRDZDCAM_QCH, 0x3020, SRDZ), |
| SFR(QCH_CON_PMU_SRDZ_QCH, 0x3024, SRDZ), |
| SFR(QCH_CON_BCM_SRDZ_QCH, 0x3028, SRDZ), |
| SFR(QCH_CON_SMMU_SRDZ_QCH, 0x302c, SRDZ), |
| SFR(QCH_CON_SRDZ_QCH, 0x3034, SRDZ), |
| SFR(QCH_CON_SRDZ_CMU_SRDZ_QCH, 0x3030, SRDZ), |
| SFR(QCH_CON_SYSREG_SRDZ_QCH, 0x3038, SRDZ), |
| SFR(CLK_CON_DIV_DIV_CLK_VPU_BUSP, 0x1800, VPU), |
| SFR(PLL_CON0_MUX_CLKCMU_VPU_BUS_USER, 0x0100, VPU), |
| SFR(PLL_CON2_MUX_CLKCMU_VPU_BUS_USER, 0x0108, VPU), |
| SFR(CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK, 0x200c, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK, 0x2058, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK, 0x2054, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK, 0x2030, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK, 0x2050, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK, 0x2014, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK, 0x2064, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK, 0x2034, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK, 0x2038, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK, 0x2044, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE, 0x2048, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK, 0x2018, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK, 0x2024, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK, 0x2028, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK, 0x201c, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE, 0x204c, VPU), |
| SFR(CLKOUT_CON_BLK_VPU_CMU_CLKOUT0, 0x0810, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK, 0x2010, VPU), |
| SFR(CLKOUT_CON_BLK_VPU_CMU_CLKOUT1, 0x0814, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK, 0x203c, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK, 0x2040, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK, 0x2060, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK, 0x2020, VPU), |
| SFR(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK, 0x202c, VPU), |
| SFR(QCH_CON_BTM_VPU_QCH, 0x3000, VPU), |
| SFR(QCH_CON_LHM_AXI_P_DSPVPU_QCH, 0x3004, VPU), |
| SFR(QCH_CON_LHM_AXI_P_VPU_QCH, 0x3008, VPU), |
| SFR(QCH_CON_LHS_ACEL_D_VPU_QCH, 0x300c, VPU), |
| SFR(QCH_CON_LHS_AXI_D_VPUDSP_QCH, 0x3010, VPU), |
| SFR(QCH_CON_PMU_VPU_QCH, 0x3014, VPU), |
| SFR(QCH_CON_BCM_VPU_QCH, 0x3018, VPU), |
| SFR(QCH_CON_SMMU_VPU_QCH, 0x301c, VPU), |
| SFR(QCH_CON_SYSREG_VPU_QCH, 0x3020, VPU), |
| SFR(QCH_CON_VPU_QCH, 0x3028, VPU), |
| SFR(QCH_CON_VPU_CMU_VPU_QCH, 0x3024, VPU), |
| SFR(CLK_CON_DIV_DIV_CLK_VTS_BUS, 0x1800, VTS), |
| SFR(CLK_CON_DIV_DIV_CLK_VTS_DMICIF, 0x180c, VTS), |
| SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC, 0x1808, VTS), |
| SFR(CLKOUT_CON_BLK_VTS_CMU_CLKOUT0, 0x0810, VTS), |
| SFR(CLKOUT_CON_BLK_VTS_CMU_CLKOUT1, 0x0814, VTS), |
| SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK, 0x200c, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK, 0x202c, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK, 0x2030, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS, 0x2048, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK, 0x2038, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK, 0x203c, VTS), |
| SFR(OSC_CON2_OSC_VTS, 0x0108, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU, 0x2044, VTS), |
| SFR(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2, 0x1810, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK, 0x204c, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK, 0x2040, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK, 0x2024, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK, 0x201c, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK, 0x2034, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK, 0x2014, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK, 0x2018, VTS), |
| SFR(CLK_CON_DIV_DIV_CLK_VTS_CMUREF, 0x1804, VTS), |
| SFR(CLK_CON_MUX_MUX_CLK_VTS_CMUREF, 0x1000, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK, 0x2028, VTS), |
| SFR(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK, 0x2020, VTS), |
| SFR(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK, 0x2000, VTS), |
| SFR(DMYQCH_CON_CMU_VTS_CMUREF_QCH, 0x3000, VTS), |
| SFR(QCH_CON_DMIC_AHB_QCH_PCLK, 0x300c, VTS), |
| SFR(DMYQCH_CON_DMIC_AHB_QCH_HCLK, 0x3004, VTS), |
| SFR(QCH_CON_DMIC_IF_QCH_PCLK, 0x3010, VTS), |
| SFR(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK, 0x3008, VTS), |
| SFR(QCH_CON_GPIO_VTS_QCH, 0x3014, VTS), |
| SFR(QCH_CON_LHM_AXI_P_VTS_QCH, 0x3018, VTS), |
| SFR(QCH_CON_LHS_AXI_D_VTS_QCH, 0x301c, VTS), |
| SFR(QCH_CON_MAILBOX_VTS2AP_QCH, 0x3020, VTS), |
| SFR(QCH_CON_SYSREG_VTS_QCH, 0x3024, VTS), |
| SFR(QCH_CON_VTS_QCH_CPU, 0x302c, VTS), |
| SFR(QCH_CON_VTS_QCH_SYS, 0x3030, VTS), |
| SFR(QCH_CON_VTS_QCH_SYS_DMIC, 0x3034, VTS), |
| SFR(QCH_CON_VTS_CMU_VTS_QCH, 0x3028, VTS), |
| SFR(QCH_CON_WDT_VTS_QCH, 0x3038, VTS), |
| /*====================The section of controller option SFR instance===================*/ |
| SFR(ABOX_CMU_CONTROLLER_OPTION, 0x0800, ABOX), |
| SFR(APM_CMU_CONTROLLER_OPTION, 0x0800, APM), |
| SFR(BUS1_CMU_CONTROLLER_OPTION, 0x0800, BUS1), |
| SFR(BUSC_CMU_CONTROLLER_OPTION, 0x0800, BUSC), |
| SFR(CAM_CMU_CONTROLLER_OPTION, 0x0800, CAM), |
| SFR(CMU_CMU_CONTROLLER_OPTION, 0x0800, CMU), |
| SFR(CORE_CMU_CONTROLLER_OPTION, 0x0800, CORE), |
| SFR(CPUCL0_CMU_CONTROLLER_OPTION, 0x0800, CPUCL0), |
| SFR(CPUCL1_CMU_CONTROLLER_OPTION, 0x0800, CPUCL1), |
| SFR(DBG_CMU_CONTROLLER_OPTION, 0x0800, DBG), |
| SFR(DCAM_CMU_CONTROLLER_OPTION, 0x0800, DCAM), |
| SFR(DPU0_CMU_CONTROLLER_OPTION, 0x0800, DPU0), |
| SFR(DPU1_CMU_CONTROLLER_OPTION, 0x0800, DPU1), |
| SFR(DSP_CMU_CONTROLLER_OPTION, 0x0800, DSP), |
| SFR(FSYS0_CMU_CONTROLLER_OPTION, 0x0800, FSYS0), |
| SFR(FSYS1_CMU_CONTROLLER_OPTION, 0x0800, FSYS1), |
| SFR(G2D_CMU_CONTROLLER_OPTION, 0x0800, G2D), |
| SFR(G3D_CMU_CONTROLLER_OPTION, 0x0800, G3D), |
| SFR(IMEM_CMU_CONTROLLER_OPTION, 0x0800, IMEM), |
| SFR(ISPHQ_CMU_CONTROLLER_OPTION, 0x0800, ISPHQ), |
| SFR(ISPLP_CMU_CONTROLLER_OPTION, 0x0800, ISPLP), |
| SFR(IVA_CMU_CONTROLLER_OPTION, 0x0800, IVA), |
| SFR(MFC_CMU_CONTROLLER_OPTION, 0x0800, MFC), |
| SFR(MIF_CMU_CONTROLLER_OPTION, 0x0800, MIF), |
| SFR(MIF1_CMU_CONTROLLER_OPTION, 0x0800, MIF1), |
| SFR(MIF2_CMU_CONTROLLER_OPTION, 0x0800, MIF2), |
| SFR(MIF3_CMU_CONTROLLER_OPTION, 0x0800, MIF3), |
| SFR(PERIC0_CMU_CONTROLLER_OPTION, 0x0800, PERIC0), |
| SFR(PERIC1_CMU_CONTROLLER_OPTION, 0x0800, PERIC1), |
| SFR(PERIS_CMU_CONTROLLER_OPTION, 0x0800, PERIS), |
| SFR(SRDZ_CMU_CONTROLLER_OPTION, 0x0800, SRDZ), |
| SFR(VPU_CMU_CONTROLLER_OPTION, 0x0800, VPU), |
| SFR(VTS_CMU_CONTROLLER_OPTION, 0x0800, VTS), |
| }; |
| |
| unsigned int cmucal_sfr_size = 2075; |
| unsigned int dbg_offset = 0x4000; |
| |
| /*====================The section of SFR Access instance===================*/ |
| struct sfr_access cmucal_sfr_access_list[] __initdata = { |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_P, 8, 6, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_M, 16, 10, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_DIV_S, 0, 3, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_ENABLE, 31, 1, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON0_PLL_AUD_STABLE, 29, 1, PLL_CON0_PLL_AUD), |
| SFR_ACCESS(PLL_CON3_PLL_AUD_DIV_K, 0, 16, PLL_CON3_PLL_AUD), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_AUD_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_AUD), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_PLL_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_PLL_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_ABOX_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_AUDIF_DIVRATIO, 0, 9, CLK_CON_DIV_DIV_CLK_ABOX_AUDIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ABOX_CPU_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DSIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_DSIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_DSIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DSIF_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_DSIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF0_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF1_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF2_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF3_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_ABOX_CMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ABOX_CPUABOX_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ABOX_CPUABOX_USER), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_CPU_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_CPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_CPU), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_CPU_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BCM_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SMMU_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_SYSREG_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_DSIF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHS_ATB_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_GPIO_ABOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_AXI_US_32TO128_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ABOX_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_DSIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ABOX_CPU_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_BTM_ABOX_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ASB), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ABOX_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_ACLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_CA7), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_CPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_ABOX_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_LHM_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_PERI_AXI_ASB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WDT_ABOXCPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_DMIC), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_DMIC), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_DMIC_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_ABOX_DMIC), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DMIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_CCLK_ATB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_DAP_IPCLKPORT_DAPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_TREX_ABOX_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_WRAP2_CONV_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ABOX_UAIF4_DIVRATIO, 0, 5, CLK_CON_DIV_DIV_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_ABOX_UAIF4_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_ABOX_UAIF4), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ABOX_UID_DFTMUX_ABOX_IPCLKPORT_AUD_CODEC_MCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_RSTNSYNC_CLK_ABOX_UAIF4_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ABOX_UID_ABOX_TOP_IPCLKPORT_BCLK_UAIF4), |
| SFR_ACCESS(QCH_CON_ABOX_CMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_ABOX_CMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_ABOX_CMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_ABOX_CMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_ABOX_CMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ABOX_CMU_ABOX_QCH), |
| SFR_ACCESS(DMYQCH_CON_ABOX_TOP_QCH_ENABLE, 0, 1, DMYQCH_CON_ABOX_TOP_QCH), |
| SFR_ACCESS(DMYQCH_CON_ABOX_TOP_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_ABOX_TOP_QCH), |
| SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_ENABLE, 0, 1, QCH_CON_BTM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BTM_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ABOX_QCH), |
| SFR_ACCESS(DMYQCH_CON_DMIC_QCH_ENABLE, 0, 1, DMYQCH_CON_DMIC_QCH), |
| SFR_ACCESS(DMYQCH_CON_DMIC_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_ABOX_QCH_ENABLE, 0, 1, QCH_CON_GPIO_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_PMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_ENABLE, 0, 1, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_BCM_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_ENABLE, 0, 1, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ABOX_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_TREX_ABOX_QCH_ENABLE, 0, 1, QCH_CON_TREX_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_TREX_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_TREX_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_ENABLE, 0, 1, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(QCH_CON_WDT_ABOXCPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_ABOXCPU_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_APM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_APM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_APM_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_APM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_APM_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_APM_IPCLKPORT_ACLK_XIU_D_ALIVE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_SCAN2AXI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2CP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM2GNSS_IPCLKPORT_PCLK), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_ENABLE, 0, 1, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_QCH_SYS_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_SYS), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_ENABLE, 0, 1, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(QCH_CON_APM_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_APM_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_APM_QCH_OSCCLK_ENABLE, 0, 1, DMYQCH_CON_APM_QCH_OSCCLK), |
| SFR_ACCESS(DMYQCH_CON_APM_QCH_OSCCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_APM_QCH_OSCCLK), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_ENABLE, 0, 1, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_APM_CMU_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APM_CMU_APM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2CP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_APM2GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_APM2GNSS_QCH), |
| SFR_ACCESS(QCH_CON_SCAN2AXI_QCH_ENABLE, 0, 1, QCH_CON_SCAN2AXI_QCH), |
| SFR_ACCESS(QCH_CON_SCAN2AXI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SCAN2AXI_QCH), |
| SFR_ACCESS(QCH_CON_SCAN2AXI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SCAN2AXI_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_ENABLE, 0, 1, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(QCH_CON_WDT_APM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_APM_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUS1_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUS1_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUS1_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUS1_BUSP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUS1_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_BUS1_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_BUS1_CMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_GNSS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_D_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_BUS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_TREX_P_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_AXI2APB_BUS1_TREX_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_PMU_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_SYSREG_BUS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHM_AXI_D_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_LHS_AXI_P_ALIVE_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUS1_UID_RSTNSYNC_CLK_BUS1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_ENABLE, 0, 1, QCH_CON_BUS1_CMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUS1_CMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_BUS1_CMU_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUS1_CMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_GNSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_GNSS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ALIVE_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ALIVE_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ALIVE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ALIVE_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUS1_QCH_ENABLE, 0, 1, QCH_CON_PMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUS1_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUS1_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_BUSC_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_BUSC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_BUSC_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_BUSC_UID_BUSC_CMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSCP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AXI2APB_BUSC_TDP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GPIO_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SYSREG_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_BUSIF_CMUTOPC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PMU_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SECMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_MBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ADCIF_BUSC_IPCLKPORT_PCLK_S1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_D_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_PCLK_BUSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_BUSC_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_BUSC_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SMC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_GNSSMBOX_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_PCLK_BATCHER_SPEEDY), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_AP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPEEDY_BATCHER_WRAP_IPCLKPORT_I_PCLK_BATCHER_CP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_BUSC_BUSPHSI2C_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_BUSC_BUSPHSI2C_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_HSI2CDF_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_HSI2CDF_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_RSTNSYNC_CLK_BUSC_BUSPHSI2C_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_ASYNCSFR_WR_SCI_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_PDMA0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_SPDMA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_PDMA0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_AD_APB_SPDMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHM_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ABOX_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_LHS_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_BUSC_UID_TREX_P_BUSC_IPCLKPORT_ACLK_BUSC), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S0_ENABLE, 0, 1, QCH_CON_ADCIF_BUSC_QCH_S0), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S0_CLOCK_REQ, 1, 1, QCH_CON_ADCIF_BUSC_QCH_S0), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S0_EXPIRE_VAL, 16, 10, QCH_CON_ADCIF_BUSC_QCH_S0), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S1_ENABLE, 0, 1, QCH_CON_ADCIF_BUSC_QCH_S1), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S1_CLOCK_REQ, 1, 1, QCH_CON_ADCIF_BUSC_QCH_S1), |
| SFR_ACCESS(QCH_CON_ADCIF_BUSC_QCH_S1_EXPIRE_VAL, 16, 10, QCH_CON_ADCIF_BUSC_QCH_S1), |
| SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_ENABLE, 0, 1, QCH_CON_BUSC_CMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSC_CMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_BUSC_CMU_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSC_CMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_CMUTOPC_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_CMUTOPC_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_CMUTOPC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_CMUTOPC_QCH), |
| SFR_ACCESS(QCH_CON_GNSSMBOX_QCH_ENABLE, 0, 1, QCH_CON_GNSSMBOX_QCH), |
| SFR_ACCESS(QCH_CON_GNSSMBOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_GNSSMBOX_QCH), |
| SFR_ACCESS(QCH_CON_GNSSMBOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GNSSMBOX_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_BUSC_QCH_ENABLE, 0, 1, QCH_CON_GPIO_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_HSI2CDF_QCH_ENABLE, 0, 1, QCH_CON_HSI2CDF_QCH), |
| SFR_ACCESS(QCH_CON_HSI2CDF_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2CDF_QCH), |
| SFR_ACCESS(QCH_CON_HSI2CDF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2CDF_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_DSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_VPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACEL_D_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVASC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ABOX_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ABOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ABOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ABOX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_MBOX_QCH_ENABLE, 0, 1, QCH_CON_MBOX_QCH), |
| SFR_ACCESS(QCH_CON_MBOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_MBOX_QCH), |
| SFR_ACCESS(QCH_CON_MBOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MBOX_QCH), |
| SFR_ACCESS(QCH_CON_PDMA0_QCH_ENABLE, 0, 1, QCH_CON_PDMA0_QCH), |
| SFR_ACCESS(QCH_CON_PDMA0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PDMA0_QCH), |
| SFR_ACCESS(QCH_CON_PDMA0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PDMA0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUSC_QCH_ENABLE, 0, 1, QCH_CON_PMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_PMU_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_SECMBOX_QCH_ENABLE, 0, 1, QCH_CON_SECMBOX_QCH), |
| SFR_ACCESS(QCH_CON_SECMBOX_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECMBOX_QCH), |
| SFR_ACCESS(QCH_CON_SECMBOX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECMBOX_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_QCH_ENABLE, 0, 1, QCH_CON_SPDMA_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPDMA_QCH), |
| SFR_ACCESS(QCH_CON_SPDMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPDMA_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_ENABLE, 0, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_SPEEDY), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_ENABLE, 0, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_CP), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_ENABLE, 0, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP), |
| SFR_ACCESS(QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY_BATCHER_WRAP_QCH_BATCHER_AP), |
| SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_ENABLE, 0, 1, QCH_CON_TREX_P_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P_BUSC_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P_BUSC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P_BUSC_QCH), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_CFW_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_SYSMMU_CAM1), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CAM_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CAM_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSD_DIV2), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CAM_TPU0_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CAM_TPU0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_VRA_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CAM_VRA_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CAM_VRA_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CAM_VRA_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CAM_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CAM_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CAM_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D0_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHS_AXI_D1_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BCM_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_CSISX4), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPLP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_CAM_ISPHQ), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU0_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_VRA), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_AXI_P_CAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS0_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS1_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS2_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSIS3_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_AXI2APB_IS_CAM_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_SYSMMU_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_D_CAM0_4X1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_P_CAM_1X2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_MC_SCALER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_MCSC_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPLP_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_ISPHQ_CAM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_SYSREG_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_BNS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSD_DIV2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_VRA_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_CSISX4_DMA), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CAM_UID_CAM_CMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CAM_TPU1_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CAM_TPU1_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_QE_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBS_2TO1_ISP_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_PXL_ASBM_1TO2_TPU1_MCSC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_XIU_ASYNCS_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_BTM_CAMD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_RSTNSYNC_CLK_CAM_TPU1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_PCLK_ASYNCS_APB_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_IS_CAM_IPCLKPORT_ACLK_APB_ASYNCM_CSIS3), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_PMU_CAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_LHM_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CAM_UID_ISP_EWGEN_CAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(QCH_CON_BTM_CAMD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_CAMD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_CAMD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_CAMD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_CAMD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_CAMD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_CAMD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_CAMD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_CAMD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_CAMD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_CAMD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_CAMD1_QCH), |
| SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_ENABLE, 0, 1, QCH_CON_CAM_CMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_CAM_CMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_CAM_CMU_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CAM_CMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_CAM_QCH_ENABLE, 0, 1, QCH_CON_ISP_EWGEN_CAM_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISP_EWGEN_CAM_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISP_EWGEN_CAM_QCH), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS0_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_CSIS0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS0_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_CSIS0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS0_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_CSIS0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS1_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_CSIS1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS1_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_CSIS1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS1_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_CSIS1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS2_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_CSIS2), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS2_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_CSIS2), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS2_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_CSIS2), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS3_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_CSIS3), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS3_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_CSIS3), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSIS3_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_CSIS3), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_MC_SCALER_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_MC_SCALER), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_MC_SCALER_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_MC_SCALER), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_MC_SCALER_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_MC_SCALER), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSISX4_DMA_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_CSISX4_DMA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSISX4_DMA_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_CSISX4_DMA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_CSISX4_DMA_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_CSISX4_DMA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM0_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_SYSMMU_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_SYSMMU_CAM1_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_SYSMMU_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM0_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_BCM_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM0_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_BCM_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM0_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_BCM_CAM0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM1_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_BCM_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM1_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_BCM_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BCM_CAM1_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_BCM_CAM1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU0_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU0_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU0_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_VRA_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU0_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_QE_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU0_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_QE_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU0_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_QE_TPU0), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_VRA_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_QE_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_VRA_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_QE_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_VRA_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_QE_VRA), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BNS_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_BNS), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BNS_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_BNS), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_BNS_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_BNS), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_CSISX4_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_QE_CSISX4), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_CSISX4_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_QE_CSISX4), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_CSISX4_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_QE_CSISX4), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU1_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_QE_TPU1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU1_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_QE_TPU1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_QE_TPU1_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_QE_TPU1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU1_ENABLE, 0, 1, QCH_CON_IS_CAM_QCH_TPU1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU1_CLOCK_REQ, 1, 1, QCH_CON_IS_CAM_QCH_TPU1), |
| SFR_ACCESS(QCH_CON_IS_CAM_QCH_TPU1_EXPIRE_VAL, 16, 10, QCH_CON_IS_CAM_QCH_TPU1), |
| SFR_ACCESS(QCH_CON_LHM_ATB_SRDZCAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_SRDZCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_SRDZCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_CAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_CAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CAM_QCH_ENABLE, 0, 1, QCH_CON_PMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_CAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CAM_QCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_APM_BUS_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G3D_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIS_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DPU_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DPU_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DPU_BUS), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_P, 8, 6, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_M, 16, 10, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_DIV_S, 0, 3, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_ENABLE, 31, 1, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED1_STABLE, 29, 1, PLL_CON0_PLL_SHARED1), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUS1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI00_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI00_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI01_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI01_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI02_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI02_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI03_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC0_USI03_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED2_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED2_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED3_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED3_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED4_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED4_DIV2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_P, 8, 6, PLL_CON0_PLL_SHARED4), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_M, 16, 10, PLL_CON0_PLL_SHARED4), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED4_DIV_S, 0, 3, PLL_CON0_PLL_SHARED4), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED4_ENABLE, 31, 1, PLL_CON0_PLL_SHARED4), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED4_STABLE, 29, 1, PLL_CON0_PLL_SHARED4), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED4_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED4), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED0_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED0_DIV4), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MFC_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MFC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MFC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MFC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_G2D_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS0_USBDRD30), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_UFS_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD_DIVRATIO, 0, 9, CLK_CON_DIV_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPU_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_VPU_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_VPU_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_VPU_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DSP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_UART_DBG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI00), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI02), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_UART_BT_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_UART_BT), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI05_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI05_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI05_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI05), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI06_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI06_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI06_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI06), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI07_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI07_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI08_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI08_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI09_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI09_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI10_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI10_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI10_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI10), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI11_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI11_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI11_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI11), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI12_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI12_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI12_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI12), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI13_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI13_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI13_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI13), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_P, 8, 6, PLL_CON0_PLL_SHARED3), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_M, 16, 10, PLL_CON0_PLL_SHARED3), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED3_DIV_S, 0, 3, PLL_CON0_PLL_SHARED3), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED3_ENABLE, 31, 1, PLL_CON0_PLL_SHARED3), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED3_STABLE, 29, 1, PLL_CON0_PLL_SHARED3), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED3), |
| SFR_ACCESS(PLL_CON0_MUX_CP2AP_MIF_CLK_USER_BUSY, 7, 1, PLL_CON0_MUX_CP2AP_MIF_CLK_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CP2AP_MIF_CLK_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CP2AP_MIF_CLK_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CP2AP_MIF_CLK_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CP2AP_MIF_CLK_USER), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUSC_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_G2D_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI08), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI07), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI04_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI04_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_USI04_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_USI04), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC0_USI03), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC0_USI01), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_P, 8, 6, PLL_CON0_PLL_SHARED2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_M, 16, 10, PLL_CON0_PLL_SHARED2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED2_DIV_S, 0, 3, PLL_CON0_PLL_SHARED2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED2_ENABLE, 31, 1, PLL_CON0_PLL_SHARED2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED2_STABLE, 29, 1, PLL_CON0_PLL_SHARED2), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED2), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_P, 8, 6, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_M, 16, 10, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_DIV_S, 0, 3, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_ENABLE, 31, 1, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_CON0_PLL_SHARED0_STABLE, 29, 1, PLL_CON0_PLL_SHARED0), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_SHARED0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_USI09), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DSP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_FSYS0_MMC_EMBD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CORE_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CORE_BUS_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH_SELECT, 0, 3, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CAM_TPU0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_TPU1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CAM_TPU1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPLP_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPLP_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ISPHQ_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ISPHQ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_ABOX_CPUABOX_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_ABOX_CPUABOX), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_JPEG_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_G2D_JPEG_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_G2D_JPEG), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_HPM_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_HPM_DIVRATIO, 0, 2, CLK_CON_DIV_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_HPM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_HPM), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DBG_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DBG_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DBG_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DBG_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DBG_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_SPI_CAM1), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DROOPDETECTOR_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DROOPDETECTOR_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DROOPDETECTOR), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CMU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CMU_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK0_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK1_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK2_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CIS_CLK3_DIVRATIO, 0, 5, CLK_CON_DIV_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_OTP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_OTP), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IVA_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IVA_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IVA_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_FSYS1_UFS_CARD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_BUSC_BUSPHSI2C), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_VRA_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_CAM_VRA_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CAM_VRA_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CAM_VRA), |
| SFR_ACCESS(CLK_CON_DIV_DIV_PLL_SHARED1_DIV4_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_PLL_SHARED1_DIV4), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_FSYS0_DPGTC_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED0_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MODEM_SHARED0), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_MODEM_SHARED1_DIVRATIO, 0, 3, CLK_CON_DIV_CLKCMU_MODEM_SHARED1), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DCAM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IMEM_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_IMEM_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_IMEM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_FSYS0_DPGTC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_PCIE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CMU_CMUREF_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_IMGD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_IMGD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_SRDZ_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_BUS_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_SRDZ_BUS_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_SRDZ_BUS), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_IMGD_BUSY, 16, 1, CLK_CON_DIV_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_CLKCMU_DCAM_IMGD_DIVRATIO, 0, 4, CLK_CON_DIV_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_DCAM_IMGD), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CP2AP_MIF_CLK_DIV2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_PERIC1_SPEEDY2), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_APM_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_APM_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS_SELECT, 0, 1, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CMU_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CMU_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_BUSY, 16, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH_SELECT, 0, 2, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_CMU_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_CMU_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK0), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK1), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK2), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_ENABLE, 0, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3), |
| SFR_ACCESS(DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3_CLOCK_REQ, 1, 1, DMYQCH_CON_DFTMUX_TOP_QCH_CIS_CLK3), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CORE_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CORE_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CORE_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PMU_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_SYSREG_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_0_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_MPACE2AXI_1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCMPPC_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_ACLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P0_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CORE_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CORE_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CORE_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CORE_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_CPACE_D_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CORE_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CORE_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CORE_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_RSTNSYNC_CLK_CORE_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G0_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G1_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G2_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_DBG_G3_DMC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_ADM_APB_G_BDU_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BDU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_APBBR_CCI_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_P1_CORE_IPCLKPORT_PCLK_CORE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_AXI2APB_CORE_TP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BCM_G3D3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_PPCFW_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHS_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_P_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_AXI_D_CP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D0_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D1_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D2_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_LHM_ACE_D3_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CORE_UID_HPM_CORE_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_BUSIF_HPMCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CORE_UID_TREX_D_CORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(QCH_CON_APBBR_CCI_QCH_ENABLE, 0, 1, QCH_CON_APBBR_CCI_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_CCI_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_CCI_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_CCI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_CCI_QCH), |
| SFR_ACCESS(QCH_CON_BDU_QCH_ENABLE, 0, 1, QCH_CON_BDU_QCH), |
| SFR_ACCESS(QCH_CON_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BDU_QCH), |
| SFR_ACCESS(QCH_CON_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BDU_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCORE_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCORE_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCORE_QCH), |
| SFR_ACCESS(DMYQCH_CON_CCI_QCH_ENABLE, 0, 1, DMYQCH_CON_CCI_QCH), |
| SFR_ACCESS(DMYQCH_CON_CCI_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CCI_QCH), |
| SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_CORE_CMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_CORE_CMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_CORE_CMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CORE_CMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D0_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D0_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D0_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D0_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D1_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D1_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D1_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D1_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D2_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D2_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D2_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D2_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D3_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D3_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D3_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D3_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ACE_D_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ACE_D_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DBG_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IMEM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CORE_QCH_ENABLE, 0, 1, QCH_CON_PMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_CORE_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_ENABLE, 0, 1, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PPCFW_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PPCFW_G3D_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BCM_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_BCM_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D0_QCH_ENABLE, 0, 1, QCH_CON_BCM_G3D0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G3D0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G3D0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D1_QCH_ENABLE, 0, 1, QCH_CON_BCM_G3D1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G3D1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G3D1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D2_QCH_ENABLE, 0, 1, QCH_CON_BCM_G3D2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G3D2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G3D2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D3_QCH_ENABLE, 0, 1, QCH_CON_BCM_G3D3_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G3D3_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G3D3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G3D3_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CORE_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CORE_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_D_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_D_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P0_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P0_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P0_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P0_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_ENABLE, 0, 1, QCH_CON_TREX_P1_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_TREX_P1_CORE_QCH), |
| SFR_ACCESS(QCH_CON_TREX_P1_CORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TREX_P1_CORE_QCH), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL0_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL0_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL0_CMUREF), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL0_STABLE, 29, 1, PLL_CON0_PLL_CPUCL0), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL0_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL0), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL0_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_CPUCL0_CMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_AXI2APB_CPUCL0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_SYSREG_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_DROOPDETECTOR_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_LHM_AXI_P_CPUCL0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_HPM_CPUCL0_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER0_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_BUSIF_HPMCPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_PMU_CPUCL0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP0_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL0_UID_DROOP_DETECTOR_CPUCL0_GRP1_IPCLKPORT_CK_IN), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL0_UID_RSTNSYNC_CLK_CPUCL0_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL0_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL0_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL0_CPU), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL0_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_ENABLE, 0, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP0), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_ENABLE, 0, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1), |
| SFR_ACCESS(QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_DROOPDETECTOR_CPUCL0_QCH_GRP1), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL0_QCH), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_ENABLE, 0, 1, DMYQCH_CON_CLUSTER0_QCH), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER0_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_LHS_ATB_T0_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_LHS_ATB_T1_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_LHS_ATB_T2_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_ENABLE, 0, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER0_QCH_LHS_ATB_T3_CLUSTER0), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL0_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL0_CMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL0_CMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_PMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL0_QCH), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_P, 8, 6, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_M, 16, 10, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_DIV_S, 0, 3, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_ENABLE, 31, 1, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_PLL_CPUCL1_STABLE, 29, 1, PLL_CON0_PLL_CPUCL1), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_CPUCL1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_CPUCL1), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_CPUCL1_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_CPUCL1_PLL_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_CPUCL1_PLL), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_CPUCL1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CPUCL1_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_CPUCL1_CMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_AXI2APB_CPUCL1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_LHM_AXI_P_CPUCL1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_SYSREG_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_PMU_CPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_BUSIF_HPMCPUCL1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_CPUCL1_UID_HPM_CPUCL1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_CNTCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_ACLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK_DIVRATIO, 0, 4, CLK_CON_DIV_DIV_CLK_CLUSTER1_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_CPUCL1_UID_RSTNSYNC_CLK_CPUCL1_PCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_CPUCL1_CPU_DIVRATIO, 0, 12, CLK_CON_DIV_DIV_CLK_CPUCL1_CPU), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_CPUCL1_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMCPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMCPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMCPUCL1_QCH), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_CPU_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_CPU), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_ENABLE, 0, 1, DMYQCH_CON_CLUSTER1_QCH_DBG), |
| SFR_ACCESS(DMYQCH_CON_CLUSTER1_QCH_DBG_CLOCK_REQ, 1, 1, DMYQCH_CON_CLUSTER1_QCH_DBG), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ACE_D_CPUCL1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T0_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T1_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T2_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_ENABLE, 0, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_CLOCK_REQ, 1, 1, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1_EXPIRE_VAL, 16, 10, QCH_CON_CLUSTER1_QCH_LHS_ATB_T3_CLUSTER1), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_ENABLE, 0, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CMU_CPUCL1_SHORTSTOP_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_CPUCL1_CMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CPUCL1_CMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_PMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_CPUCL1_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DBG_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DBG_UID_DBG_CMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_AXI_P_DBG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T0_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T1_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T2_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T3_CLUSTER1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_AUD_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_AXI2APB_CORESIGHT_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHM_ATB_T_BDU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_STM_TXACTOR_IPCLKPORT_I_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_ATCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_CSSYS_IPCLKPORT_PCLKDBG), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SECJTAG_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_PMU_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_SYSREG_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DBG_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_LHS_AXI_G_CSSYS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DBG_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DBG_CMU_CLKOUT1), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DBG_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DBG_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DBG_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DBG_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_ATCLK_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_RSTNSYNC_CLK_DBG_PCLKDBG_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DBG_UID_DUMPPC_CPUCL1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(QCH_CON_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_DBG_CMU_DBG_QCH_ENABLE, 0, 1, QCH_CON_DBG_CMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_DBG_CMU_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_DBG_CMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_DBG_CMU_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DBG_CMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL0_QCH_ENABLE, 0, 1, QCH_CON_DUMPPC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMPPC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMPPC_CPUCL0_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL1_QCH_ENABLE, 0, 1, QCH_CON_DUMPPC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DUMPPC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_DUMPPC_CPUCL1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DUMPPC_CPUCL1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T0_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T0_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T0_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T1_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T1_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T1_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T2_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T2_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T2_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T3_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T3_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T3_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T_AUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T_AUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_AUD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T_AUD_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_T_BDU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_T_BDU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DBG_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DBG_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_CSSYS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_CSSYS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DBG_QCH_ENABLE, 0, 1, QCH_CON_PMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_DBG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_ENABLE, 0, 1, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_SECJTAG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SECJTAG_QCH), |
| SFR_ACCESS(QCH_CON_STM_TXACTOR_QCH_ENABLE, 0, 1, QCH_CON_STM_TXACTOR_QCH), |
| SFR_ACCESS(QCH_CON_STM_TXACTOR_QCH_CLOCK_REQ, 1, 1, QCH_CON_STM_TXACTOR_QCH), |
| SFR_ACCESS(QCH_CON_STM_TXACTOR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_STM_TXACTOR_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DBG_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DBG_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DBG_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DBG_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCAM_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DCAM_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCAM_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DCAM_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DCAM_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DCAM_BUSP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DCAM_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DCAM_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DCAM_UID_DCAM_CMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DCAM_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_DCP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PMU_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_SYSREG_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AXI2APB_DCAM_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_AD_APB_DCAM_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_XIU_P_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BCM_DCAM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHM_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBM_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DCAM_IMGD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DCAM_IMGD_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_PXL_ASBS_DCAM_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_LHS_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_RSTNSYNC_CLK_DCAM_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DCAM_UID_BTM_DCAM_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(QCH_CON_BTM_DCAM_QCH_ENABLE, 0, 1, QCH_CON_BTM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_DCAM_CMU_DCAM_QCH_ENABLE, 0, 1, QCH_CON_DCAM_CMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_DCAM_CMU_DCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_DCAM_CMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_DCAM_CMU_DCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DCAM_CMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_DCP_QCH_ENABLE, 0, 1, QCH_CON_DCP_QCH), |
| SFR_ACCESS(QCH_CON_DCP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DCP_QCH), |
| SFR_ACCESS(QCH_CON_DCP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DCP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DCAMSRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DCAMSRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DCAMSRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DCAM_QCH_ENABLE, 0, 1, QCH_CON_PMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DCAM_QCH_ENABLE, 0, 1, QCH_CON_BCM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DCAM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DCAM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DCAM_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DPU_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSD_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSD), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSD_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSD), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSD), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU0_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DPU0_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU0_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DPU0_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DPU0_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DPU0_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSP_CG_VAL, 21, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSP_MANUAL, 20, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLKCMU_DPU1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLKCMU_DPU1_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU0_UID_DPU0_CMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DECON0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_PMU_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSREG_DPU0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AXI2APB_DPU0P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHM_AXI_P0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_XIU_P0_DPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DECON0_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM0_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_MIPI_DSIM1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPP_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_VGR_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G0_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU0_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPP_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_WB_MUX_IPCLKPORT_DPP_G1_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_WB), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_CH_INTF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_DPU_DMA_IPCLKPORT_ACLK_SFR), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_LHS_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BTM_DPUD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_SECURE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_AD_APB_DPU_WB_MUX_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_SYSMMU_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_BCM_DPUD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU0_UID_RSTNSYNC_CLK_DPU0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_BTM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_BTM_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_DECON0_QCH_ENABLE, 0, 1, QCH_CON_DECON0_QCH), |
| SFR_ACCESS(QCH_CON_DECON0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DECON0_QCH), |
| SFR_ACCESS(QCH_CON_DECON0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DECON0_QCH), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G0_ENABLE, 0, 1, QCH_CON_DPP_QCH_DPP_G0), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G0_CLOCK_REQ, 1, 1, QCH_CON_DPP_QCH_DPP_G0), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G0_EXPIRE_VAL, 16, 10, QCH_CON_DPP_QCH_DPP_G0), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G1_ENABLE, 0, 1, QCH_CON_DPP_QCH_DPP_G1), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G1_CLOCK_REQ, 1, 1, QCH_CON_DPP_QCH_DPP_G1), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_G1_EXPIRE_VAL, 16, 10, QCH_CON_DPP_QCH_DPP_G1), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_VGR_ENABLE, 0, 1, QCH_CON_DPP_QCH_DPP_VGR), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_VGR_CLOCK_REQ, 1, 1, QCH_CON_DPP_QCH_DPP_VGR), |
| SFR_ACCESS(QCH_CON_DPP_QCH_DPP_VGR_EXPIRE_VAL, 16, 10, QCH_CON_DPP_QCH_DPP_VGR), |
| SFR_ACCESS(QCH_CON_DPU0_CMU_DPU0_QCH_ENABLE, 0, 1, QCH_CON_DPU0_CMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_DPU0_CMU_DPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU0_CMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_DPU0_CMU_DPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU0_CMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_DPU_DMA_QCH_ENABLE, 0, 1, QCH_CON_DPU_DMA_QCH), |
| SFR_ACCESS(QCH_CON_DPU_DMA_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU_DMA_QCH), |
| SFR_ACCESS(QCH_CON_DPU_DMA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU_DMA_QCH), |
| SFR_ACCESS(QCH_CON_DPU_WB_MUX_QCH_ENABLE, 0, 1, QCH_CON_DPU_WB_MUX_QCH), |
| SFR_ACCESS(QCH_CON_DPU_WB_MUX_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU_WB_MUX_QCH), |
| SFR_ACCESS(QCH_CON_DPU_WB_MUX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU_WB_MUX_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D2_DPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D2_DPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_USBTV_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_USBTV_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_USBTV_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU0_QCH_ENABLE, 0, 1, QCH_CON_PMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_BCM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_BCM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_BCM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD0_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD1_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_ENABLE, 0, 1, QCH_CON_SYSMMU_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSMMU_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_SYSMMU_DPUD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSMMU_DPUD2_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPU0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPU0_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU1_BUSD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DPU1_BUSD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DPU1_BUSP_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DPU1_BUSP_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DPU1_UID_DPU1_CMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_SYSREG_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_PMU_DPU1_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_PLL_DPU_DIV_P, 8, 6, PLL_CON0_PLL_DPU), |
| SFR_ACCESS(PLL_CON0_PLL_DPU_DIV_M, 16, 10, PLL_CON0_PLL_DPU), |
| SFR_ACCESS(PLL_CON0_PLL_DPU_DIV_S, 0, 3, PLL_CON0_PLL_DPU), |
| SFR_ACCESS(PLL_CON0_PLL_DPU_ENABLE, 31, 1, PLL_CON0_PLL_DPU), |
| SFR_ACCESS(PLL_CON0_PLL_DPU_STABLE, 29, 1, PLL_CON0_PLL_DPU), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_DPU_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_DPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLKCMU_DPU1_DECON2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AXI2APB_DPU1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_LHM_AXI_P_DPU1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON1_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_AD_APB_DECON2_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DPU1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_RSTNSYNC_CLK_DPU1_DECON2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DPU1_UID_DECON2_IPCLKPORT_VCLK), |
| SFR_ACCESS(QCH_CON_DECON1_QCH_ENABLE, 0, 1, QCH_CON_DECON1_QCH), |
| SFR_ACCESS(QCH_CON_DECON1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DECON1_QCH), |
| SFR_ACCESS(QCH_CON_DECON1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DECON1_QCH), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_ACLK_ENABLE, 0, 1, QCH_CON_DECON2_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_DECON2_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_DECON2_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_VCLK_ENABLE, 0, 1, QCH_CON_DECON2_QCH_VCLK), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_VCLK_CLOCK_REQ, 1, 1, QCH_CON_DECON2_QCH_VCLK), |
| SFR_ACCESS(QCH_CON_DECON2_QCH_VCLK_EXPIRE_VAL, 16, 10, QCH_CON_DECON2_QCH_VCLK), |
| SFR_ACCESS(QCH_CON_DPU1_CMU_DPU1_QCH_ENABLE, 0, 1, QCH_CON_DPU1_CMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_DPU1_CMU_DPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DPU1_CMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_DPU1_CMU_DPU1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DPU1_CMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DPU1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DPTX_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_DPTX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DPTX_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_DPTX_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_DPTX_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_DPTX_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU1_QCH_ENABLE, 0, 1, QCH_CON_PMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DPU1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DPU1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DPU1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DPU1_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_DSP_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_DSP_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_DSP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_DSP_BUSP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_DSP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_DSP_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_DSP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_DSP_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_DSP_UID_DSP_CMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SCORE_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_PMU_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SYSREG_DSP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AXI2APB_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_AD_APB_SCORE_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BCM_SCORE_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_BTM_SCORE_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_SMMU_SCORE_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSP_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_DSP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_DSP_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_ACEL_D_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_RSTNSYNC_CLK_DSP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_D_DSP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_XIU_P_DSP_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHM_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_LHS_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_DSP_UID_WRAP2_CONV_DSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(QCH_CON_BTM_SCORE_QCH_ENABLE, 0, 1, QCH_CON_BTM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_BTM_SCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_BTM_SCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_ENABLE, 0, 1, QCH_CON_DSP_CMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_DSP_CMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_DSP_CMU_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DSP_CMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVADSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VPUDSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VPUDSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_VPUDSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVADSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_DSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_DSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPIVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPVPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPVPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_DSPVPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DSP_QCH_ENABLE, 0, 1, QCH_CON_PMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_DSP_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SCORE_QCH_ENABLE, 0, 1, QCH_CON_BCM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SCORE_QCH_ENABLE, 0, 1, QCH_CON_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SCORE_QCH_ENABLE, 0, 1, QCH_CON_SMMU_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SCORE_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SCORE_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_SCORE_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_DSP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_DSP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_DSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_DSP_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_UFS_EMBD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_UFS_EMBD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_MMC_EMBD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_MMC_EMBD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_USBDRD30_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_USBDRD30_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHS_ACEL_D_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AHBBR_FSYS0_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_G_ETR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_P_FSYS0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_LHM_AXI_D_USBTV_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_US_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2AHB_USB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_AXI2APB_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_ETR_MIU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_GPIO_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_MMC_EMBD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PMU_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_SYSREG_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BCM_FSYS0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_D_FSYS0_USB_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_XIU_P_FSYS0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_CORE_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_SUSPEND_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_REF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_BTM_FSYS0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_AHB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USBTVH_XIU_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_USBTV_IPCLKPORT_I_USB30DRD_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS0_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_RSTNSYNC_CLK_FSYS0_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS0_DPGTC_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS0_DPGTC_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS0_UID_DP_LINK_IPCLKPORT_I_GTC_EXT_CLK), |
| SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_BTM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_DP_LINK_QCH_ENABLE, 0, 1, QCH_CON_DP_LINK_QCH), |
| SFR_ACCESS(QCH_CON_DP_LINK_QCH_CLOCK_REQ, 1, 1, QCH_CON_DP_LINK_QCH), |
| SFR_ACCESS(QCH_CON_DP_LINK_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DP_LINK_QCH), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_ENABLE, 0, 1, QCH_CON_ETR_MIU_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_CLOCK_REQ, 1, 1, QCH_CON_ETR_MIU_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_ETR_MIU_QCH_ACLK_EXPIRE_VAL, 16, 10, QCH_CON_ETR_MIU_QCH_ACLK), |
| SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_FSYS0_CMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS0_CMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_FSYS0_CMU_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS0_CMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_USBTV_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_USBTV_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_USBTV_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_USBTV_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_G_ETR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_G_ETR_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_ENABLE, 0, 1, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_PMU_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_PMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_BCM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS0_QCH), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_EMBD_QCH_FMP), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_EMBD_QCH_FMP), |
| SFR_ACCESS(QCH_CON_UFS_EMBD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_EMBD_QCH_FMP), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USB30DRD_LINK_ENABLE, 0, 1, QCH_CON_USBTV_QCH_USB30DRD_LINK), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USB30DRD_LINK_CLOCK_REQ, 1, 1, QCH_CON_USBTV_QCH_USB30DRD_LINK), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USB30DRD_LINK_EXPIRE_VAL, 16, 10, QCH_CON_USBTV_QCH_USB30DRD_LINK), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USBTV_HOST_ENABLE, 0, 1, QCH_CON_USBTV_QCH_USBTV_HOST), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USBTV_HOST_CLOCK_REQ, 1, 1, QCH_CON_USBTV_QCH_USBTV_HOST), |
| SFR_ACCESS(QCH_CON_USBTV_QCH_USBTV_HOST_EXPIRE_VAL, 16, 10, QCH_CON_USBTV_QCH_USBTV_HOST), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_MMC_CARD_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_TOE_WIFI1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SSS_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RTIC_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_SYSREG_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PMU_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_GPIO_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHS_ACEL_D_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_LHM_AXI_P_FSYS1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_D_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_XIU_P_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BCM_FSYS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2AHB_FSYS1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AHBBR_FSYS1_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_AXI2APB_FSYS1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_BTM_FSYS1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_FSYS1_UID_PCIE_IPCLKPORT_PHY_REF_CLK_IN), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_FSYS1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_RSTNSYNC_CLK_FSYS1_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_PCIE_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_PCIE_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_FSYS1_UFS_CARD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_FSYS1_UFS_CARD_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_MSTR_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_SLV_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_DBI_ACLK_1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_PCIE_IPCLKPORT_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_FMP_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_UFS_CARD_IPCLKPORT_I_CLK_UNIPRO), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_FSYS1_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_ENABLE, 0, 1, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_ADM_AHB_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ADM_AHB_SSS_QCH), |
| SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_BTM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_FSYS1_CMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_FSYS1_CMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_FSYS1_CMU_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_FSYS1_CMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_ENABLE, 0, 1, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_MMC_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MMC_CARD_QCH), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_MSTR_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE0_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_MSTR_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE0_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_MSTR_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE0_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PCS_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE_PCS), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PCS_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE_PCS), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PCS_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE_PCS), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PHY_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE_PHY), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PHY_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE_PHY), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE_PHY_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE_PHY), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_DBI_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE0_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE0_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE0_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_APB_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE0_APB), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE0_APB), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE0_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE0_APB), |
| SFR_ACCESS(DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_ENABLE, 0, 1, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL), |
| SFR_ACCESS(DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL_CLOCK_REQ, 1, 1, DMYQCH_CON_PCIE_QCH_PCIE_SOCPLL), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_MSTR_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE1_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_MSTR_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE1_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_MSTR_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE1_MSTR), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_DBI_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE1_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_DBI_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE1_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_DBI_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE1_DBI), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_APB_ENABLE, 0, 1, QCH_CON_PCIE_QCH_PCIE1_APB), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_APB_CLOCK_REQ, 1, 1, QCH_CON_PCIE_QCH_PCIE1_APB), |
| SFR_ACCESS(QCH_CON_PCIE_QCH_PCIE1_APB_EXPIRE_VAL, 16, 10, QCH_CON_PCIE_QCH_PCIE1_APB), |
| SFR_ACCESS(QCH_CON_PMU_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_PMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_BCM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_ENABLE, 0, 1, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_RTIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_RTIC_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_ENABLE, 0, 1, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SSS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SSS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_FSYS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_FSYS1_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI0_QCH_ENABLE, 0, 1, QCH_CON_TOE_WIFI0_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI0_QCH_CLOCK_REQ, 1, 1, QCH_CON_TOE_WIFI0_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TOE_WIFI0_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI1_QCH_ENABLE, 0, 1, QCH_CON_TOE_WIFI1_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_TOE_WIFI1_QCH), |
| SFR_ACCESS(QCH_CON_TOE_WIFI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TOE_WIFI1_QCH), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_ENABLE, 0, 1, QCH_CON_UFS_CARD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_CLOCK_REQ, 1, 1, QCH_CON_UFS_CARD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UFS_CARD_QCH), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_ENABLE, 0, 1, QCH_CON_UFS_CARD_QCH_FMP), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_CLOCK_REQ, 1, 1, QCH_CON_UFS_CARD_QCH_FMP), |
| SFR_ACCESS(QCH_CON_UFS_CARD_QCH_FMP_EXPIRE_VAL, 16, 10, QCH_CON_UFS_CARD_QCH_FMP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_G2D_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_G2D_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_G2D_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_G2D_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G2D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G2D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G2D_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G2D_UID_G2D_CMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SYSREG_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D0_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D1_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHM_AXI_P_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_G2DP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_G2D_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_PMU_G2D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_P_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AXI2APB_G2DP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G2D_JPEG_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G2D_JPEG_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_JPEG_IPCLKPORT_I_SMFC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BTM_G2DD2_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_JPEG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_QE_M2MSCALER_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_BCM_G2DD2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_LHS_ACEL_D2_G2D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_JPEGP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_XIU_D_G2D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G2D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G2D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G2D_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_SMMU_G2DD2_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_AS_P_M2MSCALERP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_G2D_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G2D_UID_RSTNSYNC_CLK_G2D_JPEG_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_BTM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_BTM_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_G2D_CMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G2D_CMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_G2D_CMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G2D_CMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_ENABLE, 0, 1, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D0_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D0_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D1_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D1_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D2_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D2_G2D_QCH), |
| SFR_ACCESS(QCH_CON_M2MSCALER_QCH_ENABLE, 0, 1, QCH_CON_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_M2MSCALER_QCH_CLOCK_REQ, 1, 1, QCH_CON_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_M2MSCALER_QCH_EXPIRE_VAL, 16, 10, QCH_CON_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G2D_QCH_ENABLE, 0, 1, QCH_CON_PMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_G2D_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_BCM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_BCM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_BCM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_BCM_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_QE_JPEG_QCH_ENABLE, 0, 1, QCH_CON_QE_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_QE_JPEG_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_QE_JPEG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_JPEG_QCH), |
| SFR_ACCESS(QCH_CON_QE_M2MSCALER_QCH_ENABLE, 0, 1, QCH_CON_QE_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_QE_M2MSCALER_QCH_CLOCK_REQ, 1, 1, QCH_CON_QE_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_QE_M2MSCALER_QCH_EXPIRE_VAL, 16, 10, QCH_CON_QE_M2MSCALER_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD0_QCH_ENABLE, 0, 1, QCH_CON_SMMU_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_G2DD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD1_QCH_ENABLE, 0, 1, QCH_CON_SMMU_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_G2DD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD2_QCH_ENABLE, 0, 1, QCH_CON_SMMU_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_G2DD2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_G2DD2_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G2D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G2D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G2D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G2D_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_G3D_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_G3D_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_AXI2APB_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_XIU_P_G3D_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHS_AXI_G3DSFR_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_LHM_AXI_P_G3D_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_BUSIF_HPMG3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_HPM_G3D_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_G3D_SWITCH_USER), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_G3D_BUSD_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_G3D_BUSD), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_PMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_SYSREG_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_G3D_UID_RSTNSYNC_CLK_G3D_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_G3D_UID_G3D_CMU_G3D_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_P, 8, 6, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_M, 16, 10, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_DIV_S, 0, 3, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_ENABLE, 31, 1, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_CON0_PLL_G3D_STABLE, 29, 1, PLL_CON0_PLL_G3D), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_G3D_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_G3D), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_G3D_AGPU_CG_VAL, 21, 1, CLK_CON_GAT_GATE_CLK_G3D_AGPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_G3D_AGPU_MANUAL, 20, 1, CLK_CON_GAT_GATE_CLK_G3D_AGPU), |
| SFR_ACCESS(CLK_CON_GAT_GATE_CLK_G3D_AGPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GATE_CLK_G3D_AGPU), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_G3D_EMBEDDED_CMU_CLKOUT1), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_G3D_ENABLE, 0, 1, QCH_CON_AGPU_QCH_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_G3D_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_G3D_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_ENABLE, 0, 1, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_LHM_AXI_G3DSFR), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_ENABLE, 0, 1, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_LHS_ACE_D0_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_ENABLE, 0, 1, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_LHS_ACE_D1_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_ENABLE, 0, 1, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_LHS_ACE_D2_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_ENABLE, 0, 1, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_CLOCK_REQ, 1, 1, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D), |
| SFR_ACCESS(QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D_EXPIRE_VAL, 16, 10, QCH_CON_AGPU_QCH_LHS_ACE_D3_G3D), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMG3D_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMG3D_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMG3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMG3D_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_G3D_CMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_G3D_CMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_G3D_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_G3DSFR_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_G3DSFR_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G3D_QCH_ENABLE, 0, 1, QCH_CON_PMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_PMU_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_G3D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_G3D_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_G3D_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IMEM_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IMEM_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_LHM_AXI_P_IMEM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_RSTNSYNC_CLK_IMEM_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_AXI2APB_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_XIU_P_IMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_SYSREG_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_PMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IMEM_UID_IMEM_CMU_IMEM_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IMEM_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IMEM_UID_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(QCH_CON_IMEM_CMU_IMEM_QCH_ENABLE, 0, 1, QCH_CON_IMEM_CMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_IMEM_CMU_IMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_IMEM_CMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_IMEM_CMU_IMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IMEM_CMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IMEM_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IMEM_QCH_ENABLE, 0, 1, QCH_CON_PMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IMEM_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_IMEM_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_IMEM_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPHQ_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPHQ_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISPHQ_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_TAA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHM_AXI_P_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_LHS_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_XIU_D_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_AXI2APB_BRIDGE_ISPHQ_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPHQ_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_RSTNSYNC_CLK_ISPHQ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_3AA_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_APB_ASYNC_TOP_ISPHQ_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_3AA_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_IS_ISPHQ_IPCLKPORT_QE_ISPHQ_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_PMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_SYSREG_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISPHQ_UID_ISPHQ_CMU_ISPHQ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPHQ_UID_ISP_EWGEN_ISPHQ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_ISPHQ_CMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISPHQ_CMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_ISPHQ_CMU_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISPHQ_CMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_ISP_EWGEN_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISP_EWGEN_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISP_EWGEN_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_3AA_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_ISPHQ), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_ISPHQ), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_3AA_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_QE_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_3AA_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_QE_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_3AA_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_QE_3AA), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_ENABLE, 0, 1, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ), |
| SFR_ACCESS(QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPHQ_QCH_QE_ISPHQ), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_LD_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_LD_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_LD_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_PMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISPHQ_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_ISPLP_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_ISPLP_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_ISPLP_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_ISPLP_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_TAAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_P_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHS_AXI_D_ISPLP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_XIU_D_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_ISPLP_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_RSTNSYNC_CLK_ISPLP_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_BTM_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_3AAW_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_APB_ASYNC_TOP_ISPLP_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_BCM_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_3AAW_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_SMMU_ISPLP_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_PMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_SYSREG_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_AXI2APB_BRIDGE_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_ISPLP_UID_ISPLP_CMU_ISPLP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_LHM_AXI_LD_ISPHQ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_ISP_EWGEN_ISPLP_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_ISPLP_UID_IS_ISPLP_IPCLKPORT_QE_ISPLP_ACLK), |
| SFR_ACCESS(QCH_CON_BTM_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_BTM_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_BTM_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_BTM_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_ISPLP_CMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISPLP_CMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISPLP_CMU_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISPLP_CMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_ISP_EWGEN_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_ISP_EWGEN_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_ISP_EWGEN_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_ISP_EWGEN_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_3AAW_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_3AAW_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_3AAW_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_3AAW_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_QE_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_3AAW_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_QE_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_3AAW_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_QE_3AAW), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_QE_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_QE_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_QE_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_QE_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_SMMU_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_ENABLE, 0, 1, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_CLOCK_REQ, 1, 1, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP), |
| SFR_ACCESS(QCH_CON_IS_ISPLP_QCH_BCM_ISPLP_EXPIRE_VAL, 16, 10, QCH_CON_IS_ISPLP_QCH_BCM_ISPLP), |
| SFR_ACCESS(QCH_CON_LHM_AXI_LD_ISPHQ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_LD_ISPHQ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_LD_ISPHQ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_LD_ISPHQ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_PMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_ISPLP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_ISPLP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_ISPLP_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_IVA_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_IVA_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_IVA_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_IVA_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_IVA_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_IVA_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_IVA_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_IVA_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_IVA_UID_IVA_CMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IVA_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_IVA_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_IVA_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_ACEL_D_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_D_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHS_AXI_P_IVADSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_DSPIVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_P_IVA_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BTM_IVA_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_BCM_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SMMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_D_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_XIU_P_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AD_APB_IVA_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_2M_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_AXI2APB_IVA_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_SYSREG_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_PMU_IVA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_IPCLKPORT_CLK_A), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_RSTNSYNC_CLK_IVA_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_IVA_INTMEM_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_IVA_UID_LHM_AXI_D_IVASC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(QCH_CON_BTM_IVA_QCH_ENABLE, 0, 1, QCH_CON_BTM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_BTM_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_BTM_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_QCH_ENABLE, 0, 1, QCH_CON_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_IVA_CMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_IVA_CMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_CMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IVA_CMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_ENABLE, 0, 1, QCH_CON_IVA_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_CLOCK_REQ, 1, 1, QCH_CON_IVA_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_IVA_INTMEM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_IVA_INTMEM_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_IVASC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_IVASC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPIVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPIVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPIVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSPIVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_IVA_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_IVADSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_IVADSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_IVADSP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_PMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_PMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_BCM_IVA_QCH_ENABLE, 0, 1, QCH_CON_BCM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_BCM_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_BCM_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IVA_QCH_ENABLE, 0, 1, QCH_CON_SMMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_IVA_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_IVA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_IVA_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_MFC_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_MFC_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_MFC_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_MFC_BUS_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MFC_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MFC_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MFC_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MFC_UID_MFC_CMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_MFC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AS_P_MFCP_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_AXI2APB_MFC_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_PMU_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SYSREG_MFC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D0_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHS_AXI_D1_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_LHM_AXI_P_MFC_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BCM_MFCD1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD0_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_BTM_MFCD1_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFC_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD0_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_SMMU_MFCD1_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MFC_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MFC_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MFC_UID_RSTNSYNC_CLK_MFC_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_BTM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_BTM_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D0_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D0_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D1_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D1_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_MFC_CMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_MFC_CMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_MFC_CMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MFC_CMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MFC_QCH_ENABLE, 0, 1, QCH_CON_PMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_MFC_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_BCM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_BCM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_BCM_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD0_QCH_ENABLE, 0, 1, QCH_CON_SMMU_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_MFCD0_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD1_QCH_ENABLE, 0, 1, QCH_CON_SMMU_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_MFCD1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_MFCD1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MFC_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MFC_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MFC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MFC_QCH), |
| SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_P, 8, 6, PLL_CON0_PLL_MIF), |
| SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_M, 16, 10, PLL_CON0_PLL_MIF), |
| SFR_ACCESS(PLL_CON0_PLL_MIF_DIV_S, 0, 3, PLL_CON0_PLL_MIF), |
| SFR_ACCESS(PLL_CON0_PLL_MIF_ENABLE, 31, 1, PLL_CON0_PLL_MIF), |
| SFR_ACCESS(PLL_CON0_PLL_MIF_STABLE, 29, 1, PLL_CON0_PLL_MIF), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_MIF_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_BUSY, 16, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X_SELECT, 0, 1, CLK_CON_MUX_CLKMUX_MIF_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_DIV_CLK_MIF_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF_BUSD), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_PRE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_MIF_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_MIF_CMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_SYSREG_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_PMU_MIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BUSIF_HPMMIF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_LHM_AXI_P_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_AXI2APB_MIF_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DDRPHY_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMC_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_APBBR_DMCTZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_HPM_MIF_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_DMC_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_DMC_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_LHM_PSCDC_D_MIF_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DEBUG_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_BCMPPC_DVFS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF_UID_RSTNSYNC_CLK_MIF_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF_CMUREF), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMCTZ_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMCTZ_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMCTZ_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY_QCH_ENABLE, 0, 1, QCH_CON_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY_QCH_CLOCK_REQ, 1, 1, QCH_CON_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DDRPHY_QCH), |
| SFR_ACCESS(QCH_CON_DMC_QCH_ENABLE, 0, 1, QCH_CON_DMC_QCH), |
| SFR_ACCESS(QCH_CON_DMC_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC_QCH), |
| SFR_ACCESS(QCH_CON_DMC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF_QCH), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_MIF_CMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF_CMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF_QCH_ENABLE, 0, 1, QCH_CON_PMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_MIF_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DEBUG_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DEBUG_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DEBUG_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DVFS_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DVFS_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DVFS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF_QCH), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF1_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF1_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF1_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF1_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_PRE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF1_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_PRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF1_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_PRE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF1_PRE), |
| SFR_ACCESS(CLK_CON_DIV_CLK_MIF1_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF1_BUSD), |
| SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_P, 8, 6, PLL_CON0_PLL_MIF1), |
| SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_M, 16, 10, PLL_CON0_PLL_MIF1), |
| SFR_ACCESS(PLL_CON0_PLL_MIF1_DIV_S, 0, 3, PLL_CON0_PLL_MIF1), |
| SFR_ACCESS(PLL_CON0_PLL_MIF1_ENABLE, 31, 1, PLL_CON0_PLL_MIF1), |
| SFR_ACCESS(PLL_CON0_PLL_MIF1_STABLE, 29, 1, PLL_CON0_PLL_MIF1), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_MIF1_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF1), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_BUSY, 16, 1, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X_SELECT, 0, 1, CLK_CON_MUX_CLKMUX_MIF1_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF1_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF1_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF1_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_MIF1_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_HPM_MIF1_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_MIF1_CMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_APBBR_DMCTZ1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_AXI2APB_MIF1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BUSIF_HPMMIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DDRPHY1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_DMC1_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_LHM_AXI_P_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_PMU_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_SYSREG_MIF1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_DMC1_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_LHM_PSCDC_D_MIF1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DEBUG1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_BCMPPC_DVFS1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF1_UID_RSTNSYNC_CLK_MIF_BUSD1_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY1_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY1_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC1_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ1_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMCTZ1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ1_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMCTZ1_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMCTZ1_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF1_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF1_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF1_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF1_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF1_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF1_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF1_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY1_QCH_ENABLE, 0, 1, QCH_CON_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DDRPHY1_QCH), |
| SFR_ACCESS(QCH_CON_DMC1_QCH_ENABLE, 0, 1, QCH_CON_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_DMC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_DMC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_ENABLE, 0, 1, QCH_CON_MIF1_CMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF1_CMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_MIF1_CMU_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF1_CMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF1_QCH_ENABLE, 0, 1, QCH_CON_PMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG1_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DEBUG1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DEBUG1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DEBUG1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS1_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DVFS1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS1_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DVFS1_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DVFS1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF1_QCH), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF2_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF2_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF2_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF2_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF2_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF2_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF2_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_PRE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF2_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_PRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF2_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_PRE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF2_PRE), |
| SFR_ACCESS(CLK_CON_DIV_CLK_MIF2_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF2_BUSD), |
| SFR_ACCESS(PLL_CON0_PLL_MIF2_DIV_P, 8, 6, PLL_CON0_PLL_MIF2), |
| SFR_ACCESS(PLL_CON0_PLL_MIF2_DIV_M, 16, 10, PLL_CON0_PLL_MIF2), |
| SFR_ACCESS(PLL_CON0_PLL_MIF2_DIV_S, 0, 3, PLL_CON0_PLL_MIF2), |
| SFR_ACCESS(PLL_CON0_PLL_MIF2_ENABLE, 31, 1, PLL_CON0_PLL_MIF2), |
| SFR_ACCESS(PLL_CON0_PLL_MIF2_STABLE, 29, 1, PLL_CON0_PLL_MIF2), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_MIF2_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF2), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_BUSY, 16, 1, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X_SELECT, 0, 1, CLK_CON_MUX_CLKMUX_MIF2_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF2_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF2_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF2_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_MIF2_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_MIF2_CMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_HPM_MIF2_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMC2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_APBBR_DMCTZ2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_AXI2APB_MIF2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BUSIF_HPMMIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DDRPHY2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_DMC2_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_LHM_AXI_P_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_PMU_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF2_UID_SYSREG_MIF2_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_DMC2_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_LHM_PSCDC_D_MIF2_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DEBUG2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_BCMPPC_DVFS2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF2_UID_RSTNSYNC_CLK_MIF_BUSD2_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY2_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY2_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC2_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ2_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMCTZ2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ2_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMCTZ2_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMCTZ2_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF2_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF2_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF2_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF2_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF2_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF2_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF2_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF2_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY2_QCH_ENABLE, 0, 1, QCH_CON_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY2_QCH_CLOCK_REQ, 1, 1, QCH_CON_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DDRPHY2_QCH), |
| SFR_ACCESS(QCH_CON_DMC2_QCH_ENABLE, 0, 1, QCH_CON_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_DMC2_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_DMC2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC2_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF2_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_MIF2_CMU_MIF2_QCH_ENABLE, 0, 1, QCH_CON_MIF2_CMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_MIF2_CMU_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF2_CMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_MIF2_CMU_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF2_CMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF2_QCH_ENABLE, 0, 1, QCH_CON_PMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG2_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DEBUG2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DEBUG2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DEBUG2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS2_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DVFS2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS2_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DVFS2_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DVFS2_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF2_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF2_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF2_QCH), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_MIF3_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF3_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_MIF3_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF3_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_MIF3_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_MIF3_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_MIF3_CMUREF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_PRE_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF3_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_PRE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF3_PRE), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_PRE_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_MIF3_PRE), |
| SFR_ACCESS(CLK_CON_DIV_CLK_MIF3_BUSD_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_CLK_MIF3_BUSD), |
| SFR_ACCESS(PLL_CON0_PLL_MIF3_DIV_P, 8, 6, PLL_CON0_PLL_MIF3), |
| SFR_ACCESS(PLL_CON0_PLL_MIF3_DIV_M, 16, 10, PLL_CON0_PLL_MIF3), |
| SFR_ACCESS(PLL_CON0_PLL_MIF3_DIV_S, 0, 3, PLL_CON0_PLL_MIF3), |
| SFR_ACCESS(PLL_CON0_PLL_MIF3_ENABLE, 31, 1, PLL_CON0_PLL_MIF3), |
| SFR_ACCESS(PLL_CON0_PLL_MIF3_STABLE, 29, 1, PLL_CON0_PLL_MIF3), |
| SFR_ACCESS(PLL_LOCKTIME_PLL_MIF3_PLL_LOCK_TIME, 0, 20, PLL_LOCKTIME_PLL_MIF3), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_BUSY, 16, 1, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X_SELECT, 0, 1, CLK_CON_MUX_CLKMUX_MIF3_DDRPHY2X), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_MIF3_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_MIF3_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_MIF3_BUSP_DIVRATIO, 0, 2, CLK_CON_DIV_DIV_CLK_MIF3_BUSP), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_HPM_MIF3_IPCLKPORT_HPM_TARGETCLK_C), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMC3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_APBBR_DMCTZ3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_AXI2APB_MIF3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BUSIF_HPMMIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DDRPHY3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_LHM_AXI_P_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_PMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSP3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_SYSREG_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_DMC3_IPCLKPORT_PCLK2), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_MIF3_CMU_MIF3_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_DMC3_IPCLKPORT_SOC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_LHM_PSCDC_D_MIF3_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DEBUG3_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_MIF3_UID_BCMPPC_DVFS3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_MIF3_UID_RSTNSYNC_CLK_MIF_BUSD3_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY3_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY3_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DDRPHY3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC3_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMC3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ3_QCH_ENABLE, 0, 1, QCH_CON_APBBR_DMCTZ3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ3_QCH_CLOCK_REQ, 1, 1, QCH_CON_APBBR_DMCTZ3_QCH), |
| SFR_ACCESS(QCH_CON_APBBR_DMCTZ3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_APBBR_DMCTZ3_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF3_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_HPMMIF3_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_HPMMIF3_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_HPMMIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_HPMMIF3_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF3_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_MIF3_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_MIF3_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_MIF3_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY3_QCH_ENABLE, 0, 1, QCH_CON_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY3_QCH_CLOCK_REQ, 1, 1, QCH_CON_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_DDRPHY3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DDRPHY3_QCH), |
| SFR_ACCESS(QCH_CON_DMC3_QCH_ENABLE, 0, 1, QCH_CON_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_DMC3_QCH_CLOCK_REQ, 1, 1, QCH_CON_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_DMC3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_DMC3_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF3_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_MIF3_CMU_MIF3_QCH_ENABLE, 0, 1, QCH_CON_MIF3_CMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_MIF3_CMU_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_MIF3_CMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_MIF3_CMU_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MIF3_CMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF3_QCH_ENABLE, 0, 1, QCH_CON_PMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_PMU_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG3_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DEBUG3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DEBUG3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DEBUG3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DEBUG3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS3_QCH_ENABLE, 0, 1, QCH_CON_BCMPPC_DVFS3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS3_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCMPPC_DVFS3_QCH), |
| SFR_ACCESS(QCH_CON_BCMPPC_DVFS3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCMPPC_DVFS3_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF3_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF3_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_MIF3_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_MIF3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_MIF3_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PWM_IPCLKPORT_I_PCLK_S0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_UART_DBG_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_UART_DBG_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI00_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_USI00_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI01_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_USI01_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI02_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_USI02_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC0_USI03_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC0_USI03_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_UART_DBG_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI00_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI01_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI02_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_USI03_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_AXI2APB_PERIC0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC0_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SPEEDY2_TSP_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC0_CMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PERIC0_CMU_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC0_CMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_PMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_PWM_QCH_ENABLE, 0, 1, QCH_CON_PWM_QCH), |
| SFR_ACCESS(QCH_CON_PWM_QCH_CLOCK_REQ, 1, 1, QCH_CON_PWM_QCH), |
| SFR_ACCESS(QCH_CON_PWM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PWM_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_TSP_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_TSP_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_TSP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC0_QCH), |
| SFR_ACCESS(QCH_CON_UART_DBG_QCH_ENABLE, 0, 1, QCH_CON_UART_DBG_QCH), |
| SFR_ACCESS(QCH_CON_UART_DBG_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_DBG_QCH), |
| SFR_ACCESS(QCH_CON_UART_DBG_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_DBG_QCH), |
| SFR_ACCESS(QCH_CON_USI00_QCH_ENABLE, 0, 1, QCH_CON_USI00_QCH), |
| SFR_ACCESS(QCH_CON_USI00_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI00_QCH), |
| SFR_ACCESS(QCH_CON_USI00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI00_QCH), |
| SFR_ACCESS(QCH_CON_USI01_QCH_ENABLE, 0, 1, QCH_CON_USI01_QCH), |
| SFR_ACCESS(QCH_CON_USI01_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI01_QCH), |
| SFR_ACCESS(QCH_CON_USI01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI01_QCH), |
| SFR_ACCESS(QCH_CON_USI02_QCH_ENABLE, 0, 1, QCH_CON_USI02_QCH), |
| SFR_ACCESS(QCH_CON_USI02_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI02_QCH), |
| SFR_ACCESS(QCH_CON_USI02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI02_QCH), |
| SFR_ACCESS(QCH_CON_USI03_QCH_ENABLE, 0, 1, QCH_CON_USI03_QCH), |
| SFR_ACCESS(QCH_CON_USI03_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI03_QCH), |
| SFR_ACCESS(QCH_CON_USI03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI03_QCH), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_XIU_P_PERIC1_IPCLKPORT_ACLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_UART_BT_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_UART_BT_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P0_IPCLKPORT_ACLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI05_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI05_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI06_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI06_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI07_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI07_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI08_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI08_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI09_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI09_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI10_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI11_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI12_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI13_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_UART_BT_IPCLKPORT_EXT_UCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI10_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI11_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI12_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI13_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI05_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI06_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI07_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI08_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI09_IPCLKPORT_I_SCLK_USI), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_USI04_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_USI04_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM2_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM3_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM0_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM0_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPI_CAM1_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_SPI_CAM1_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM0_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPI_CAM1_IPCLKPORT_SPI_EXT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_USI04_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM1_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_HSI2C_CAM0_IPCLKPORT_IPCLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIC1_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_CLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIC1_SPEEDY2_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIC1_SPEEDY2_USER), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_SPEEDY2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI1_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_DDI2_IPCLKPORT_SCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP1_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SPEEDY2_TSP2_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIC1_UID_AXI2APB_PERIC1P2_IPCLKPORT_ACLK), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_GPIO_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM0_QCH_ENABLE, 0, 1, QCH_CON_HSI2C_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2C_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2C_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM1_QCH_ENABLE, 0, 1, QCH_CON_HSI2C_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2C_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2C_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM2_QCH_ENABLE, 0, 1, QCH_CON_HSI2C_CAM2_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM2_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2C_CAM2_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2C_CAM2_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM3_QCH_ENABLE, 0, 1, QCH_CON_HSI2C_CAM3_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM3_QCH_CLOCK_REQ, 1, 1, QCH_CON_HSI2C_CAM3_QCH), |
| SFR_ACCESS(QCH_CON_HSI2C_CAM3_QCH_EXPIRE_VAL, 16, 10, QCH_CON_HSI2C_CAM3_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIC1_CMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PERIC1_CMU_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIC1_CMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_PMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_DDI_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_DDI_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_DDI_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI1_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_DDI1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_DDI1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_DDI1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI2_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_DDI2_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_DDI2_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_DDI2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_DDI2_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP1_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_TSP1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_TSP1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_TSP1_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP2_QCH_ENABLE, 0, 1, QCH_CON_SPEEDY2_TSP2_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP2_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPEEDY2_TSP2_QCH), |
| SFR_ACCESS(QCH_CON_SPEEDY2_TSP2_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPEEDY2_TSP2_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_ENABLE, 0, 1, QCH_CON_SPI_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_CAM0_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM1_QCH_ENABLE, 0, 1, QCH_CON_SPI_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SPI_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_SPI_CAM1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SPI_CAM1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIC1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIC1_QCH), |
| SFR_ACCESS(QCH_CON_UART_BT_QCH_ENABLE, 0, 1, QCH_CON_UART_BT_QCH), |
| SFR_ACCESS(QCH_CON_UART_BT_QCH_CLOCK_REQ, 1, 1, QCH_CON_UART_BT_QCH), |
| SFR_ACCESS(QCH_CON_UART_BT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_UART_BT_QCH), |
| SFR_ACCESS(QCH_CON_USI04_QCH_ENABLE, 0, 1, QCH_CON_USI04_QCH), |
| SFR_ACCESS(QCH_CON_USI04_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI04_QCH), |
| SFR_ACCESS(QCH_CON_USI04_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI04_QCH), |
| SFR_ACCESS(QCH_CON_USI05_QCH_ENABLE, 0, 1, QCH_CON_USI05_QCH), |
| SFR_ACCESS(QCH_CON_USI05_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI05_QCH), |
| SFR_ACCESS(QCH_CON_USI05_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI05_QCH), |
| SFR_ACCESS(QCH_CON_USI06_QCH_ENABLE, 0, 1, QCH_CON_USI06_QCH), |
| SFR_ACCESS(QCH_CON_USI06_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI06_QCH), |
| SFR_ACCESS(QCH_CON_USI06_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI06_QCH), |
| SFR_ACCESS(QCH_CON_USI07_QCH_ENABLE, 0, 1, QCH_CON_USI07_QCH), |
| SFR_ACCESS(QCH_CON_USI07_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI07_QCH), |
| SFR_ACCESS(QCH_CON_USI07_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI07_QCH), |
| SFR_ACCESS(QCH_CON_USI08_QCH_ENABLE, 0, 1, QCH_CON_USI08_QCH), |
| SFR_ACCESS(QCH_CON_USI08_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI08_QCH), |
| SFR_ACCESS(QCH_CON_USI08_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI08_QCH), |
| SFR_ACCESS(QCH_CON_USI09_QCH_ENABLE, 0, 1, QCH_CON_USI09_QCH), |
| SFR_ACCESS(QCH_CON_USI09_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI09_QCH), |
| SFR_ACCESS(QCH_CON_USI09_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI09_QCH), |
| SFR_ACCESS(QCH_CON_USI10_QCH_ENABLE, 0, 1, QCH_CON_USI10_QCH), |
| SFR_ACCESS(QCH_CON_USI10_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI10_QCH), |
| SFR_ACCESS(QCH_CON_USI10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI10_QCH), |
| SFR_ACCESS(QCH_CON_USI11_QCH_ENABLE, 0, 1, QCH_CON_USI11_QCH), |
| SFR_ACCESS(QCH_CON_USI11_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI11_QCH), |
| SFR_ACCESS(QCH_CON_USI11_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI11_QCH), |
| SFR_ACCESS(QCH_CON_USI12_QCH_ENABLE, 0, 1, QCH_CON_USI12_QCH), |
| SFR_ACCESS(QCH_CON_USI12_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI12_QCH), |
| SFR_ACCESS(QCH_CON_USI12_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI12_QCH), |
| SFR_ACCESS(QCH_CON_USI13_QCH_ENABLE, 0, 1, QCH_CON_USI13_QCH), |
| SFR_ACCESS(QCH_CON_USI13_QCH_CLOCK_REQ, 1, 1, QCH_CON_USI13_QCH), |
| SFR_ACCESS(QCH_CON_USI13_QCH_EXPIRE_VAL, 16, 10, QCH_CON_USI13_QCH), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP0_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AXI2APB_PERISP1_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_LHM_AXI_P_PERIS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_XIU_P_PERIS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_MCT_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_TOP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_PMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_BUSIF_TMU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC00_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC01_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC10_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC11_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC12_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC13_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC14_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC15_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC02_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC03_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC04_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC05_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC06_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC07_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC08_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_TZPC09_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_PERIS_UID_PERIS_CMU_PERIS_IPCLKPORT_PCLK), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_PERIS_BUS_USER), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_PERIS_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_PERIS_GIC), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_PERIS_GIC_SELECT, 0, 5, CLK_CON_MUX_MUX_CLK_PERIS_GIC), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_RSTNSYNC_CLK_PERIS_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_AD_AXI_P_PERIS_IPCLKPORT_ACLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_OTP_CON_BIRA_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_PERIS_UID_GIC_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_ENABLE, 0, 1, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_BUSIF_TMU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BUSIF_TMU_QCH), |
| SFR_ACCESS(QCH_CON_GIC_QCH_ENABLE, 0, 1, QCH_CON_GIC_QCH), |
| SFR_ACCESS(QCH_CON_GIC_QCH_CLOCK_REQ, 1, 1, QCH_CON_GIC_QCH), |
| SFR_ACCESS(QCH_CON_GIC_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GIC_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_ENABLE, 0, 1, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_CLOCK_REQ, 1, 1, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_MCT_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MCT_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_BIRA_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_BIRA_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_BIRA_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_BIRA_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_ENABLE, 0, 1, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_CLOCK_REQ, 1, 1, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_OTP_CON_TOP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_OTP_CON_TOP_QCH), |
| SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_ENABLE, 0, 1, QCH_CON_PERIS_CMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PERIS_CMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_PERIS_CMU_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PERIS_CMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIS_QCH_ENABLE, 0, 1, QCH_CON_PMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_PMU_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_PERIS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_PERIS_QCH), |
| SFR_ACCESS(QCH_CON_TZPC00_QCH_ENABLE, 0, 1, QCH_CON_TZPC00_QCH), |
| SFR_ACCESS(QCH_CON_TZPC00_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC00_QCH), |
| SFR_ACCESS(QCH_CON_TZPC00_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC00_QCH), |
| SFR_ACCESS(QCH_CON_TZPC01_QCH_ENABLE, 0, 1, QCH_CON_TZPC01_QCH), |
| SFR_ACCESS(QCH_CON_TZPC01_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC01_QCH), |
| SFR_ACCESS(QCH_CON_TZPC01_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC01_QCH), |
| SFR_ACCESS(QCH_CON_TZPC02_QCH_ENABLE, 0, 1, QCH_CON_TZPC02_QCH), |
| SFR_ACCESS(QCH_CON_TZPC02_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC02_QCH), |
| SFR_ACCESS(QCH_CON_TZPC02_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC02_QCH), |
| SFR_ACCESS(QCH_CON_TZPC03_QCH_ENABLE, 0, 1, QCH_CON_TZPC03_QCH), |
| SFR_ACCESS(QCH_CON_TZPC03_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC03_QCH), |
| SFR_ACCESS(QCH_CON_TZPC03_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC03_QCH), |
| SFR_ACCESS(QCH_CON_TZPC04_QCH_ENABLE, 0, 1, QCH_CON_TZPC04_QCH), |
| SFR_ACCESS(QCH_CON_TZPC04_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC04_QCH), |
| SFR_ACCESS(QCH_CON_TZPC04_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC04_QCH), |
| SFR_ACCESS(QCH_CON_TZPC05_QCH_ENABLE, 0, 1, QCH_CON_TZPC05_QCH), |
| SFR_ACCESS(QCH_CON_TZPC05_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC05_QCH), |
| SFR_ACCESS(QCH_CON_TZPC05_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC05_QCH), |
| SFR_ACCESS(QCH_CON_TZPC06_QCH_ENABLE, 0, 1, QCH_CON_TZPC06_QCH), |
| SFR_ACCESS(QCH_CON_TZPC06_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC06_QCH), |
| SFR_ACCESS(QCH_CON_TZPC06_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC06_QCH), |
| SFR_ACCESS(QCH_CON_TZPC07_QCH_ENABLE, 0, 1, QCH_CON_TZPC07_QCH), |
| SFR_ACCESS(QCH_CON_TZPC07_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC07_QCH), |
| SFR_ACCESS(QCH_CON_TZPC07_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC07_QCH), |
| SFR_ACCESS(QCH_CON_TZPC08_QCH_ENABLE, 0, 1, QCH_CON_TZPC08_QCH), |
| SFR_ACCESS(QCH_CON_TZPC08_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC08_QCH), |
| SFR_ACCESS(QCH_CON_TZPC08_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC08_QCH), |
| SFR_ACCESS(QCH_CON_TZPC09_QCH_ENABLE, 0, 1, QCH_CON_TZPC09_QCH), |
| SFR_ACCESS(QCH_CON_TZPC09_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC09_QCH), |
| SFR_ACCESS(QCH_CON_TZPC09_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC09_QCH), |
| SFR_ACCESS(QCH_CON_TZPC10_QCH_ENABLE, 0, 1, QCH_CON_TZPC10_QCH), |
| SFR_ACCESS(QCH_CON_TZPC10_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC10_QCH), |
| SFR_ACCESS(QCH_CON_TZPC10_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC10_QCH), |
| SFR_ACCESS(QCH_CON_TZPC11_QCH_ENABLE, 0, 1, QCH_CON_TZPC11_QCH), |
| SFR_ACCESS(QCH_CON_TZPC11_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC11_QCH), |
| SFR_ACCESS(QCH_CON_TZPC11_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC11_QCH), |
| SFR_ACCESS(QCH_CON_TZPC12_QCH_ENABLE, 0, 1, QCH_CON_TZPC12_QCH), |
| SFR_ACCESS(QCH_CON_TZPC12_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC12_QCH), |
| SFR_ACCESS(QCH_CON_TZPC12_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC12_QCH), |
| SFR_ACCESS(QCH_CON_TZPC13_QCH_ENABLE, 0, 1, QCH_CON_TZPC13_QCH), |
| SFR_ACCESS(QCH_CON_TZPC13_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC13_QCH), |
| SFR_ACCESS(QCH_CON_TZPC13_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC13_QCH), |
| SFR_ACCESS(QCH_CON_TZPC14_QCH_ENABLE, 0, 1, QCH_CON_TZPC14_QCH), |
| SFR_ACCESS(QCH_CON_TZPC14_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC14_QCH), |
| SFR_ACCESS(QCH_CON_TZPC14_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC14_QCH), |
| SFR_ACCESS(QCH_CON_TZPC15_QCH_ENABLE, 0, 1, QCH_CON_TZPC15_QCH), |
| SFR_ACCESS(QCH_CON_TZPC15_QCH_CLOCK_REQ, 1, 1, QCH_CON_TZPC15_QCH), |
| SFR_ACCESS(QCH_CON_TZPC15_QCH_EXPIRE_VAL, 16, 10, QCH_CON_TZPC15_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER0_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER0_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_ENABLE, 0, 1, QCH_CON_WDT_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_CLUSTER1_QCH), |
| SFR_ACCESS(QCH_CON_WDT_CLUSTER1_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_CLUSTER1_QCH), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SRDZ_IMGD_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_SRDZ_IMGD_USER), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_SRDZ_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_SRDZ_BUSP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_SRDZ_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_SRDZ_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_SRDZ_UID_SRDZ_CMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_RSTNSYNC_CLK_SRDZ_IMGD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PMU_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SYSREG_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AXI2APB_SRDZ_SYS_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_AD_APB_SRDZ_IPCLKPORT_PCLKM), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_D_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_XIU_P_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BCM_SRDZ_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_SMMU_SRDZ_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_BTM_SRDZ_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_P_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_D_SRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_AXI_P_SRDZDCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_AXI_D_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHS_ATB_SRDZCAM_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_SRDZ_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_LHM_ATB_DCAMSRDZ_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBM_1TO2_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_SRDZ_UID_PXL_ASBS_SRDZ_IPCLKPORT_CLK), |
| SFR_ACCESS(QCH_CON_BTM_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_BTM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_BTM_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_BTM_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_DCAMSRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHM_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_DCAMSRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_ATB_DCAMSRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_ATB_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_D_DCAMSRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_SRDZCAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_SRDZCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ATB_SRDZCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ATB_SRDZCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_P_SRDZDCAM_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_P_SRDZDCAM_QCH), |
| SFR_ACCESS(QCH_CON_PMU_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_PMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_PMU_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_BCM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_BCM_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_SMMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_CMU_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_SRDZ_CMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_CMU_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SRDZ_CMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SRDZ_CMU_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SRDZ_CMU_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_SRDZ_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_SRDZ_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_SRDZ_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_SRDZ_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_SRDZ_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPU_BUSP_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VPU_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPU_BUSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VPU_BUSP), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VPU_BUSP_DIVRATIO, 0, 3, CLK_CON_DIV_DIV_CLK_VPU_BUSP), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_BUSY, 7, 1, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER), |
| SFR_ACCESS(PLL_CON0_MUX_CLKCMU_VPU_BUS_USER_MUX_SEL, 4, 1, PLL_CON0_MUX_CLKCMU_VPU_BUS_USER), |
| SFR_ACCESS(PLL_CON2_MUX_CLKCMU_VPU_BUS_USER_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PLL_CON2_MUX_CLKCMU_VPU_BUS_USER), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VPU_UID_VPU_CMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_VPU_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_PMU_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SYSREG_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2APB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_P_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BCM_VPU_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_NONSECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_ACEL_D_VPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_BTM_VPU_IPCLKPORT_I_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_SMMU_VPU_IPCLKPORT_PCLK_SECURE), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VPU_CMU_CLKOUT0), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_AXI2AHB_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_VPU_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VPU_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSD_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_RSTNSYNC_CLK_VPU_BUSP_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_XIU_D_VPU_IPCLKPORT_ACLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHM_AXI_P_DSPVPU_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VPU_UID_LHS_AXI_D_VPUDSP_IPCLKPORT_I_CLK), |
| SFR_ACCESS(QCH_CON_BTM_VPU_QCH_ENABLE, 0, 1, QCH_CON_BTM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_BTM_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BTM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_BTM_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BTM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPVPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPVPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_DSPVPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_DSPVPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VPU_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_VPU_QCH_ENABLE, 0, 1, QCH_CON_LHS_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_ACEL_D_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_ACEL_D_VPU_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VPUDSP_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VPUDSP_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VPUDSP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VPUDSP_QCH), |
| SFR_ACCESS(QCH_CON_PMU_VPU_QCH_ENABLE, 0, 1, QCH_CON_PMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_PMU_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_PMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_PMU_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_PMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_VPU_QCH_ENABLE, 0, 1, QCH_CON_BCM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_BCM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_BCM_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_BCM_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_VPU_QCH_ENABLE, 0, 1, QCH_CON_SMMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SMMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SMMU_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SMMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VPU_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VPU_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_QCH_ENABLE, 0, 1, QCH_CON_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_CMU_VPU_QCH_ENABLE, 0, 1, QCH_CON_VPU_CMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_CMU_VPU_QCH_CLOCK_REQ, 1, 1, QCH_CON_VPU_CMU_VPU_QCH), |
| SFR_ACCESS(QCH_CON_VPU_CMU_VPU_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VPU_CMU_VPU_QCH), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_BUS_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLK_VTS_BUS), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMICIF_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMICIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMICIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMICIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMICIF_DIVRATIO, 0, 6, CLK_CON_DIV_DIV_CLK_VTS_DMICIF), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_SELECT, 8, 5, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_BUSY, 16, 1, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VTS_CMU_CLKOUT0), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_SELECT, 8, 5, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_BUSY, 16, 1, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1), |
| SFR_ACCESS(CLKOUT_CON_BLK_VTS_CMU_CLKOUT1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLKOUT_CON_BLK_VTS_CMU_CLKOUT1), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_VTS_CMU_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHM_AXI_P_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_LHS_AXI_D_VTS_IPCLKPORT_I_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_SYS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_BUS_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_RSTNSYNC_CLK_VTS_DMICIF_IPCLKPORT_CLK), |
| SFR_ACCESS(OSC_CON2_OSC_VTS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, OSC_CON2_OSC_VTS), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_VTS_IPCLKPORT_ACLK_CPU), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_BUSY, 16, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2_DIVRATIO, 0, 1, CLK_CON_DIV_DIV_CLK_VTS_DMIC_DIV2), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_WDT_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_SYSREG_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMICIF_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_MAILBOX_VTS2AP_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_HCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_AHB_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_DIV_DIV_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_DIV_DIV_CLK_VTS_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_CMUREF_BUSY, 16, 1, CLK_CON_MUX_MUX_CLK_VTS_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_CMUREF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_MUX_MUX_CLK_VTS_CMUREF), |
| SFR_ACCESS(CLK_CON_MUX_MUX_CLK_VTS_CMUREF_SELECT, 0, 1, CLK_CON_MUX_MUX_CLK_VTS_CMUREF), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_GPIO_VTS_IPCLKPORT_PCLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_CG_VAL, 21, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_MANUAL, 20, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK), |
| SFR_ACCESS(CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_GOUT_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_DIV2_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_CG_VAL, 21, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_MANUAL, 20, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK), |
| SFR_ACCESS(CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CLK_CON_GAT_CLK_BLK_VTS_UID_DMIC_IF_IPCLKPORT_DMIC_CLK), |
| SFR_ACCESS(DMYQCH_CON_CMU_VTS_CMUREF_QCH_ENABLE, 0, 1, DMYQCH_CON_CMU_VTS_CMUREF_QCH), |
| SFR_ACCESS(DMYQCH_CON_CMU_VTS_CMUREF_QCH_CLOCK_REQ, 1, 1, DMYQCH_CON_CMU_VTS_CMUREF_QCH), |
| SFR_ACCESS(QCH_CON_DMIC_AHB_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_AHB_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_DMIC_AHB_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_AHB_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_DMIC_AHB_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_AHB_QCH_PCLK), |
| SFR_ACCESS(DMYQCH_CON_DMIC_AHB_QCH_HCLK_ENABLE, 0, 1, DMYQCH_CON_DMIC_AHB_QCH_HCLK), |
| SFR_ACCESS(DMYQCH_CON_DMIC_AHB_QCH_HCLK_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_AHB_QCH_HCLK), |
| SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_ENABLE, 0, 1, QCH_CON_DMIC_IF_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_CLOCK_REQ, 1, 1, QCH_CON_DMIC_IF_QCH_PCLK), |
| SFR_ACCESS(QCH_CON_DMIC_IF_QCH_PCLK_EXPIRE_VAL, 16, 10, QCH_CON_DMIC_IF_QCH_PCLK), |
| SFR_ACCESS(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_ENABLE, 0, 1, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK), |
| SFR_ACCESS(DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK_CLOCK_REQ, 1, 1, DMYQCH_CON_DMIC_IF_QCH_DMIC_CLK), |
| SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_ENABLE, 0, 1, QCH_CON_GPIO_VTS_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_GPIO_VTS_QCH), |
| SFR_ACCESS(QCH_CON_GPIO_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_GPIO_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHM_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHM_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHM_AXI_P_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHM_AXI_P_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_ENABLE, 0, 1, QCH_CON_LHS_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_LHS_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_LHS_AXI_D_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_LHS_AXI_D_VTS_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_VTS2AP_QCH_ENABLE, 0, 1, QCH_CON_MAILBOX_VTS2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_VTS2AP_QCH_CLOCK_REQ, 1, 1, QCH_CON_MAILBOX_VTS2AP_QCH), |
| SFR_ACCESS(QCH_CON_MAILBOX_VTS2AP_QCH_EXPIRE_VAL, 16, 10, QCH_CON_MAILBOX_VTS2AP_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_ENABLE, 0, 1, QCH_CON_SYSREG_VTS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_SYSREG_VTS_QCH), |
| SFR_ACCESS(QCH_CON_SYSREG_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_SYSREG_VTS_QCH), |
| SFR_ACCESS(QCH_CON_VTS_QCH_CPU_ENABLE, 0, 1, QCH_CON_VTS_QCH_CPU), |
| SFR_ACCESS(QCH_CON_VTS_QCH_CPU_CLOCK_REQ, 1, 1, QCH_CON_VTS_QCH_CPU), |
| SFR_ACCESS(QCH_CON_VTS_QCH_CPU_EXPIRE_VAL, 16, 10, QCH_CON_VTS_QCH_CPU), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_ENABLE, 0, 1, QCH_CON_VTS_QCH_SYS), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_CLOCK_REQ, 1, 1, QCH_CON_VTS_QCH_SYS), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_EXPIRE_VAL, 16, 10, QCH_CON_VTS_QCH_SYS), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_DMIC_ENABLE, 0, 1, QCH_CON_VTS_QCH_SYS_DMIC), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_DMIC_CLOCK_REQ, 1, 1, QCH_CON_VTS_QCH_SYS_DMIC), |
| SFR_ACCESS(QCH_CON_VTS_QCH_SYS_DMIC_EXPIRE_VAL, 16, 10, QCH_CON_VTS_QCH_SYS_DMIC), |
| SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_ENABLE, 0, 1, QCH_CON_VTS_CMU_VTS_QCH), |
| SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_VTS_CMU_VTS_QCH), |
| SFR_ACCESS(QCH_CON_VTS_CMU_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_VTS_CMU_VTS_QCH), |
| SFR_ACCESS(QCH_CON_WDT_VTS_QCH_ENABLE, 0, 1, QCH_CON_WDT_VTS_QCH), |
| SFR_ACCESS(QCH_CON_WDT_VTS_QCH_CLOCK_REQ, 1, 1, QCH_CON_WDT_VTS_QCH), |
| SFR_ACCESS(QCH_CON_WDT_VTS_QCH_EXPIRE_VAL, 16, 10, QCH_CON_WDT_VTS_QCH), |
| /*====================The section of controller option SFR ACCESS instance===================*/ |
| SFR_ACCESS(ABOX_ENABLE_POWER_MANAGEMENT, 29, 1, ABOX_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(ABOX_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ABOX_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(APM_ENABLE_POWER_MANAGEMENT, 29, 1, APM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(APM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, APM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(BUS1_ENABLE_POWER_MANAGEMENT, 29, 1, BUS1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(BUS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUS1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(BUSC_ENABLE_POWER_MANAGEMENT, 29, 1, BUSC_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(BUSC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, BUSC_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CAM_ENABLE_POWER_MANAGEMENT, 29, 1, CAM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CAM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CMU_ENABLE_POWER_MANAGEMENT, 29, 1, CMU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CMU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CMU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CORE_ENABLE_POWER_MANAGEMENT, 29, 1, CORE_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CORE_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CORE_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL0_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL1_ENABLE_POWER_MANAGEMENT, 29, 1, CPUCL1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(CPUCL1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, CPUCL1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DBG_ENABLE_POWER_MANAGEMENT, 29, 1, DBG_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DBG_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DBG_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DCAM_ENABLE_POWER_MANAGEMENT, 29, 1, DCAM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DCAM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DCAM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DPU0_ENABLE_POWER_MANAGEMENT, 29, 1, DPU0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DPU0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPU0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DPU1_ENABLE_POWER_MANAGEMENT, 29, 1, DPU1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DPU1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DPU1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DSP_ENABLE_POWER_MANAGEMENT, 29, 1, DSP_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(DSP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, DSP_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS0_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS1_ENABLE_POWER_MANAGEMENT, 29, 1, FSYS1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(FSYS1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, FSYS1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G2D_ENABLE_POWER_MANAGEMENT, 29, 1, G2D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G2D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G2D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G3D_ENABLE_POWER_MANAGEMENT, 29, 1, G3D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(G3D_ENABLE_AUTOMATIC_CLKGATING, 28, 1, G3D_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IMEM_ENABLE_POWER_MANAGEMENT, 29, 1, IMEM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IMEM_ENABLE_AUTOMATIC_CLKGATING, 28, 1, IMEM_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(ISPHQ_ENABLE_POWER_MANAGEMENT, 29, 1, ISPHQ_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(ISPHQ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISPHQ_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(ISPLP_ENABLE_POWER_MANAGEMENT, 29, 1, ISPLP_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(ISPLP_ENABLE_AUTOMATIC_CLKGATING, 28, 1, ISPLP_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IVA_ENABLE_POWER_MANAGEMENT, 29, 1, IVA_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(IVA_ENABLE_AUTOMATIC_CLKGATING, 28, 1, IVA_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MFC_ENABLE_POWER_MANAGEMENT, 29, 1, MFC_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MFC_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MFC_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF_ENABLE_POWER_MANAGEMENT, 29, 1, MIF_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF1_ENABLE_POWER_MANAGEMENT, 29, 1, MIF1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF2_ENABLE_POWER_MANAGEMENT, 29, 1, MIF2_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF2_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF2_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF3_ENABLE_POWER_MANAGEMENT, 29, 1, MIF3_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(MIF3_ENABLE_AUTOMATIC_CLKGATING, 28, 1, MIF3_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIC0_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIC0_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC0_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIC1_ENABLE_POWER_MANAGEMENT, 29, 1, PERIC1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIC1_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIC1_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIS_ENABLE_POWER_MANAGEMENT, 29, 1, PERIS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(PERIS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, PERIS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(SRDZ_ENABLE_POWER_MANAGEMENT, 29, 1, SRDZ_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(SRDZ_ENABLE_AUTOMATIC_CLKGATING, 28, 1, SRDZ_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(VPU_ENABLE_POWER_MANAGEMENT, 29, 1, VPU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(VPU_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VPU_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(VTS_ENABLE_POWER_MANAGEMENT, 29, 1, VTS_CMU_CONTROLLER_OPTION), |
| SFR_ACCESS(VTS_ENABLE_AUTOMATIC_CLKGATING, 28, 1, VTS_CMU_CONTROLLER_OPTION), |
| }; |
| |
| unsigned int cmucal_sfr_access_size = 5950; |
| |