drivers/net/wireless/rtlwifi/rtl8192ce/phy.c - LeafOS-Devices/android_kernel_samsung_exynos9820 - Gitiles

 /******************************************************************************
  *
  * Copyright(c) 2009-2012  Realtek Corporation.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of version 2 of the GNU General Public License as
  * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
  *
  * You should have received a copy of the GNU General Public License along with
  * this program; if not, write to the Free Software Foundation, Inc.,
  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  *
  * The full GNU General Public License is included in this distribution in the
  * file called LICENSE.
  *
  * Contact Information:
  * wlanfae <wlanfae@realtek.com>
  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  * Hsinchu 300, Taiwan.
  *
  * Larry Finger <Larry.Finger@lwfinger.net>
  *
  *****************************************************************************/

 #include "../wifi.h"
 #include "../pci.h"
 #include "../ps.h"
 #include "reg.h"
 #include "def.h"
 #include "hw.h"
 #include "phy.h"
 #include "rf.h"
 #include "dm.h"
 #include "table.h"

 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);

 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
 			    enum radio_path rfpath, u32 regaddr, u32 bitmask)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u32 original_value, readback_value, bitshift;
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);

 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 		 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
 		 regaddr, rfpath, bitmask);

 	spin_lock(&rtlpriv->locks.rf_lock);

 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
 		original_value = _rtl92c_phy_rf_serial_read(hw,
 							    rfpath, regaddr);
 	} else {
 		original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 							       rfpath, regaddr);
 	}

 	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 	readback_value = (original_value & bitmask) >> bitshift;

 	spin_unlock(&rtlpriv->locks.rf_lock);

 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 		 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
 		 regaddr, rfpath, bitmask, original_value);

 	return readback_value;
 }

 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 	bool is92c = IS_92C_SERIAL(rtlhal->version);
 	bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);

 	if (is92c)
 		rtl_write_byte(rtlpriv, 0x14, 0x71);
 	return rtstatus;
 }

 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
 {
 	bool rtstatus = true;
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u16 regval;
 	u32 regvaldw;
 	u8 reg_hwparafile = 1;

 	_rtl92c_phy_init_bb_rf_register_definition(hw);
 	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
 		       regval | BIT(13) | BIT(0) | BIT(1));
 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
 	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
 	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
 		       FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
 		       FEN_BB_GLB_RSTn | FEN_BBRSTB);
 	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
 	regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
 	rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
 	if (reg_hwparafile == 1)
 		rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
 	return rtstatus;
 }

 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
 			    enum radio_path rfpath,
 			    u32 regaddr, u32 bitmask, u32 data)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 	u32 original_value, bitshift;

 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 		 regaddr, bitmask, data, rfpath);

 	spin_lock(&rtlpriv->locks.rf_lock);

 	if (rtlphy->rf_mode != RF_OP_BY_FW) {
 		if (bitmask != RFREG_OFFSET_MASK) {
 			original_value = _rtl92c_phy_rf_serial_read(hw,
 								    rfpath,
 								    regaddr);
 			bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 			data =
 			    ((original_value & (~bitmask)) |
 			     (data << bitshift));
 		}

 		_rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
 	} else {
 		if (bitmask != RFREG_OFFSET_MASK) {
 			original_value = _rtl92c_phy_fw_rf_serial_read(hw,
 								       rfpath,
 								       regaddr);
 			bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
 			data =
 			    ((original_value & (~bitmask)) |
 			     (data << bitshift));
 		}
 		_rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
 	}

 	spin_unlock(&rtlpriv->locks.rf_lock);

 	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
 		 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
 		 regaddr, bitmask, data, rfpath);
 }

 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	u32 i;
 	u32 arraylength;
 	u32 *ptrarray;

 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
 	arraylength = MAC_2T_ARRAYLENGTH;
 	ptrarray = RTL8192CEMAC_2T_ARRAY;
 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
 	for (i = 0; i < arraylength; i = i + 2)
 		rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
 	return true;
 }

 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
 					    u8 configtype)
 {
 	int i;
 	u32 *phy_regarray_table;
 	u32 *agctab_array_table;
 	u16 phy_reg_arraylen, agctab_arraylen;
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));

 	if (IS_92C_SERIAL(rtlhal->version)) {
 		agctab_arraylen = AGCTAB_2TARRAYLENGTH;
 		agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
 		phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
 		phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
 	} else {
 		agctab_arraylen = AGCTAB_1TARRAYLENGTH;
 		agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
 		phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
 		phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
 	}
 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
 		for (i = 0; i < phy_reg_arraylen; i = i + 2) {
 			if (phy_regarray_table[i] == 0xfe)
 				mdelay(50);
 			else if (phy_regarray_table[i] == 0xfd)
 				mdelay(5);
 			else if (phy_regarray_table[i] == 0xfc)
 				mdelay(1);
 			else if (phy_regarray_table[i] == 0xfb)
 				udelay(50);
 			else if (phy_regarray_table[i] == 0xfa)
 				udelay(5);
 			else if (phy_regarray_table[i] == 0xf9)
 				udelay(1);
 			rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
 				      phy_regarray_table[i + 1]);
 			udelay(1);
 			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 				 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 				 phy_regarray_table[i],
 				 phy_regarray_table[i + 1]);
 		}
 	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
 		for (i = 0; i < agctab_arraylen; i = i + 2) {
 			rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
 				      agctab_array_table[i + 1]);
 			udelay(1);
 			RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 				 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
 				 agctab_array_table[i],
 				 agctab_array_table[i + 1]);
 		}
 	}
 	return true;
 }

 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
 					      u8 configtype)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	int i;
 	u32 *phy_regarray_table_pg;
 	u16 phy_regarray_pg_len;

 	phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
 	phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;

 	if (configtype == BASEBAND_CONFIG_PHY_REG) {
 		for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
 			if (phy_regarray_table_pg[i] == 0xfe)
 				mdelay(50);
 			else if (phy_regarray_table_pg[i] == 0xfd)
 				mdelay(5);
 			else if (phy_regarray_table_pg[i] == 0xfc)
 				mdelay(1);
 			else if (phy_regarray_table_pg[i] == 0xfb)
 				udelay(50);
 			else if (phy_regarray_table_pg[i] == 0xfa)
 				udelay(5);
 			else if (phy_regarray_table_pg[i] == 0xf9)
 				udelay(1);

 			_rtl92c_store_pwrIndex_diffrate_offset(hw,
 					       phy_regarray_table_pg[i],
 					       phy_regarray_table_pg[i + 1],
 					       phy_regarray_table_pg[i + 2]);
 		}
 	} else {

 		RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
 			 "configtype != BaseBand_Config_PHY_REG\n");
 	}
 	return true;
 }

 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 					  enum radio_path rfpath)
 {

 	int i;
 	u32 *radioa_array_table;
 	u32 *radiob_array_table;
 	u16 radioa_arraylen, radiob_arraylen;
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));

 	if (IS_92C_SERIAL(rtlhal->version)) {
 		radioa_arraylen = RADIOA_2TARRAYLENGTH;
 		radioa_array_table = RTL8192CERADIOA_2TARRAY;
 		radiob_arraylen = RADIOB_2TARRAYLENGTH;
 		radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 			 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 			 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
 	} else {
 		radioa_arraylen = RADIOA_1TARRAYLENGTH;
 		radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
 		radiob_arraylen = RADIOB_1TARRAYLENGTH;
 		radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 			 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
 		RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 			 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
 	}
 	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
 	switch (rfpath) {
 	case RF90_PATH_A:
 		for (i = 0; i < radioa_arraylen; i = i + 2) {
 			if (radioa_array_table[i] == 0xfe)
 				mdelay(50);
 			else if (radioa_array_table[i] == 0xfd)
 				mdelay(5);
 			else if (radioa_array_table[i] == 0xfc)
 				mdelay(1);
 			else if (radioa_array_table[i] == 0xfb)
 				udelay(50);
 			else if (radioa_array_table[i] == 0xfa)
 				udelay(5);
 			else if (radioa_array_table[i] == 0xf9)
 				udelay(1);
 			else {
 				rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
 					      RFREG_OFFSET_MASK,
 					      radioa_array_table[i + 1]);
 				udelay(1);
 			}
 		}
 		break;
 	case RF90_PATH_B:
 		for (i = 0; i < radiob_arraylen; i = i + 2) {
 			if (radiob_array_table[i] == 0xfe) {
 				mdelay(50);
 			} else if (radiob_array_table[i] == 0xfd)
 				mdelay(5);
 			else if (radiob_array_table[i] == 0xfc)
 				mdelay(1);
 			else if (radiob_array_table[i] == 0xfb)
 				udelay(50);
 			else if (radiob_array_table[i] == 0xfa)
 				udelay(5);
 			else if (radiob_array_table[i] == 0xf9)
 				udelay(1);
 			else {
 				rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
 					      RFREG_OFFSET_MASK,
 					      radiob_array_table[i + 1]);
 				udelay(1);
 			}
 		}
 		break;
 	case RF90_PATH_C:
 		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 			 "switch case not processed\n");
 		break;
 	case RF90_PATH_D:
 		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 			 "switch case not processed\n");
 		break;
 	}
 	return true;
 }

 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 	struct rtl_phy *rtlphy = &(rtlpriv->phy);
 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 	u8 reg_bw_opmode;
 	u8 reg_prsr_rsc;

 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
 		 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
 		 "20MHz" : "40MHz");

 	if (is_hal_stop(rtlhal)) {
 		rtlphy->set_bwmode_inprogress = false;
 		return;
 	}

 	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
 	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);

 	switch (rtlphy->current_chan_bw) {
 	case HT_CHANNEL_WIDTH_20:
 		reg_bw_opmode |= BW_OPMODE_20MHZ;
 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 		break;
 	case HT_CHANNEL_WIDTH_20_40:
 		reg_bw_opmode &= ~BW_OPMODE_20MHZ;
 		rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 		reg_prsr_rsc =
 		    (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
 		rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
 		break;
 	default:
 		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 			 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 		break;
 	}

 	switch (rtlphy->current_chan_bw) {
 	case HT_CHANNEL_WIDTH_20:
 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 		break;
 	case HT_CHANNEL_WIDTH_20_40:
 		rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
 		rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);

 		rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
 			      (mac->cur_40_prime_sc >> 1));
 		rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
 		rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);

 		rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
 			      (mac->cur_40_prime_sc ==
 			       HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 		break;
 	default:
 		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 			 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
 		break;
 	}
 	rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
 	rtlphy->set_bwmode_inprogress = false;
 	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
 }

 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
 {
 	u8 tmpreg;
 	u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
 	struct rtl_priv *rtlpriv = rtl_priv(hw);

 	tmpreg = rtl_read_byte(rtlpriv, 0xd03);

 	if ((tmpreg & 0x70) != 0)
 		rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
 	else
 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);

 	if ((tmpreg & 0x70) != 0) {
 		rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);

 		if (is2t)
 			rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
 						  MASK12BITS);

 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
 			      (rf_a_mode & 0x8FFFF) | 0x10000);

 		if (is2t)
 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 				      (rf_b_mode & 0x8FFFF) | 0x10000);
 	}
 	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);

 	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);

 	mdelay(100);

 	if ((tmpreg & 0x70) != 0) {
 		rtl_write_byte(rtlpriv, 0xd03, tmpreg);
 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);

 		if (is2t)
 			rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
 				      rf_b_mode);
 	} else {
 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 	}
 }

 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
 {
 	u32 u4b_tmp;
 	u8 delay = 5;
 	struct rtl_priv *rtlpriv = rtl_priv(hw);

 	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
 	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 	u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 	while (u4b_tmp != 0 && delay > 0) {
 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
 		rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
 		u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
 		delay--;
 	}
 	if (delay == 0) {
 		rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 		rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
 		rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
 		RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
 			 "Switch RF timeout !!!\n");
 		return;
 	}
 	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
 	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
 }

 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
 					    enum rf_pwrstate rfpwr_state)
 {
 	struct rtl_priv *rtlpriv = rtl_priv(hw);
 	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 	bool bresult = true;
 	u8 i, queue_id;
 	struct rtl8192_tx_ring *ring = NULL;

 	switch (rfpwr_state) {
 	case ERFON:{
 			if ((ppsc->rfpwr_state == ERFOFF) &&
 			    RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
 				bool rtstatus;
 				u32 InitializeCount = 0;
 				do {
 					InitializeCount++;
 					RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 						 "IPS Set eRf nic enable\n");
 					rtstatus = rtl_ps_enable_nic(hw);
 				} while (!rtstatus && (InitializeCount < 10));
 				RT_CLEAR_PS_LEVEL(ppsc,
 						  RT_RF_OFF_LEVL_HALT_NIC);
 			} else {
 				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 					 "Set ERFON sleeped:%d ms\n",
 					 jiffies_to_msecs(jiffies -
 							  ppsc->
 							  last_sleep_jiffies));
 				ppsc->last_awake_jiffies = jiffies;
 				rtl92ce_phy_set_rf_on(hw);
 			}
 			if (mac->link_state == MAC80211_LINKED) {
 				rtlpriv->cfg->ops->led_control(hw,
 							       LED_CTL_LINK);
 			} else {
 				rtlpriv->cfg->ops->led_control(hw,
 							       LED_CTL_NO_LINK);
 			}
 			break;
 		}
 	case ERFOFF:{
 			if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
 				RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 					 "IPS Set eRf nic disable\n");
 				rtl_ps_disable_nic(hw);
 				RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
 			} else {
 				if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
 					rtlpriv->cfg->ops->led_control(hw,
 							       LED_CTL_NO_LINK);
 				} else {
 					rtlpriv->cfg->ops->led_control(hw,
 							     LED_CTL_POWER_OFF);
 				}
 			}
 			break;
 		}
 	case ERFSLEEP:{
 			if (ppsc->rfpwr_state == ERFOFF)
 				return false;
 			for (queue_id = 0, i = 0;
 			     queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
 				ring = &pcipriv->dev.tx_ring[queue_id];
 				if (skb_queue_len(&ring->queue) == 0) {
 					queue_id++;
 					continue;
 				} else {
 					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 						 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
 						 i + 1, queue_id,
 						 skb_queue_len(&ring->queue));

 					udelay(10);
 					i++;
 				}
 				if (i >= MAX_DOZE_WAITING_TIMES_9x) {
 					RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 						 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
 						 MAX_DOZE_WAITING_TIMES_9x,
 						 queue_id,
 						 skb_queue_len(&ring->queue));
 					break;
 				}
 			}
 			RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
 				 "Set ERFSLEEP awaked:%d ms\n",
 				 jiffies_to_msecs(jiffies -
 						  ppsc->last_awake_jiffies));
 			ppsc->last_sleep_jiffies = jiffies;
 			_rtl92ce_phy_set_rf_sleep(hw);
 			break;
 		}
 	default:
 		RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 			 "switch case not processed\n");
 		bresult = false;
 		break;
 	}
 	if (bresult)
 		ppsc->rfpwr_state = rfpwr_state;
 	return bresult;
 }

 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
 				   enum rf_pwrstate rfpwr_state)
 {
 	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));

 	bool bresult = false;

 	if (rfpwr_state == ppsc->rfpwr_state)
 		return bresult;
 	bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
 	return bresult;
 }
	/******************************************************************************
	*
	* Copyright(c) 2009-2012 Realtek Corporation.
	*
	* This program is free software; you can redistribute it and/or modify it
	* under the terms of version 2 of the GNU General Public License as
	* published by the Free Software Foundation.
	*
	* This program is distributed in the hope that it will be useful, but WITHOUT
	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	* more details.
	*
	* You should have received a copy of the GNU General Public License along with
	* this program; if not, write to the Free Software Foundation, Inc.,
	* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
	*
	* The full GNU General Public License is included in this distribution in the
	* file called LICENSE.
	*
	* Contact Information:
	* wlanfae <wlanfae@realtek.com>
	* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
	* Hsinchu 300, Taiwan.
	*
	* Larry Finger <Larry.Finger@lwfinger.net>
	*
	*****************************************************************************/

	#include "../wifi.h"
	#include "../pci.h"
	#include "../ps.h"
	#include "reg.h"
	#include "def.h"
	#include "hw.h"
	#include "phy.h"
	#include "rf.h"
	#include "dm.h"
	#include "table.h"

	static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);

	u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
	enum radio_path rfpath, u32 regaddr, u32 bitmask)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u32 original_value, readback_value, bitshift;
	struct rtl_phy *rtlphy = &(rtlpriv->phy);

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	"regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
	regaddr, rfpath, bitmask);

	spin_lock(&rtlpriv->locks.rf_lock);

	if (rtlphy->rf_mode != RF_OP_BY_FW) {
	original_value = _rtl92c_phy_rf_serial_read(hw,
	rfpath, regaddr);
	} else {
	original_value = _rtl92c_phy_fw_rf_serial_read(hw,
	rfpath, regaddr);
	}

	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	readback_value = (original_value & bitmask) >> bitshift;

	spin_unlock(&rtlpriv->locks.rf_lock);

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	"regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
	regaddr, rfpath, bitmask, original_value);

	return readback_value;
	}

	bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	bool is92c = IS_92C_SERIAL(rtlhal->version);
	bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);

	if (is92c)
	rtl_write_byte(rtlpriv, 0x14, 0x71);
	return rtstatus;
	}

	bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
	{
	bool rtstatus = true;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u16 regval;
	u32 regvaldw;
	u8 reg_hwparafile = 1;

	_rtl92c_phy_init_bb_rf_register_definition(hw);
	regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
	rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
	regval \| BIT(13) \| BIT(0) \| BIT(1));
	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
	rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
	rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN \| RF_RSTB \| RF_SDMRSTB);
	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
	FEN_PPLL \| FEN_PCIEA \| FEN_DIO_PCIE \|
	FEN_BB_GLB_RSTn \| FEN_BBRSTB);
	rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
	regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
	rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw \| BIT(23));
	if (reg_hwparafile == 1)
	rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
	return rtstatus;
	}

	void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
	enum radio_path rfpath,
	u32 regaddr, u32 bitmask, u32 data)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	u32 original_value, bitshift;

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
	regaddr, bitmask, data, rfpath);

	spin_lock(&rtlpriv->locks.rf_lock);

	if (rtlphy->rf_mode != RF_OP_BY_FW) {
	if (bitmask != RFREG_OFFSET_MASK) {
	original_value = _rtl92c_phy_rf_serial_read(hw,
	rfpath,
	regaddr);
	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	data =
	((original_value & (~bitmask)) \|
	(data << bitshift));
	}

	_rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
	} else {
	if (bitmask != RFREG_OFFSET_MASK) {
	original_value = _rtl92c_phy_fw_rf_serial_read(hw,
	rfpath,
	regaddr);
	bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
	data =
	((original_value & (~bitmask)) \|
	(data << bitshift));
	}
	_rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
	}

	spin_unlock(&rtlpriv->locks.rf_lock);

	RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
	"regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
	regaddr, bitmask, data, rfpath);
	}

	static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	u32 i;
	u32 arraylength;
	u32 *ptrarray;

	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
	arraylength = MAC_2T_ARRAYLENGTH;
	ptrarray = RTL8192CEMAC_2T_ARRAY;
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
	for (i = 0; i < arraylength; i = i + 2)
	rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
	return true;
	}

	bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
	u8 configtype)
	{
	int i;
	u32 *phy_regarray_table;
	u32 *agctab_array_table;
	u16 phy_reg_arraylen, agctab_arraylen;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));

	if (IS_92C_SERIAL(rtlhal->version)) {
	agctab_arraylen = AGCTAB_2TARRAYLENGTH;
	agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
	phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
	phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
	} else {
	agctab_arraylen = AGCTAB_1TARRAYLENGTH;
	agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
	phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
	phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
	}
	if (configtype == BASEBAND_CONFIG_PHY_REG) {
	for (i = 0; i < phy_reg_arraylen; i = i + 2) {
	if (phy_regarray_table[i] == 0xfe)
	mdelay(50);
	else if (phy_regarray_table[i] == 0xfd)
	mdelay(5);
	else if (phy_regarray_table[i] == 0xfc)
	mdelay(1);
	else if (phy_regarray_table[i] == 0xfb)
	udelay(50);
	else if (phy_regarray_table[i] == 0xfa)
	udelay(5);
	else if (phy_regarray_table[i] == 0xf9)
	udelay(1);
	rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
	phy_regarray_table[i + 1]);
	udelay(1);
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
	phy_regarray_table[i],
	phy_regarray_table[i + 1]);
	}
	} else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
	for (i = 0; i < agctab_arraylen; i = i + 2) {
	rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
	agctab_array_table[i + 1]);
	udelay(1);
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
	agctab_array_table[i],
	agctab_array_table[i + 1]);
	}
	}
	return true;
	}

	bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
	u8 configtype)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	int i;
	u32 *phy_regarray_table_pg;
	u16 phy_regarray_pg_len;

	phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
	phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;

	if (configtype == BASEBAND_CONFIG_PHY_REG) {
	for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
	if (phy_regarray_table_pg[i] == 0xfe)
	mdelay(50);
	else if (phy_regarray_table_pg[i] == 0xfd)
	mdelay(5);
	else if (phy_regarray_table_pg[i] == 0xfc)
	mdelay(1);
	else if (phy_regarray_table_pg[i] == 0xfb)
	udelay(50);
	else if (phy_regarray_table_pg[i] == 0xfa)
	udelay(5);
	else if (phy_regarray_table_pg[i] == 0xf9)
	udelay(1);

	_rtl92c_store_pwrIndex_diffrate_offset(hw,
	phy_regarray_table_pg[i],
	phy_regarray_table_pg[i + 1],
	phy_regarray_table_pg[i + 2]);
	}
	} else {

	RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
	"configtype != BaseBand_Config_PHY_REG\n");
	}
	return true;
	}

	bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
	enum radio_path rfpath)
	{

	int i;
	u32 *radioa_array_table;
	u32 *radiob_array_table;
	u16 radioa_arraylen, radiob_arraylen;
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));

	if (IS_92C_SERIAL(rtlhal->version)) {
	radioa_arraylen = RADIOA_2TARRAYLENGTH;
	radioa_array_table = RTL8192CERADIOA_2TARRAY;
	radiob_arraylen = RADIOB_2TARRAYLENGTH;
	radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"Radio_A:RTL8192CERADIOA_2TARRAY\n");
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
	} else {
	radioa_arraylen = RADIOA_1TARRAYLENGTH;
	radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
	radiob_arraylen = RADIOB_1TARRAYLENGTH;
	radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
	"Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
	}
	RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
	switch (rfpath) {
	case RF90_PATH_A:
	for (i = 0; i < radioa_arraylen; i = i + 2) {
	if (radioa_array_table[i] == 0xfe)
	mdelay(50);
	else if (radioa_array_table[i] == 0xfd)
	mdelay(5);
	else if (radioa_array_table[i] == 0xfc)
	mdelay(1);
	else if (radioa_array_table[i] == 0xfb)
	udelay(50);
	else if (radioa_array_table[i] == 0xfa)
	udelay(5);
	else if (radioa_array_table[i] == 0xf9)
	udelay(1);
	else {
	rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
	RFREG_OFFSET_MASK,
	radioa_array_table[i + 1]);
	udelay(1);
	}
	}
	break;
	case RF90_PATH_B:
	for (i = 0; i < radiob_arraylen; i = i + 2) {
	if (radiob_array_table[i] == 0xfe) {
	mdelay(50);
	} else if (radiob_array_table[i] == 0xfd)
	mdelay(5);
	else if (radiob_array_table[i] == 0xfc)
	mdelay(1);
	else if (radiob_array_table[i] == 0xfb)
	udelay(50);
	else if (radiob_array_table[i] == 0xfa)
	udelay(5);
	else if (radiob_array_table[i] == 0xf9)
	udelay(1);
	else {
	rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
	RFREG_OFFSET_MASK,
	radiob_array_table[i + 1]);
	udelay(1);
	}
	}
	break;
	case RF90_PATH_C:
	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	"switch case not processed\n");
	break;
	case RF90_PATH_D:
	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	"switch case not processed\n");
	break;
	}
	return true;
	}

	void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
	struct rtl_phy *rtlphy = &(rtlpriv->phy);
	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	u8 reg_bw_opmode;
	u8 reg_prsr_rsc;

	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
	rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
	"20MHz" : "40MHz");

	if (is_hal_stop(rtlhal)) {
	rtlphy->set_bwmode_inprogress = false;
	return;
	}

	reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
	reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);

	switch (rtlphy->current_chan_bw) {
	case HT_CHANNEL_WIDTH_20:
	reg_bw_opmode \|= BW_OPMODE_20MHZ;
	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
	break;
	case HT_CHANNEL_WIDTH_20_40:
	reg_bw_opmode &= ~BW_OPMODE_20MHZ;
	rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
	reg_prsr_rsc =
	(reg_prsr_rsc & 0x90) \| (mac->cur_40_prime_sc << 5);
	rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
	break;
	default:
	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	"unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
	break;
	}

	switch (rtlphy->current_chan_bw) {
	case HT_CHANNEL_WIDTH_20:
	rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
	rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
	break;
	case HT_CHANNEL_WIDTH_20_40:
	rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
	rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);

	rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
	(mac->cur_40_prime_sc >> 1));
	rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
	rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);

	rtl_set_bbreg(hw, 0x818, (BIT(26) \| BIT(27)),
	(mac->cur_40_prime_sc ==
	HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
	break;
	default:
	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	"unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
	break;
	}
	rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
	rtlphy->set_bwmode_inprogress = false;
	RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
	}

	void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
	{
	u8 tmpreg;
	u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	tmpreg = rtl_read_byte(rtlpriv, 0xd03);

	if ((tmpreg & 0x70) != 0)
	rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
	else
	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);

	if ((tmpreg & 0x70) != 0) {
	rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);

	if (is2t)
	rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
	MASK12BITS);

	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
	(rf_a_mode & 0x8FFFF) \| 0x10000);

	if (is2t)
	rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
	(rf_b_mode & 0x8FFFF) \| 0x10000);
	}
	lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);

	rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal \| 0x08000);

	mdelay(100);

	if ((tmpreg & 0x70) != 0) {
	rtl_write_byte(rtlpriv, 0xd03, tmpreg);
	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);

	if (is2t)
	rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
	rf_b_mode);
	} else {
	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
	}
	}

	static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
	{
	u32 u4b_tmp;
	u8 delay = 5;
	struct rtl_priv *rtlpriv = rtl_priv(hw);

	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
	u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
	while (u4b_tmp != 0 && delay > 0) {
	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
	rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
	u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
	delay--;
	}
	if (delay == 0) {
	rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
	rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
	RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
	"Switch RF timeout !!!\n");
	return;
	}
	rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
	rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
	}

	static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
	enum rf_pwrstate rfpwr_state)
	{
	struct rtl_priv *rtlpriv = rtl_priv(hw);
	struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
	struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
	bool bresult = true;
	u8 i, queue_id;
	struct rtl8192_tx_ring *ring = NULL;

	switch (rfpwr_state) {
	case ERFON:{
	if ((ppsc->rfpwr_state == ERFOFF) &&
	RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
	bool rtstatus;
	u32 InitializeCount = 0;
	do {
	InitializeCount++;
	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
	"IPS Set eRf nic enable\n");
	rtstatus = rtl_ps_enable_nic(hw);
	} while (!rtstatus && (InitializeCount < 10));
	RT_CLEAR_PS_LEVEL(ppsc,
	RT_RF_OFF_LEVL_HALT_NIC);
	} else {
	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
	"Set ERFON sleeped:%d ms\n",
	jiffies_to_msecs(jiffies -
	ppsc->
	last_sleep_jiffies));
	ppsc->last_awake_jiffies = jiffies;
	rtl92ce_phy_set_rf_on(hw);
	}
	if (mac->link_state == MAC80211_LINKED) {
	rtlpriv->cfg->ops->led_control(hw,
	LED_CTL_LINK);
	} else {
	rtlpriv->cfg->ops->led_control(hw,
	LED_CTL_NO_LINK);
	}
	break;
	}
	case ERFOFF:{
	if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
	"IPS Set eRf nic disable\n");
	rtl_ps_disable_nic(hw);
	RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
	} else {
	if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
	rtlpriv->cfg->ops->led_control(hw,
	LED_CTL_NO_LINK);
	} else {
	rtlpriv->cfg->ops->led_control(hw,
	LED_CTL_POWER_OFF);
	}
	}
	break;
	}
	case ERFSLEEP:{
	if (ppsc->rfpwr_state == ERFOFF)
	return false;
	for (queue_id = 0, i = 0;
	queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
	ring = &pcipriv->dev.tx_ring[queue_id];
	if (skb_queue_len(&ring->queue) == 0) {
	queue_id++;
	continue;
	} else {
	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
	"eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
	i + 1, queue_id,
	skb_queue_len(&ring->queue));

	udelay(10);
	i++;
	}
	if (i >= MAX_DOZE_WAITING_TIMES_9x) {
	RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
	"ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
	MAX_DOZE_WAITING_TIMES_9x,
	queue_id,
	skb_queue_len(&ring->queue));
	break;
	}
	}
	RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
	"Set ERFSLEEP awaked:%d ms\n",
	jiffies_to_msecs(jiffies -
	ppsc->last_awake_jiffies));
	ppsc->last_sleep_jiffies = jiffies;
	_rtl92ce_phy_set_rf_sleep(hw);
	break;
	}
	default:
	RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
	"switch case not processed\n");
	bresult = false;
	break;
	}
	if (bresult)
	ppsc->rfpwr_state = rfpwr_state;
	return bresult;
	}

	bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
	enum rf_pwrstate rfpwr_state)
	{
	struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));

	bool bresult = false;

	if (rfpwr_state == ppsc->rfpwr_state)
	return bresult;
	bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);
	return bresult;
	}