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Rajendra Nayak97f67892011-02-25 15:49:01 -07001/*
2 * OMAP4-specific DPLL control functions
3 *
4 * Copyright (C) 2011 Texas Instruments, Inc.
5 * Rajendra Nayak
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/bitops.h>
17
Rajendra Nayak97f67892011-02-25 15:49:01 -070018#include "clock.h"
Rajendra Nayak97f67892011-02-25 15:49:01 -070019
Jon Hunter3ff51ed2012-12-15 01:35:46 -070020/*
21 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
22 * can supported when using the DPLL low-power mode. Frequencies are
23 * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
24 * Status, and Low-Power Operation Mode".
25 */
26#define OMAP4_DPLL_LP_FINT_MAX 1000000
27#define OMAP4_DPLL_LP_FOUT_MAX 100000000
28
Tero Kristo44b65e72014-07-02 11:47:38 +030029/*
30 * Bitfield declarations
31 */
32#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
33#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
34#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
35
36/* Static rate multiplier for OMAP4 REGM4XEN clocks */
37#define OMAP4430_REGM4XEN_MULT 4
38
Rajendra Nayak97f67892011-02-25 15:49:01 -070039/* Supported only on OMAP4 */
Mike Turquette32cc0022012-11-10 16:58:41 -070040int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
Rajendra Nayak97f67892011-02-25 15:49:01 -070041{
42 u32 v;
43 u32 mask;
44
Tero Kristo74b9b622014-07-02 11:47:37 +030045 if (!clk || !clk->clksel_reg)
Rajendra Nayak97f67892011-02-25 15:49:01 -070046 return -EINVAL;
47
48 mask = clk->flags & CLOCK_CLKOUTX2 ?
49 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
50 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
51
Tero Kristo519ab8b2013-10-22 11:49:58 +030052 v = omap2_clk_readl(clk, clk->clksel_reg);
Rajendra Nayak97f67892011-02-25 15:49:01 -070053 v &= mask;
54 v >>= __ffs(mask);
55
56 return v;
57}
58
Mike Turquette32cc0022012-11-10 16:58:41 -070059void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
Rajendra Nayak97f67892011-02-25 15:49:01 -070060{
61 u32 v;
62 u32 mask;
63
Tero Kristo74b9b622014-07-02 11:47:37 +030064 if (!clk || !clk->clksel_reg)
Rajendra Nayak97f67892011-02-25 15:49:01 -070065 return;
66
67 mask = clk->flags & CLOCK_CLKOUTX2 ?
68 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
69 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
70
Tero Kristo519ab8b2013-10-22 11:49:58 +030071 v = omap2_clk_readl(clk, clk->clksel_reg);
Rajendra Nayak97f67892011-02-25 15:49:01 -070072 /* Clear the bit to allow gatectrl */
73 v &= ~mask;
Tero Kristo519ab8b2013-10-22 11:49:58 +030074 omap2_clk_writel(v, clk, clk->clksel_reg);
Rajendra Nayak97f67892011-02-25 15:49:01 -070075}
76
Mike Turquette32cc0022012-11-10 16:58:41 -070077void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
Rajendra Nayak97f67892011-02-25 15:49:01 -070078{
79 u32 v;
80 u32 mask;
81
Tero Kristo74b9b622014-07-02 11:47:37 +030082 if (!clk || !clk->clksel_reg)
Rajendra Nayak97f67892011-02-25 15:49:01 -070083 return;
84
85 mask = clk->flags & CLOCK_CLKOUTX2 ?
86 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
87 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
88
Tero Kristo519ab8b2013-10-22 11:49:58 +030089 v = omap2_clk_readl(clk, clk->clksel_reg);
Rajendra Nayak97f67892011-02-25 15:49:01 -070090 /* Set the bit to deny gatectrl */
91 v |= mask;
Tero Kristo519ab8b2013-10-22 11:49:58 +030092 omap2_clk_writel(v, clk, clk->clksel_reg);
Rajendra Nayak97f67892011-02-25 15:49:01 -070093}
Rajendra Nayak70db8a62011-02-25 15:49:02 -070094
Mike Turquette32cc0022012-11-10 16:58:41 -070095const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
96 .allow_idle = omap4_dpllmx_allow_gatectrl,
97 .deny_idle = omap4_dpllmx_deny_gatectrl,
98};
Rajendra Nayak70db8a62011-02-25 15:49:02 -070099
Mike Turquettea1900f22011-10-07 00:52:58 -0600100/**
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700101 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
102 * @dd: pointer to the dpll data structure
103 *
104 * Calculates if low-power mode can be enabled based upon the last
105 * multiplier and divider values calculated. If low-power mode can be
106 * enabled, then the bit to enable low-power mode is stored in the
107 * last_rounded_lpmode variable. This implementation is based upon the
108 * criteria for enabling low-power mode as described in the OMAP4430/60
109 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
110 * Operation Mode".
111 */
112static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
113{
114 long fint, fout;
115
116 fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
117 fout = fint * dd->last_rounded_m;
118
119 if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
120 dd->last_rounded_lpmode = 1;
121 else
122 dd->last_rounded_lpmode = 0;
123}
124
125/**
Mike Turquettea1900f22011-10-07 00:52:58 -0600126 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
127 * @clk: struct clk * of the DPLL to compute the rate for
128 *
129 * Compute the output rate for the OMAP4 DPLL represented by @clk.
130 * Takes the REGM4XEN bit into consideration, which is needed for the
131 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
132 * upon success, or 0 upon error.
133 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700134unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
135 unsigned long parent_rate)
136{
137 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
Mike Turquettea1900f22011-10-07 00:52:58 -0600138 u32 v;
139 unsigned long rate;
140 struct dpll_data *dd;
141
142 if (!clk || !clk->dpll_data)
143 return 0;
144
145 dd = clk->dpll_data;
146
147 rate = omap2_get_dpll_rate(clk);
148
149 /* regm4xen adds a multiplier of 4 to DPLL calculations */
Tero Kristo519ab8b2013-10-22 11:49:58 +0300150 v = omap2_clk_readl(clk, dd->control_reg);
Mike Turquettea1900f22011-10-07 00:52:58 -0600151 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
152 rate *= OMAP4430_REGM4XEN_MULT;
153
154 return rate;
155}
156
157/**
158 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
159 * @clk: struct clk * of the DPLL to round a rate for
160 * @target_rate: the desired rate of the DPLL
161 *
162 * Compute the rate that would be programmed into the DPLL hardware
163 * for @clk if set_rate() were to be provided with the rate
164 * @target_rate. Takes the REGM4XEN bit into consideration, which is
165 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
166 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
167 * ~0 if an error occurred in omap2_dpll_round_rate().
168 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700169long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
170 unsigned long target_rate,
171 unsigned long *parent_rate)
172{
173 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
Mike Turquettea1900f22011-10-07 00:52:58 -0600174 struct dpll_data *dd;
175 long r;
176
177 if (!clk || !clk->dpll_data)
178 return -EINVAL;
179
180 dd = clk->dpll_data;
181
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700182 dd->last_rounded_m4xen = 0;
Mike Turquettea1900f22011-10-07 00:52:58 -0600183
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700184 /*
185 * First try to compute the DPLL configuration for
186 * target rate without using the 4X multiplier.
187 */
Mike Turquette32cc0022012-11-10 16:58:41 -0700188 r = omap2_dpll_round_rate(hw, target_rate, NULL);
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700189 if (r != ~0)
190 goto out;
191
192 /*
193 * If we did not find a valid DPLL configuration, try again, but
194 * this time see if using the 4X multiplier can help. Enabling the
195 * 4X multiplier is equivalent to dividing the target rate by 4.
196 */
197 r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
198 NULL);
Mike Turquettea1900f22011-10-07 00:52:58 -0600199 if (r == ~0)
200 return r;
201
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700202 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
203 dd->last_rounded_m4xen = 1;
Mike Turquettea1900f22011-10-07 00:52:58 -0600204
Jon Hunter3ff51ed2012-12-15 01:35:46 -0700205out:
206 omap4_dpll_lpmode_recalc(dd);
207
208 return dd->last_rounded_rate;
Mike Turquettea1900f22011-10-07 00:52:58 -0600209}
Tero Kristo83501ff2014-10-03 16:57:12 +0300210
211/**
212 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
213 * @hw: pointer to the clock to determine rate for
214 * @rate: target rate for the DPLL
215 * @best_parent_rate: pointer for returning best parent rate
216 * @best_parent_clk: pointer for returning best parent clock
217 *
218 * Determines which DPLL mode to use for reaching a desired rate.
219 * Checks whether the DPLL shall be in bypass or locked mode, and if
220 * locked, calculates the M,N values for the DPLL via round-rate.
221 * Returns a positive clock rate with success, negative error value
222 * in failure.
223 */
224long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long *best_parent_rate,
Tero Kristo6f8e8532014-12-12 15:22:00 +0200226 struct clk_hw **best_parent_clk)
Tero Kristo83501ff2014-10-03 16:57:12 +0300227{
228 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
229 struct dpll_data *dd;
230
231 if (!hw || !rate)
232 return -EINVAL;
233
234 dd = clk->dpll_data;
235 if (!dd)
236 return -EINVAL;
237
238 if (__clk_get_rate(dd->clk_bypass) == rate &&
239 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
Tero Kristo6f8e8532014-12-12 15:22:00 +0200240 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
Tero Kristo83501ff2014-10-03 16:57:12 +0300241 } else {
242 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
243 best_parent_rate);
Tero Kristo6f8e8532014-12-12 15:22:00 +0200244 *best_parent_clk = __clk_get_hw(dd->clk_ref);
Tero Kristo83501ff2014-10-03 16:57:12 +0300245 }
246
247 *best_parent_rate = rate;
248
249 return rate;
250}