Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2010 Broadcom Corporation |
| 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY |
| 11 | * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION |
| 13 | * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN |
| 14 | * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | * |
| 16 | * File contents: support functions for PCI/PCIe |
| 17 | */ |
| 18 | |
Joe Perches | 8505a7e | 2011-11-13 11:41:04 -0800 | [diff] [blame] | 19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 20 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 21 | #include <linux/delay.h> |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 22 | |
| 23 | #include <defs.h> |
| 24 | #include <chipcommon.h> |
| 25 | #include <brcmu_utils.h> |
| 26 | #include <brcm_hw_ids.h> |
| 27 | #include <soc.h> |
| 28 | #include "types.h" |
| 29 | #include "pub.h" |
| 30 | #include "pmu.h" |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 31 | #include "aiutils.h" |
| 32 | |
| 33 | /* slow_clk_ctl */ |
| 34 | /* slow clock source mask */ |
| 35 | #define SCC_SS_MASK 0x00000007 |
| 36 | /* source of slow clock is LPO */ |
| 37 | #define SCC_SS_LPO 0x00000000 |
| 38 | /* source of slow clock is crystal */ |
| 39 | #define SCC_SS_XTAL 0x00000001 |
| 40 | /* source of slow clock is PCI */ |
| 41 | #define SCC_SS_PCI 0x00000002 |
| 42 | /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ |
| 43 | #define SCC_LF 0x00000200 |
| 44 | /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ |
| 45 | #define SCC_LP 0x00000400 |
| 46 | /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ |
| 47 | #define SCC_FS 0x00000800 |
| 48 | /* IgnorePllOffReq, 1/0: |
| 49 | * power logic ignores/honors PLL clock disable requests from core |
| 50 | */ |
| 51 | #define SCC_IP 0x00001000 |
| 52 | /* XtalControlEn, 1/0: |
| 53 | * power logic does/doesn't disable crystal when appropriate |
| 54 | */ |
| 55 | #define SCC_XC 0x00002000 |
| 56 | /* XtalPU (RO), 1/0: crystal running/disabled */ |
| 57 | #define SCC_XP 0x00004000 |
| 58 | /* ClockDivider (SlowClk = 1/(4+divisor)) */ |
| 59 | #define SCC_CD_MASK 0xffff0000 |
| 60 | #define SCC_CD_SHIFT 16 |
| 61 | |
| 62 | /* system_clk_ctl */ |
| 63 | /* ILPen: Enable Idle Low Power */ |
| 64 | #define SYCC_IE 0x00000001 |
| 65 | /* ALPen: Enable Active Low Power */ |
| 66 | #define SYCC_AE 0x00000002 |
| 67 | /* ForcePLLOn */ |
| 68 | #define SYCC_FP 0x00000004 |
| 69 | /* Force ALP (or HT if ALPen is not set */ |
| 70 | #define SYCC_AR 0x00000008 |
| 71 | /* Force HT */ |
| 72 | #define SYCC_HR 0x00000010 |
| 73 | /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ |
| 74 | #define SYCC_CD_MASK 0xffff0000 |
| 75 | #define SYCC_CD_SHIFT 16 |
| 76 | |
| 77 | #define CST4329_SPROM_OTP_SEL_MASK 0x00000003 |
| 78 | /* OTP is powered up, use def. CIS, no SPROM */ |
| 79 | #define CST4329_DEFCIS_SEL 0 |
| 80 | /* OTP is powered up, SPROM is present */ |
| 81 | #define CST4329_SPROM_SEL 1 |
| 82 | /* OTP is powered up, no SPROM */ |
| 83 | #define CST4329_OTP_SEL 2 |
| 84 | /* OTP is powered down, SPROM is present */ |
| 85 | #define CST4329_OTP_PWRDN 3 |
| 86 | |
| 87 | #define CST4329_SPI_SDIO_MODE_MASK 0x00000004 |
| 88 | #define CST4329_SPI_SDIO_MODE_SHIFT 2 |
| 89 | |
| 90 | /* 43224 chip-specific ChipControl register bits */ |
| 91 | #define CCTRL43224_GPIO_TOGGLE 0x8000 |
| 92 | /* 12 mA drive strength */ |
| 93 | #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 |
| 94 | /* 12 mA drive strength for later 43224s */ |
| 95 | #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0 |
| 96 | |
| 97 | /* 43236 Chip specific ChipStatus register bits */ |
| 98 | #define CST43236_SFLASH_MASK 0x00000040 |
| 99 | #define CST43236_OTP_MASK 0x00000080 |
| 100 | #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ |
| 101 | #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ |
| 102 | #define CST43236_BOOT_MASK 0x00001800 |
| 103 | #define CST43236_BOOT_SHIFT 11 |
| 104 | #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ |
| 105 | #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ |
| 106 | #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ |
| 107 | #define CST43236_BOOT_FROM_INVALID 3 |
| 108 | |
| 109 | /* 4331 chip-specific ChipControl register bits */ |
| 110 | /* 0 disable */ |
| 111 | #define CCTRL4331_BT_COEXIST (1<<0) |
| 112 | /* 0 SECI is disabled (JTAG functional) */ |
| 113 | #define CCTRL4331_SECI (1<<1) |
| 114 | /* 0 disable */ |
| 115 | #define CCTRL4331_EXT_LNA (1<<2) |
| 116 | /* sprom/gpio13-15 mux */ |
| 117 | #define CCTRL4331_SPROM_GPIO13_15 (1<<3) |
| 118 | /* 0 ext pa disable, 1 ext pa enabled */ |
| 119 | #define CCTRL4331_EXTPA_EN (1<<4) |
| 120 | /* set drive out GPIO_CLK on sprom_cs pin */ |
| 121 | #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) |
| 122 | /* use sprom_cs pin as PCIE mdio interface */ |
| 123 | #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) |
| 124 | /* aband extpa will be at gpio2/5 and sprom_dout */ |
| 125 | #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) |
| 126 | /* override core control on pipe_AuxClkEnable */ |
| 127 | #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) |
| 128 | /* override core control on pipe_AuxPowerDown */ |
| 129 | #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) |
| 130 | /* pcie_auxclkenable */ |
| 131 | #define CCTRL4331_PCIE_AUXCLKEN (1<<10) |
| 132 | /* pcie_pipe_pllpowerdown */ |
| 133 | #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) |
| 134 | /* enable bt_shd0 at gpio4 */ |
| 135 | #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) |
| 136 | /* enable bt_shd1 at gpio5 */ |
| 137 | #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) |
| 138 | |
| 139 | /* 4331 Chip specific ChipStatus register bits */ |
| 140 | /* crystal frequency 20/40Mhz */ |
| 141 | #define CST4331_XTAL_FREQ 0x00000001 |
| 142 | #define CST4331_SPROM_PRESENT 0x00000002 |
| 143 | #define CST4331_OTP_PRESENT 0x00000004 |
| 144 | #define CST4331_LDO_RF 0x00000008 |
| 145 | #define CST4331_LDO_PAR 0x00000010 |
| 146 | |
| 147 | /* 4319 chip-specific ChipStatus register bits */ |
| 148 | #define CST4319_SPI_CPULESSUSB 0x00000001 |
| 149 | #define CST4319_SPI_CLK_POL 0x00000002 |
| 150 | #define CST4319_SPI_CLK_PH 0x00000008 |
| 151 | /* gpio [7:6], SDIO CIS selection */ |
| 152 | #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0 |
| 153 | #define CST4319_SPROM_OTP_SEL_SHIFT 6 |
| 154 | /* use default CIS, OTP is powered up */ |
| 155 | #define CST4319_DEFCIS_SEL 0x00000000 |
| 156 | /* use SPROM, OTP is powered up */ |
| 157 | #define CST4319_SPROM_SEL 0x00000040 |
| 158 | /* use OTP, OTP is powered up */ |
| 159 | #define CST4319_OTP_SEL 0x00000080 |
| 160 | /* use SPROM, OTP is powered down */ |
| 161 | #define CST4319_OTP_PWRDN 0x000000c0 |
| 162 | /* gpio [8], sdio/usb mode */ |
| 163 | #define CST4319_SDIO_USB_MODE 0x00000100 |
| 164 | #define CST4319_REMAP_SEL_MASK 0x00000600 |
| 165 | #define CST4319_ILPDIV_EN 0x00000800 |
| 166 | #define CST4319_XTAL_PD_POL 0x00001000 |
| 167 | #define CST4319_LPO_SEL 0x00002000 |
| 168 | #define CST4319_RES_INIT_MODE 0x0000c000 |
| 169 | /* PALDO is configured with external PNP */ |
| 170 | #define CST4319_PALDO_EXTPNP 0x00010000 |
| 171 | #define CST4319_CBUCK_MODE_MASK 0x00060000 |
| 172 | #define CST4319_CBUCK_MODE_BURST 0x00020000 |
| 173 | #define CST4319_CBUCK_MODE_LPBURST 0x00060000 |
| 174 | #define CST4319_RCAL_VALID 0x01000000 |
| 175 | #define CST4319_RCAL_VALUE_MASK 0x3e000000 |
| 176 | #define CST4319_RCAL_VALUE_SHIFT 25 |
| 177 | |
| 178 | /* 4336 chip-specific ChipStatus register bits */ |
| 179 | #define CST4336_SPI_MODE_MASK 0x00000001 |
| 180 | #define CST4336_SPROM_PRESENT 0x00000002 |
| 181 | #define CST4336_OTP_PRESENT 0x00000004 |
| 182 | #define CST4336_ARMREMAP_0 0x00000008 |
| 183 | #define CST4336_ILPDIV_EN_MASK 0x00000010 |
| 184 | #define CST4336_ILPDIV_EN_SHIFT 4 |
| 185 | #define CST4336_XTAL_PD_POL_MASK 0x00000020 |
| 186 | #define CST4336_XTAL_PD_POL_SHIFT 5 |
| 187 | #define CST4336_LPO_SEL_MASK 0x00000040 |
| 188 | #define CST4336_LPO_SEL_SHIFT 6 |
| 189 | #define CST4336_RES_INIT_MODE_MASK 0x00000180 |
| 190 | #define CST4336_RES_INIT_MODE_SHIFT 7 |
| 191 | #define CST4336_CBUCK_MODE_MASK 0x00000600 |
| 192 | #define CST4336_CBUCK_MODE_SHIFT 9 |
| 193 | |
| 194 | /* 4313 chip-specific ChipStatus register bits */ |
| 195 | #define CST4313_SPROM_PRESENT 1 |
| 196 | #define CST4313_OTP_PRESENT 2 |
| 197 | #define CST4313_SPROM_OTP_SEL_MASK 0x00000002 |
| 198 | #define CST4313_SPROM_OTP_SEL_SHIFT 0 |
| 199 | |
| 200 | /* 4313 Chip specific ChipControl register bits */ |
| 201 | /* 12 mA drive strengh for later 4313 */ |
| 202 | #define CCTRL_4313_12MA_LED_DRIVE 0x00000007 |
| 203 | |
| 204 | /* Manufacturer Ids */ |
| 205 | #define MFGID_ARM 0x43b |
| 206 | #define MFGID_BRCM 0x4bf |
| 207 | #define MFGID_MIPS 0x4a7 |
| 208 | |
| 209 | /* Enumeration ROM registers */ |
| 210 | #define ER_EROMENTRY 0x000 |
| 211 | #define ER_REMAPCONTROL 0xe00 |
| 212 | #define ER_REMAPSELECT 0xe04 |
| 213 | #define ER_MASTERSELECT 0xe10 |
| 214 | #define ER_ITCR 0xf00 |
| 215 | #define ER_ITIP 0xf04 |
| 216 | |
| 217 | /* Erom entries */ |
| 218 | #define ER_TAG 0xe |
| 219 | #define ER_TAG1 0x6 |
| 220 | #define ER_VALID 1 |
| 221 | #define ER_CI 0 |
| 222 | #define ER_MP 2 |
| 223 | #define ER_ADD 4 |
| 224 | #define ER_END 0xe |
| 225 | #define ER_BAD 0xffffffff |
| 226 | |
| 227 | /* EROM CompIdentA */ |
| 228 | #define CIA_MFG_MASK 0xfff00000 |
| 229 | #define CIA_MFG_SHIFT 20 |
| 230 | #define CIA_CID_MASK 0x000fff00 |
| 231 | #define CIA_CID_SHIFT 8 |
| 232 | #define CIA_CCL_MASK 0x000000f0 |
| 233 | #define CIA_CCL_SHIFT 4 |
| 234 | |
| 235 | /* EROM CompIdentB */ |
| 236 | #define CIB_REV_MASK 0xff000000 |
| 237 | #define CIB_REV_SHIFT 24 |
| 238 | #define CIB_NSW_MASK 0x00f80000 |
| 239 | #define CIB_NSW_SHIFT 19 |
| 240 | #define CIB_NMW_MASK 0x0007c000 |
| 241 | #define CIB_NMW_SHIFT 14 |
| 242 | #define CIB_NSP_MASK 0x00003e00 |
| 243 | #define CIB_NSP_SHIFT 9 |
| 244 | #define CIB_NMP_MASK 0x000001f0 |
| 245 | #define CIB_NMP_SHIFT 4 |
| 246 | |
| 247 | /* EROM AddrDesc */ |
| 248 | #define AD_ADDR_MASK 0xfffff000 |
| 249 | #define AD_SP_MASK 0x00000f00 |
| 250 | #define AD_SP_SHIFT 8 |
| 251 | #define AD_ST_MASK 0x000000c0 |
| 252 | #define AD_ST_SHIFT 6 |
| 253 | #define AD_ST_SLAVE 0x00000000 |
| 254 | #define AD_ST_BRIDGE 0x00000040 |
| 255 | #define AD_ST_SWRAP 0x00000080 |
| 256 | #define AD_ST_MWRAP 0x000000c0 |
| 257 | #define AD_SZ_MASK 0x00000030 |
| 258 | #define AD_SZ_SHIFT 4 |
| 259 | #define AD_SZ_4K 0x00000000 |
| 260 | #define AD_SZ_8K 0x00000010 |
| 261 | #define AD_SZ_16K 0x00000020 |
| 262 | #define AD_SZ_SZD 0x00000030 |
| 263 | #define AD_AG32 0x00000008 |
| 264 | #define AD_ADDR_ALIGN 0x00000fff |
| 265 | #define AD_SZ_BASE 0x00001000 /* 4KB */ |
| 266 | |
| 267 | /* EROM SizeDesc */ |
| 268 | #define SD_SZ_MASK 0xfffff000 |
| 269 | #define SD_SG32 0x00000008 |
| 270 | #define SD_SZ_ALIGN 0x00000fff |
| 271 | |
| 272 | /* PCI config space bit 4 for 4306c0 slow clock source */ |
| 273 | #define PCI_CFG_GPIO_SCS 0x10 |
| 274 | /* PCI config space GPIO 14 for Xtal power-up */ |
| 275 | #define PCI_CFG_GPIO_XTAL 0x40 |
| 276 | /* PCI config space GPIO 15 for PLL power-down */ |
| 277 | #define PCI_CFG_GPIO_PLL 0x80 |
| 278 | |
| 279 | /* power control defines */ |
| 280 | #define PLL_DELAY 150 /* us pll on delay */ |
| 281 | #define FREF_DELAY 200 /* us fref change delay */ |
| 282 | #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */ |
| 283 | |
| 284 | /* resetctrl */ |
| 285 | #define AIRC_RESET 1 |
| 286 | |
| 287 | #define NOREV -1 /* Invalid rev */ |
| 288 | |
| 289 | /* GPIO Based LED powersave defines */ |
| 290 | #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ |
| 291 | #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ |
| 292 | |
| 293 | /* When Srom support present, fields in sromcontrol */ |
| 294 | #define SRC_START 0x80000000 |
| 295 | #define SRC_BUSY 0x80000000 |
| 296 | #define SRC_OPCODE 0x60000000 |
| 297 | #define SRC_OP_READ 0x00000000 |
| 298 | #define SRC_OP_WRITE 0x20000000 |
| 299 | #define SRC_OP_WRDIS 0x40000000 |
| 300 | #define SRC_OP_WREN 0x60000000 |
| 301 | #define SRC_OTPSEL 0x00000010 |
| 302 | #define SRC_LOCK 0x00000008 |
| 303 | #define SRC_SIZE_MASK 0x00000006 |
| 304 | #define SRC_SIZE_1K 0x00000000 |
| 305 | #define SRC_SIZE_4K 0x00000002 |
| 306 | #define SRC_SIZE_16K 0x00000004 |
| 307 | #define SRC_SIZE_SHIFT 1 |
| 308 | #define SRC_PRESENT 0x00000001 |
| 309 | |
| 310 | /* External PA enable mask */ |
| 311 | #define GPIO_CTRL_EPA_EN_MASK 0x40 |
| 312 | |
| 313 | #define DEFAULT_GPIOTIMERVAL \ |
| 314 | ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) |
| 315 | |
| 316 | #define BADIDX (SI_MAXCORES + 1) |
| 317 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 318 | #define IS_SIM(chippkg) \ |
| 319 | ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) |
| 320 | |
Joe Perches | 8ae7465 | 2012-01-15 00:38:38 -0800 | [diff] [blame] | 321 | #ifdef DEBUG |
Joe Perches | 8505a7e | 2011-11-13 11:41:04 -0800 | [diff] [blame] | 322 | #define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 323 | #else |
Joe Perches | 8505a7e | 2011-11-13 11:41:04 -0800 | [diff] [blame] | 324 | #define SI_MSG(fmt, ...) no_printk(fmt, ##__VA_ARGS__) |
Joe Perches | 8ae7465 | 2012-01-15 00:38:38 -0800 | [diff] [blame] | 325 | #endif /* DEBUG */ |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 326 | |
| 327 | #define GOODCOREADDR(x, b) \ |
| 328 | (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ |
| 329 | IS_ALIGNED((x), SI_CORE_SIZE)) |
| 330 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 331 | struct aidmp { |
| 332 | u32 oobselina30; /* 0x000 */ |
| 333 | u32 oobselina74; /* 0x004 */ |
| 334 | u32 PAD[6]; |
| 335 | u32 oobselinb30; /* 0x020 */ |
| 336 | u32 oobselinb74; /* 0x024 */ |
| 337 | u32 PAD[6]; |
| 338 | u32 oobselinc30; /* 0x040 */ |
| 339 | u32 oobselinc74; /* 0x044 */ |
| 340 | u32 PAD[6]; |
| 341 | u32 oobselind30; /* 0x060 */ |
| 342 | u32 oobselind74; /* 0x064 */ |
| 343 | u32 PAD[38]; |
| 344 | u32 oobselouta30; /* 0x100 */ |
| 345 | u32 oobselouta74; /* 0x104 */ |
| 346 | u32 PAD[6]; |
| 347 | u32 oobseloutb30; /* 0x120 */ |
| 348 | u32 oobseloutb74; /* 0x124 */ |
| 349 | u32 PAD[6]; |
| 350 | u32 oobseloutc30; /* 0x140 */ |
| 351 | u32 oobseloutc74; /* 0x144 */ |
| 352 | u32 PAD[6]; |
| 353 | u32 oobseloutd30; /* 0x160 */ |
| 354 | u32 oobseloutd74; /* 0x164 */ |
| 355 | u32 PAD[38]; |
| 356 | u32 oobsynca; /* 0x200 */ |
| 357 | u32 oobseloutaen; /* 0x204 */ |
| 358 | u32 PAD[6]; |
| 359 | u32 oobsyncb; /* 0x220 */ |
| 360 | u32 oobseloutben; /* 0x224 */ |
| 361 | u32 PAD[6]; |
| 362 | u32 oobsyncc; /* 0x240 */ |
| 363 | u32 oobseloutcen; /* 0x244 */ |
| 364 | u32 PAD[6]; |
| 365 | u32 oobsyncd; /* 0x260 */ |
| 366 | u32 oobseloutden; /* 0x264 */ |
| 367 | u32 PAD[38]; |
| 368 | u32 oobaextwidth; /* 0x300 */ |
| 369 | u32 oobainwidth; /* 0x304 */ |
| 370 | u32 oobaoutwidth; /* 0x308 */ |
| 371 | u32 PAD[5]; |
| 372 | u32 oobbextwidth; /* 0x320 */ |
| 373 | u32 oobbinwidth; /* 0x324 */ |
| 374 | u32 oobboutwidth; /* 0x328 */ |
| 375 | u32 PAD[5]; |
| 376 | u32 oobcextwidth; /* 0x340 */ |
| 377 | u32 oobcinwidth; /* 0x344 */ |
| 378 | u32 oobcoutwidth; /* 0x348 */ |
| 379 | u32 PAD[5]; |
| 380 | u32 oobdextwidth; /* 0x360 */ |
| 381 | u32 oobdinwidth; /* 0x364 */ |
| 382 | u32 oobdoutwidth; /* 0x368 */ |
| 383 | u32 PAD[37]; |
| 384 | u32 ioctrlset; /* 0x400 */ |
| 385 | u32 ioctrlclear; /* 0x404 */ |
| 386 | u32 ioctrl; /* 0x408 */ |
| 387 | u32 PAD[61]; |
| 388 | u32 iostatus; /* 0x500 */ |
| 389 | u32 PAD[127]; |
| 390 | u32 ioctrlwidth; /* 0x700 */ |
| 391 | u32 iostatuswidth; /* 0x704 */ |
| 392 | u32 PAD[62]; |
| 393 | u32 resetctrl; /* 0x800 */ |
| 394 | u32 resetstatus; /* 0x804 */ |
| 395 | u32 resetreadid; /* 0x808 */ |
| 396 | u32 resetwriteid; /* 0x80c */ |
| 397 | u32 PAD[60]; |
| 398 | u32 errlogctrl; /* 0x900 */ |
| 399 | u32 errlogdone; /* 0x904 */ |
| 400 | u32 errlogstatus; /* 0x908 */ |
| 401 | u32 errlogaddrlo; /* 0x90c */ |
| 402 | u32 errlogaddrhi; /* 0x910 */ |
| 403 | u32 errlogid; /* 0x914 */ |
| 404 | u32 errloguser; /* 0x918 */ |
| 405 | u32 errlogflags; /* 0x91c */ |
| 406 | u32 PAD[56]; |
| 407 | u32 intstatus; /* 0xa00 */ |
| 408 | u32 PAD[127]; |
| 409 | u32 config; /* 0xe00 */ |
| 410 | u32 PAD[63]; |
| 411 | u32 itcr; /* 0xf00 */ |
| 412 | u32 PAD[3]; |
| 413 | u32 itipooba; /* 0xf10 */ |
| 414 | u32 itipoobb; /* 0xf14 */ |
| 415 | u32 itipoobc; /* 0xf18 */ |
| 416 | u32 itipoobd; /* 0xf1c */ |
| 417 | u32 PAD[4]; |
| 418 | u32 itipoobaout; /* 0xf30 */ |
| 419 | u32 itipoobbout; /* 0xf34 */ |
| 420 | u32 itipoobcout; /* 0xf38 */ |
| 421 | u32 itipoobdout; /* 0xf3c */ |
| 422 | u32 PAD[4]; |
| 423 | u32 itopooba; /* 0xf50 */ |
| 424 | u32 itopoobb; /* 0xf54 */ |
| 425 | u32 itopoobc; /* 0xf58 */ |
| 426 | u32 itopoobd; /* 0xf5c */ |
| 427 | u32 PAD[4]; |
| 428 | u32 itopoobain; /* 0xf70 */ |
| 429 | u32 itopoobbin; /* 0xf74 */ |
| 430 | u32 itopoobcin; /* 0xf78 */ |
| 431 | u32 itopoobdin; /* 0xf7c */ |
| 432 | u32 PAD[4]; |
| 433 | u32 itopreset; /* 0xf90 */ |
| 434 | u32 PAD[15]; |
| 435 | u32 peripherialid4; /* 0xfd0 */ |
| 436 | u32 peripherialid5; /* 0xfd4 */ |
| 437 | u32 peripherialid6; /* 0xfd8 */ |
| 438 | u32 peripherialid7; /* 0xfdc */ |
| 439 | u32 peripherialid0; /* 0xfe0 */ |
| 440 | u32 peripherialid1; /* 0xfe4 */ |
| 441 | u32 peripherialid2; /* 0xfe8 */ |
| 442 | u32 peripherialid3; /* 0xfec */ |
| 443 | u32 componentid0; /* 0xff0 */ |
| 444 | u32 componentid1; /* 0xff4 */ |
| 445 | u32 componentid2; /* 0xff8 */ |
| 446 | u32 componentid3; /* 0xffc */ |
| 447 | }; |
| 448 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 449 | static bool |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 450 | ai_buscore_setup(struct si_info *sii, struct bcma_device *cc) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 451 | { |
Arend van Spriel | 99559f1 | 2011-12-12 15:15:10 -0800 | [diff] [blame] | 452 | /* no cores found, bail out */ |
| 453 | if (cc->bus->nr_cores == 0) |
| 454 | return false; |
| 455 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 456 | /* get chipcommon rev */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 457 | sii->pub.ccrev = cc->id.rev; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 458 | |
| 459 | /* get chipcommon chipstatus */ |
Hauke Mehrtens | d43c1c5 | 2012-04-29 02:50:28 +0200 | [diff] [blame] | 460 | sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus)); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 461 | |
| 462 | /* get chipcommon capabilites */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 463 | sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities)); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 464 | |
| 465 | /* get pmu rev and caps */ |
Arend van Spriel | b2ffec4 | 2011-12-08 15:06:45 -0800 | [diff] [blame] | 466 | if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) { |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 467 | sii->pub.pmucaps = bcma_read32(cc, |
| 468 | CHIPCREGOFFS(pmucapabilities)); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 469 | sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK; |
| 470 | } |
| 471 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 472 | return true; |
| 473 | } |
| 474 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 475 | static struct si_info *ai_doattach(struct si_info *sii, |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 476 | struct bcma_bus *pbus) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 477 | { |
| 478 | struct si_pub *sih = &sii->pub; |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 479 | struct bcma_device *cc; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 480 | |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 481 | sii->icbus = pbus; |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 482 | sii->pcibus = pbus->host_pci; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 483 | |
Arend van Spriel | 16d2812 | 2011-12-08 15:06:51 -0800 | [diff] [blame] | 484 | /* switch to Chipcommon core */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 485 | cc = pbus->drv_cc.core; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 486 | |
Hauke Mehrtens | 1928ad7 | 2012-04-29 02:50:27 +0200 | [diff] [blame] | 487 | sih->chip = pbus->chipinfo.id; |
| 488 | sih->chiprev = pbus->chipinfo.rev; |
| 489 | sih->chippkg = pbus->chipinfo.pkg; |
| 490 | sih->boardvendor = pbus->boardinfo.vendor; |
| 491 | sih->boardtype = pbus->boardinfo.type; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 492 | |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 493 | if (!ai_buscore_setup(sii, cc)) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 494 | goto exit; |
| 495 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 496 | /* === NVRAM, clock is ready === */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 497 | bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0); |
| 498 | bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 499 | |
| 500 | /* PMU specific initializations */ |
Arend van Spriel | b2ffec4 | 2011-12-08 15:06:45 -0800 | [diff] [blame] | 501 | if (ai_get_cccaps(sih) & CC_CAP_PMU) { |
Arend van Spriel | 291ed3d | 2011-12-12 15:15:05 -0800 | [diff] [blame] | 502 | (void)si_pmu_measure_alpclk(sih); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 503 | } |
| 504 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 505 | return sii; |
| 506 | |
| 507 | exit: |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 508 | |
| 509 | return NULL; |
| 510 | } |
| 511 | |
| 512 | /* |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 513 | * Allocate a si handle and do the attach. |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 514 | */ |
| 515 | struct si_pub * |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 516 | ai_attach(struct bcma_bus *pbus) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 517 | { |
| 518 | struct si_info *sii; |
| 519 | |
| 520 | /* alloc struct si_info */ |
Larry Finger | 00d2ec0 | 2011-12-14 20:23:03 -0600 | [diff] [blame] | 521 | sii = kzalloc(sizeof(struct si_info), GFP_ATOMIC); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 522 | if (sii == NULL) |
| 523 | return NULL; |
| 524 | |
Arend van Spriel | 28a5344 | 2011-12-08 15:06:49 -0800 | [diff] [blame] | 525 | if (ai_doattach(sii, pbus) == NULL) { |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 526 | kfree(sii); |
| 527 | return NULL; |
| 528 | } |
| 529 | |
| 530 | return (struct si_pub *) sii; |
| 531 | } |
| 532 | |
| 533 | /* may be called with core in reset */ |
| 534 | void ai_detach(struct si_pub *sih) |
| 535 | { |
| 536 | struct si_info *sii; |
| 537 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 538 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 539 | |
| 540 | if (sii == NULL) |
| 541 | return; |
| 542 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 543 | kfree(sii); |
| 544 | } |
| 545 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 546 | /* |
Arend van Spriel | 3b758a6 | 2011-12-12 15:15:09 -0800 | [diff] [blame] | 547 | * read/modify chipcommon core register. |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 548 | */ |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 549 | uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 550 | { |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 551 | struct bcma_device *cc; |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 552 | u32 w; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 553 | struct si_info *sii; |
| 554 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 555 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 556 | cc = sii->icbus->drv_cc.core; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 557 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 558 | /* mask and set */ |
Chris Yungmann | 2b0446c | 2012-06-03 00:57:57 -0500 | [diff] [blame] | 559 | if (mask || val) |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 560 | bcma_maskset32(cc, regoff, ~mask, val); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 561 | |
| 562 | /* readback */ |
Arend van Spriel | 7d8e18e | 2011-12-08 15:06:56 -0800 | [diff] [blame] | 563 | w = bcma_read32(cc, regoff); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 564 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 565 | return w; |
| 566 | } |
| 567 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 568 | /* return the slow clock source - LPO, XTAL, or PCI */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 569 | static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 570 | { |
Hauke Mehrtens | d43c1c5 | 2012-04-29 02:50:28 +0200 | [diff] [blame] | 571 | return SCC_SS_XTAL; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 572 | } |
| 573 | |
| 574 | /* |
| 575 | * return the ILP (slowclock) min or max frequency |
| 576 | * precondition: we've established the chip has dynamic clk control |
| 577 | */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 578 | static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq, |
| 579 | struct bcma_device *cc) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 580 | { |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 581 | uint div; |
| 582 | |
Hauke Mehrtens | d43c1c5 | 2012-04-29 02:50:28 +0200 | [diff] [blame] | 583 | /* Chipc rev 10 is InstaClock */ |
| 584 | div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl)); |
| 585 | div = 4 * ((div >> SYCC_CD_SHIFT) + 1); |
| 586 | return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | static void |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 590 | ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 591 | { |
| 592 | uint slowmaxfreq, pll_delay, slowclk; |
| 593 | uint pll_on_delay, fref_sel_delay; |
| 594 | |
| 595 | pll_delay = PLL_DELAY; |
| 596 | |
| 597 | /* |
| 598 | * If the slow clock is not sourced by the xtal then |
| 599 | * add the xtal_on_delay since the xtal will also be |
| 600 | * powered down by dynamic clk control logic. |
| 601 | */ |
| 602 | |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 603 | slowclk = ai_slowclk_src(sih, cc); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 604 | if (slowclk != SCC_SS_XTAL) |
| 605 | pll_delay += XTAL_ON_DELAY; |
| 606 | |
| 607 | /* Starting with 4318 it is ILP that is used for the delays */ |
| 608 | slowmaxfreq = |
Hauke Mehrtens | d43c1c5 | 2012-04-29 02:50:28 +0200 | [diff] [blame] | 609 | ai_slowclk_freq(sih, false, cc); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 610 | |
| 611 | pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000; |
| 612 | fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000; |
| 613 | |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 614 | bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay); |
| 615 | bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 616 | } |
| 617 | |
| 618 | /* initialize power control delay registers */ |
| 619 | void ai_clkctl_init(struct si_pub *sih) |
| 620 | { |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 621 | struct si_info *sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 622 | struct bcma_device *cc; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 623 | |
Arend van Spriel | b2ffec4 | 2011-12-08 15:06:45 -0800 | [diff] [blame] | 624 | if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 625 | return; |
| 626 | |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 627 | cc = sii->icbus->drv_cc.core; |
Arend van Spriel | ad5db13 | 2011-12-08 15:06:55 -0800 | [diff] [blame] | 628 | if (cc == NULL) |
| 629 | return; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 630 | |
| 631 | /* set all Instaclk chip ILP to 1 MHz */ |
Hauke Mehrtens | d43c1c5 | 2012-04-29 02:50:28 +0200 | [diff] [blame] | 632 | bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK, |
| 633 | (ILP_DIV_1MHZ << SYCC_CD_SHIFT)); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 634 | |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 635 | ai_clkctl_setdelay(sih, cc); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 636 | } |
| 637 | |
| 638 | /* |
| 639 | * return the value suitable for writing to the |
| 640 | * dot11 core FAST_PWRUP_DELAY register |
| 641 | */ |
| 642 | u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) |
| 643 | { |
| 644 | struct si_info *sii; |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 645 | struct bcma_device *cc; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 646 | uint slowminfreq; |
| 647 | u16 fpdelay; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 648 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 649 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | b2ffec4 | 2011-12-08 15:06:45 -0800 | [diff] [blame] | 650 | if (ai_get_cccaps(sih) & CC_CAP_PMU) { |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 651 | fpdelay = si_pmu_fast_pwrup_delay(sih); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 652 | return fpdelay; |
| 653 | } |
| 654 | |
Arend van Spriel | b2ffec4 | 2011-12-08 15:06:45 -0800 | [diff] [blame] | 655 | if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL)) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 656 | return 0; |
| 657 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 658 | fpdelay = 0; |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 659 | cc = sii->icbus->drv_cc.core; |
Arend van Spriel | a232c8a | 2011-12-12 15:15:06 -0800 | [diff] [blame] | 660 | if (cc) { |
| 661 | slowminfreq = ai_slowclk_freq(sih, false, cc); |
| 662 | fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2) |
| 663 | * 1000000) + (slowminfreq - 1)) / slowminfreq; |
| 664 | } |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 665 | return fpdelay; |
| 666 | } |
| 667 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 668 | /* |
| 669 | * clock control policy function throught chipcommon |
| 670 | * |
| 671 | * set dynamic clk control mode (forceslow, forcefast, dynamic) |
| 672 | * returns true if we are forcing fast clock |
| 673 | * this is a wrapper over the next internal function |
| 674 | * to allow flexible policy settings for outside caller |
| 675 | */ |
Hauke Mehrtens | 712e3c1 | 2012-04-29 02:50:35 +0200 | [diff] [blame] | 676 | bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode) |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 677 | { |
| 678 | struct si_info *sii; |
Hauke Mehrtens | 712e3c1 | 2012-04-29 02:50:35 +0200 | [diff] [blame] | 679 | struct bcma_device *cc; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 680 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 681 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 682 | |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 683 | cc = sii->icbus->drv_cc.core; |
Hauke Mehrtens | 712e3c1 | 2012-04-29 02:50:35 +0200 | [diff] [blame] | 684 | bcma_core_set_clockmode(cc, mode); |
| 685 | return mode == BCMA_CLKMODE_FAST; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 686 | } |
| 687 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 688 | void ai_pci_up(struct si_pub *sih) |
| 689 | { |
| 690 | struct si_info *sii; |
| 691 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 692 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 693 | |
Hauke Mehrtens | a55b316 | 2012-06-30 15:16:04 +0200 | [diff] [blame] | 694 | if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) |
Hauke Mehrtens | 2ffd795 | 2012-04-29 02:50:38 +0200 | [diff] [blame] | 695 | bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 696 | } |
| 697 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 698 | /* Unconfigure and/or apply various WARs when going down */ |
| 699 | void ai_pci_down(struct si_pub *sih) |
| 700 | { |
| 701 | struct si_info *sii; |
| 702 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 703 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 704 | |
Hauke Mehrtens | a55b316 | 2012-06-30 15:16:04 +0200 | [diff] [blame] | 705 | if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) |
Hauke Mehrtens | 2ffd795 | 2012-04-29 02:50:38 +0200 | [diff] [blame] | 706 | bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 707 | } |
| 708 | |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 709 | /* Enable BT-COEX & Ex-PA for 4313 */ |
| 710 | void ai_epa_4313war(struct si_pub *sih) |
| 711 | { |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 712 | struct si_info *sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 713 | struct bcma_device *cc; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 714 | |
Hauke Mehrtens | 40bd94c | 2012-06-30 15:16:08 +0200 | [diff] [blame] | 715 | cc = sii->icbus->drv_cc.core; |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 716 | |
| 717 | /* EPA Fix */ |
Arend van Spriel | c808674 | 2011-12-12 15:15:03 -0800 | [diff] [blame] | 718 | bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 719 | } |
| 720 | |
| 721 | /* check if the device is removed */ |
| 722 | bool ai_deviceremoved(struct si_pub *sih) |
| 723 | { |
| 724 | u32 w; |
| 725 | struct si_info *sii; |
| 726 | |
Hauke Mehrtens | ed1dd81 | 2012-06-30 15:16:07 +0200 | [diff] [blame] | 727 | sii = container_of(sih, struct si_info, pub); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 728 | |
Hauke Mehrtens | 22291ce | 2012-04-29 02:50:43 +0200 | [diff] [blame] | 729 | if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI) |
| 730 | return false; |
| 731 | |
Arend van Spriel | cbc80db | 2011-12-08 15:06:48 -0800 | [diff] [blame] | 732 | pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w); |
Arend van Spriel | 5b435de | 2011-10-05 13:19:03 +0200 | [diff] [blame] | 733 | if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM) |
| 734 | return true; |
| 735 | |
| 736 | return false; |
| 737 | } |