blob: b15e4ea0b0911bdffa62b3c122663d9f8b8a5134 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Maciej W. Rozyckifc095a92006-09-12 19:12:18 +01002 * Copyright (C) 1999, 2006 MIPS Technologies, Inc. All rights reserved.
3 * Authors: Carsten Langgaard <carstenl@mips.com>
4 * Maciej W. Rozycki <macro@mips.com>
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * ########################################################################
7 *
8 * This program is free software; you can distribute it and/or modify it
9 * under the terms of the GNU General Public License (Version 2) as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 *
21 * ########################################################################
22 *
23 * Defines for the Atlas interrupt controller.
24 *
25 */
26#ifndef _MIPS_ATLASINT_H
27#define _MIPS_ATLASINT_H
28
Maciej W. Rozyckifc095a92006-09-12 19:12:18 +010029/*
30 * Interrupts 0..7 are used for Atlas CPU interrupts (nonEIC mode)
31 */
32#define MIPSCPU_INT_BASE 0
33
34/* CPU interrupt offsets */
35#define MIPSCPU_INT_SW0 0
36#define MIPSCPU_INT_SW1 1
37#define MIPSCPU_INT_MB0 2
38#define MIPSCPU_INT_ATLAS MIPSCPU_INT_MB0
39#define MIPSCPU_INT_MB1 3
40#define MIPSCPU_INT_MB2 4
41#define MIPSCPU_INT_MB3 5
42#define MIPSCPU_INT_MB4 6
43#define MIPSCPU_INT_CPUCTR 7
44
45/*
46 * Interrupts 8..39 are used for Atlas interrupt controller interrupts
47 */
48#define ATLAS_INT_BASE 8
49#define ATLAS_INT_UART (ATLAS_INT_BASE + 0)
50#define ATLAS_INT_TIM0 (ATLAS_INT_BASE + 1)
51#define ATLAS_INT_RES2 (ATLAS_INT_BASE + 2)
52#define ATLAS_INT_RES3 (ATLAS_INT_BASE + 3)
53#define ATLAS_INT_RTC (ATLAS_INT_BASE + 4)
54#define ATLAS_INT_COREHI (ATLAS_INT_BASE + 5)
55#define ATLAS_INT_CORELO (ATLAS_INT_BASE + 6)
56#define ATLAS_INT_RES7 (ATLAS_INT_BASE + 7)
57#define ATLAS_INT_PCIA (ATLAS_INT_BASE + 8)
58#define ATLAS_INT_PCIB (ATLAS_INT_BASE + 9)
59#define ATLAS_INT_PCIC (ATLAS_INT_BASE + 10)
60#define ATLAS_INT_PCID (ATLAS_INT_BASE + 11)
61#define ATLAS_INT_ENUM (ATLAS_INT_BASE + 12)
62#define ATLAS_INT_DEG (ATLAS_INT_BASE + 13)
63#define ATLAS_INT_ATXFAIL (ATLAS_INT_BASE + 14)
64#define ATLAS_INT_INTA (ATLAS_INT_BASE + 15)
65#define ATLAS_INT_INTB (ATLAS_INT_BASE + 16)
66#define ATLAS_INT_ETH ATLAS_INT_INTB
67#define ATLAS_INT_INTC (ATLAS_INT_BASE + 17)
68#define ATLAS_INT_SCSI ATLAS_INT_INTC
69#define ATLAS_INT_INTD (ATLAS_INT_BASE + 18)
70#define ATLAS_INT_SERR (ATLAS_INT_BASE + 19)
71#define ATLAS_INT_RES20 (ATLAS_INT_BASE + 20)
72#define ATLAS_INT_RES21 (ATLAS_INT_BASE + 21)
73#define ATLAS_INT_RES22 (ATLAS_INT_BASE + 22)
74#define ATLAS_INT_RES23 (ATLAS_INT_BASE + 23)
75#define ATLAS_INT_RES24 (ATLAS_INT_BASE + 24)
76#define ATLAS_INT_RES25 (ATLAS_INT_BASE + 25)
77#define ATLAS_INT_RES26 (ATLAS_INT_BASE + 26)
78#define ATLAS_INT_RES27 (ATLAS_INT_BASE + 27)
79#define ATLAS_INT_RES28 (ATLAS_INT_BASE + 28)
80#define ATLAS_INT_RES29 (ATLAS_INT_BASE + 29)
81#define ATLAS_INT_RES30 (ATLAS_INT_BASE + 30)
82#define ATLAS_INT_RES31 (ATLAS_INT_BASE + 31)
83#define ATLAS_INT_END (ATLAS_INT_BASE + 31)
84
85/*
86 * Interrupts 64..127 are used for Soc-it Classic interrupts
87 */
88#define MSC01C_INT_BASE 64
89
90/* SOC-it Classic interrupt offsets */
91#define MSC01C_INT_TMR 0
92#define MSC01C_INT_PCI 1
93
94/*
95 * Interrupts 64..127 are used for Soc-it EIC interrupts
96 */
97#define MSC01E_INT_BASE 64
98
99/* SOC-it EIC interrupt offsets */
100#define MSC01E_INT_SW0 1
101#define MSC01E_INT_SW1 2
102#define MSC01E_INT_MB0 3
103#define MSC01E_INT_ATLAS MSC01E_INT_MB0
104#define MSC01E_INT_MB1 4
105#define MSC01E_INT_MB2 5
106#define MSC01E_INT_MB3 6
107#define MSC01E_INT_MB4 7
108#define MSC01E_INT_TMR 8
109#define MSC01E_INT_PCI 9
110#define MSC01E_INT_PERFCTR 10
111#define MSC01E_INT_CPUCTR 11
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113#endif /* !(_MIPS_ATLASINT_H) */