blob: ae407f7226c89961fde14ddd6d932f174c64d8fc [file] [log] [blame]
Ingo Molnar241771e2008-12-03 10:39:53 +01001/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +02002 * Performance events x86 architecture code
Ingo Molnar241771e2008-12-03 10:39:53 +01003 *
Ingo Molnar98144512009-04-29 14:52:50 +02004 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
Markus Metzger30dd5682009-07-21 15:56:48 +02009 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
Stephane Eranian1da53e02010-01-18 10:58:01 +020010 * Copyright (C) 2009 Google, Inc., Stephane Eranian
Ingo Molnar241771e2008-12-03 10:39:53 +010011 *
12 * For licencing details see kernel-base/COPYING
13 */
14
Ingo Molnarcdd6c482009-09-21 12:02:48 +020015#include <linux/perf_event.h>
Ingo Molnar241771e2008-12-03 10:39:53 +010016#include <linux/capability.h>
17#include <linux/notifier.h>
18#include <linux/hardirq.h>
19#include <linux/kprobes.h>
Thomas Gleixner4ac13292008-12-09 21:43:39 +010020#include <linux/module.h>
Ingo Molnar241771e2008-12-03 10:39:53 +010021#include <linux/kdebug.h>
22#include <linux/sched.h>
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +020023#include <linux/uaccess.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Markus Metzger30dd5682009-07-21 15:56:48 +020025#include <linux/cpu.h>
Peter Zijlstra272d30b2010-01-22 16:32:17 +010026#include <linux/bitops.h>
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +010027#include <linux/device.h>
Ingo Molnar241771e2008-12-03 10:39:53 +010028
Ingo Molnar241771e2008-12-03 10:39:53 +010029#include <asm/apic.h>
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +020030#include <asm/stacktrace.h>
Peter Zijlstra4e935e42009-03-30 19:07:16 +020031#include <asm/nmi.h>
Lin Ming69092622011-03-03 10:34:50 +080032#include <asm/smp.h>
Robert Richterc8e59102011-04-16 02:27:55 +020033#include <asm/alternative.h>
Peter Zijlstrae3f35412011-11-21 11:43:53 +010034#include <asm/timer.h>
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +020035#include <asm/desc.h>
36#include <asm/ldt.h>
Ingo Molnar241771e2008-12-03 10:39:53 +010037
Kevin Winchesterde0428a2011-08-30 20:41:05 -030038#include "perf_event.h"
39
Kevin Winchesterde0428a2011-08-30 20:41:05 -030040struct x86_pmu x86_pmu __read_mostly;
Stephane Eranianefc9f052011-06-06 16:57:03 +020041
Kevin Winchesterde0428a2011-08-30 20:41:05 -030042DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
Peter Zijlstrab0f3f282009-03-05 18:08:27 +010043 .enabled = 1,
44};
Ingo Molnar241771e2008-12-03 10:39:53 +010045
Kevin Winchesterde0428a2011-08-30 20:41:05 -030046u64 __read_mostly hw_cache_event_ids
Ingo Molnar8326f442009-06-05 20:22:46 +020047 [PERF_COUNT_HW_CACHE_MAX]
48 [PERF_COUNT_HW_CACHE_OP_MAX]
49 [PERF_COUNT_HW_CACHE_RESULT_MAX];
Kevin Winchesterde0428a2011-08-30 20:41:05 -030050u64 __read_mostly hw_cache_extra_regs
Andi Kleene994d7d2011-03-03 10:34:48 +080051 [PERF_COUNT_HW_CACHE_MAX]
52 [PERF_COUNT_HW_CACHE_OP_MAX]
53 [PERF_COUNT_HW_CACHE_RESULT_MAX];
Ingo Molnar8326f442009-06-05 20:22:46 +020054
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +053055/*
Ingo Molnarcdd6c482009-09-21 12:02:48 +020056 * Propagate event elapsed time into the generic event.
57 * Can only be executed on the CPU where the event is active.
Ingo Molnaree060942008-12-13 09:00:03 +010058 * Returns the delta events processed.
59 */
Kevin Winchesterde0428a2011-08-30 20:41:05 -030060u64 x86_perf_event_update(struct perf_event *event)
Ingo Molnaree060942008-12-13 09:00:03 +010061{
Peter Zijlstracc2ad4b2010-03-02 20:18:39 +010062 struct hw_perf_event *hwc = &event->hw;
Robert Richter948b1bb2010-03-29 18:36:50 +020063 int shift = 64 - x86_pmu.cntval_bits;
Peter Zijlstraec3232b2009-05-13 09:45:19 +020064 u64 prev_raw_count, new_raw_count;
Peter Zijlstracc2ad4b2010-03-02 20:18:39 +010065 int idx = hwc->idx;
Peter Zijlstraec3232b2009-05-13 09:45:19 +020066 s64 delta;
Ingo Molnaree060942008-12-13 09:00:03 +010067
Robert Richter15c7ad52012-06-20 20:46:33 +020068 if (idx == INTEL_PMC_IDX_FIXED_BTS)
Markus Metzger30dd5682009-07-21 15:56:48 +020069 return 0;
70
Ingo Molnaree060942008-12-13 09:00:03 +010071 /*
Ingo Molnarcdd6c482009-09-21 12:02:48 +020072 * Careful: an NMI might modify the previous event value.
Ingo Molnaree060942008-12-13 09:00:03 +010073 *
74 * Our tactic to handle this is to first atomically read and
75 * exchange a new raw count - then add that new-prev delta
Ingo Molnarcdd6c482009-09-21 12:02:48 +020076 * count to the generic event atomically:
Ingo Molnaree060942008-12-13 09:00:03 +010077 */
78again:
Peter Zijlstrae7850592010-05-21 14:43:08 +020079 prev_raw_count = local64_read(&hwc->prev_count);
Vince Weaverc48b6052012-03-01 17:28:14 -050080 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
Ingo Molnaree060942008-12-13 09:00:03 +010081
Peter Zijlstrae7850592010-05-21 14:43:08 +020082 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
Ingo Molnaree060942008-12-13 09:00:03 +010083 new_raw_count) != prev_raw_count)
84 goto again;
85
86 /*
87 * Now we have the new raw value and have updated the prev
88 * timestamp already. We can now calculate the elapsed delta
Ingo Molnarcdd6c482009-09-21 12:02:48 +020089 * (event-)time and add that to the generic event.
Ingo Molnaree060942008-12-13 09:00:03 +010090 *
91 * Careful, not all hw sign-extends above the physical width
Peter Zijlstraec3232b2009-05-13 09:45:19 +020092 * of the count.
Ingo Molnaree060942008-12-13 09:00:03 +010093 */
Peter Zijlstraec3232b2009-05-13 09:45:19 +020094 delta = (new_raw_count << shift) - (prev_raw_count << shift);
95 delta >>= shift;
Ingo Molnaree060942008-12-13 09:00:03 +010096
Peter Zijlstrae7850592010-05-21 14:43:08 +020097 local64_add(delta, &event->count);
98 local64_sub(delta, &hwc->period_left);
Robert Richter4b7bfd02009-04-29 12:47:22 +020099
100 return new_raw_count;
Ingo Molnaree060942008-12-13 09:00:03 +0100101}
102
Andi Kleena7e3ed12011-03-03 10:34:47 +0800103/*
104 * Find and validate any extra registers to set up.
105 */
106static int x86_pmu_extra_regs(u64 config, struct perf_event *event)
107{
Stephane Eranianefc9f052011-06-06 16:57:03 +0200108 struct hw_perf_event_extra *reg;
Andi Kleena7e3ed12011-03-03 10:34:47 +0800109 struct extra_reg *er;
110
Stephane Eranianefc9f052011-06-06 16:57:03 +0200111 reg = &event->hw.extra_reg;
Andi Kleena7e3ed12011-03-03 10:34:47 +0800112
113 if (!x86_pmu.extra_regs)
114 return 0;
115
116 for (er = x86_pmu.extra_regs; er->msr; er++) {
117 if (er->event != (config & er->config_mask))
118 continue;
119 if (event->attr.config1 & ~er->valid_mask)
120 return -EINVAL;
Stephane Eranianefc9f052011-06-06 16:57:03 +0200121
122 reg->idx = er->idx;
123 reg->config = event->attr.config1;
124 reg->reg = er->msr;
Andi Kleena7e3ed12011-03-03 10:34:47 +0800125 break;
126 }
127 return 0;
128}
129
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200130static atomic_t active_events;
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200131static DEFINE_MUTEX(pmc_reserve_mutex);
132
Robert Richterb27ea292010-03-17 12:49:10 +0100133#ifdef CONFIG_X86_LOCAL_APIC
134
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200135static bool reserve_pmc_hardware(void)
136{
137 int i;
138
Robert Richter948b1bb2010-03-29 18:36:50 +0200139 for (i = 0; i < x86_pmu.num_counters; i++) {
Robert Richter41bf4982011-02-02 17:40:57 +0100140 if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200141 goto perfctr_fail;
142 }
143
Robert Richter948b1bb2010-03-29 18:36:50 +0200144 for (i = 0; i < x86_pmu.num_counters; i++) {
Robert Richter41bf4982011-02-02 17:40:57 +0100145 if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200146 goto eventsel_fail;
147 }
148
149 return true;
150
151eventsel_fail:
152 for (i--; i >= 0; i--)
Robert Richter41bf4982011-02-02 17:40:57 +0100153 release_evntsel_nmi(x86_pmu_config_addr(i));
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200154
Robert Richter948b1bb2010-03-29 18:36:50 +0200155 i = x86_pmu.num_counters;
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200156
157perfctr_fail:
158 for (i--; i >= 0; i--)
Robert Richter41bf4982011-02-02 17:40:57 +0100159 release_perfctr_nmi(x86_pmu_event_addr(i));
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200160
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200161 return false;
162}
163
164static void release_pmc_hardware(void)
165{
166 int i;
167
Robert Richter948b1bb2010-03-29 18:36:50 +0200168 for (i = 0; i < x86_pmu.num_counters; i++) {
Robert Richter41bf4982011-02-02 17:40:57 +0100169 release_perfctr_nmi(x86_pmu_event_addr(i));
170 release_evntsel_nmi(x86_pmu_config_addr(i));
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200171 }
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200172}
173
Robert Richterb27ea292010-03-17 12:49:10 +0100174#else
175
176static bool reserve_pmc_hardware(void) { return true; }
177static void release_pmc_hardware(void) {}
178
179#endif
180
Don Zickus33c6d6a2010-11-22 16:55:23 -0500181static bool check_hw_exists(void)
182{
George Dunlapa5ebe0b2013-04-03 15:46:28 +0100183 u64 val, val_fail, val_new= ~0;
184 int i, reg, reg_fail, ret = 0;
185 int bios_fail = 0;
Don Zickus33c6d6a2010-11-22 16:55:23 -0500186
Peter Zijlstra44072042010-12-08 15:56:23 +0100187 /*
188 * Check to see if the BIOS enabled any of the counters, if so
189 * complain and bail.
190 */
191 for (i = 0; i < x86_pmu.num_counters; i++) {
Robert Richter41bf4982011-02-02 17:40:57 +0100192 reg = x86_pmu_config_addr(i);
Peter Zijlstra44072042010-12-08 15:56:23 +0100193 ret = rdmsrl_safe(reg, &val);
194 if (ret)
195 goto msr_fail;
George Dunlapa5ebe0b2013-04-03 15:46:28 +0100196 if (val & ARCH_PERFMON_EVENTSEL_ENABLE) {
197 bios_fail = 1;
198 val_fail = val;
199 reg_fail = reg;
200 }
Peter Zijlstra44072042010-12-08 15:56:23 +0100201 }
202
203 if (x86_pmu.num_counters_fixed) {
204 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
205 ret = rdmsrl_safe(reg, &val);
206 if (ret)
207 goto msr_fail;
208 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
George Dunlapa5ebe0b2013-04-03 15:46:28 +0100209 if (val & (0x03 << i*4)) {
210 bios_fail = 1;
211 val_fail = val;
212 reg_fail = reg;
213 }
Peter Zijlstra44072042010-12-08 15:56:23 +0100214 }
215 }
216
217 /*
Andre Przywarabffd5fc2012-10-09 17:38:35 +0200218 * Read the current value, change it and read it back to see if it
219 * matches, this is needed to detect certain hardware emulators
220 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
Peter Zijlstra44072042010-12-08 15:56:23 +0100221 */
Robert Richterf285f922012-06-20 20:46:36 +0200222 reg = x86_pmu_event_addr(0);
Andre Przywarabffd5fc2012-10-09 17:38:35 +0200223 if (rdmsrl_safe(reg, &val))
224 goto msr_fail;
225 val ^= 0xffffUL;
Robert Richterf285f922012-06-20 20:46:36 +0200226 ret = wrmsrl_safe(reg, val);
227 ret |= rdmsrl_safe(reg, &val_new);
Don Zickus33c6d6a2010-11-22 16:55:23 -0500228 if (ret || val != val_new)
Peter Zijlstra44072042010-12-08 15:56:23 +0100229 goto msr_fail;
Don Zickus33c6d6a2010-11-22 16:55:23 -0500230
Ingo Molnar45daae52011-03-25 10:24:23 +0100231 /*
232 * We still allow the PMU driver to operate:
233 */
George Dunlapa5ebe0b2013-04-03 15:46:28 +0100234 if (bios_fail) {
235 printk(KERN_CONT "Broken BIOS detected, complain to your hardware vendor.\n");
236 printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg_fail, val_fail);
237 }
Ingo Molnar45daae52011-03-25 10:24:23 +0100238
239 return true;
Peter Zijlstra44072042010-12-08 15:56:23 +0100240
241msr_fail:
242 printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
Robert Richterf285f922012-06-20 20:46:36 +0200243 printk(KERN_ERR "Failed to access perfctr msr (MSR %x is %Lx)\n", reg, val_new);
Ingo Molnar45daae52011-03-25 10:24:23 +0100244
Peter Zijlstra44072042010-12-08 15:56:23 +0100245 return false;
Don Zickus33c6d6a2010-11-22 16:55:23 -0500246}
247
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200248static void hw_perf_event_destroy(struct perf_event *event)
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200249{
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200250 if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200251 release_pmc_hardware();
Peter Zijlstraca037702010-03-02 19:52:12 +0100252 release_ds_buffers();
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200253 mutex_unlock(&pmc_reserve_mutex);
254 }
255}
256
Robert Richter85cf9db2009-04-29 12:47:20 +0200257static inline int x86_pmu_initialized(void)
258{
259 return x86_pmu.handle_irq != NULL;
260}
261
Ingo Molnar8326f442009-06-05 20:22:46 +0200262static inline int
Andi Kleene994d7d2011-03-03 10:34:48 +0800263set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event)
Ingo Molnar8326f442009-06-05 20:22:46 +0200264{
Andi Kleene994d7d2011-03-03 10:34:48 +0800265 struct perf_event_attr *attr = &event->attr;
Ingo Molnar8326f442009-06-05 20:22:46 +0200266 unsigned int cache_type, cache_op, cache_result;
267 u64 config, val;
268
269 config = attr->config;
270
271 cache_type = (config >> 0) & 0xff;
272 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
273 return -EINVAL;
274
275 cache_op = (config >> 8) & 0xff;
276 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
277 return -EINVAL;
278
279 cache_result = (config >> 16) & 0xff;
280 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
281 return -EINVAL;
282
283 val = hw_cache_event_ids[cache_type][cache_op][cache_result];
284
285 if (val == 0)
286 return -ENOENT;
287
288 if (val == -1)
289 return -EINVAL;
290
291 hwc->config |= val;
Andi Kleene994d7d2011-03-03 10:34:48 +0800292 attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result];
293 return x86_pmu_extra_regs(val, event);
Ingo Molnar8326f442009-06-05 20:22:46 +0200294}
295
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300296int x86_setup_perfctr(struct perf_event *event)
Robert Richterc1726f32010-04-13 22:23:11 +0200297{
298 struct perf_event_attr *attr = &event->attr;
299 struct hw_perf_event *hwc = &event->hw;
300 u64 config;
301
Franck Bui-Huu6c7e5502010-11-23 16:21:43 +0100302 if (!is_sampling_event(event)) {
Robert Richterc1726f32010-04-13 22:23:11 +0200303 hwc->sample_period = x86_pmu.max_period;
304 hwc->last_period = hwc->sample_period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200305 local64_set(&hwc->period_left, hwc->sample_period);
Robert Richterc1726f32010-04-13 22:23:11 +0200306 } else {
307 /*
308 * If we have a PMU initialized but no APIC
309 * interrupts, we cannot sample hardware
310 * events (user-space has to fall back and
311 * sample via a hrtimer based software event):
312 */
313 if (!x86_pmu.apic)
314 return -EOPNOTSUPP;
315 }
316
317 if (attr->type == PERF_TYPE_RAW)
Peter Zijlstraed13ec52011-11-14 10:03:25 +0100318 return x86_pmu_extra_regs(event->attr.config, event);
Robert Richterc1726f32010-04-13 22:23:11 +0200319
320 if (attr->type == PERF_TYPE_HW_CACHE)
Andi Kleene994d7d2011-03-03 10:34:48 +0800321 return set_ext_hw_attr(hwc, event);
Robert Richterc1726f32010-04-13 22:23:11 +0200322
323 if (attr->config >= x86_pmu.max_events)
324 return -EINVAL;
325
326 /*
327 * The generic map:
328 */
329 config = x86_pmu.event_map(attr->config);
330
331 if (config == 0)
332 return -ENOENT;
333
334 if (config == -1LL)
335 return -EINVAL;
336
337 /*
338 * Branch tracing:
339 */
Peter Zijlstra18a073a2011-04-26 13:24:33 +0200340 if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS &&
341 !attr->freq && hwc->sample_period == 1) {
Robert Richterc1726f32010-04-13 22:23:11 +0200342 /* BTS is not supported by this architecture. */
Peter Zijlstra6809b6e2010-10-19 14:22:50 +0200343 if (!x86_pmu.bts_active)
Robert Richterc1726f32010-04-13 22:23:11 +0200344 return -EOPNOTSUPP;
345
346 /* BTS is currently only allowed for user-mode. */
347 if (!attr->exclude_kernel)
348 return -EOPNOTSUPP;
349 }
350
351 hwc->config |= config;
352
353 return 0;
354}
Robert Richter4261e0e2010-04-13 22:23:10 +0200355
Stephane Eranianff3fb512012-02-09 23:20:54 +0100356/*
357 * check that branch_sample_type is compatible with
358 * settings needed for precise_ip > 1 which implies
359 * using the LBR to capture ALL taken branches at the
360 * priv levels of the measurement
361 */
362static inline int precise_br_compat(struct perf_event *event)
363{
364 u64 m = event->attr.branch_sample_type;
365 u64 b = 0;
366
367 /* must capture all branches */
368 if (!(m & PERF_SAMPLE_BRANCH_ANY))
369 return 0;
370
371 m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER;
372
373 if (!event->attr.exclude_user)
374 b |= PERF_SAMPLE_BRANCH_USER;
375
376 if (!event->attr.exclude_kernel)
377 b |= PERF_SAMPLE_BRANCH_KERNEL;
378
379 /*
380 * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86
381 */
382
383 return m == b;
384}
385
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300386int x86_pmu_hw_config(struct perf_event *event)
Cyrill Gorcunova0727382010-03-11 19:54:39 +0300387{
Peter Zijlstraab608342010-04-08 23:03:20 +0200388 if (event->attr.precise_ip) {
389 int precise = 0;
390
391 /* Support for constant skid */
Peter Zijlstrac93dc842012-06-08 14:50:50 +0200392 if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) {
Peter Zijlstraab608342010-04-08 23:03:20 +0200393 precise++;
394
Peter Zijlstra5553be22010-10-19 14:38:11 +0200395 /* Support for IP fixup */
396 if (x86_pmu.lbr_nr)
397 precise++;
398 }
Peter Zijlstraab608342010-04-08 23:03:20 +0200399
400 if (event->attr.precise_ip > precise)
401 return -EOPNOTSUPP;
Stephane Eranianff3fb512012-02-09 23:20:54 +0100402 /*
403 * check that PEBS LBR correction does not conflict with
404 * whatever the user is asking with attr->branch_sample_type
405 */
Andi Kleen130768b2013-06-17 17:36:47 -0700406 if (event->attr.precise_ip > 1 &&
407 x86_pmu.intel_cap.pebs_format < 2) {
Stephane Eranianff3fb512012-02-09 23:20:54 +0100408 u64 *br_type = &event->attr.branch_sample_type;
409
410 if (has_branch_stack(event)) {
411 if (!precise_br_compat(event))
412 return -EOPNOTSUPP;
413
414 /* branch_sample_type is compatible */
415
416 } else {
417 /*
418 * user did not specify branch_sample_type
419 *
420 * For PEBS fixups, we capture all
421 * the branches at the priv level of the
422 * event.
423 */
424 *br_type = PERF_SAMPLE_BRANCH_ANY;
425
426 if (!event->attr.exclude_user)
427 *br_type |= PERF_SAMPLE_BRANCH_USER;
428
429 if (!event->attr.exclude_kernel)
430 *br_type |= PERF_SAMPLE_BRANCH_KERNEL;
431 }
432 }
Peter Zijlstraab608342010-04-08 23:03:20 +0200433 }
434
Cyrill Gorcunova0727382010-03-11 19:54:39 +0300435 /*
436 * Generate PMC IRQs:
437 * (keep 'enabled' bit clear for now)
438 */
Peter Zijlstrab4cdc5c2010-03-30 17:00:06 +0200439 event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
Cyrill Gorcunova0727382010-03-11 19:54:39 +0300440
441 /*
442 * Count user and OS events unless requested not to
443 */
Peter Zijlstrab4cdc5c2010-03-30 17:00:06 +0200444 if (!event->attr.exclude_user)
445 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
446 if (!event->attr.exclude_kernel)
447 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
448
449 if (event->attr.type == PERF_TYPE_RAW)
450 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
Cyrill Gorcunova0727382010-03-11 19:54:39 +0300451
Robert Richter9d0fcba62010-04-13 22:23:12 +0200452 return x86_setup_perfctr(event);
Cyrill Gorcunova0727382010-03-11 19:54:39 +0300453}
454
Ingo Molnaree060942008-12-13 09:00:03 +0100455/*
Peter Zijlstra0d486962009-06-02 19:22:16 +0200456 * Setup the hardware configuration for a given attr_type
Ingo Molnar241771e2008-12-03 10:39:53 +0100457 */
Peter Zijlstrab0a873e2010-06-11 13:35:08 +0200458static int __x86_pmu_event_init(struct perf_event *event)
Ingo Molnar241771e2008-12-03 10:39:53 +0100459{
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200460 int err;
Ingo Molnar241771e2008-12-03 10:39:53 +0100461
Robert Richter85cf9db2009-04-29 12:47:20 +0200462 if (!x86_pmu_initialized())
463 return -ENODEV;
Ingo Molnar241771e2008-12-03 10:39:53 +0100464
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200465 err = 0;
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200466 if (!atomic_inc_not_zero(&active_events)) {
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200467 mutex_lock(&pmc_reserve_mutex);
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200468 if (atomic_read(&active_events) == 0) {
Markus Metzger30dd5682009-07-21 15:56:48 +0200469 if (!reserve_pmc_hardware())
470 err = -EBUSY;
Peter Zijlstraf80c9e32010-10-19 14:50:02 +0200471 else
472 reserve_ds_buffers();
Markus Metzger30dd5682009-07-21 15:56:48 +0200473 }
474 if (!err)
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200475 atomic_inc(&active_events);
Peter Zijlstra4e935e42009-03-30 19:07:16 +0200476 mutex_unlock(&pmc_reserve_mutex);
477 }
478 if (err)
479 return err;
480
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200481 event->destroy = hw_perf_event_destroy;
Peter Zijlstraa1792cdac2009-09-09 10:04:47 +0200482
Robert Richter4261e0e2010-04-13 22:23:10 +0200483 event->hw.idx = -1;
484 event->hw.last_cpu = -1;
485 event->hw.last_tag = ~0ULL;
Stephane Eranianb6900812009-10-06 16:42:09 +0200486
Stephane Eranianefc9f052011-06-06 16:57:03 +0200487 /* mark unused */
488 event->hw.extra_reg.idx = EXTRA_REG_NONE;
Stephane Eranianb36817e2012-02-09 23:20:53 +0100489 event->hw.branch_reg.idx = EXTRA_REG_NONE;
490
Robert Richter9d0fcba62010-04-13 22:23:12 +0200491 return x86_pmu.hw_config(event);
Robert Richter4261e0e2010-04-13 22:23:10 +0200492}
493
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300494void x86_pmu_disable_all(void)
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530495{
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200496 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
Peter Zijlstra9e35ad32009-05-13 16:21:38 +0200497 int idx;
Peter Zijlstrab0f3f282009-03-05 18:08:27 +0100498
Robert Richter948b1bb2010-03-29 18:36:50 +0200499 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
Peter Zijlstrab0f3f282009-03-05 18:08:27 +0100500 u64 val;
501
Robert Richter43f62012009-04-29 16:55:56 +0200502 if (!test_bit(idx, cpuc->active_mask))
Robert Richter4295ee62009-04-29 12:47:01 +0200503 continue;
Robert Richter41bf4982011-02-02 17:40:57 +0100504 rdmsrl(x86_pmu_config_addr(idx), val);
Robert Richterbb1165d2010-03-01 14:21:23 +0100505 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
Robert Richter4295ee62009-04-29 12:47:01 +0200506 continue;
Robert Richterbb1165d2010-03-01 14:21:23 +0100507 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
Robert Richter41bf4982011-02-02 17:40:57 +0100508 wrmsrl(x86_pmu_config_addr(idx), val);
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530509 }
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530510}
511
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200512static void x86_pmu_disable(struct pmu *pmu)
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +0530513{
Stephane Eranian1da53e02010-01-18 10:58:01 +0200514 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
515
Robert Richter85cf9db2009-04-29 12:47:20 +0200516 if (!x86_pmu_initialized())
Peter Zijlstra9e35ad32009-05-13 16:21:38 +0200517 return;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200518
Peter Zijlstra1a6e21f2010-01-27 23:07:47 +0100519 if (!cpuc->enabled)
520 return;
521
522 cpuc->n_added = 0;
523 cpuc->enabled = 0;
524 barrier();
Stephane Eranian1da53e02010-01-18 10:58:01 +0200525
526 x86_pmu.disable_all();
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +0530527}
Ingo Molnar241771e2008-12-03 10:39:53 +0100528
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300529void x86_pmu_enable_all(int added)
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530530{
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200531 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530532 int idx;
533
Robert Richter948b1bb2010-03-29 18:36:50 +0200534 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
Robert Richterd45dd922011-02-02 17:40:56 +0100535 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
Peter Zijlstrab0f3f282009-03-05 18:08:27 +0100536
Robert Richter43f62012009-04-29 16:55:56 +0200537 if (!test_bit(idx, cpuc->active_mask))
Robert Richter4295ee62009-04-29 12:47:01 +0200538 continue;
Peter Zijlstra984b8382009-07-10 09:59:56 +0200539
Robert Richterd45dd922011-02-02 17:40:56 +0100540 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +0530541 }
542}
543
Peter Zijlstra51b0fe32010-06-11 13:35:57 +0200544static struct pmu pmu;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200545
546static inline int is_x86_event(struct perf_event *event)
547{
548 return event->pmu == &pmu;
549}
550
Robert Richter1e2ad282011-11-18 12:35:21 +0100551/*
552 * Event scheduler state:
553 *
554 * Assign events iterating over all events and counters, beginning
555 * with events with least weights first. Keep the current iterator
556 * state in struct sched_state.
557 */
558struct sched_state {
559 int weight;
560 int event; /* event index */
561 int counter; /* counter index */
562 int unassigned; /* number of events to be assigned left */
563 unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
564};
565
Robert Richterbc1738f2011-11-18 12:35:22 +0100566/* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */
567#define SCHED_STATES_MAX 2
568
Robert Richter1e2ad282011-11-18 12:35:21 +0100569struct perf_sched {
570 int max_weight;
571 int max_events;
Andrew Hunter43b457802013-05-23 11:07:03 -0700572 struct perf_event **events;
Robert Richter1e2ad282011-11-18 12:35:21 +0100573 struct sched_state state;
Robert Richterbc1738f2011-11-18 12:35:22 +0100574 int saved_states;
575 struct sched_state saved[SCHED_STATES_MAX];
Robert Richter1e2ad282011-11-18 12:35:21 +0100576};
577
578/*
579 * Initialize interator that runs through all events and counters.
580 */
Andrew Hunter43b457802013-05-23 11:07:03 -0700581static void perf_sched_init(struct perf_sched *sched, struct perf_event **events,
Robert Richter1e2ad282011-11-18 12:35:21 +0100582 int num, int wmin, int wmax)
583{
584 int idx;
585
586 memset(sched, 0, sizeof(*sched));
587 sched->max_events = num;
588 sched->max_weight = wmax;
Andrew Hunter43b457802013-05-23 11:07:03 -0700589 sched->events = events;
Robert Richter1e2ad282011-11-18 12:35:21 +0100590
591 for (idx = 0; idx < num; idx++) {
Andrew Hunter43b457802013-05-23 11:07:03 -0700592 if (events[idx]->hw.constraint->weight == wmin)
Robert Richter1e2ad282011-11-18 12:35:21 +0100593 break;
594 }
595
596 sched->state.event = idx; /* start with min weight */
597 sched->state.weight = wmin;
598 sched->state.unassigned = num;
599}
600
Robert Richterbc1738f2011-11-18 12:35:22 +0100601static void perf_sched_save_state(struct perf_sched *sched)
602{
603 if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX))
604 return;
605
606 sched->saved[sched->saved_states] = sched->state;
607 sched->saved_states++;
608}
609
610static bool perf_sched_restore_state(struct perf_sched *sched)
611{
612 if (!sched->saved_states)
613 return false;
614
615 sched->saved_states--;
616 sched->state = sched->saved[sched->saved_states];
617
618 /* continue with next counter: */
619 clear_bit(sched->state.counter++, sched->state.used);
620
621 return true;
622}
623
Robert Richter1e2ad282011-11-18 12:35:21 +0100624/*
625 * Select a counter for the current event to schedule. Return true on
626 * success.
627 */
Robert Richterbc1738f2011-11-18 12:35:22 +0100628static bool __perf_sched_find_counter(struct perf_sched *sched)
Robert Richter1e2ad282011-11-18 12:35:21 +0100629{
630 struct event_constraint *c;
631 int idx;
632
633 if (!sched->state.unassigned)
634 return false;
635
636 if (sched->state.event >= sched->max_events)
637 return false;
638
Andrew Hunter43b457802013-05-23 11:07:03 -0700639 c = sched->events[sched->state.event]->hw.constraint;
Peter Zijlstra4defea82011-11-10 15:15:42 +0100640 /* Prefer fixed purpose counters */
Robert Richter15c7ad52012-06-20 20:46:33 +0200641 if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) {
642 idx = INTEL_PMC_IDX_FIXED;
Akinobu Mita307b1cd2012-03-23 15:02:03 -0700643 for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) {
Peter Zijlstra4defea82011-11-10 15:15:42 +0100644 if (!__test_and_set_bit(idx, sched->state.used))
645 goto done;
646 }
647 }
Robert Richter1e2ad282011-11-18 12:35:21 +0100648 /* Grab the first unused counter starting with idx */
649 idx = sched->state.counter;
Robert Richter15c7ad52012-06-20 20:46:33 +0200650 for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) {
Robert Richter1e2ad282011-11-18 12:35:21 +0100651 if (!__test_and_set_bit(idx, sched->state.used))
Peter Zijlstra4defea82011-11-10 15:15:42 +0100652 goto done;
Robert Richter1e2ad282011-11-18 12:35:21 +0100653 }
Robert Richter1e2ad282011-11-18 12:35:21 +0100654
Peter Zijlstra4defea82011-11-10 15:15:42 +0100655 return false;
656
657done:
658 sched->state.counter = idx;
Robert Richter1e2ad282011-11-18 12:35:21 +0100659
Robert Richterbc1738f2011-11-18 12:35:22 +0100660 if (c->overlap)
661 perf_sched_save_state(sched);
662
663 return true;
664}
665
666static bool perf_sched_find_counter(struct perf_sched *sched)
667{
668 while (!__perf_sched_find_counter(sched)) {
669 if (!perf_sched_restore_state(sched))
670 return false;
671 }
672
Robert Richter1e2ad282011-11-18 12:35:21 +0100673 return true;
674}
675
676/*
677 * Go through all unassigned events and find the next one to schedule.
678 * Take events with the least weight first. Return true on success.
679 */
680static bool perf_sched_next_event(struct perf_sched *sched)
681{
682 struct event_constraint *c;
683
684 if (!sched->state.unassigned || !--sched->state.unassigned)
685 return false;
686
687 do {
688 /* next event */
689 sched->state.event++;
690 if (sched->state.event >= sched->max_events) {
691 /* next weight */
692 sched->state.event = 0;
693 sched->state.weight++;
694 if (sched->state.weight > sched->max_weight)
695 return false;
696 }
Andrew Hunter43b457802013-05-23 11:07:03 -0700697 c = sched->events[sched->state.event]->hw.constraint;
Robert Richter1e2ad282011-11-18 12:35:21 +0100698 } while (c->weight != sched->state.weight);
699
700 sched->state.counter = 0; /* start with first counter */
701
702 return true;
703}
704
705/*
706 * Assign a counter for each event.
707 */
Andrew Hunter43b457802013-05-23 11:07:03 -0700708int perf_assign_events(struct perf_event **events, int n,
Yan, Zheng4b4969b2012-06-15 14:31:30 +0800709 int wmin, int wmax, int *assign)
Robert Richter1e2ad282011-11-18 12:35:21 +0100710{
711 struct perf_sched sched;
712
Andrew Hunter43b457802013-05-23 11:07:03 -0700713 perf_sched_init(&sched, events, n, wmin, wmax);
Robert Richter1e2ad282011-11-18 12:35:21 +0100714
715 do {
716 if (!perf_sched_find_counter(&sched))
717 break; /* failed */
718 if (assign)
719 assign[sched.state.event] = sched.state.counter;
720 } while (perf_sched_next_event(&sched));
721
722 return sched.state.unassigned;
723}
724
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300725int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
Stephane Eranian1da53e02010-01-18 10:58:01 +0200726{
Andrew Hunter43b457802013-05-23 11:07:03 -0700727 struct event_constraint *c;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200728 unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
Stephane Eranian2f7f73a2013-06-20 18:42:54 +0200729 struct perf_event *e;
Robert Richter1e2ad282011-11-18 12:35:21 +0100730 int i, wmin, wmax, num = 0;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200731 struct hw_perf_event *hwc;
732
733 bitmap_zero(used_mask, X86_PMC_IDX_MAX);
734
Robert Richter1e2ad282011-11-18 12:35:21 +0100735 for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
Andrew Hunter43b457802013-05-23 11:07:03 -0700736 hwc = &cpuc->event_list[i]->hw;
Peter Zijlstrab622d642010-02-01 15:36:30 +0100737 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
Andrew Hunter43b457802013-05-23 11:07:03 -0700738 hwc->constraint = c;
739
Robert Richter1e2ad282011-11-18 12:35:21 +0100740 wmin = min(wmin, c->weight);
741 wmax = max(wmax, c->weight);
Stephane Eranian1da53e02010-01-18 10:58:01 +0200742 }
743
744 /*
Stephane Eranian81130702010-01-21 17:39:01 +0200745 * fastpath, try to reuse previous register
746 */
Peter Zijlstrac933c1a2010-01-22 16:40:12 +0100747 for (i = 0; i < n; i++) {
Stephane Eranian81130702010-01-21 17:39:01 +0200748 hwc = &cpuc->event_list[i]->hw;
Andrew Hunter43b457802013-05-23 11:07:03 -0700749 c = hwc->constraint;
Stephane Eranian81130702010-01-21 17:39:01 +0200750
751 /* never assigned */
752 if (hwc->idx == -1)
753 break;
754
755 /* constraint still honored */
Peter Zijlstra63b14642010-01-22 16:32:17 +0100756 if (!test_bit(hwc->idx, c->idxmsk))
Stephane Eranian81130702010-01-21 17:39:01 +0200757 break;
758
759 /* not already used */
760 if (test_bit(hwc->idx, used_mask))
761 break;
762
Peter Zijlstra34538ee2010-03-02 21:16:55 +0100763 __set_bit(hwc->idx, used_mask);
Stephane Eranian81130702010-01-21 17:39:01 +0200764 if (assign)
765 assign[i] = hwc->idx;
766 }
Stephane Eranian81130702010-01-21 17:39:01 +0200767
Robert Richter1e2ad282011-11-18 12:35:21 +0100768 /* slow path */
769 if (i != n)
Andrew Hunter43b457802013-05-23 11:07:03 -0700770 num = perf_assign_events(cpuc->event_list, n, wmin,
771 wmax, assign);
Stephane Eranian81130702010-01-21 17:39:01 +0200772
Stephane Eranian1da53e02010-01-18 10:58:01 +0200773 /*
Stephane Eranian2f7f73a2013-06-20 18:42:54 +0200774 * Mark the event as committed, so we do not put_constraint()
775 * in case new events are added and fail scheduling.
776 */
777 if (!num && assign) {
778 for (i = 0; i < n; i++) {
779 e = cpuc->event_list[i];
780 e->hw.flags |= PERF_X86_EVENT_COMMITTED;
781 }
782 }
783 /*
Stephane Eranian1da53e02010-01-18 10:58:01 +0200784 * scheduling failed or is just a simulation,
785 * free resources if necessary
786 */
787 if (!assign || num) {
788 for (i = 0; i < n; i++) {
Stephane Eranian2f7f73a2013-06-20 18:42:54 +0200789 e = cpuc->event_list[i];
790 /*
791 * do not put_constraint() on comitted events,
792 * because they are good to go
793 */
794 if ((e->hw.flags & PERF_X86_EVENT_COMMITTED))
795 continue;
796
Stephane Eranian1da53e02010-01-18 10:58:01 +0200797 if (x86_pmu.put_event_constraints)
Stephane Eranian2f7f73a2013-06-20 18:42:54 +0200798 x86_pmu.put_event_constraints(cpuc, e);
Stephane Eranian1da53e02010-01-18 10:58:01 +0200799 }
800 }
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100801 return num ? -EINVAL : 0;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200802}
803
804/*
805 * dogrp: true if must collect siblings events (group)
806 * returns total number of events and error code
807 */
808static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
809{
810 struct perf_event *event;
811 int n, max_count;
812
Robert Richter948b1bb2010-03-29 18:36:50 +0200813 max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200814
815 /* current number of events already accepted */
816 n = cpuc->n_events;
817
818 if (is_x86_event(leader)) {
819 if (n >= max_count)
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100820 return -EINVAL;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200821 cpuc->event_list[n] = leader;
822 n++;
823 }
824 if (!dogrp)
825 return n;
826
827 list_for_each_entry(event, &leader->sibling_list, group_entry) {
828 if (!is_x86_event(event) ||
Stephane Eranian81130702010-01-21 17:39:01 +0200829 event->state <= PERF_EVENT_STATE_OFF)
Stephane Eranian1da53e02010-01-18 10:58:01 +0200830 continue;
831
832 if (n >= max_count)
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +0100833 return -EINVAL;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200834
835 cpuc->event_list[n] = event;
836 n++;
837 }
838 return n;
839}
840
Stephane Eranian1da53e02010-01-18 10:58:01 +0200841static inline void x86_assign_hw_event(struct perf_event *event,
Stephane Eranian447a1942010-02-01 14:50:01 +0200842 struct cpu_hw_events *cpuc, int i)
Stephane Eranian1da53e02010-01-18 10:58:01 +0200843{
Stephane Eranian447a1942010-02-01 14:50:01 +0200844 struct hw_perf_event *hwc = &event->hw;
845
846 hwc->idx = cpuc->assign[i];
847 hwc->last_cpu = smp_processor_id();
848 hwc->last_tag = ++cpuc->tags[i];
Stephane Eranian1da53e02010-01-18 10:58:01 +0200849
Robert Richter15c7ad52012-06-20 20:46:33 +0200850 if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) {
Stephane Eranian1da53e02010-01-18 10:58:01 +0200851 hwc->config_base = 0;
852 hwc->event_base = 0;
Robert Richter15c7ad52012-06-20 20:46:33 +0200853 } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
Stephane Eranian1da53e02010-01-18 10:58:01 +0200854 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
Robert Richter15c7ad52012-06-20 20:46:33 +0200855 hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED);
856 hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200857 } else {
Robert Richter73d6e522011-02-02 17:40:59 +0100858 hwc->config_base = x86_pmu_config_addr(hwc->idx);
859 hwc->event_base = x86_pmu_event_addr(hwc->idx);
Jacob Shin0fbdad02013-02-06 11:26:28 -0600860 hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx);
Stephane Eranian1da53e02010-01-18 10:58:01 +0200861 }
862}
863
Stephane Eranian447a1942010-02-01 14:50:01 +0200864static inline int match_prev_assignment(struct hw_perf_event *hwc,
865 struct cpu_hw_events *cpuc,
866 int i)
867{
868 return hwc->idx == cpuc->assign[i] &&
869 hwc->last_cpu == smp_processor_id() &&
870 hwc->last_tag == cpuc->tags[i];
871}
872
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200873static void x86_pmu_start(struct perf_event *event, int flags);
Peter Zijlstra2e841872010-01-25 15:58:43 +0100874
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200875static void x86_pmu_enable(struct pmu *pmu)
Ingo Molnaree060942008-12-13 09:00:03 +0100876{
Stephane Eranian1da53e02010-01-18 10:58:01 +0200877 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
878 struct perf_event *event;
879 struct hw_perf_event *hwc;
Peter Zijlstra11164cd2010-03-26 14:08:44 +0100880 int i, added = cpuc->n_added;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200881
Robert Richter85cf9db2009-04-29 12:47:20 +0200882 if (!x86_pmu_initialized())
Ingo Molnar2b9ff0d2008-12-14 18:36:30 +0100883 return;
Peter Zijlstra1a6e21f2010-01-27 23:07:47 +0100884
885 if (cpuc->enabled)
886 return;
887
Stephane Eranian1da53e02010-01-18 10:58:01 +0200888 if (cpuc->n_added) {
Peter Zijlstra19925ce2010-03-06 13:20:40 +0100889 int n_running = cpuc->n_events - cpuc->n_added;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200890 /*
891 * apply assignment obtained either from
892 * hw_perf_group_sched_in() or x86_pmu_enable()
893 *
894 * step1: save events moving to new counters
Stephane Eranian1da53e02010-01-18 10:58:01 +0200895 */
Peter Zijlstra19925ce2010-03-06 13:20:40 +0100896 for (i = 0; i < n_running; i++) {
Stephane Eranian1da53e02010-01-18 10:58:01 +0200897 event = cpuc->event_list[i];
898 hwc = &event->hw;
899
Stephane Eranian447a1942010-02-01 14:50:01 +0200900 /*
901 * we can avoid reprogramming counter if:
902 * - assigned same counter as last time
903 * - running on same CPU as last time
904 * - no other event has used the counter since
905 */
906 if (hwc->idx == -1 ||
907 match_prev_assignment(hwc, cpuc, i))
Stephane Eranian1da53e02010-01-18 10:58:01 +0200908 continue;
909
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200910 /*
911 * Ensure we don't accidentally enable a stopped
912 * counter simply because we rescheduled.
913 */
914 if (hwc->state & PERF_HES_STOPPED)
915 hwc->state |= PERF_HES_ARCH;
916
917 x86_pmu_stop(event, PERF_EF_UPDATE);
Stephane Eranian1da53e02010-01-18 10:58:01 +0200918 }
919
Peter Zijlstrac347a2f2014-02-24 12:26:21 +0100920 /*
921 * step2: reprogram moved events into new counters
922 */
Stephane Eranian1da53e02010-01-18 10:58:01 +0200923 for (i = 0; i < cpuc->n_events; i++) {
Stephane Eranian1da53e02010-01-18 10:58:01 +0200924 event = cpuc->event_list[i];
925 hwc = &event->hw;
926
Peter Zijlstra45e16a62010-03-11 13:40:30 +0100927 if (!match_prev_assignment(hwc, cpuc, i))
Stephane Eranian447a1942010-02-01 14:50:01 +0200928 x86_assign_hw_event(event, cpuc, i);
Peter Zijlstra45e16a62010-03-11 13:40:30 +0100929 else if (i < n_running)
930 continue;
Stephane Eranian1da53e02010-01-18 10:58:01 +0200931
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +0200932 if (hwc->state & PERF_HES_ARCH)
933 continue;
934
935 x86_pmu_start(event, PERF_EF_RELOAD);
Stephane Eranian1da53e02010-01-18 10:58:01 +0200936 }
937 cpuc->n_added = 0;
938 perf_events_lapic_init();
939 }
Peter Zijlstra1a6e21f2010-01-27 23:07:47 +0100940
941 cpuc->enabled = 1;
942 barrier();
943
Peter Zijlstra11164cd2010-03-26 14:08:44 +0100944 x86_pmu.enable_all(added);
Ingo Molnaree060942008-12-13 09:00:03 +0100945}
Ingo Molnaree060942008-12-13 09:00:03 +0100946
Tejun Heo245b2e72009-06-24 15:13:48 +0900947static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
Ingo Molnar241771e2008-12-03 10:39:53 +0100948
Ingo Molnaree060942008-12-13 09:00:03 +0100949/*
950 * Set the next IRQ period, based on the hwc->period_left value.
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200951 * To be called with the event disabled in hw:
Ingo Molnaree060942008-12-13 09:00:03 +0100952 */
Kevin Winchesterde0428a2011-08-30 20:41:05 -0300953int x86_perf_event_set_period(struct perf_event *event)
Ingo Molnar241771e2008-12-03 10:39:53 +0100954{
Peter Zijlstra07088ed2010-03-02 20:16:01 +0100955 struct hw_perf_event *hwc = &event->hw;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200956 s64 left = local64_read(&hwc->period_left);
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +0200957 s64 period = hwc->sample_period;
Peter Zijlstra7645a242010-03-08 13:51:31 +0100958 int ret = 0, idx = hwc->idx;
Ingo Molnar241771e2008-12-03 10:39:53 +0100959
Robert Richter15c7ad52012-06-20 20:46:33 +0200960 if (idx == INTEL_PMC_IDX_FIXED_BTS)
Markus Metzger30dd5682009-07-21 15:56:48 +0200961 return 0;
962
Ingo Molnaree060942008-12-13 09:00:03 +0100963 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -0200964 * If we are way outside a reasonable range then just skip forward:
Ingo Molnaree060942008-12-13 09:00:03 +0100965 */
966 if (unlikely(left <= -period)) {
967 left = period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200968 local64_set(&hwc->period_left, left);
Peter Zijlstra9e350de2009-06-10 21:34:59 +0200969 hwc->last_period = period;
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +0200970 ret = 1;
Ingo Molnaree060942008-12-13 09:00:03 +0100971 }
972
973 if (unlikely(left <= 0)) {
974 left += period;
Peter Zijlstrae7850592010-05-21 14:43:08 +0200975 local64_set(&hwc->period_left, left);
Peter Zijlstra9e350de2009-06-10 21:34:59 +0200976 hwc->last_period = period;
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +0200977 ret = 1;
Ingo Molnaree060942008-12-13 09:00:03 +0100978 }
Ingo Molnar1c80f4b2009-05-15 08:25:22 +0200979 /*
Ingo Molnardfc65092009-09-21 11:31:35 +0200980 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
Ingo Molnar1c80f4b2009-05-15 08:25:22 +0200981 */
982 if (unlikely(left < 2))
983 left = 2;
Ingo Molnaree060942008-12-13 09:00:03 +0100984
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +0200985 if (left > x86_pmu.max_period)
986 left = x86_pmu.max_period;
987
Tejun Heo245b2e72009-06-24 15:13:48 +0900988 per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
Ingo Molnaree060942008-12-13 09:00:03 +0100989
990 /*
Ingo Molnarcdd6c482009-09-21 12:02:48 +0200991 * The hw event starts counting from this event offset,
Ingo Molnaree060942008-12-13 09:00:03 +0100992 * mark it to be able to extra future deltas:
993 */
Peter Zijlstrae7850592010-05-21 14:43:08 +0200994 local64_set(&hwc->prev_count, (u64)-left);
Ingo Molnaree060942008-12-13 09:00:03 +0100995
Robert Richter73d6e522011-02-02 17:40:59 +0100996 wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask);
Cyrill Gorcunov68aa00a2010-06-03 01:23:04 +0400997
998 /*
999 * Due to erratum on certan cpu we need
1000 * a second write to be sure the register
1001 * is updated properly
1002 */
1003 if (x86_pmu.perfctr_second_write) {
Robert Richter73d6e522011-02-02 17:40:59 +01001004 wrmsrl(hwc->event_base,
Robert Richter948b1bb2010-03-29 18:36:50 +02001005 (u64)(-left) & x86_pmu.cntval_mask);
Cyrill Gorcunov68aa00a2010-06-03 01:23:04 +04001006 }
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +02001007
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001008 perf_event_update_userpage(event);
Peter Zijlstra194002b2009-06-22 16:35:24 +02001009
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +02001010 return ret;
Ingo Molnar2f18d1e2008-12-22 11:10:42 +01001011}
1012
Kevin Winchesterde0428a2011-08-30 20:41:05 -03001013void x86_pmu_enable_event(struct perf_event *event)
Robert Richter7c90cc42009-04-29 12:47:18 +02001014{
Tejun Heo0a3aee02010-12-18 16:28:55 +01001015 if (__this_cpu_read(cpu_hw_events.enabled))
Robert Richter31fa58a2010-04-13 22:23:14 +02001016 __x86_pmu_enable_event(&event->hw,
1017 ARCH_PERFMON_EVENTSEL_ENABLE);
Ingo Molnar241771e2008-12-03 10:39:53 +01001018}
1019
Ingo Molnaree060942008-12-13 09:00:03 +01001020/*
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001021 * Add a single event to the PMU.
Stephane Eranian1da53e02010-01-18 10:58:01 +02001022 *
1023 * The event is added to the group of enabled events
1024 * but only if it can be scehduled with existing events.
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001025 */
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001026static int x86_pmu_add(struct perf_event *event, int flags)
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001027{
1028 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001029 struct hw_perf_event *hwc;
1030 int assign[X86_PMC_IDX_MAX];
1031 int n, n0, ret;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001032
Stephane Eranian1da53e02010-01-18 10:58:01 +02001033 hwc = &event->hw;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001034
Peter Zijlstra33696fc2010-06-14 08:49:00 +02001035 perf_pmu_disable(event->pmu);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001036 n0 = cpuc->n_events;
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001037 ret = n = collect_events(cpuc, event, false);
1038 if (ret < 0)
1039 goto out;
Ingo Molnar53b441a2009-05-25 21:41:28 +02001040
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001041 hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1042 if (!(flags & PERF_EF_START))
1043 hwc->state |= PERF_HES_ARCH;
1044
Lin Ming4d1c52b2010-04-23 13:56:12 +08001045 /*
1046 * If group events scheduling transaction was started,
Lucas De Marchi0d2eb442011-03-17 16:24:16 -03001047 * skip the schedulability test here, it will be performed
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001048 * at commit time (->commit_txn) as a whole.
Lin Ming4d1c52b2010-04-23 13:56:12 +08001049 */
Peter Zijlstra8d2cacb2010-05-25 17:49:05 +02001050 if (cpuc->group_flag & PERF_EVENT_TXN)
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001051 goto done_collect;
Lin Ming4d1c52b2010-04-23 13:56:12 +08001052
Cyrill Gorcunova0727382010-03-11 19:54:39 +03001053 ret = x86_pmu.schedule_events(cpuc, n, assign);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001054 if (ret)
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001055 goto out;
Stephane Eranian1da53e02010-01-18 10:58:01 +02001056 /*
1057 * copy new assignment, now we know it is possible
1058 * will be used by hw_perf_enable()
1059 */
1060 memcpy(cpuc->assign, assign, n*sizeof(int));
Ingo Molnar241771e2008-12-03 10:39:53 +01001061
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001062done_collect:
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001063 /*
1064 * Commit the collect_events() state. See x86_pmu_del() and
1065 * x86_pmu_*_txn().
1066 */
Stephane Eranian1da53e02010-01-18 10:58:01 +02001067 cpuc->n_events = n;
Peter Zijlstra356e1f22010-03-06 13:49:56 +01001068 cpuc->n_added += n - n0;
Stephane Eranian90151c352010-05-25 16:23:10 +02001069 cpuc->n_txn += n - n0;
Ingo Molnar7e2ae342008-12-09 11:40:46 +01001070
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001071 ret = 0;
1072out:
Peter Zijlstra33696fc2010-06-14 08:49:00 +02001073 perf_pmu_enable(event->pmu);
Peter Zijlstra24cd7f52010-06-11 17:32:03 +02001074 return ret;
Ingo Molnar241771e2008-12-03 10:39:53 +01001075}
1076
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001077static void x86_pmu_start(struct perf_event *event, int flags)
Stephane Eraniand76a0812010-02-08 17:06:01 +02001078{
Peter Zijlstrac08053e2010-03-06 13:19:24 +01001079 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1080 int idx = event->hw.idx;
1081
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001082 if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1083 return;
Stephane Eraniand76a0812010-02-08 17:06:01 +02001084
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001085 if (WARN_ON_ONCE(idx == -1))
1086 return;
1087
1088 if (flags & PERF_EF_RELOAD) {
1089 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1090 x86_perf_event_set_period(event);
1091 }
1092
1093 event->hw.state = 0;
1094
Peter Zijlstrac08053e2010-03-06 13:19:24 +01001095 cpuc->events[idx] = event;
1096 __set_bit(idx, cpuc->active_mask);
Robert Richter63e6be62010-09-15 18:20:34 +02001097 __set_bit(idx, cpuc->running);
Peter Zijlstraaff3d912010-03-02 20:32:08 +01001098 x86_pmu.enable(event);
Peter Zijlstrac08053e2010-03-06 13:19:24 +01001099 perf_event_update_userpage(event);
Peter Zijlstraa78ac322009-05-25 17:39:05 +02001100}
1101
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001102void perf_event_print_debug(void)
Ingo Molnar241771e2008-12-03 10:39:53 +01001103{
Ingo Molnar2f18d1e2008-12-22 11:10:42 +01001104 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
Peter Zijlstraca037702010-03-02 19:52:12 +01001105 u64 pebs;
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001106 struct cpu_hw_events *cpuc;
Peter Zijlstra5bb9efe2009-05-13 08:12:51 +02001107 unsigned long flags;
Ingo Molnar1e125672008-12-09 12:18:18 +01001108 int cpu, idx;
1109
Robert Richter948b1bb2010-03-29 18:36:50 +02001110 if (!x86_pmu.num_counters)
Ingo Molnar1e125672008-12-09 12:18:18 +01001111 return;
Ingo Molnar241771e2008-12-03 10:39:53 +01001112
Peter Zijlstra5bb9efe2009-05-13 08:12:51 +02001113 local_irq_save(flags);
Ingo Molnar241771e2008-12-03 10:39:53 +01001114
1115 cpu = smp_processor_id();
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001116 cpuc = &per_cpu(cpu_hw_events, cpu);
Ingo Molnar241771e2008-12-03 10:39:53 +01001117
Robert Richterfaa28ae2009-04-29 12:47:13 +02001118 if (x86_pmu.version >= 2) {
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301119 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1120 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1121 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1122 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
Peter Zijlstraca037702010-03-02 19:52:12 +01001123 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
Ingo Molnar241771e2008-12-03 10:39:53 +01001124
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301125 pr_info("\n");
1126 pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl);
1127 pr_info("CPU#%d: status: %016llx\n", cpu, status);
1128 pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow);
1129 pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed);
Peter Zijlstraca037702010-03-02 19:52:12 +01001130 pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs);
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +05301131 }
Peter Zijlstra7645a242010-03-08 13:51:31 +01001132 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask);
Ingo Molnar241771e2008-12-03 10:39:53 +01001133
Robert Richter948b1bb2010-03-29 18:36:50 +02001134 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
Robert Richter41bf4982011-02-02 17:40:57 +01001135 rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
1136 rdmsrl(x86_pmu_event_addr(idx), pmc_count);
Ingo Molnar241771e2008-12-03 10:39:53 +01001137
Tejun Heo245b2e72009-06-24 15:13:48 +09001138 prev_left = per_cpu(pmc_prev_left[idx], cpu);
Ingo Molnar241771e2008-12-03 10:39:53 +01001139
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301140 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
Ingo Molnar241771e2008-12-03 10:39:53 +01001141 cpu, idx, pmc_ctrl);
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301142 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
Ingo Molnar241771e2008-12-03 10:39:53 +01001143 cpu, idx, pmc_count);
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301144 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
Ingo Molnaree060942008-12-13 09:00:03 +01001145 cpu, idx, prev_left);
Ingo Molnar241771e2008-12-03 10:39:53 +01001146 }
Robert Richter948b1bb2010-03-29 18:36:50 +02001147 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
Ingo Molnar2f18d1e2008-12-22 11:10:42 +01001148 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1149
Jaswinder Singh Rajputa1ef58f2009-02-28 18:45:39 +05301150 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
Ingo Molnar2f18d1e2008-12-22 11:10:42 +01001151 cpu, idx, pmc_count);
1152 }
Peter Zijlstra5bb9efe2009-05-13 08:12:51 +02001153 local_irq_restore(flags);
Ingo Molnar241771e2008-12-03 10:39:53 +01001154}
1155
Kevin Winchesterde0428a2011-08-30 20:41:05 -03001156void x86_pmu_stop(struct perf_event *event, int flags)
Ingo Molnar241771e2008-12-03 10:39:53 +01001157{
Stephane Eraniand76a0812010-02-08 17:06:01 +02001158 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001159 struct hw_perf_event *hwc = &event->hw;
Ingo Molnar241771e2008-12-03 10:39:53 +01001160
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001161 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1162 x86_pmu.disable(event);
1163 cpuc->events[hwc->idx] = NULL;
1164 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1165 hwc->state |= PERF_HES_STOPPED;
1166 }
Peter Zijlstra71e2d282010-03-08 17:51:33 +01001167
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001168 if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1169 /*
1170 * Drain the remaining delta count out of a event
1171 * that we are disabling:
1172 */
1173 x86_perf_event_update(event);
1174 hwc->state |= PERF_HES_UPTODATE;
1175 }
Peter Zijlstra2e841872010-01-25 15:58:43 +01001176}
1177
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001178static void x86_pmu_del(struct perf_event *event, int flags)
Peter Zijlstra2e841872010-01-25 15:58:43 +01001179{
1180 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1181 int i;
1182
Stephane Eranian90151c352010-05-25 16:23:10 +02001183 /*
Stephane Eranian2f7f73a2013-06-20 18:42:54 +02001184 * event is descheduled
1185 */
1186 event->hw.flags &= ~PERF_X86_EVENT_COMMITTED;
1187
1188 /*
Stephane Eranian90151c352010-05-25 16:23:10 +02001189 * If we're called during a txn, we don't need to do anything.
1190 * The events never got scheduled and ->cancel_txn will truncate
1191 * the event_list.
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001192 *
1193 * XXX assumes any ->del() called during a TXN will only be on
1194 * an event added during that same TXN.
Stephane Eranian90151c352010-05-25 16:23:10 +02001195 */
Peter Zijlstra8d2cacb2010-05-25 17:49:05 +02001196 if (cpuc->group_flag & PERF_EVENT_TXN)
Stephane Eranian90151c352010-05-25 16:23:10 +02001197 return;
1198
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001199 /*
1200 * Not a TXN, therefore cleanup properly.
1201 */
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001202 x86_pmu_stop(event, PERF_EF_UPDATE);
Peter Zijlstra194002b2009-06-22 16:35:24 +02001203
Stephane Eranian1da53e02010-01-18 10:58:01 +02001204 for (i = 0; i < cpuc->n_events; i++) {
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001205 if (event == cpuc->event_list[i])
Peter Zijlstra6c9687a2010-01-25 11:57:25 +01001206 break;
Stephane Eranian1da53e02010-01-18 10:58:01 +02001207 }
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001208
1209 if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */
1210 return;
1211
1212 /* If we have a newly added event; make sure to decrease n_added. */
1213 if (i >= cpuc->n_events - cpuc->n_added)
1214 --cpuc->n_added;
1215
1216 if (x86_pmu.put_event_constraints)
1217 x86_pmu.put_event_constraints(cpuc, event);
1218
1219 /* Delete the array entry. */
1220 while (++i < cpuc->n_events)
1221 cpuc->event_list[i-1] = cpuc->event_list[i];
1222 --cpuc->n_events;
1223
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001224 perf_event_update_userpage(event);
Ingo Molnar241771e2008-12-03 10:39:53 +01001225}
1226
Kevin Winchesterde0428a2011-08-30 20:41:05 -03001227int x86_pmu_handle_irq(struct pt_regs *regs)
Robert Richtera29aa8a2009-04-29 12:47:21 +02001228{
Peter Zijlstradf1a1322009-06-10 21:02:22 +02001229 struct perf_sample_data data;
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001230 struct cpu_hw_events *cpuc;
1231 struct perf_event *event;
Vince Weaver11d15782009-07-08 17:46:14 -04001232 int idx, handled = 0;
Ingo Molnar9029a5e2009-05-15 08:26:20 +02001233 u64 val;
1234
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001235 cpuc = &__get_cpu_var(cpu_hw_events);
Robert Richtera29aa8a2009-04-29 12:47:21 +02001236
Don Zickus2bce5da2011-04-27 06:32:33 -04001237 /*
1238 * Some chipsets need to unmask the LVTPC in a particular spot
1239 * inside the nmi handler. As a result, the unmasking was pushed
1240 * into all the nmi handlers.
1241 *
1242 * This generic handler doesn't seem to have any issues where the
1243 * unmasking occurs so it was left at the top.
1244 */
1245 apic_write(APIC_LVTPC, APIC_DM_NMI);
1246
Robert Richter948b1bb2010-03-29 18:36:50 +02001247 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
Robert Richter63e6be62010-09-15 18:20:34 +02001248 if (!test_bit(idx, cpuc->active_mask)) {
1249 /*
1250 * Though we deactivated the counter some cpus
1251 * might still deliver spurious interrupts still
1252 * in flight. Catch them:
1253 */
1254 if (__test_and_clear_bit(idx, cpuc->running))
1255 handled++;
Robert Richtera29aa8a2009-04-29 12:47:21 +02001256 continue;
Robert Richter63e6be62010-09-15 18:20:34 +02001257 }
Peter Zijlstra962bf7a2009-05-13 13:21:36 +02001258
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001259 event = cpuc->events[idx];
Peter Zijlstraa4016a72009-05-14 14:52:17 +02001260
Peter Zijlstracc2ad4b2010-03-02 20:18:39 +01001261 val = x86_perf_event_update(event);
Robert Richter948b1bb2010-03-29 18:36:50 +02001262 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
Peter Zijlstra48e22d52009-05-25 17:39:04 +02001263 continue;
Peter Zijlstra962bf7a2009-05-13 13:21:36 +02001264
Peter Zijlstra9e350de2009-06-10 21:34:59 +02001265 /*
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001266 * event overflow
Peter Zijlstra9e350de2009-06-10 21:34:59 +02001267 */
Robert Richter4177c422010-09-02 15:07:48 -04001268 handled++;
Robert Richterfd0d0002012-04-02 20:19:08 +02001269 perf_sample_data_init(&data, 0, event->hw.last_period);
Peter Zijlstra9e350de2009-06-10 21:34:59 +02001270
Peter Zijlstra07088ed2010-03-02 20:16:01 +01001271 if (!x86_perf_event_set_period(event))
Peter Zijlstrae4abb5d2009-06-02 16:08:20 +02001272 continue;
1273
Peter Zijlstraa8b0ca12011-06-27 14:41:57 +02001274 if (perf_event_overflow(event, &data, regs))
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001275 x86_pmu_stop(event, 0);
Robert Richtera29aa8a2009-04-29 12:47:21 +02001276 }
Peter Zijlstra962bf7a2009-05-13 13:21:36 +02001277
Peter Zijlstra9e350de2009-06-10 21:34:59 +02001278 if (handled)
1279 inc_irq_stat(apic_perf_irqs);
1280
Robert Richtera29aa8a2009-04-29 12:47:21 +02001281 return handled;
1282}
Robert Richter39d81ea2009-04-29 12:47:05 +02001283
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001284void perf_events_lapic_init(void)
Ingo Molnar241771e2008-12-03 10:39:53 +01001285{
Ingo Molnar04da8a42009-08-11 10:40:08 +02001286 if (!x86_pmu.apic || !x86_pmu_initialized())
Ingo Molnar241771e2008-12-03 10:39:53 +01001287 return;
Robert Richter85cf9db2009-04-29 12:47:20 +02001288
Ingo Molnar241771e2008-12-03 10:39:53 +01001289 /*
Yong Wangc323d952009-05-29 13:28:35 +08001290 * Always use NMI for PMU
Ingo Molnar241771e2008-12-03 10:39:53 +01001291 */
Yong Wangc323d952009-05-29 13:28:35 +08001292 apic_write(APIC_LVTPC, APIC_DM_NMI);
Ingo Molnar241771e2008-12-03 10:39:53 +01001293}
1294
1295static int __kprobes
Don Zickus9c48f1c2011-09-30 15:06:21 -04001296perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs)
Ingo Molnar241771e2008-12-03 10:39:53 +01001297{
Dave Hansen14c63f12013-06-21 08:51:36 -07001298 u64 start_clock;
1299 u64 finish_clock;
Peter Zijlstrae8a923c2013-10-17 15:32:10 +02001300 int ret;
Dave Hansen14c63f12013-06-21 08:51:36 -07001301
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001302 if (!atomic_read(&active_events))
Don Zickus9c48f1c2011-09-30 15:06:21 -04001303 return NMI_DONE;
Peter Zijlstra63a809a2009-05-01 12:23:17 +02001304
Peter Zijlstrae8a923c2013-10-17 15:32:10 +02001305 start_clock = sched_clock();
Dave Hansen14c63f12013-06-21 08:51:36 -07001306 ret = x86_pmu.handle_irq(regs);
Peter Zijlstrae8a923c2013-10-17 15:32:10 +02001307 finish_clock = sched_clock();
Dave Hansen14c63f12013-06-21 08:51:36 -07001308
1309 perf_sample_event_took(finish_clock - start_clock);
1310
1311 return ret;
Ingo Molnar241771e2008-12-03 10:39:53 +01001312}
1313
Kevin Winchesterde0428a2011-08-30 20:41:05 -03001314struct event_constraint emptyconstraint;
1315struct event_constraint unconstrained;
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +05301316
Paul Gortmaker148f9bb2013-06-18 18:23:59 -04001317static int
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001318x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1319{
1320 unsigned int cpu = (long)hcpu;
Peter Zijlstra7fdba1c2011-07-22 13:41:54 +02001321 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
Peter Zijlstrab38b24e2010-03-23 19:31:15 +01001322 int ret = NOTIFY_OK;
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001323
1324 switch (action & ~CPU_TASKS_FROZEN) {
1325 case CPU_UP_PREPARE:
Peter Zijlstra7fdba1c2011-07-22 13:41:54 +02001326 cpuc->kfree_on_online = NULL;
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001327 if (x86_pmu.cpu_prepare)
Peter Zijlstrab38b24e2010-03-23 19:31:15 +01001328 ret = x86_pmu.cpu_prepare(cpu);
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001329 break;
1330
1331 case CPU_STARTING:
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001332 if (x86_pmu.attr_rdpmc)
1333 set_in_cr4(X86_CR4_PCE);
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001334 if (x86_pmu.cpu_starting)
1335 x86_pmu.cpu_starting(cpu);
1336 break;
1337
Peter Zijlstra7fdba1c2011-07-22 13:41:54 +02001338 case CPU_ONLINE:
1339 kfree(cpuc->kfree_on_online);
1340 break;
1341
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001342 case CPU_DYING:
1343 if (x86_pmu.cpu_dying)
1344 x86_pmu.cpu_dying(cpu);
1345 break;
1346
Peter Zijlstrab38b24e2010-03-23 19:31:15 +01001347 case CPU_UP_CANCELED:
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001348 case CPU_DEAD:
1349 if (x86_pmu.cpu_dead)
1350 x86_pmu.cpu_dead(cpu);
1351 break;
1352
1353 default:
1354 break;
1355 }
1356
Peter Zijlstrab38b24e2010-03-23 19:31:15 +01001357 return ret;
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001358}
1359
Cyrill Gorcunov12558032009-12-10 19:56:34 +03001360static void __init pmu_check_apic(void)
1361{
1362 if (cpu_has_apic)
1363 return;
1364
1365 x86_pmu.apic = 0;
1366 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1367 pr_info("no hardware sampling interrupt available.\n");
1368}
1369
Jiri Olsa641cc932012-03-15 20:09:14 +01001370static struct attribute_group x86_pmu_format_group = {
1371 .name = "format",
1372 .attrs = NULL,
1373};
1374
Jiri Olsa8300daa2012-10-10 14:53:12 +02001375/*
1376 * Remove all undefined events (x86_pmu.event_map(id) == 0)
1377 * out of events_attr attributes.
1378 */
1379static void __init filter_events(struct attribute **attrs)
1380{
Stephane Eranian3a54aaa2013-01-24 16:10:26 +01001381 struct device_attribute *d;
1382 struct perf_pmu_events_attr *pmu_attr;
Jiri Olsa8300daa2012-10-10 14:53:12 +02001383 int i, j;
1384
1385 for (i = 0; attrs[i]; i++) {
Stephane Eranian3a54aaa2013-01-24 16:10:26 +01001386 d = (struct device_attribute *)attrs[i];
1387 pmu_attr = container_of(d, struct perf_pmu_events_attr, attr);
1388 /* str trumps id */
1389 if (pmu_attr->event_str)
1390 continue;
Jiri Olsa8300daa2012-10-10 14:53:12 +02001391 if (x86_pmu.event_map(i))
1392 continue;
1393
1394 for (j = i; attrs[j]; j++)
1395 attrs[j] = attrs[j + 1];
1396
1397 /* Check the shifted attr. */
1398 i--;
1399 }
1400}
1401
Andi Kleen1a6461b2013-01-24 16:10:25 +01001402/* Merge two pointer arrays */
1403static __init struct attribute **merge_attr(struct attribute **a, struct attribute **b)
1404{
1405 struct attribute **new;
1406 int j, i;
1407
1408 for (j = 0; a[j]; j++)
1409 ;
1410 for (i = 0; b[i]; i++)
1411 j++;
1412 j++;
1413
1414 new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
1415 if (!new)
1416 return NULL;
1417
1418 j = 0;
1419 for (i = 0; a[i]; i++)
1420 new[j++] = a[i];
1421 for (i = 0; b[i]; i++)
1422 new[j++] = b[i];
1423 new[j] = NULL;
1424
1425 return new;
1426}
1427
Stephane Eranianf20093e2013-01-24 16:10:32 +01001428ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
Jiri Olsaa4747392012-10-10 14:53:11 +02001429 char *page)
1430{
1431 struct perf_pmu_events_attr *pmu_attr = \
1432 container_of(attr, struct perf_pmu_events_attr, attr);
Jiri Olsaa4747392012-10-10 14:53:11 +02001433 u64 config = x86_pmu.event_map(pmu_attr->id);
Stephane Eranian3a54aaa2013-01-24 16:10:26 +01001434
1435 /* string trumps id */
1436 if (pmu_attr->event_str)
1437 return sprintf(page, "%s", pmu_attr->event_str);
1438
Jiri Olsaa4747392012-10-10 14:53:11 +02001439 return x86_pmu.events_sysfs_show(page, config);
1440}
1441
Jiri Olsaa4747392012-10-10 14:53:11 +02001442EVENT_ATTR(cpu-cycles, CPU_CYCLES );
1443EVENT_ATTR(instructions, INSTRUCTIONS );
1444EVENT_ATTR(cache-references, CACHE_REFERENCES );
1445EVENT_ATTR(cache-misses, CACHE_MISSES );
1446EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS );
1447EVENT_ATTR(branch-misses, BRANCH_MISSES );
1448EVENT_ATTR(bus-cycles, BUS_CYCLES );
1449EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND );
1450EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND );
1451EVENT_ATTR(ref-cycles, REF_CPU_CYCLES );
1452
1453static struct attribute *empty_attrs;
1454
Peter Huewe95d18aa2012-10-29 21:48:17 +01001455static struct attribute *events_attr[] = {
Jiri Olsaa4747392012-10-10 14:53:11 +02001456 EVENT_PTR(CPU_CYCLES),
1457 EVENT_PTR(INSTRUCTIONS),
1458 EVENT_PTR(CACHE_REFERENCES),
1459 EVENT_PTR(CACHE_MISSES),
1460 EVENT_PTR(BRANCH_INSTRUCTIONS),
1461 EVENT_PTR(BRANCH_MISSES),
1462 EVENT_PTR(BUS_CYCLES),
1463 EVENT_PTR(STALLED_CYCLES_FRONTEND),
1464 EVENT_PTR(STALLED_CYCLES_BACKEND),
1465 EVENT_PTR(REF_CPU_CYCLES),
1466 NULL,
1467};
1468
1469static struct attribute_group x86_pmu_events_group = {
1470 .name = "events",
1471 .attrs = events_attr,
1472};
1473
Jiri Olsa0bf79d42012-10-10 14:53:14 +02001474ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
Jiri Olsa43c032f2012-10-10 14:53:13 +02001475{
Jiri Olsa43c032f2012-10-10 14:53:13 +02001476 u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8;
1477 u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24;
1478 bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE);
1479 bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL);
1480 bool any = (config & ARCH_PERFMON_EVENTSEL_ANY);
1481 bool inv = (config & ARCH_PERFMON_EVENTSEL_INV);
1482 ssize_t ret;
1483
1484 /*
1485 * We have whole page size to spend and just little data
1486 * to write, so we can safely use sprintf.
1487 */
1488 ret = sprintf(page, "event=0x%02llx", event);
1489
1490 if (umask)
1491 ret += sprintf(page + ret, ",umask=0x%02llx", umask);
1492
1493 if (edge)
1494 ret += sprintf(page + ret, ",edge");
1495
1496 if (pc)
1497 ret += sprintf(page + ret, ",pc");
1498
1499 if (any)
1500 ret += sprintf(page + ret, ",any");
1501
1502 if (inv)
1503 ret += sprintf(page + ret, ",inv");
1504
1505 if (cmask)
1506 ret += sprintf(page + ret, ",cmask=0x%02llx", cmask);
1507
1508 ret += sprintf(page + ret, "\n");
1509
1510 return ret;
1511}
1512
Yinghai Ludda99112011-01-21 15:30:01 -08001513static int __init init_hw_perf_events(void)
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +05301514{
Peter Zijlstrac1d6f422011-12-06 14:07:15 +01001515 struct x86_pmu_quirk *quirk;
Robert Richter72eae042009-04-29 12:47:10 +02001516 int err;
1517
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001518 pr_info("Performance Events: ");
Ingo Molnar1123e3a2009-05-29 11:25:09 +02001519
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +05301520 switch (boot_cpu_data.x86_vendor) {
1521 case X86_VENDOR_INTEL:
Robert Richter72eae042009-04-29 12:47:10 +02001522 err = intel_pmu_init();
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +05301523 break;
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +05301524 case X86_VENDOR_AMD:
Robert Richter72eae042009-04-29 12:47:10 +02001525 err = amd_pmu_init();
Jaswinder Singh Rajputf87ad352009-02-27 20:15:14 +05301526 break;
Robert Richter41389602009-04-29 12:47:00 +02001527 default:
Ingo Molnar8a3da6c72013-09-28 15:48:48 +02001528 err = -ENOTSUPP;
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +05301529 }
Ingo Molnar1123e3a2009-05-29 11:25:09 +02001530 if (err != 0) {
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001531 pr_cont("no PMU driver, software events only.\n");
Peter Zijlstra004417a2010-11-25 18:38:29 +01001532 return 0;
Ingo Molnar1123e3a2009-05-29 11:25:09 +02001533 }
Jaswinder Singh Rajputb56a3802009-02-27 18:09:09 +05301534
Cyrill Gorcunov12558032009-12-10 19:56:34 +03001535 pmu_check_apic();
1536
Don Zickus33c6d6a2010-11-22 16:55:23 -05001537 /* sanity check that the hardware exists or is emulated */
Peter Zijlstra44072042010-12-08 15:56:23 +01001538 if (!check_hw_exists())
Peter Zijlstra004417a2010-11-25 18:38:29 +01001539 return 0;
Don Zickus33c6d6a2010-11-22 16:55:23 -05001540
Ingo Molnar1123e3a2009-05-29 11:25:09 +02001541 pr_cont("%s PMU driver.\n", x86_pmu.name);
Robert Richterfaa28ae2009-04-29 12:47:13 +02001542
Peter Zijlstrae97df762014-02-05 20:48:51 +01001543 x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */
1544
Peter Zijlstrac1d6f422011-12-06 14:07:15 +01001545 for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next)
1546 quirk->func();
Peter Zijlstra3c447802010-03-04 21:49:01 +01001547
Robert Richtera1eac7a2012-06-20 20:46:34 +02001548 if (!x86_pmu.intel_ctrl)
1549 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
Ingo Molnar862a1a52008-12-17 13:09:20 +01001550
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001551 perf_events_lapic_init();
Don Zickus9c48f1c2011-09-30 15:06:21 -04001552 register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI");
Ingo Molnar1123e3a2009-05-29 11:25:09 +02001553
Peter Zijlstra63b14642010-01-22 16:32:17 +01001554 unconstrained = (struct event_constraint)
Robert Richter948b1bb2010-03-29 18:36:50 +02001555 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
Stephane Eranian9fac2cf2013-01-24 16:10:27 +01001556 0, x86_pmu.num_counters, 0, 0);
Peter Zijlstra63b14642010-01-22 16:32:17 +01001557
Jiri Olsa641cc932012-03-15 20:09:14 +01001558 x86_pmu_format_group.attrs = x86_pmu.format_attrs;
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001559
Stephane Eranianf20093e2013-01-24 16:10:32 +01001560 if (x86_pmu.event_attrs)
1561 x86_pmu_events_group.attrs = x86_pmu.event_attrs;
1562
Jiri Olsaa4747392012-10-10 14:53:11 +02001563 if (!x86_pmu.events_sysfs_show)
1564 x86_pmu_events_group.attrs = &empty_attrs;
Jiri Olsa8300daa2012-10-10 14:53:12 +02001565 else
1566 filter_events(x86_pmu_events_group.attrs);
Jiri Olsaa4747392012-10-10 14:53:11 +02001567
Andi Kleen1a6461b2013-01-24 16:10:25 +01001568 if (x86_pmu.cpu_events) {
1569 struct attribute **tmp;
1570
1571 tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events);
1572 if (!WARN_ON(!tmp))
1573 x86_pmu_events_group.attrs = tmp;
1574 }
1575
Ingo Molnar57c0c152009-09-21 12:20:38 +02001576 pr_info("... version: %d\n", x86_pmu.version);
Robert Richter948b1bb2010-03-29 18:36:50 +02001577 pr_info("... bit width: %d\n", x86_pmu.cntval_bits);
1578 pr_info("... generic registers: %d\n", x86_pmu.num_counters);
1579 pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask);
Ingo Molnar57c0c152009-09-21 12:20:38 +02001580 pr_info("... max period: %016Lx\n", x86_pmu.max_period);
Robert Richter948b1bb2010-03-29 18:36:50 +02001581 pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed);
Robert Richterd6dc0b42010-03-17 12:49:13 +01001582 pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl);
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001583
Peter Zijlstra2e80a822010-11-17 23:17:36 +01001584 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
Peter Zijlstra3f6da392010-03-05 13:01:18 +01001585 perf_cpu_notifier(x86_pmu_notifier);
Peter Zijlstra004417a2010-11-25 18:38:29 +01001586
1587 return 0;
Ingo Molnar241771e2008-12-03 10:39:53 +01001588}
Peter Zijlstra004417a2010-11-25 18:38:29 +01001589early_initcall(init_hw_perf_events);
Ingo Molnar621a01e2008-12-11 12:46:46 +01001590
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001591static inline void x86_pmu_read(struct perf_event *event)
Ingo Molnaree060942008-12-13 09:00:03 +01001592{
Peter Zijlstracc2ad4b2010-03-02 20:18:39 +01001593 x86_perf_event_update(event);
Ingo Molnaree060942008-12-13 09:00:03 +01001594}
1595
Lin Ming4d1c52b2010-04-23 13:56:12 +08001596/*
1597 * Start group events scheduling transaction
1598 * Set the flag to make pmu::enable() not perform the
1599 * schedulability test, it will be performed at commit time
1600 */
Peter Zijlstra51b0fe32010-06-11 13:35:57 +02001601static void x86_pmu_start_txn(struct pmu *pmu)
Lin Ming4d1c52b2010-04-23 13:56:12 +08001602{
Peter Zijlstra33696fc2010-06-14 08:49:00 +02001603 perf_pmu_disable(pmu);
Tejun Heo0a3aee02010-12-18 16:28:55 +01001604 __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1605 __this_cpu_write(cpu_hw_events.n_txn, 0);
Lin Ming4d1c52b2010-04-23 13:56:12 +08001606}
1607
1608/*
1609 * Stop group events scheduling transaction
1610 * Clear the flag and pmu::enable() will perform the
1611 * schedulability test.
1612 */
Peter Zijlstra51b0fe32010-06-11 13:35:57 +02001613static void x86_pmu_cancel_txn(struct pmu *pmu)
Lin Ming4d1c52b2010-04-23 13:56:12 +08001614{
Tejun Heo0a3aee02010-12-18 16:28:55 +01001615 __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
Stephane Eranian90151c352010-05-25 16:23:10 +02001616 /*
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001617 * Truncate collected array by the number of events added in this
1618 * transaction. See x86_pmu_add() and x86_pmu_*_txn().
Stephane Eranian90151c352010-05-25 16:23:10 +02001619 */
Tejun Heo0a3aee02010-12-18 16:28:55 +01001620 __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1621 __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
Peter Zijlstra33696fc2010-06-14 08:49:00 +02001622 perf_pmu_enable(pmu);
Lin Ming4d1c52b2010-04-23 13:56:12 +08001623}
1624
1625/*
1626 * Commit group events scheduling transaction
1627 * Perform the group schedulability test as a whole
1628 * Return 0 if success
Peter Zijlstrac347a2f2014-02-24 12:26:21 +01001629 *
1630 * Does not cancel the transaction on failure; expects the caller to do this.
Lin Ming4d1c52b2010-04-23 13:56:12 +08001631 */
Peter Zijlstra51b0fe32010-06-11 13:35:57 +02001632static int x86_pmu_commit_txn(struct pmu *pmu)
Lin Ming4d1c52b2010-04-23 13:56:12 +08001633{
1634 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1635 int assign[X86_PMC_IDX_MAX];
1636 int n, ret;
1637
1638 n = cpuc->n_events;
1639
1640 if (!x86_pmu_initialized())
1641 return -EAGAIN;
1642
1643 ret = x86_pmu.schedule_events(cpuc, n, assign);
1644 if (ret)
1645 return ret;
1646
1647 /*
1648 * copy new assignment, now we know it is possible
1649 * will be used by hw_perf_enable()
1650 */
1651 memcpy(cpuc->assign, assign, n*sizeof(int));
1652
Peter Zijlstra8d2cacb2010-05-25 17:49:05 +02001653 cpuc->group_flag &= ~PERF_EVENT_TXN;
Peter Zijlstra33696fc2010-06-14 08:49:00 +02001654 perf_pmu_enable(pmu);
Lin Ming4d1c52b2010-04-23 13:56:12 +08001655 return 0;
1656}
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001657/*
1658 * a fake_cpuc is used to validate event groups. Due to
1659 * the extra reg logic, we need to also allocate a fake
1660 * per_core and per_cpu structure. Otherwise, group events
1661 * using extra reg may conflict without the kernel being
1662 * able to catch this when the last event gets added to
1663 * the group.
1664 */
1665static void free_fake_cpuc(struct cpu_hw_events *cpuc)
1666{
1667 kfree(cpuc->shared_regs);
1668 kfree(cpuc);
1669}
1670
1671static struct cpu_hw_events *allocate_fake_cpuc(void)
1672{
1673 struct cpu_hw_events *cpuc;
1674 int cpu = raw_smp_processor_id();
1675
1676 cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL);
1677 if (!cpuc)
1678 return ERR_PTR(-ENOMEM);
1679
1680 /* only needed, if we have extra_regs */
1681 if (x86_pmu.extra_regs) {
1682 cpuc->shared_regs = allocate_shared_regs(cpu);
1683 if (!cpuc->shared_regs)
1684 goto error;
1685 }
Peter Zijlstrab430f7c2012-06-05 15:30:31 +02001686 cpuc->is_fake = 1;
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001687 return cpuc;
1688error:
1689 free_fake_cpuc(cpuc);
1690 return ERR_PTR(-ENOMEM);
1691}
Lin Ming4d1c52b2010-04-23 13:56:12 +08001692
Stephane Eranian1da53e02010-01-18 10:58:01 +02001693/*
Peter Zijlstraca037702010-03-02 19:52:12 +01001694 * validate that we can schedule this event
1695 */
1696static int validate_event(struct perf_event *event)
1697{
1698 struct cpu_hw_events *fake_cpuc;
1699 struct event_constraint *c;
1700 int ret = 0;
1701
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001702 fake_cpuc = allocate_fake_cpuc();
1703 if (IS_ERR(fake_cpuc))
1704 return PTR_ERR(fake_cpuc);
Peter Zijlstraca037702010-03-02 19:52:12 +01001705
1706 c = x86_pmu.get_event_constraints(fake_cpuc, event);
1707
1708 if (!c || !c->weight)
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +01001709 ret = -EINVAL;
Peter Zijlstraca037702010-03-02 19:52:12 +01001710
1711 if (x86_pmu.put_event_constraints)
1712 x86_pmu.put_event_constraints(fake_cpuc, event);
1713
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001714 free_fake_cpuc(fake_cpuc);
Peter Zijlstraca037702010-03-02 19:52:12 +01001715
1716 return ret;
1717}
1718
1719/*
Stephane Eranian1da53e02010-01-18 10:58:01 +02001720 * validate a single event group
1721 *
1722 * validation include:
Ingo Molnar184f4122010-01-27 08:39:39 +01001723 * - check events are compatible which each other
1724 * - events do not compete for the same counter
1725 * - number of events <= number of counters
Stephane Eranian1da53e02010-01-18 10:58:01 +02001726 *
1727 * validation ensures the group can be loaded onto the
1728 * PMU if it was the only group available.
1729 */
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001730static int validate_group(struct perf_event *event)
1731{
Stephane Eranian1da53e02010-01-18 10:58:01 +02001732 struct perf_event *leader = event->group_leader;
Peter Zijlstra502568d2010-01-22 14:35:46 +01001733 struct cpu_hw_events *fake_cpuc;
Peter Zijlstraaa2bc1a2011-11-09 17:56:37 +01001734 int ret = -EINVAL, n;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001735
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001736 fake_cpuc = allocate_fake_cpuc();
1737 if (IS_ERR(fake_cpuc))
1738 return PTR_ERR(fake_cpuc);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001739 /*
1740 * the event is not yet connected with its
1741 * siblings therefore we must first collect
1742 * existing siblings, then add the new event
1743 * before we can simulate the scheduling
1744 */
Peter Zijlstra502568d2010-01-22 14:35:46 +01001745 n = collect_events(fake_cpuc, leader, true);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001746 if (n < 0)
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001747 goto out;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001748
Peter Zijlstra502568d2010-01-22 14:35:46 +01001749 fake_cpuc->n_events = n;
1750 n = collect_events(fake_cpuc, event, false);
Stephane Eranian1da53e02010-01-18 10:58:01 +02001751 if (n < 0)
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001752 goto out;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001753
Peter Zijlstra502568d2010-01-22 14:35:46 +01001754 fake_cpuc->n_events = n;
Stephane Eranian1da53e02010-01-18 10:58:01 +02001755
Cyrill Gorcunova0727382010-03-11 19:54:39 +03001756 ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
Peter Zijlstra502568d2010-01-22 14:35:46 +01001757
Peter Zijlstra502568d2010-01-22 14:35:46 +01001758out:
Stephane Eraniancd8a38d2011-06-06 16:57:08 +02001759 free_fake_cpuc(fake_cpuc);
Peter Zijlstra502568d2010-01-22 14:35:46 +01001760 return ret;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001761}
1762
Yinghai Ludda99112011-01-21 15:30:01 -08001763static int x86_pmu_event_init(struct perf_event *event)
Ingo Molnar621a01e2008-12-11 12:46:46 +01001764{
Peter Zijlstra51b0fe32010-06-11 13:35:57 +02001765 struct pmu *tmp;
Ingo Molnar621a01e2008-12-11 12:46:46 +01001766 int err;
1767
Peter Zijlstrab0a873e2010-06-11 13:35:08 +02001768 switch (event->attr.type) {
1769 case PERF_TYPE_RAW:
1770 case PERF_TYPE_HARDWARE:
1771 case PERF_TYPE_HW_CACHE:
1772 break;
1773
1774 default:
1775 return -ENOENT;
1776 }
1777
1778 err = __x86_pmu_event_init(event);
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001779 if (!err) {
Stephane Eranian81130702010-01-21 17:39:01 +02001780 /*
1781 * we temporarily connect event to its pmu
1782 * such that validate_group() can classify
1783 * it as an x86 event using is_x86_event()
1784 */
1785 tmp = event->pmu;
1786 event->pmu = &pmu;
1787
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001788 if (event->group_leader != event)
1789 err = validate_group(event);
Peter Zijlstraca037702010-03-02 19:52:12 +01001790 else
1791 err = validate_event(event);
Stephane Eranian81130702010-01-21 17:39:01 +02001792
1793 event->pmu = tmp;
Peter Zijlstrafe9081c2009-10-08 11:56:07 +02001794 }
Peter Zijlstraa1792cdac2009-09-09 10:04:47 +02001795 if (err) {
Ingo Molnarcdd6c482009-09-21 12:02:48 +02001796 if (event->destroy)
1797 event->destroy(event);
Peter Zijlstraa1792cdac2009-09-09 10:04:47 +02001798 }
Ingo Molnar621a01e2008-12-11 12:46:46 +01001799
Peter Zijlstrab0a873e2010-06-11 13:35:08 +02001800 return err;
Ingo Molnar621a01e2008-12-11 12:46:46 +01001801}
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001802
Peter Zijlstrafe4a3302011-11-20 20:44:06 +01001803static int x86_pmu_event_idx(struct perf_event *event)
1804{
1805 int idx = event->hw.idx;
1806
Peter Zijlstrac7206202012-03-22 17:26:36 +01001807 if (!x86_pmu.attr_rdpmc)
1808 return 0;
1809
Robert Richter15c7ad52012-06-20 20:46:33 +02001810 if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) {
1811 idx -= INTEL_PMC_IDX_FIXED;
Peter Zijlstrafe4a3302011-11-20 20:44:06 +01001812 idx |= 1 << 30;
1813 }
1814
1815 return idx + 1;
1816}
1817
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001818static ssize_t get_attr_rdpmc(struct device *cdev,
1819 struct device_attribute *attr,
1820 char *buf)
1821{
1822 return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc);
1823}
1824
1825static void change_rdpmc(void *info)
1826{
1827 bool enable = !!(unsigned long)info;
1828
1829 if (enable)
1830 set_in_cr4(X86_CR4_PCE);
1831 else
1832 clear_in_cr4(X86_CR4_PCE);
1833}
1834
1835static ssize_t set_attr_rdpmc(struct device *cdev,
1836 struct device_attribute *attr,
1837 const char *buf, size_t count)
1838{
Shuah Khane2b297f2012-06-10 21:13:41 -06001839 unsigned long val;
1840 ssize_t ret;
1841
1842 ret = kstrtoul(buf, 0, &val);
1843 if (ret)
1844 return ret;
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001845
Peter Zijlstrae97df762014-02-05 20:48:51 +01001846 if (x86_pmu.attr_rdpmc_broken)
1847 return -ENOTSUPP;
1848
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001849 if (!!val != !!x86_pmu.attr_rdpmc) {
1850 x86_pmu.attr_rdpmc = !!val;
Peter Zijlstra0e9f2202014-02-05 11:19:56 +01001851 on_each_cpu(change_rdpmc, (void *)val, 1);
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001852 }
1853
1854 return count;
1855}
1856
1857static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc);
1858
1859static struct attribute *x86_pmu_attrs[] = {
1860 &dev_attr_rdpmc.attr,
1861 NULL,
1862};
1863
1864static struct attribute_group x86_pmu_attr_group = {
1865 .attrs = x86_pmu_attrs,
1866};
1867
1868static const struct attribute_group *x86_pmu_attr_groups[] = {
1869 &x86_pmu_attr_group,
Jiri Olsa641cc932012-03-15 20:09:14 +01001870 &x86_pmu_format_group,
Jiri Olsaa4747392012-10-10 14:53:11 +02001871 &x86_pmu_events_group,
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001872 NULL,
1873};
1874
Stephane Eraniand010b332012-02-09 23:21:00 +01001875static void x86_pmu_flush_branch_stack(void)
1876{
1877 if (x86_pmu.flush_branch_stack)
1878 x86_pmu.flush_branch_stack();
1879}
1880
Peter Zijlstrac93dc842012-06-08 14:50:50 +02001881void perf_check_microcode(void)
1882{
1883 if (x86_pmu.check_microcode)
1884 x86_pmu.check_microcode();
1885}
1886EXPORT_SYMBOL_GPL(perf_check_microcode);
1887
Peter Zijlstrab0a873e2010-06-11 13:35:08 +02001888static struct pmu pmu = {
Stephane Eraniand010b332012-02-09 23:21:00 +01001889 .pmu_enable = x86_pmu_enable,
1890 .pmu_disable = x86_pmu_disable,
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001891
Peter Zijlstrac93dc842012-06-08 14:50:50 +02001892 .attr_groups = x86_pmu_attr_groups,
Peter Zijlstra0c9d42e2011-11-20 23:30:47 +01001893
Peter Zijlstrac93dc842012-06-08 14:50:50 +02001894 .event_init = x86_pmu_event_init,
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001895
Stephane Eraniand010b332012-02-09 23:21:00 +01001896 .add = x86_pmu_add,
1897 .del = x86_pmu_del,
1898 .start = x86_pmu_start,
1899 .stop = x86_pmu_stop,
1900 .read = x86_pmu_read,
Peter Zijlstraa4eaf7f2010-06-16 14:37:10 +02001901
Peter Zijlstrac93dc842012-06-08 14:50:50 +02001902 .start_txn = x86_pmu_start_txn,
1903 .cancel_txn = x86_pmu_cancel_txn,
1904 .commit_txn = x86_pmu_commit_txn,
Peter Zijlstrafe4a3302011-11-20 20:44:06 +01001905
Peter Zijlstrac93dc842012-06-08 14:50:50 +02001906 .event_idx = x86_pmu_event_idx,
Stephane Eraniand010b332012-02-09 23:21:00 +01001907 .flush_branch_stack = x86_pmu_flush_branch_stack,
Peter Zijlstrab0a873e2010-06-11 13:35:08 +02001908};
1909
Peter Zijlstrac7206202012-03-22 17:26:36 +01001910void arch_perf_update_userpage(struct perf_event_mmap_page *userpg, u64 now)
Peter Zijlstrae3f35412011-11-21 11:43:53 +01001911{
Peter Zijlstra20d1c862013-11-29 15:40:29 +01001912 struct cyc2ns_data *data;
1913
Peter Zijlstrafa731582013-09-19 10:16:42 +02001914 userpg->cap_user_time = 0;
1915 userpg->cap_user_time_zero = 0;
1916 userpg->cap_user_rdpmc = x86_pmu.attr_rdpmc;
Peter Zijlstrac7206202012-03-22 17:26:36 +01001917 userpg->pmc_width = x86_pmu.cntval_bits;
1918
Peter Zijlstra35af99e2013-11-28 19:38:42 +01001919 if (!sched_clock_stable())
Peter Zijlstrae3f35412011-11-21 11:43:53 +01001920 return;
1921
Peter Zijlstra20d1c862013-11-29 15:40:29 +01001922 data = cyc2ns_read_begin();
1923
Peter Zijlstrafa731582013-09-19 10:16:42 +02001924 userpg->cap_user_time = 1;
Peter Zijlstra20d1c862013-11-29 15:40:29 +01001925 userpg->time_mult = data->cyc2ns_mul;
1926 userpg->time_shift = data->cyc2ns_shift;
1927 userpg->time_offset = data->cyc2ns_offset - now;
Adrian Hunterc73deb62013-06-28 16:22:18 +03001928
Peter Zijlstrad8b11a02013-10-03 16:00:14 +02001929 userpg->cap_user_time_zero = 1;
Peter Zijlstra20d1c862013-11-29 15:40:29 +01001930 userpg->time_zero = data->cyc2ns_offset;
1931
1932 cyc2ns_read_end(data);
Peter Zijlstrae3f35412011-11-21 11:43:53 +01001933}
1934
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001935/*
1936 * callchain support
1937 */
1938
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001939static int backtrace_stack(void *data, char *name)
1940{
Ingo Molnar038e8362009-06-15 09:57:59 +02001941 return 0;
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001942}
1943
1944static void backtrace_address(void *data, unsigned long addr, int reliable)
1945{
1946 struct perf_callchain_entry *entry = data;
1947
Frederic Weisbecker70791ce2010-06-29 19:34:05 +02001948 perf_callchain_store(entry, addr);
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001949}
1950
1951static const struct stacktrace_ops backtrace_ops = {
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001952 .stack = backtrace_stack,
1953 .address = backtrace_address,
Frederic Weisbecker06d65bd2009-12-17 05:40:34 +01001954 .walk_stack = print_context_stack_bp,
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001955};
1956
Frederic Weisbecker56962b42010-06-30 23:03:51 +02001957void
1958perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001959{
Frederic Weisbecker927c7a92010-07-01 16:20:36 +02001960 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1961 /* TODO: We don't support guest os callchain now */
Peter Zijlstraed805262010-08-20 14:30:41 +02001962 return;
Frederic Weisbecker927c7a92010-07-01 16:20:36 +02001963 }
1964
Frederic Weisbecker70791ce2010-06-29 19:34:05 +02001965 perf_callchain_store(entry, regs->ip);
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001966
Namhyung Kime8e999cf2011-03-18 11:40:06 +09001967 dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02001968}
1969
Arun Sharmabc6ca7b2012-04-20 15:41:35 -07001970static inline int
1971valid_user_frame(const void __user *fp, unsigned long size)
1972{
1973 return (__range_not_ok(fp, size, TASK_SIZE) == 0);
1974}
1975
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02001976static unsigned long get_segment_base(unsigned int segment)
1977{
1978 struct desc_struct *desc;
1979 int idx = segment >> 3;
1980
1981 if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) {
1982 if (idx > LDT_ENTRIES)
1983 return 0;
1984
1985 if (idx > current->active_mm->context.size)
1986 return 0;
1987
1988 desc = current->active_mm->context.ldt;
1989 } else {
1990 if (idx > GDT_ENTRIES)
1991 return 0;
1992
1993 desc = __this_cpu_ptr(&gdt_page.gdt[0]);
1994 }
1995
1996 return get_desc_base(desc + idx);
1997}
1998
Torok Edwin257ef9d2010-03-17 12:07:16 +02001999#ifdef CONFIG_COMPAT
H. Peter Anvind1a797f2012-02-19 10:06:34 -08002000
2001#include <asm/compat.h>
2002
Torok Edwin257ef9d2010-03-17 12:07:16 +02002003static inline int
2004perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
Peter Zijlstra74193ef2009-06-15 13:07:24 +02002005{
Torok Edwin257ef9d2010-03-17 12:07:16 +02002006 /* 32-bit process in 64-bit kernel. */
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002007 unsigned long ss_base, cs_base;
Torok Edwin257ef9d2010-03-17 12:07:16 +02002008 struct stack_frame_ia32 frame;
2009 const void __user *fp;
Peter Zijlstra74193ef2009-06-15 13:07:24 +02002010
Torok Edwin257ef9d2010-03-17 12:07:16 +02002011 if (!test_thread_flag(TIF_IA32))
2012 return 0;
Peter Zijlstra74193ef2009-06-15 13:07:24 +02002013
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002014 cs_base = get_segment_base(regs->cs);
2015 ss_base = get_segment_base(regs->ss);
2016
2017 fp = compat_ptr(ss_base + regs->bp);
Torok Edwin257ef9d2010-03-17 12:07:16 +02002018 while (entry->nr < PERF_MAX_STACK_DEPTH) {
2019 unsigned long bytes;
2020 frame.next_frame = 0;
2021 frame.return_address = 0;
2022
2023 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
Peter Zijlstra0a196842013-10-30 21:16:22 +01002024 if (bytes != 0)
Torok Edwin257ef9d2010-03-17 12:07:16 +02002025 break;
2026
Arun Sharmabc6ca7b2012-04-20 15:41:35 -07002027 if (!valid_user_frame(fp, sizeof(frame)))
2028 break;
2029
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002030 perf_callchain_store(entry, cs_base + frame.return_address);
2031 fp = compat_ptr(ss_base + frame.next_frame);
Torok Edwin257ef9d2010-03-17 12:07:16 +02002032 }
2033 return 1;
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002034}
Torok Edwin257ef9d2010-03-17 12:07:16 +02002035#else
2036static inline int
2037perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
2038{
2039 return 0;
2040}
2041#endif
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002042
Frederic Weisbecker56962b42010-06-30 23:03:51 +02002043void
2044perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002045{
2046 struct stack_frame frame;
2047 const void __user *fp;
2048
Frederic Weisbecker927c7a92010-07-01 16:20:36 +02002049 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
2050 /* TODO: We don't support guest os callchain now */
Peter Zijlstraed805262010-08-20 14:30:41 +02002051 return;
Frederic Weisbecker927c7a92010-07-01 16:20:36 +02002052 }
Ingo Molnar5a6cec32009-05-29 11:25:09 +02002053
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002054 /*
2055 * We don't know what to do with VM86 stacks.. ignore them for now.
2056 */
2057 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
2058 return;
2059
Peter Zijlstra74193ef2009-06-15 13:07:24 +02002060 fp = (void __user *)regs->bp;
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002061
Frederic Weisbecker70791ce2010-06-29 19:34:05 +02002062 perf_callchain_store(entry, regs->ip);
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002063
Andrey Vagin20afc602011-08-30 12:32:36 +04002064 if (!current->mm)
2065 return;
2066
Torok Edwin257ef9d2010-03-17 12:07:16 +02002067 if (perf_callchain_user32(regs, entry))
2068 return;
2069
Peter Zijlstraf9188e02009-06-18 22:20:52 +02002070 while (entry->nr < PERF_MAX_STACK_DEPTH) {
Torok Edwin257ef9d2010-03-17 12:07:16 +02002071 unsigned long bytes;
Ingo Molnar038e8362009-06-15 09:57:59 +02002072 frame.next_frame = NULL;
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002073 frame.return_address = 0;
2074
Torok Edwin257ef9d2010-03-17 12:07:16 +02002075 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
Peter Zijlstra0a196842013-10-30 21:16:22 +01002076 if (bytes != 0)
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002077 break;
2078
Arun Sharmabc6ca7b2012-04-20 15:41:35 -07002079 if (!valid_user_frame(fp, sizeof(frame)))
2080 break;
2081
Frederic Weisbecker70791ce2010-06-29 19:34:05 +02002082 perf_callchain_store(entry, frame.return_address);
Ingo Molnar038e8362009-06-15 09:57:59 +02002083 fp = frame.next_frame;
Peter Zijlstrad7d59fb2009-03-30 19:07:15 +02002084 }
2085}
2086
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002087/*
2088 * Deal with code segment offsets for the various execution modes:
2089 *
2090 * VM86 - the good olde 16 bit days, where the linear address is
2091 * 20 bits and we use regs->ip + 0x10 * regs->cs.
2092 *
2093 * IA32 - Where we need to look at GDT/LDT segment descriptor tables
2094 * to figure out what the 32bit base address is.
2095 *
2096 * X32 - has TIF_X32 set, but is running in x86_64
2097 *
2098 * X86_64 - CS,DS,SS,ES are all zero based.
2099 */
2100static unsigned long code_segment_base(struct pt_regs *regs)
2101{
2102 /*
2103 * If we are in VM86 mode, add the segment offset to convert to a
2104 * linear address.
2105 */
2106 if (regs->flags & X86_VM_MASK)
2107 return 0x10 * regs->cs;
2108
2109 /*
2110 * For IA32 we look at the GDT/LDT segment base to convert the
2111 * effective IP to a linear address.
2112 */
2113#ifdef CONFIG_X86_32
2114 if (user_mode(regs) && regs->cs != __USER_CS)
2115 return get_segment_base(regs->cs);
2116#else
2117 if (test_thread_flag(TIF_IA32)) {
2118 if (user_mode(regs) && regs->cs != __USER32_CS)
2119 return get_segment_base(regs->cs);
2120 }
2121#endif
2122 return 0;
2123}
2124
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002125unsigned long perf_instruction_pointer(struct pt_regs *regs)
2126{
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002127 if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002128 return perf_guest_cbs->get_guest_ip();
Zhang, Yanmindcf46b92010-04-20 10:13:58 +08002129
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002130 return regs->ip + code_segment_base(regs);
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002131}
2132
2133unsigned long perf_misc_flags(struct pt_regs *regs)
2134{
2135 int misc = 0;
Zhang, Yanmindcf46b92010-04-20 10:13:58 +08002136
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002137 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
Zhang, Yanmindcf46b92010-04-20 10:13:58 +08002138 if (perf_guest_cbs->is_user_mode())
2139 misc |= PERF_RECORD_MISC_GUEST_USER;
2140 else
2141 misc |= PERF_RECORD_MISC_GUEST_KERNEL;
2142 } else {
Peter Zijlstrad07bdfd2012-07-10 09:42:15 +02002143 if (user_mode(regs))
Zhang, Yanmindcf46b92010-04-20 10:13:58 +08002144 misc |= PERF_RECORD_MISC_USER;
2145 else
2146 misc |= PERF_RECORD_MISC_KERNEL;
2147 }
2148
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002149 if (regs->flags & PERF_EFLAGS_EXACT)
Peter Zijlstraab608342010-04-08 23:03:20 +02002150 misc |= PERF_RECORD_MISC_EXACT_IP;
Zhang, Yanmin39447b32010-04-19 13:32:41 +08002151
2152 return misc;
2153}
Gleb Natapovb3d94682011-11-10 14:57:27 +02002154
2155void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
2156{
2157 cap->version = x86_pmu.version;
2158 cap->num_counters_gp = x86_pmu.num_counters;
2159 cap->num_counters_fixed = x86_pmu.num_counters_fixed;
2160 cap->bit_width_gp = x86_pmu.cntval_bits;
2161 cap->bit_width_fixed = x86_pmu.cntval_bits;
2162 cap->events_mask = (unsigned int)x86_pmu.events_maskl;
2163 cap->events_mask_len = x86_pmu.events_mask_len;
2164}
2165EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);