Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap/clock.c |
| 3 | * |
| 4 | * Copyright (C) 2004 Nokia corporation |
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
| 11 | #include <linux/module.h> |
| 12 | #include <linux/kernel.h> |
| 13 | #include <linux/list.h> |
| 14 | #include <linux/errno.h> |
| 15 | #include <linux/err.h> |
| 16 | |
| 17 | #include <asm/semaphore.h> |
| 18 | #include <asm/hardware/clock.h> |
| 19 | #include <asm/arch/board.h> |
| 20 | #include <asm/arch/usb.h> |
| 21 | |
| 22 | #include "clock.h" |
| 23 | |
| 24 | static LIST_HEAD(clocks); |
| 25 | static DECLARE_MUTEX(clocks_sem); |
| 26 | static DEFINE_SPINLOCK(clockfw_lock); |
| 27 | static void propagate_rate(struct clk * clk); |
| 28 | /* External clock (MCLK & BCLK) functions */ |
| 29 | static int set_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 30 | static long round_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 31 | static void init_ext_clk(struct clk * clk); |
| 32 | /* MPU virtual clock functions */ |
| 33 | static int select_table_rate(struct clk * clk, unsigned long rate); |
| 34 | static long round_to_table_rate(struct clk * clk, unsigned long rate); |
| 35 | void clk_setdpll(__u16, __u16); |
| 36 | |
| 37 | struct mpu_rate rate_table[] = { |
| 38 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL |
| 39 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv |
| 40 | */ |
| 41 | #if defined(CONFIG_OMAP_ARM_216MHZ) |
| 42 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ |
| 43 | #endif |
| 44 | #if defined(CONFIG_OMAP_ARM_195MHZ) |
| 45 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ |
| 46 | #endif |
| 47 | #if defined(CONFIG_OMAP_ARM_192MHZ) |
| 48 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ |
| 49 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ |
| 50 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ |
| 51 | { 48000000, 12000000, 192000000, 0x0ccf, 0x2810 }, /* 4/4/4/4/8/8 */ |
| 52 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ |
| 53 | #endif |
| 54 | #if defined(CONFIG_OMAP_ARM_182MHZ) |
| 55 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ |
| 56 | #endif |
| 57 | #if defined(CONFIG_OMAP_ARM_168MHZ) |
| 58 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ |
| 59 | #endif |
| 60 | #if defined(CONFIG_OMAP_ARM_150MHZ) |
| 61 | { 150000000, 12000000, 150000000, 0x150a, 0x2cb0 }, /* 0/0/1/1/2/2 */ |
| 62 | #endif |
| 63 | #if defined(CONFIG_OMAP_ARM_120MHZ) |
| 64 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ |
| 65 | #endif |
| 66 | #if defined(CONFIG_OMAP_ARM_96MHZ) |
| 67 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ |
| 68 | #endif |
| 69 | #if defined(CONFIG_OMAP_ARM_60MHZ) |
| 70 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ |
| 71 | #endif |
| 72 | #if defined(CONFIG_OMAP_ARM_30MHZ) |
| 73 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ |
| 74 | #endif |
| 75 | { 0, 0, 0, 0, 0 }, |
| 76 | }; |
| 77 | |
| 78 | |
| 79 | static void ckctl_recalc(struct clk * clk) |
| 80 | { |
| 81 | int dsor; |
| 82 | |
| 83 | /* Calculate divisor encoded as 2-bit exponent */ |
| 84 | dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); |
| 85 | if (unlikely(clk->rate == clk->parent->rate / dsor)) |
| 86 | return; /* No change, quick exit */ |
| 87 | clk->rate = clk->parent->rate / dsor; |
| 88 | |
| 89 | if (unlikely(clk->flags & RATE_PROPAGATES)) |
| 90 | propagate_rate(clk); |
| 91 | } |
| 92 | |
| 93 | |
| 94 | static void followparent_recalc(struct clk * clk) |
| 95 | { |
| 96 | clk->rate = clk->parent->rate; |
| 97 | } |
| 98 | |
| 99 | |
| 100 | static void watchdog_recalc(struct clk * clk) |
| 101 | { |
| 102 | clk->rate = clk->parent->rate / 14; |
| 103 | } |
| 104 | |
| 105 | |
| 106 | static struct clk ck_ref = { |
| 107 | .name = "ck_ref", |
| 108 | .rate = 12000000, |
| 109 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 110 | ALWAYS_ENABLED, |
| 111 | }; |
| 112 | |
| 113 | static struct clk ck_dpll1 = { |
| 114 | .name = "ck_dpll1", |
| 115 | .parent = &ck_ref, |
| 116 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 117 | RATE_PROPAGATES | ALWAYS_ENABLED, |
| 118 | }; |
| 119 | |
| 120 | static struct clk ck_dpll1out = { |
| 121 | .name = "ck_dpll1out", |
| 122 | .parent = &ck_dpll1, |
| 123 | .flags = CLOCK_IN_OMAP16XX, |
| 124 | .enable_reg = ARM_IDLECT2, |
| 125 | .enable_bit = EN_CKOUT_ARM, |
| 126 | .recalc = &followparent_recalc, |
| 127 | }; |
| 128 | |
| 129 | static struct clk arm_ck = { |
| 130 | .name = "arm_ck", |
| 131 | .parent = &ck_dpll1, |
| 132 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 133 | RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, |
| 134 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
| 135 | .recalc = &ckctl_recalc, |
| 136 | }; |
| 137 | |
| 138 | static struct clk armper_ck = { |
| 139 | .name = "armper_ck", |
| 140 | .parent = &ck_dpll1, |
| 141 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 142 | RATE_CKCTL, |
| 143 | .enable_reg = ARM_IDLECT2, |
| 144 | .enable_bit = EN_PERCK, |
| 145 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 146 | .recalc = &ckctl_recalc, |
| 147 | }; |
| 148 | |
| 149 | static struct clk arm_gpio_ck = { |
| 150 | .name = "arm_gpio_ck", |
| 151 | .parent = &ck_dpll1, |
| 152 | .flags = CLOCK_IN_OMAP1510, |
| 153 | .enable_reg = ARM_IDLECT2, |
| 154 | .enable_bit = EN_GPIOCK, |
| 155 | .recalc = &followparent_recalc, |
| 156 | }; |
| 157 | |
| 158 | static struct clk armxor_ck = { |
| 159 | .name = "armxor_ck", |
| 160 | .parent = &ck_ref, |
| 161 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
| 162 | .enable_reg = ARM_IDLECT2, |
| 163 | .enable_bit = EN_XORPCK, |
| 164 | .recalc = &followparent_recalc, |
| 165 | }; |
| 166 | |
| 167 | static struct clk armtim_ck = { |
| 168 | .name = "armtim_ck", |
| 169 | .parent = &ck_ref, |
| 170 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
| 171 | .enable_reg = ARM_IDLECT2, |
| 172 | .enable_bit = EN_TIMCK, |
| 173 | .recalc = &followparent_recalc, |
| 174 | }; |
| 175 | |
| 176 | static struct clk armwdt_ck = { |
| 177 | .name = "armwdt_ck", |
| 178 | .parent = &ck_ref, |
| 179 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
| 180 | .enable_reg = ARM_IDLECT2, |
| 181 | .enable_bit = EN_WDTCK, |
| 182 | .recalc = &watchdog_recalc, |
| 183 | }; |
| 184 | |
| 185 | static struct clk arminth_ck16xx = { |
| 186 | .name = "arminth_ck", |
| 187 | .parent = &arm_ck, |
| 188 | .flags = CLOCK_IN_OMAP16XX, |
| 189 | .recalc = &followparent_recalc, |
| 190 | /* Note: On 16xx the frequency can be divided by 2 by programming |
| 191 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 |
| 192 | * |
| 193 | * 1510 version is in TC clocks. |
| 194 | */ |
| 195 | }; |
| 196 | |
| 197 | static struct clk dsp_ck = { |
| 198 | .name = "dsp_ck", |
| 199 | .parent = &ck_dpll1, |
| 200 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 201 | RATE_CKCTL, |
| 202 | .enable_reg = ARM_CKCTL, |
| 203 | .enable_bit = EN_DSPCK, |
| 204 | .rate_offset = CKCTL_DSPDIV_OFFSET, |
| 205 | .recalc = &ckctl_recalc, |
| 206 | }; |
| 207 | |
| 208 | static struct clk dspmmu_ck = { |
| 209 | .name = "dspmmu_ck", |
| 210 | .parent = &ck_dpll1, |
| 211 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 212 | RATE_CKCTL | ALWAYS_ENABLED, |
| 213 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
| 214 | .recalc = &ckctl_recalc, |
| 215 | }; |
| 216 | |
| 217 | static struct clk tc_ck = { |
| 218 | .name = "tc_ck", |
| 219 | .parent = &ck_dpll1, |
| 220 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | |
| 221 | RATE_CKCTL | RATE_PROPAGATES | ALWAYS_ENABLED, |
| 222 | .rate_offset = CKCTL_TCDIV_OFFSET, |
| 223 | .recalc = &ckctl_recalc, |
| 224 | }; |
| 225 | |
| 226 | static struct clk arminth_ck1510 = { |
| 227 | .name = "arminth_ck", |
| 228 | .parent = &tc_ck, |
| 229 | .flags = CLOCK_IN_OMAP1510, |
| 230 | .recalc = &followparent_recalc, |
| 231 | /* Note: On 1510 the frequency follows TC_CK |
| 232 | * |
| 233 | * 16xx version is in MPU clocks. |
| 234 | */ |
| 235 | }; |
| 236 | |
| 237 | static struct clk tipb_ck = { |
| 238 | .name = "tibp_ck", |
| 239 | .parent = &tc_ck, |
| 240 | .flags = CLOCK_IN_OMAP1510, |
| 241 | .recalc = &followparent_recalc, |
| 242 | }; |
| 243 | |
| 244 | static struct clk l3_ocpi_ck = { |
| 245 | .name = "l3_ocpi_ck", |
| 246 | .parent = &tc_ck, |
| 247 | .flags = CLOCK_IN_OMAP16XX, |
| 248 | .enable_reg = ARM_IDLECT3, |
| 249 | .enable_bit = EN_OCPI_CK, |
| 250 | .recalc = &followparent_recalc, |
| 251 | }; |
| 252 | |
| 253 | static struct clk tc1_ck = { |
| 254 | .name = "tc1_ck", |
| 255 | .parent = &tc_ck, |
| 256 | .flags = CLOCK_IN_OMAP16XX, |
| 257 | .enable_reg = ARM_IDLECT3, |
| 258 | .enable_bit = EN_TC1_CK, |
| 259 | .recalc = &followparent_recalc, |
| 260 | }; |
| 261 | |
| 262 | static struct clk tc2_ck = { |
| 263 | .name = "tc2_ck", |
| 264 | .parent = &tc_ck, |
| 265 | .flags = CLOCK_IN_OMAP16XX, |
| 266 | .enable_reg = ARM_IDLECT3, |
| 267 | .enable_bit = EN_TC2_CK, |
| 268 | .recalc = &followparent_recalc, |
| 269 | }; |
| 270 | |
| 271 | static struct clk dma_ck = { |
| 272 | .name = "dma_ck", |
| 273 | .parent = &tc_ck, |
| 274 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
| 275 | .recalc = &followparent_recalc, |
| 276 | }; |
| 277 | |
| 278 | static struct clk dma_lcdfree_ck = { |
| 279 | .name = "dma_lcdfree_ck", |
| 280 | .parent = &tc_ck, |
| 281 | .flags = CLOCK_IN_OMAP16XX, |
| 282 | .recalc = &followparent_recalc, |
| 283 | }; |
| 284 | |
| 285 | static struct clk api_ck = { |
| 286 | .name = "api_ck", |
| 287 | .parent = &tc_ck, |
| 288 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX, |
| 289 | .enable_reg = ARM_IDLECT2, |
| 290 | .enable_bit = EN_APICK, |
| 291 | .recalc = &followparent_recalc, |
| 292 | }; |
| 293 | |
| 294 | static struct clk lb_ck = { |
| 295 | .name = "lb_ck", |
| 296 | .parent = &tc_ck, |
| 297 | .flags = CLOCK_IN_OMAP1510, |
| 298 | .enable_reg = ARM_IDLECT2, |
| 299 | .enable_bit = EN_LBCK, |
| 300 | .recalc = &followparent_recalc, |
| 301 | }; |
| 302 | |
| 303 | static struct clk rhea1_ck = { |
| 304 | .name = "rhea1_ck", |
| 305 | .parent = &tc_ck, |
| 306 | .flags = CLOCK_IN_OMAP16XX, |
| 307 | .recalc = &followparent_recalc, |
| 308 | }; |
| 309 | |
| 310 | static struct clk rhea2_ck = { |
| 311 | .name = "rhea2_ck", |
| 312 | .parent = &tc_ck, |
| 313 | .flags = CLOCK_IN_OMAP16XX, |
| 314 | .recalc = &followparent_recalc, |
| 315 | }; |
| 316 | |
| 317 | static struct clk lcd_ck = { |
| 318 | .name = "lcd_ck", |
| 319 | .parent = &ck_dpll1, |
| 320 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | |
| 321 | RATE_CKCTL, |
| 322 | .enable_reg = ARM_IDLECT2, |
| 323 | .enable_bit = EN_LCDCK, |
| 324 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 325 | .recalc = &ckctl_recalc, |
| 326 | }; |
| 327 | |
| 328 | static struct clk uart1_ck = { |
| 329 | .name = "uart1_ck", |
| 330 | /* Direct from ULPD, no parent */ |
| 331 | .rate = 48000000, |
| 332 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 333 | RATE_FIXED | ENABLE_REG_32BIT, |
| 334 | .enable_reg = MOD_CONF_CTRL_0, |
| 335 | .enable_bit = 29, |
| 336 | /* (Only on 1510) |
| 337 | * The "enable bit" actually chooses between 48MHz and 12MHz. |
| 338 | */ |
| 339 | }; |
| 340 | |
| 341 | static struct clk uart2_ck = { |
| 342 | .name = "uart2_ck", |
| 343 | /* Direct from ULPD, no parent */ |
| 344 | .rate = 48000000, |
| 345 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 346 | RATE_FIXED | ENABLE_REG_32BIT, |
| 347 | .enable_reg = MOD_CONF_CTRL_0, |
| 348 | .enable_bit = 30, |
| 349 | /* (for both 1510 and 16xx) |
| 350 | * The "enable bit" actually chooses between 48MHz and 12MHz/32kHz. |
| 351 | */ |
| 352 | }; |
| 353 | |
| 354 | static struct clk uart3_ck = { |
| 355 | .name = "uart3_ck", |
| 356 | /* Direct from ULPD, no parent */ |
| 357 | .rate = 48000000, |
| 358 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 359 | RATE_FIXED | ENABLE_REG_32BIT, |
| 360 | .enable_reg = MOD_CONF_CTRL_0, |
| 361 | .enable_bit = 31, |
| 362 | /* (Only on 1510) |
| 363 | * The "enable bit" actually chooses between 48MHz and 12MHz. |
| 364 | */ |
| 365 | }; |
| 366 | |
| 367 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ |
| 368 | .name = "usb_clko", |
| 369 | /* Direct from ULPD, no parent */ |
| 370 | .rate = 6000000, |
| 371 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 372 | RATE_FIXED | ENABLE_REG_32BIT, |
| 373 | .enable_reg = ULPD_CLOCK_CTRL, |
| 374 | .enable_bit = USB_MCLK_EN_BIT, |
| 375 | }; |
| 376 | |
| 377 | static struct clk usb_hhc_ck1510 = { |
| 378 | .name = "usb_hhc_ck", |
| 379 | /* Direct from ULPD, no parent */ |
| 380 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
| 381 | .flags = CLOCK_IN_OMAP1510 | |
| 382 | RATE_FIXED | ENABLE_REG_32BIT, |
| 383 | .enable_reg = MOD_CONF_CTRL_0, |
| 384 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
| 385 | }; |
| 386 | |
| 387 | static struct clk usb_hhc_ck16xx = { |
| 388 | .name = "usb_hhc_ck", |
| 389 | /* Direct from ULPD, no parent */ |
| 390 | .rate = 48000000, |
| 391 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 392 | .flags = CLOCK_IN_OMAP16XX | |
| 393 | RATE_FIXED | ENABLE_REG_32BIT, |
| 394 | .enable_reg = OTG_BASE + 0x08 /* OTG_SYSCON_2 */, |
| 395 | .enable_bit = 8 /* UHOST_EN */, |
| 396 | }; |
| 397 | |
| 398 | static struct clk mclk_1510 = { |
| 399 | .name = "mclk", |
| 400 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 401 | .rate = 12000000, |
| 402 | .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, |
| 403 | }; |
| 404 | |
| 405 | static struct clk mclk_16xx = { |
| 406 | .name = "mclk", |
| 407 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 408 | .flags = CLOCK_IN_OMAP16XX, |
| 409 | .enable_reg = COM_CLK_DIV_CTRL_SEL, |
| 410 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
| 411 | .set_rate = &set_ext_clk_rate, |
| 412 | .round_rate = &round_ext_clk_rate, |
| 413 | .init = &init_ext_clk, |
| 414 | }; |
| 415 | |
| 416 | static struct clk bclk_1510 = { |
| 417 | .name = "bclk", |
| 418 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 419 | .rate = 12000000, |
| 420 | .flags = CLOCK_IN_OMAP1510 | RATE_FIXED, |
| 421 | }; |
| 422 | |
| 423 | static struct clk bclk_16xx = { |
| 424 | .name = "bclk", |
| 425 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 426 | .flags = CLOCK_IN_OMAP16XX, |
| 427 | .enable_reg = SWD_CLK_DIV_CTRL_SEL, |
| 428 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
| 429 | .set_rate = &set_ext_clk_rate, |
| 430 | .round_rate = &round_ext_clk_rate, |
| 431 | .init = &init_ext_clk, |
| 432 | }; |
| 433 | |
| 434 | static struct clk mmc1_ck = { |
| 435 | .name = "mmc1_ck", |
| 436 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 437 | .parent = &armper_ck, |
| 438 | .rate = 48000000, |
| 439 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 440 | RATE_FIXED | ENABLE_REG_32BIT, |
| 441 | .enable_reg = MOD_CONF_CTRL_0, |
| 442 | .enable_bit = 23, |
| 443 | }; |
| 444 | |
| 445 | static struct clk mmc2_ck = { |
| 446 | .name = "mmc2_ck", |
| 447 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 448 | .parent = &armper_ck, |
| 449 | .rate = 48000000, |
| 450 | .flags = CLOCK_IN_OMAP16XX | |
| 451 | RATE_FIXED | ENABLE_REG_32BIT, |
| 452 | .enable_reg = MOD_CONF_CTRL_0, |
| 453 | .enable_bit = 20, |
| 454 | }; |
| 455 | |
| 456 | static struct clk virtual_ck_mpu = { |
| 457 | .name = "mpu", |
| 458 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
| 459 | VIRTUAL_CLOCK | ALWAYS_ENABLED, |
| 460 | .parent = &arm_ck, /* Is smarter alias for */ |
| 461 | .recalc = &followparent_recalc, |
| 462 | .set_rate = &select_table_rate, |
| 463 | .round_rate = &round_to_table_rate, |
| 464 | }; |
| 465 | |
| 466 | |
| 467 | static struct clk * onchip_clks[] = { |
| 468 | /* non-ULPD clocks */ |
| 469 | &ck_ref, |
| 470 | &ck_dpll1, |
| 471 | /* CK_GEN1 clocks */ |
| 472 | &ck_dpll1out, |
| 473 | &arm_ck, |
| 474 | &armper_ck, |
| 475 | &arm_gpio_ck, |
| 476 | &armxor_ck, |
| 477 | &armtim_ck, |
| 478 | &armwdt_ck, |
| 479 | &arminth_ck1510, &arminth_ck16xx, |
| 480 | /* CK_GEN2 clocks */ |
| 481 | &dsp_ck, |
| 482 | &dspmmu_ck, |
| 483 | /* CK_GEN3 clocks */ |
| 484 | &tc_ck, |
| 485 | &tipb_ck, |
| 486 | &l3_ocpi_ck, |
| 487 | &tc1_ck, |
| 488 | &tc2_ck, |
| 489 | &dma_ck, |
| 490 | &dma_lcdfree_ck, |
| 491 | &api_ck, |
| 492 | &lb_ck, |
| 493 | &rhea1_ck, |
| 494 | &rhea2_ck, |
| 495 | &lcd_ck, |
| 496 | /* ULPD clocks */ |
| 497 | &uart1_ck, |
| 498 | &uart2_ck, |
| 499 | &uart3_ck, |
| 500 | &usb_clko, |
| 501 | &usb_hhc_ck1510, &usb_hhc_ck16xx, |
| 502 | &mclk_1510, &mclk_16xx, |
| 503 | &bclk_1510, &bclk_16xx, |
| 504 | &mmc1_ck, |
| 505 | &mmc2_ck, |
| 506 | /* Virtual clocks */ |
| 507 | &virtual_ck_mpu, |
| 508 | }; |
| 509 | |
| 510 | struct clk *clk_get(struct device *dev, const char *id) |
| 511 | { |
| 512 | struct clk *p, *clk = ERR_PTR(-ENOENT); |
| 513 | |
| 514 | down(&clocks_sem); |
| 515 | list_for_each_entry(p, &clocks, node) { |
| 516 | if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { |
| 517 | clk = p; |
| 518 | break; |
| 519 | } |
| 520 | } |
| 521 | up(&clocks_sem); |
| 522 | |
| 523 | return clk; |
| 524 | } |
| 525 | EXPORT_SYMBOL(clk_get); |
| 526 | |
| 527 | |
| 528 | void clk_put(struct clk *clk) |
| 529 | { |
| 530 | if (clk && !IS_ERR(clk)) |
| 531 | module_put(clk->owner); |
| 532 | } |
| 533 | EXPORT_SYMBOL(clk_put); |
| 534 | |
| 535 | |
| 536 | int __clk_enable(struct clk *clk) |
| 537 | { |
| 538 | __u16 regval16; |
| 539 | __u32 regval32; |
| 540 | |
| 541 | if (clk->flags & ALWAYS_ENABLED) |
| 542 | return 0; |
| 543 | |
| 544 | if (unlikely(clk->enable_reg == 0)) { |
| 545 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 546 | clk->name); |
| 547 | return 0; |
| 548 | } |
| 549 | |
| 550 | if (clk->flags & ENABLE_REG_32BIT) { |
| 551 | regval32 = omap_readl(clk->enable_reg); |
| 552 | regval32 |= (1 << clk->enable_bit); |
| 553 | omap_writel(regval32, clk->enable_reg); |
| 554 | } else { |
| 555 | regval16 = omap_readw(clk->enable_reg); |
| 556 | regval16 |= (1 << clk->enable_bit); |
| 557 | omap_writew(regval16, clk->enable_reg); |
| 558 | } |
| 559 | |
| 560 | return 0; |
| 561 | } |
| 562 | |
| 563 | |
| 564 | void __clk_disable(struct clk *clk) |
| 565 | { |
| 566 | __u16 regval16; |
| 567 | __u32 regval32; |
| 568 | |
| 569 | if (clk->enable_reg == 0) |
| 570 | return; |
| 571 | |
| 572 | if (clk->flags & ENABLE_REG_32BIT) { |
| 573 | regval32 = omap_readl(clk->enable_reg); |
| 574 | regval32 &= ~(1 << clk->enable_bit); |
| 575 | omap_writel(regval32, clk->enable_reg); |
| 576 | } else { |
| 577 | regval16 = omap_readw(clk->enable_reg); |
| 578 | regval16 &= ~(1 << clk->enable_bit); |
| 579 | omap_writew(regval16, clk->enable_reg); |
| 580 | } |
| 581 | } |
| 582 | |
| 583 | |
| 584 | void __clk_unuse(struct clk *clk) |
| 585 | { |
| 586 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 587 | __clk_disable(clk); |
| 588 | if (likely(clk->parent)) |
| 589 | __clk_unuse(clk->parent); |
| 590 | } |
| 591 | } |
| 592 | |
| 593 | |
| 594 | int __clk_use(struct clk *clk) |
| 595 | { |
| 596 | int ret = 0; |
| 597 | if (clk->usecount++ == 0) { |
| 598 | if (likely(clk->parent)) |
| 599 | ret = __clk_use(clk->parent); |
| 600 | |
| 601 | if (unlikely(ret != 0)) { |
| 602 | clk->usecount--; |
| 603 | return ret; |
| 604 | } |
| 605 | |
| 606 | ret = __clk_enable(clk); |
| 607 | |
| 608 | if (unlikely(ret != 0) && clk->parent) { |
| 609 | __clk_unuse(clk->parent); |
| 610 | clk->usecount--; |
| 611 | } |
| 612 | } |
| 613 | |
| 614 | return ret; |
| 615 | } |
| 616 | |
| 617 | |
| 618 | int clk_enable(struct clk *clk) |
| 619 | { |
| 620 | unsigned long flags; |
| 621 | int ret; |
| 622 | |
| 623 | spin_lock_irqsave(&clockfw_lock, flags); |
| 624 | ret = __clk_enable(clk); |
| 625 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 626 | return ret; |
| 627 | } |
| 628 | EXPORT_SYMBOL(clk_enable); |
| 629 | |
| 630 | |
| 631 | void clk_disable(struct clk *clk) |
| 632 | { |
| 633 | unsigned long flags; |
| 634 | |
| 635 | spin_lock_irqsave(&clockfw_lock, flags); |
| 636 | __clk_disable(clk); |
| 637 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 638 | } |
| 639 | EXPORT_SYMBOL(clk_disable); |
| 640 | |
| 641 | |
| 642 | int clk_use(struct clk *clk) |
| 643 | { |
| 644 | unsigned long flags; |
| 645 | int ret = 0; |
| 646 | |
| 647 | spin_lock_irqsave(&clockfw_lock, flags); |
| 648 | ret = __clk_use(clk); |
| 649 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 650 | return ret; |
| 651 | } |
| 652 | EXPORT_SYMBOL(clk_use); |
| 653 | |
| 654 | |
| 655 | void clk_unuse(struct clk *clk) |
| 656 | { |
| 657 | unsigned long flags; |
| 658 | |
| 659 | spin_lock_irqsave(&clockfw_lock, flags); |
| 660 | __clk_unuse(clk); |
| 661 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 662 | } |
| 663 | EXPORT_SYMBOL(clk_unuse); |
| 664 | |
| 665 | |
| 666 | int clk_get_usecount(struct clk *clk) |
| 667 | { |
| 668 | return clk->usecount; |
| 669 | } |
| 670 | EXPORT_SYMBOL(clk_get_usecount); |
| 671 | |
| 672 | |
| 673 | unsigned long clk_get_rate(struct clk *clk) |
| 674 | { |
| 675 | return clk->rate; |
| 676 | } |
| 677 | EXPORT_SYMBOL(clk_get_rate); |
| 678 | |
| 679 | |
| 680 | static __u16 verify_ckctl_value(__u16 newval) |
| 681 | { |
| 682 | /* This function checks for following limitations set |
| 683 | * by the hardware (all conditions must be true): |
| 684 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 |
| 685 | * ARM_CK >= TC_CK |
| 686 | * DSP_CK >= TC_CK |
| 687 | * DSPMMU_CK >= TC_CK |
| 688 | * |
| 689 | * In addition following rules are enforced: |
| 690 | * LCD_CK <= TC_CK |
| 691 | * ARMPER_CK <= TC_CK |
| 692 | * |
| 693 | * However, maximum frequencies are not checked for! |
| 694 | */ |
| 695 | __u8 per_exp; |
| 696 | __u8 lcd_exp; |
| 697 | __u8 arm_exp; |
| 698 | __u8 dsp_exp; |
| 699 | __u8 tc_exp; |
| 700 | __u8 dspmmu_exp; |
| 701 | |
| 702 | per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; |
| 703 | lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; |
| 704 | arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; |
| 705 | dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; |
| 706 | tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; |
| 707 | dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; |
| 708 | |
| 709 | if (dspmmu_exp < dsp_exp) |
| 710 | dspmmu_exp = dsp_exp; |
| 711 | if (dspmmu_exp > dsp_exp+1) |
| 712 | dspmmu_exp = dsp_exp+1; |
| 713 | if (tc_exp < arm_exp) |
| 714 | tc_exp = arm_exp; |
| 715 | if (tc_exp < dspmmu_exp) |
| 716 | tc_exp = dspmmu_exp; |
| 717 | if (tc_exp > lcd_exp) |
| 718 | lcd_exp = tc_exp; |
| 719 | if (tc_exp > per_exp) |
| 720 | per_exp = tc_exp; |
| 721 | |
| 722 | newval &= 0xf000; |
| 723 | newval |= per_exp << CKCTL_PERDIV_OFFSET; |
| 724 | newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; |
| 725 | newval |= arm_exp << CKCTL_ARMDIV_OFFSET; |
| 726 | newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; |
| 727 | newval |= tc_exp << CKCTL_TCDIV_OFFSET; |
| 728 | newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; |
| 729 | |
| 730 | return newval; |
| 731 | } |
| 732 | |
| 733 | |
| 734 | static int calc_dsor_exp(struct clk *clk, unsigned long rate) |
| 735 | { |
| 736 | /* Note: If target frequency is too low, this function will return 4, |
| 737 | * which is invalid value. Caller must check for this value and act |
| 738 | * accordingly. |
| 739 | * |
| 740 | * Note: This function does not check for following limitations set |
| 741 | * by the hardware (all conditions must be true): |
| 742 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 |
| 743 | * ARM_CK >= TC_CK |
| 744 | * DSP_CK >= TC_CK |
| 745 | * DSPMMU_CK >= TC_CK |
| 746 | */ |
| 747 | unsigned long realrate; |
| 748 | struct clk * parent; |
| 749 | unsigned dsor_exp; |
| 750 | |
| 751 | if (unlikely(!(clk->flags & RATE_CKCTL))) |
| 752 | return -EINVAL; |
| 753 | |
| 754 | parent = clk->parent; |
| 755 | if (unlikely(parent == 0)) |
| 756 | return -EIO; |
| 757 | |
| 758 | realrate = parent->rate; |
| 759 | for (dsor_exp=0; dsor_exp<4; dsor_exp++) { |
| 760 | if (realrate <= rate) |
| 761 | break; |
| 762 | |
| 763 | realrate /= 2; |
| 764 | } |
| 765 | |
| 766 | return dsor_exp; |
| 767 | } |
| 768 | |
| 769 | long clk_round_rate(struct clk *clk, unsigned long rate) |
| 770 | { |
| 771 | int dsor_exp; |
| 772 | |
| 773 | if (clk->flags & RATE_FIXED) |
| 774 | return clk->rate; |
| 775 | |
| 776 | if (clk->flags & RATE_CKCTL) { |
| 777 | dsor_exp = calc_dsor_exp(clk, rate); |
| 778 | if (dsor_exp < 0) |
| 779 | return dsor_exp; |
| 780 | if (dsor_exp > 3) |
| 781 | dsor_exp = 3; |
| 782 | return clk->parent->rate / (1 << dsor_exp); |
| 783 | } |
| 784 | |
| 785 | if(clk->round_rate != 0) |
| 786 | return clk->round_rate(clk, rate); |
| 787 | |
| 788 | return clk->rate; |
| 789 | } |
| 790 | EXPORT_SYMBOL(clk_round_rate); |
| 791 | |
| 792 | |
| 793 | static void propagate_rate(struct clk * clk) |
| 794 | { |
| 795 | struct clk ** clkp; |
| 796 | |
| 797 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { |
| 798 | if (likely((*clkp)->parent != clk)) continue; |
| 799 | if (likely((*clkp)->recalc)) |
| 800 | (*clkp)->recalc(*clkp); |
| 801 | } |
| 802 | } |
| 803 | |
| 804 | |
| 805 | static int select_table_rate(struct clk * clk, unsigned long rate) |
| 806 | { |
| 807 | /* Find the highest supported frequency <= rate and switch to it */ |
| 808 | struct mpu_rate * ptr; |
| 809 | |
| 810 | if (clk != &virtual_ck_mpu) |
| 811 | return -EINVAL; |
| 812 | |
| 813 | for (ptr = rate_table; ptr->rate; ptr++) { |
| 814 | if (ptr->xtal != ck_ref.rate) |
| 815 | continue; |
| 816 | |
| 817 | /* DPLL1 cannot be reprogrammed without risking system crash */ |
| 818 | if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) |
| 819 | continue; |
| 820 | |
| 821 | /* Can check only after xtal frequency check */ |
| 822 | if (ptr->rate <= rate) |
| 823 | break; |
| 824 | } |
| 825 | |
| 826 | if (!ptr->rate) |
| 827 | return -EINVAL; |
| 828 | |
| 829 | if (unlikely(ck_dpll1.rate == 0)) { |
| 830 | omap_writew(ptr->dpllctl_val, DPLL_CTL); |
| 831 | ck_dpll1.rate = ptr->pll_rate; |
| 832 | } |
| 833 | omap_writew(ptr->ckctl_val, ARM_CKCTL); |
| 834 | propagate_rate(&ck_dpll1); |
| 835 | return 0; |
| 836 | } |
| 837 | |
| 838 | |
| 839 | static long round_to_table_rate(struct clk * clk, unsigned long rate) |
| 840 | { |
| 841 | /* Find the highest supported frequency <= rate */ |
| 842 | struct mpu_rate * ptr; |
| 843 | long highest_rate; |
| 844 | |
| 845 | if (clk != &virtual_ck_mpu) |
| 846 | return -EINVAL; |
| 847 | |
| 848 | highest_rate = -EINVAL; |
| 849 | |
| 850 | for (ptr = rate_table; ptr->rate; ptr++) { |
| 851 | if (ptr->xtal != ck_ref.rate) |
| 852 | continue; |
| 853 | |
| 854 | highest_rate = ptr->rate; |
| 855 | |
| 856 | /* Can check only after xtal frequency check */ |
| 857 | if (ptr->rate <= rate) |
| 858 | break; |
| 859 | } |
| 860 | |
| 861 | return highest_rate; |
| 862 | } |
| 863 | |
| 864 | |
| 865 | int clk_set_rate(struct clk *clk, unsigned long rate) |
| 866 | { |
| 867 | int ret = -EINVAL; |
| 868 | int dsor_exp; |
| 869 | __u16 regval; |
| 870 | unsigned long flags; |
| 871 | |
| 872 | if (clk->flags & RATE_CKCTL) { |
| 873 | dsor_exp = calc_dsor_exp(clk, rate); |
| 874 | if (dsor_exp > 3) |
| 875 | dsor_exp = -EINVAL; |
| 876 | if (dsor_exp < 0) |
| 877 | return dsor_exp; |
| 878 | |
| 879 | spin_lock_irqsave(&clockfw_lock, flags); |
| 880 | regval = omap_readw(ARM_CKCTL); |
| 881 | regval &= ~(3 << clk->rate_offset); |
| 882 | regval |= dsor_exp << clk->rate_offset; |
| 883 | regval = verify_ckctl_value(regval); |
| 884 | omap_writew(regval, ARM_CKCTL); |
| 885 | clk->rate = clk->parent->rate / (1 << dsor_exp); |
| 886 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 887 | ret = 0; |
| 888 | } else if(clk->set_rate != 0) { |
| 889 | spin_lock_irqsave(&clockfw_lock, flags); |
| 890 | ret = clk->set_rate(clk, rate); |
| 891 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 892 | } |
| 893 | |
| 894 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) |
| 895 | propagate_rate(clk); |
| 896 | |
| 897 | return ret; |
| 898 | } |
| 899 | EXPORT_SYMBOL(clk_set_rate); |
| 900 | |
| 901 | |
| 902 | static unsigned calc_ext_dsor(unsigned long rate) |
| 903 | { |
| 904 | unsigned dsor; |
| 905 | |
| 906 | /* MCLK and BCLK divisor selection is not linear: |
| 907 | * freq = 96MHz / dsor |
| 908 | * |
| 909 | * RATIO_SEL range: dsor <-> RATIO_SEL |
| 910 | * 0..6: (RATIO_SEL+2) <-> (dsor-2) |
| 911 | * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) |
| 912 | * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 |
| 913 | * can not be used. |
| 914 | */ |
| 915 | for (dsor = 2; dsor < 96; ++dsor) { |
| 916 | if ((dsor & 1) && dsor > 8) |
| 917 | continue; |
| 918 | if (rate >= 96000000 / dsor) |
| 919 | break; |
| 920 | } |
| 921 | return dsor; |
| 922 | } |
| 923 | |
| 924 | |
| 925 | static int set_ext_clk_rate(struct clk * clk, unsigned long rate) |
| 926 | { |
| 927 | unsigned dsor; |
| 928 | __u16 ratio_bits; |
| 929 | |
| 930 | dsor = calc_ext_dsor(rate); |
| 931 | clk->rate = 96000000 / dsor; |
| 932 | if (dsor > 8) |
| 933 | ratio_bits = ((dsor - 8) / 2 + 6) << 2; |
| 934 | else |
| 935 | ratio_bits = (dsor - 2) << 2; |
| 936 | |
| 937 | ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; |
| 938 | omap_writew(ratio_bits, clk->enable_reg); |
| 939 | |
| 940 | return 0; |
| 941 | } |
| 942 | |
| 943 | |
| 944 | static long round_ext_clk_rate(struct clk * clk, unsigned long rate) |
| 945 | { |
| 946 | return 96000000 / calc_ext_dsor(rate); |
| 947 | } |
| 948 | |
| 949 | |
| 950 | static void init_ext_clk(struct clk * clk) |
| 951 | { |
| 952 | unsigned dsor; |
| 953 | __u16 ratio_bits; |
| 954 | |
| 955 | /* Determine current rate and ensure clock is based on 96MHz APLL */ |
| 956 | ratio_bits = omap_readw(clk->enable_reg) & ~1; |
| 957 | omap_writew(ratio_bits, clk->enable_reg); |
| 958 | |
| 959 | ratio_bits = (ratio_bits & 0xfc) >> 2; |
| 960 | if (ratio_bits > 6) |
| 961 | dsor = (ratio_bits - 6) * 2 + 8; |
| 962 | else |
| 963 | dsor = ratio_bits + 2; |
| 964 | |
| 965 | clk-> rate = 96000000 / dsor; |
| 966 | } |
| 967 | |
| 968 | |
| 969 | int clk_register(struct clk *clk) |
| 970 | { |
| 971 | down(&clocks_sem); |
| 972 | list_add(&clk->node, &clocks); |
| 973 | if (clk->init) |
| 974 | clk->init(clk); |
| 975 | up(&clocks_sem); |
| 976 | return 0; |
| 977 | } |
| 978 | EXPORT_SYMBOL(clk_register); |
| 979 | |
| 980 | void clk_unregister(struct clk *clk) |
| 981 | { |
| 982 | down(&clocks_sem); |
| 983 | list_del(&clk->node); |
| 984 | up(&clocks_sem); |
| 985 | } |
| 986 | EXPORT_SYMBOL(clk_unregister); |
| 987 | |
| 988 | |
| 989 | |
| 990 | int __init clk_init(void) |
| 991 | { |
| 992 | struct clk ** clkp; |
| 993 | const struct omap_clock_config *info; |
| 994 | int crystal_type = 0; /* Default 12 MHz */ |
| 995 | |
| 996 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { |
| 997 | if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { |
| 998 | clk_register(*clkp); |
| 999 | continue; |
| 1000 | } |
| 1001 | |
| 1002 | if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { |
| 1003 | clk_register(*clkp); |
| 1004 | continue; |
| 1005 | } |
| 1006 | |
| 1007 | if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { |
| 1008 | clk_register(*clkp); |
| 1009 | continue; |
| 1010 | } |
| 1011 | } |
| 1012 | |
| 1013 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); |
| 1014 | if (info != NULL) { |
| 1015 | if (!cpu_is_omap1510()) |
| 1016 | crystal_type = info->system_clock_type; |
| 1017 | } |
| 1018 | |
| 1019 | #if defined(CONFIG_ARCH_OMAP730) |
| 1020 | ck_ref.rate = 13000000; |
| 1021 | #elif defined(CONFIG_ARCH_OMAP16XX) |
| 1022 | if (crystal_type == 2) |
| 1023 | ck_ref.rate = 19200000; |
| 1024 | #endif |
| 1025 | |
| 1026 | /* We want to be in syncronous scalable mode */ |
| 1027 | omap_writew(0x1000, ARM_SYSST); |
| 1028 | |
| 1029 | /* Find the highest supported frequency and enable it */ |
| 1030 | if (select_table_rate(&virtual_ck_mpu, ~0)) { |
| 1031 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); |
| 1032 | /* Guess sane values (60MHz) */ |
| 1033 | omap_writew(0x2290, DPLL_CTL); |
| 1034 | omap_writew(0x1005, ARM_CKCTL); |
| 1035 | ck_dpll1.rate = 60000000; |
| 1036 | propagate_rate(&ck_dpll1); |
| 1037 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): %ld/%ld/%ld\n", |
| 1038 | ck_ref.rate, ck_dpll1.rate, arm_ck.rate); |
| 1039 | } |
| 1040 | |
| 1041 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ |
| 1042 | propagate_rate(&ck_ref); |
| 1043 | |
| 1044 | #ifdef CONFIG_MACH_OMAP_PERSEUS2 |
| 1045 | /* Select slicer output as OMAP input clock */ |
| 1046 | omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); |
| 1047 | #endif |
| 1048 | |
| 1049 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ |
| 1050 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); |
| 1051 | |
| 1052 | /* Put DSP/MPUI into reset until needed */ |
| 1053 | omap_writew(0, ARM_RSTCT1); |
| 1054 | omap_writew(1, ARM_RSTCT2); |
| 1055 | omap_writew(0x400, ARM_IDLECT1); |
| 1056 | |
| 1057 | /* |
| 1058 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) |
| 1059 | * of the ARM_IDLECT2 register must be set to zero. The power-on |
| 1060 | * default value of this bit is one. |
| 1061 | */ |
| 1062 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ |
| 1063 | |
| 1064 | /* |
| 1065 | * Only enable those clocks we will need, let the drivers |
| 1066 | * enable other clocks as necessary |
| 1067 | */ |
| 1068 | clk_use(&armper_ck); |
| 1069 | clk_use(&armxor_ck); |
| 1070 | clk_use(&armtim_ck); |
| 1071 | |
| 1072 | if (cpu_is_omap1510()) |
| 1073 | clk_enable(&arm_gpio_ck); |
| 1074 | |
| 1075 | return 0; |
| 1076 | } |