Greg Kroah-Hartman | b244131 | 2017-11-01 15:07:57 +0100 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * Machine specific calibrate_tsc() for generic. |
| 4 | * Split out from timer_tsc.c by Osamu Tomita <tomita@cinet.co.jp> |
| 5 | */ |
| 6 | /* ------ Calibrate the TSC ------- |
| 7 | * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset(). |
| 8 | * Too much 64-bit arithmetic here to do this cleanly in C, and for |
| 9 | * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2) |
| 10 | * output busy loop as low as possible. We avoid reading the CTC registers |
| 11 | * directly because of the awkward 8-bit access mechanism of the 82C54 |
| 12 | * device. |
| 13 | */ |
H. Peter Anvin | 05e4d31 | 2008-10-23 00:01:39 -0700 | [diff] [blame] | 14 | #ifndef _ASM_X86_MACH_DEFAULT_MACH_TIMER_H |
| 15 | #define _ASM_X86_MACH_DEFAULT_MACH_TIMER_H |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
john stultz | 539eb11 | 2006-06-26 00:25:10 -0700 | [diff] [blame] | 17 | #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */ |
| 18 | #define CALIBRATE_LATCH \ |
Deepak Saxena | b0145bf | 2011-11-01 14:25:16 -0700 | [diff] [blame] | 19 | ((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
| 21 | static inline void mach_prepare_counter(void) |
| 22 | { |
| 23 | /* Set the Gate high, disable speaker */ |
| 24 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
| 25 | |
| 26 | /* |
| 27 | * Now let's take care of CTC channel 2 |
| 28 | * |
| 29 | * Set the Gate high, program CTC channel 2 for mode 0, |
| 30 | * (interrupt on terminal count mode), binary count, |
| 31 | * load 5 * LATCH count, (LSB and MSB) to begin countdown. |
| 32 | * |
| 33 | * Some devices need a delay here. |
| 34 | */ |
| 35 | outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */ |
| 36 | outb_p(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */ |
| 37 | outb_p(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */ |
| 38 | } |
| 39 | |
| 40 | static inline void mach_countup(unsigned long *count_p) |
| 41 | { |
| 42 | unsigned long count = 0; |
| 43 | do { |
| 44 | count++; |
| 45 | } while ((inb_p(0x61) & 0x20) == 0); |
| 46 | *count_p = count; |
| 47 | } |
| 48 | |
H. Peter Anvin | 05e4d31 | 2008-10-23 00:01:39 -0700 | [diff] [blame] | 49 | #endif /* _ASM_X86_MACH_DEFAULT_MACH_TIMER_H */ |