Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1 | /* Broadcom NetXtreme-C/E network driver. |
| 2 | * |
| 3 | * Copyright (c) 2014-2015 Broadcom Corporation |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #include <linux/module.h> |
| 11 | |
| 12 | #include <linux/stringify.h> |
| 13 | #include <linux/kernel.h> |
| 14 | #include <linux/timer.h> |
| 15 | #include <linux/errno.h> |
| 16 | #include <linux/ioport.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/vmalloc.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/netdevice.h> |
| 22 | #include <linux/etherdevice.h> |
| 23 | #include <linux/skbuff.h> |
| 24 | #include <linux/dma-mapping.h> |
| 25 | #include <linux/bitops.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/irq.h> |
| 28 | #include <linux/delay.h> |
| 29 | #include <asm/byteorder.h> |
| 30 | #include <asm/page.h> |
| 31 | #include <linux/time.h> |
| 32 | #include <linux/mii.h> |
| 33 | #include <linux/if.h> |
| 34 | #include <linux/if_vlan.h> |
| 35 | #include <net/ip.h> |
| 36 | #include <net/tcp.h> |
| 37 | #include <net/udp.h> |
| 38 | #include <net/checksum.h> |
| 39 | #include <net/ip6_checksum.h> |
| 40 | #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE) |
| 41 | #include <net/vxlan.h> |
| 42 | #endif |
| 43 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 44 | #include <net/busy_poll.h> |
| 45 | #endif |
| 46 | #include <linux/workqueue.h> |
| 47 | #include <linux/prefetch.h> |
| 48 | #include <linux/cache.h> |
| 49 | #include <linux/log2.h> |
| 50 | #include <linux/aer.h> |
| 51 | #include <linux/bitmap.h> |
| 52 | #include <linux/cpu_rmap.h> |
| 53 | |
| 54 | #include "bnxt_hsi.h" |
| 55 | #include "bnxt.h" |
| 56 | #include "bnxt_sriov.h" |
| 57 | #include "bnxt_ethtool.h" |
| 58 | |
| 59 | #define BNXT_TX_TIMEOUT (5 * HZ) |
| 60 | |
| 61 | static const char version[] = |
| 62 | "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n"; |
| 63 | |
| 64 | MODULE_LICENSE("GPL"); |
| 65 | MODULE_DESCRIPTION("Broadcom BCM573xx network driver"); |
| 66 | MODULE_VERSION(DRV_MODULE_VERSION); |
| 67 | |
| 68 | #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN) |
| 69 | #define BNXT_RX_DMA_OFFSET NET_SKB_PAD |
| 70 | #define BNXT_RX_COPY_THRESH 256 |
| 71 | |
| 72 | #define BNXT_TX_PUSH_THRESH 92 |
| 73 | |
| 74 | enum board_idx { |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 75 | BCM57301, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 76 | BCM57302, |
| 77 | BCM57304, |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 78 | BCM57402, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 79 | BCM57404, |
| 80 | BCM57406, |
| 81 | BCM57304_VF, |
| 82 | BCM57404_VF, |
| 83 | }; |
| 84 | |
| 85 | /* indexed by enum above */ |
| 86 | static const struct { |
| 87 | char *name; |
| 88 | } board_info[] = { |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 89 | { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" }, |
| 90 | { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" }, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 91 | { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" }, |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 92 | { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" }, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 93 | { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" }, |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 94 | { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" }, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 95 | { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" }, |
| 96 | { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" }, |
| 97 | }; |
| 98 | |
| 99 | static const struct pci_device_id bnxt_pci_tbl[] = { |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 100 | { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 }, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 101 | { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 }, |
| 102 | { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 }, |
David Christensen | fbc9a52 | 2015-12-27 18:19:29 -0500 | [diff] [blame] | 103 | { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 }, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 104 | { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 }, |
| 105 | { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 }, |
| 106 | #ifdef CONFIG_BNXT_SRIOV |
| 107 | { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF }, |
| 108 | { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF }, |
| 109 | #endif |
| 110 | { 0 } |
| 111 | }; |
| 112 | |
| 113 | MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl); |
| 114 | |
| 115 | static const u16 bnxt_vf_req_snif[] = { |
| 116 | HWRM_FUNC_CFG, |
| 117 | HWRM_PORT_PHY_QCFG, |
| 118 | HWRM_CFA_L2_FILTER_ALLOC, |
| 119 | }; |
| 120 | |
| 121 | static bool bnxt_vf_pciid(enum board_idx idx) |
| 122 | { |
| 123 | return (idx == BCM57304_VF || idx == BCM57404_VF); |
| 124 | } |
| 125 | |
| 126 | #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID) |
| 127 | #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS) |
| 128 | #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS) |
| 129 | |
| 130 | #define BNXT_CP_DB_REARM(db, raw_cons) \ |
| 131 | writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db) |
| 132 | |
| 133 | #define BNXT_CP_DB(db, raw_cons) \ |
| 134 | writel(DB_CP_FLAGS | RING_CMP(raw_cons), db) |
| 135 | |
| 136 | #define BNXT_CP_DB_IRQ_DIS(db) \ |
| 137 | writel(DB_CP_IRQ_DIS_FLAGS, db) |
| 138 | |
| 139 | static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr) |
| 140 | { |
| 141 | /* Tell compiler to fetch tx indices from memory. */ |
| 142 | barrier(); |
| 143 | |
| 144 | return bp->tx_ring_size - |
| 145 | ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask); |
| 146 | } |
| 147 | |
| 148 | static const u16 bnxt_lhint_arr[] = { |
| 149 | TX_BD_FLAGS_LHINT_512_AND_SMALLER, |
| 150 | TX_BD_FLAGS_LHINT_512_TO_1023, |
| 151 | TX_BD_FLAGS_LHINT_1024_TO_2047, |
| 152 | TX_BD_FLAGS_LHINT_1024_TO_2047, |
| 153 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 154 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 155 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 156 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 157 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 158 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 159 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 160 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 161 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 162 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 163 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 164 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 165 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 166 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 167 | TX_BD_FLAGS_LHINT_2048_AND_LARGER, |
| 168 | }; |
| 169 | |
| 170 | static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) |
| 171 | { |
| 172 | struct bnxt *bp = netdev_priv(dev); |
| 173 | struct tx_bd *txbd; |
| 174 | struct tx_bd_ext *txbd1; |
| 175 | struct netdev_queue *txq; |
| 176 | int i; |
| 177 | dma_addr_t mapping; |
| 178 | unsigned int length, pad = 0; |
| 179 | u32 len, free_size, vlan_tag_flags, cfa_action, flags; |
| 180 | u16 prod, last_frag; |
| 181 | struct pci_dev *pdev = bp->pdev; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 182 | struct bnxt_tx_ring_info *txr; |
| 183 | struct bnxt_sw_tx_bd *tx_buf; |
| 184 | |
| 185 | i = skb_get_queue_mapping(skb); |
| 186 | if (unlikely(i >= bp->tx_nr_rings)) { |
| 187 | dev_kfree_skb_any(skb); |
| 188 | return NETDEV_TX_OK; |
| 189 | } |
| 190 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 191 | txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 192 | txq = netdev_get_tx_queue(dev, i); |
| 193 | prod = txr->tx_prod; |
| 194 | |
| 195 | free_size = bnxt_tx_avail(bp, txr); |
| 196 | if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) { |
| 197 | netif_tx_stop_queue(txq); |
| 198 | return NETDEV_TX_BUSY; |
| 199 | } |
| 200 | |
| 201 | length = skb->len; |
| 202 | len = skb_headlen(skb); |
| 203 | last_frag = skb_shinfo(skb)->nr_frags; |
| 204 | |
| 205 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; |
| 206 | |
| 207 | txbd->tx_bd_opaque = prod; |
| 208 | |
| 209 | tx_buf = &txr->tx_buf_ring[prod]; |
| 210 | tx_buf->skb = skb; |
| 211 | tx_buf->nr_frags = last_frag; |
| 212 | |
| 213 | vlan_tag_flags = 0; |
| 214 | cfa_action = 0; |
| 215 | if (skb_vlan_tag_present(skb)) { |
| 216 | vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN | |
| 217 | skb_vlan_tag_get(skb); |
| 218 | /* Currently supports 8021Q, 8021AD vlan offloads |
| 219 | * QINQ1, QINQ2, QINQ3 vlan headers are deprecated |
| 220 | */ |
| 221 | if (skb->vlan_proto == htons(ETH_P_8021Q)) |
| 222 | vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT; |
| 223 | } |
| 224 | |
| 225 | if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) { |
| 226 | struct tx_push_bd *push = txr->tx_push; |
| 227 | struct tx_bd *tx_push = &push->txbd1; |
| 228 | struct tx_bd_ext *tx_push1 = &push->txbd2; |
| 229 | void *pdata = tx_push1 + 1; |
| 230 | int j; |
| 231 | |
| 232 | /* Set COAL_NOW to be ready quickly for the next push */ |
| 233 | tx_push->tx_bd_len_flags_type = |
| 234 | cpu_to_le32((length << TX_BD_LEN_SHIFT) | |
| 235 | TX_BD_TYPE_LONG_TX_BD | |
| 236 | TX_BD_FLAGS_LHINT_512_AND_SMALLER | |
| 237 | TX_BD_FLAGS_COAL_NOW | |
| 238 | TX_BD_FLAGS_PACKET_END | |
| 239 | (2 << TX_BD_FLAGS_BD_CNT_SHIFT)); |
| 240 | |
| 241 | if (skb->ip_summed == CHECKSUM_PARTIAL) |
| 242 | tx_push1->tx_bd_hsize_lflags = |
| 243 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); |
| 244 | else |
| 245 | tx_push1->tx_bd_hsize_lflags = 0; |
| 246 | |
| 247 | tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); |
| 248 | tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action); |
| 249 | |
| 250 | skb_copy_from_linear_data(skb, pdata, len); |
| 251 | pdata += len; |
| 252 | for (j = 0; j < last_frag; j++) { |
| 253 | skb_frag_t *frag = &skb_shinfo(skb)->frags[j]; |
| 254 | void *fptr; |
| 255 | |
| 256 | fptr = skb_frag_address_safe(frag); |
| 257 | if (!fptr) |
| 258 | goto normal_tx; |
| 259 | |
| 260 | memcpy(pdata, fptr, skb_frag_size(frag)); |
| 261 | pdata += skb_frag_size(frag); |
| 262 | } |
| 263 | |
| 264 | memcpy(txbd, tx_push, sizeof(*txbd)); |
| 265 | prod = NEXT_TX(prod); |
| 266 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; |
| 267 | memcpy(txbd, tx_push1, sizeof(*txbd)); |
| 268 | prod = NEXT_TX(prod); |
| 269 | push->doorbell = |
| 270 | cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod); |
| 271 | txr->tx_prod = prod; |
| 272 | |
| 273 | netdev_tx_sent_queue(txq, skb->len); |
| 274 | |
| 275 | __iowrite64_copy(txr->tx_doorbell, push, |
| 276 | (length + sizeof(*push) + 8) / 8); |
| 277 | |
| 278 | tx_buf->is_push = 1; |
| 279 | |
| 280 | goto tx_done; |
| 281 | } |
| 282 | |
| 283 | normal_tx: |
| 284 | if (length < BNXT_MIN_PKT_SIZE) { |
| 285 | pad = BNXT_MIN_PKT_SIZE - length; |
| 286 | if (skb_pad(skb, pad)) { |
| 287 | /* SKB already freed. */ |
| 288 | tx_buf->skb = NULL; |
| 289 | return NETDEV_TX_OK; |
| 290 | } |
| 291 | length = BNXT_MIN_PKT_SIZE; |
| 292 | } |
| 293 | |
| 294 | mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE); |
| 295 | |
| 296 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) { |
| 297 | dev_kfree_skb_any(skb); |
| 298 | tx_buf->skb = NULL; |
| 299 | return NETDEV_TX_OK; |
| 300 | } |
| 301 | |
| 302 | dma_unmap_addr_set(tx_buf, mapping, mapping); |
| 303 | flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD | |
| 304 | ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT); |
| 305 | |
| 306 | txbd->tx_bd_haddr = cpu_to_le64(mapping); |
| 307 | |
| 308 | prod = NEXT_TX(prod); |
| 309 | txbd1 = (struct tx_bd_ext *) |
| 310 | &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; |
| 311 | |
| 312 | txbd1->tx_bd_hsize_lflags = 0; |
| 313 | if (skb_is_gso(skb)) { |
| 314 | u32 hdr_len; |
| 315 | |
| 316 | if (skb->encapsulation) |
| 317 | hdr_len = skb_inner_network_offset(skb) + |
| 318 | skb_inner_network_header_len(skb) + |
| 319 | inner_tcp_hdrlen(skb); |
| 320 | else |
| 321 | hdr_len = skb_transport_offset(skb) + |
| 322 | tcp_hdrlen(skb); |
| 323 | |
| 324 | txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO | |
| 325 | TX_BD_FLAGS_T_IPID | |
| 326 | (hdr_len << (TX_BD_HSIZE_SHIFT - 1))); |
| 327 | length = skb_shinfo(skb)->gso_size; |
| 328 | txbd1->tx_bd_mss = cpu_to_le32(length); |
| 329 | length += hdr_len; |
| 330 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { |
| 331 | txbd1->tx_bd_hsize_lflags = |
| 332 | cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM); |
| 333 | txbd1->tx_bd_mss = 0; |
| 334 | } |
| 335 | |
| 336 | length >>= 9; |
| 337 | flags |= bnxt_lhint_arr[length]; |
| 338 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); |
| 339 | |
| 340 | txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags); |
| 341 | txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action); |
| 342 | for (i = 0; i < last_frag; i++) { |
| 343 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
| 344 | |
| 345 | prod = NEXT_TX(prod); |
| 346 | txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)]; |
| 347 | |
| 348 | len = skb_frag_size(frag); |
| 349 | mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len, |
| 350 | DMA_TO_DEVICE); |
| 351 | |
| 352 | if (unlikely(dma_mapping_error(&pdev->dev, mapping))) |
| 353 | goto tx_dma_error; |
| 354 | |
| 355 | tx_buf = &txr->tx_buf_ring[prod]; |
| 356 | dma_unmap_addr_set(tx_buf, mapping, mapping); |
| 357 | |
| 358 | txbd->tx_bd_haddr = cpu_to_le64(mapping); |
| 359 | |
| 360 | flags = len << TX_BD_LEN_SHIFT; |
| 361 | txbd->tx_bd_len_flags_type = cpu_to_le32(flags); |
| 362 | } |
| 363 | |
| 364 | flags &= ~TX_BD_LEN; |
| 365 | txbd->tx_bd_len_flags_type = |
| 366 | cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags | |
| 367 | TX_BD_FLAGS_PACKET_END); |
| 368 | |
| 369 | netdev_tx_sent_queue(txq, skb->len); |
| 370 | |
| 371 | /* Sync BD data before updating doorbell */ |
| 372 | wmb(); |
| 373 | |
| 374 | prod = NEXT_TX(prod); |
| 375 | txr->tx_prod = prod; |
| 376 | |
| 377 | writel(DB_KEY_TX | prod, txr->tx_doorbell); |
| 378 | writel(DB_KEY_TX | prod, txr->tx_doorbell); |
| 379 | |
| 380 | tx_done: |
| 381 | |
| 382 | mmiowb(); |
| 383 | |
| 384 | if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) { |
| 385 | netif_tx_stop_queue(txq); |
| 386 | |
| 387 | /* netif_tx_stop_queue() must be done before checking |
| 388 | * tx index in bnxt_tx_avail() below, because in |
| 389 | * bnxt_tx_int(), we update tx index before checking for |
| 390 | * netif_tx_queue_stopped(). |
| 391 | */ |
| 392 | smp_mb(); |
| 393 | if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh) |
| 394 | netif_tx_wake_queue(txq); |
| 395 | } |
| 396 | return NETDEV_TX_OK; |
| 397 | |
| 398 | tx_dma_error: |
| 399 | last_frag = i; |
| 400 | |
| 401 | /* start back at beginning and unmap skb */ |
| 402 | prod = txr->tx_prod; |
| 403 | tx_buf = &txr->tx_buf_ring[prod]; |
| 404 | tx_buf->skb = NULL; |
| 405 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), |
| 406 | skb_headlen(skb), PCI_DMA_TODEVICE); |
| 407 | prod = NEXT_TX(prod); |
| 408 | |
| 409 | /* unmap remaining mapped pages */ |
| 410 | for (i = 0; i < last_frag; i++) { |
| 411 | prod = NEXT_TX(prod); |
| 412 | tx_buf = &txr->tx_buf_ring[prod]; |
| 413 | dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping), |
| 414 | skb_frag_size(&skb_shinfo(skb)->frags[i]), |
| 415 | PCI_DMA_TODEVICE); |
| 416 | } |
| 417 | |
| 418 | dev_kfree_skb_any(skb); |
| 419 | return NETDEV_TX_OK; |
| 420 | } |
| 421 | |
| 422 | static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts) |
| 423 | { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 424 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 425 | int index = txr - &bp->tx_ring[0]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 426 | struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index); |
| 427 | u16 cons = txr->tx_cons; |
| 428 | struct pci_dev *pdev = bp->pdev; |
| 429 | int i; |
| 430 | unsigned int tx_bytes = 0; |
| 431 | |
| 432 | for (i = 0; i < nr_pkts; i++) { |
| 433 | struct bnxt_sw_tx_bd *tx_buf; |
| 434 | struct sk_buff *skb; |
| 435 | int j, last; |
| 436 | |
| 437 | tx_buf = &txr->tx_buf_ring[cons]; |
| 438 | cons = NEXT_TX(cons); |
| 439 | skb = tx_buf->skb; |
| 440 | tx_buf->skb = NULL; |
| 441 | |
| 442 | if (tx_buf->is_push) { |
| 443 | tx_buf->is_push = 0; |
| 444 | goto next_tx_int; |
| 445 | } |
| 446 | |
| 447 | dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping), |
| 448 | skb_headlen(skb), PCI_DMA_TODEVICE); |
| 449 | last = tx_buf->nr_frags; |
| 450 | |
| 451 | for (j = 0; j < last; j++) { |
| 452 | cons = NEXT_TX(cons); |
| 453 | tx_buf = &txr->tx_buf_ring[cons]; |
| 454 | dma_unmap_page( |
| 455 | &pdev->dev, |
| 456 | dma_unmap_addr(tx_buf, mapping), |
| 457 | skb_frag_size(&skb_shinfo(skb)->frags[j]), |
| 458 | PCI_DMA_TODEVICE); |
| 459 | } |
| 460 | |
| 461 | next_tx_int: |
| 462 | cons = NEXT_TX(cons); |
| 463 | |
| 464 | tx_bytes += skb->len; |
| 465 | dev_kfree_skb_any(skb); |
| 466 | } |
| 467 | |
| 468 | netdev_tx_completed_queue(txq, nr_pkts, tx_bytes); |
| 469 | txr->tx_cons = cons; |
| 470 | |
| 471 | /* Need to make the tx_cons update visible to bnxt_start_xmit() |
| 472 | * before checking for netif_tx_queue_stopped(). Without the |
| 473 | * memory barrier, there is a small possibility that bnxt_start_xmit() |
| 474 | * will miss it and cause the queue to be stopped forever. |
| 475 | */ |
| 476 | smp_mb(); |
| 477 | |
| 478 | if (unlikely(netif_tx_queue_stopped(txq)) && |
| 479 | (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) { |
| 480 | __netif_tx_lock(txq, smp_processor_id()); |
| 481 | if (netif_tx_queue_stopped(txq) && |
| 482 | bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh && |
| 483 | txr->dev_state != BNXT_DEV_STATE_CLOSING) |
| 484 | netif_tx_wake_queue(txq); |
| 485 | __netif_tx_unlock(txq); |
| 486 | } |
| 487 | } |
| 488 | |
| 489 | static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping, |
| 490 | gfp_t gfp) |
| 491 | { |
| 492 | u8 *data; |
| 493 | struct pci_dev *pdev = bp->pdev; |
| 494 | |
| 495 | data = kmalloc(bp->rx_buf_size, gfp); |
| 496 | if (!data) |
| 497 | return NULL; |
| 498 | |
| 499 | *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET, |
| 500 | bp->rx_buf_use_size, PCI_DMA_FROMDEVICE); |
| 501 | |
| 502 | if (dma_mapping_error(&pdev->dev, *mapping)) { |
| 503 | kfree(data); |
| 504 | data = NULL; |
| 505 | } |
| 506 | return data; |
| 507 | } |
| 508 | |
| 509 | static inline int bnxt_alloc_rx_data(struct bnxt *bp, |
| 510 | struct bnxt_rx_ring_info *rxr, |
| 511 | u16 prod, gfp_t gfp) |
| 512 | { |
| 513 | struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; |
| 514 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod]; |
| 515 | u8 *data; |
| 516 | dma_addr_t mapping; |
| 517 | |
| 518 | data = __bnxt_alloc_rx_data(bp, &mapping, gfp); |
| 519 | if (!data) |
| 520 | return -ENOMEM; |
| 521 | |
| 522 | rx_buf->data = data; |
| 523 | dma_unmap_addr_set(rx_buf, mapping, mapping); |
| 524 | |
| 525 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); |
| 526 | |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, |
| 531 | u8 *data) |
| 532 | { |
| 533 | u16 prod = rxr->rx_prod; |
| 534 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
| 535 | struct rx_bd *cons_bd, *prod_bd; |
| 536 | |
| 537 | prod_rx_buf = &rxr->rx_buf_ring[prod]; |
| 538 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
| 539 | |
| 540 | prod_rx_buf->data = data; |
| 541 | |
| 542 | dma_unmap_addr_set(prod_rx_buf, mapping, |
| 543 | dma_unmap_addr(cons_rx_buf, mapping)); |
| 544 | |
| 545 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; |
| 546 | cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)]; |
| 547 | |
| 548 | prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr; |
| 549 | } |
| 550 | |
| 551 | static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx) |
| 552 | { |
| 553 | u16 next, max = rxr->rx_agg_bmap_size; |
| 554 | |
| 555 | next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx); |
| 556 | if (next >= max) |
| 557 | next = find_first_zero_bit(rxr->rx_agg_bmap, max); |
| 558 | return next; |
| 559 | } |
| 560 | |
| 561 | static inline int bnxt_alloc_rx_page(struct bnxt *bp, |
| 562 | struct bnxt_rx_ring_info *rxr, |
| 563 | u16 prod, gfp_t gfp) |
| 564 | { |
| 565 | struct rx_bd *rxbd = |
| 566 | &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; |
| 567 | struct bnxt_sw_rx_agg_bd *rx_agg_buf; |
| 568 | struct pci_dev *pdev = bp->pdev; |
| 569 | struct page *page; |
| 570 | dma_addr_t mapping; |
| 571 | u16 sw_prod = rxr->rx_sw_agg_prod; |
| 572 | |
| 573 | page = alloc_page(gfp); |
| 574 | if (!page) |
| 575 | return -ENOMEM; |
| 576 | |
| 577 | mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE, |
| 578 | PCI_DMA_FROMDEVICE); |
| 579 | if (dma_mapping_error(&pdev->dev, mapping)) { |
| 580 | __free_page(page); |
| 581 | return -EIO; |
| 582 | } |
| 583 | |
| 584 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) |
| 585 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); |
| 586 | |
| 587 | __set_bit(sw_prod, rxr->rx_agg_bmap); |
| 588 | rx_agg_buf = &rxr->rx_agg_ring[sw_prod]; |
| 589 | rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod); |
| 590 | |
| 591 | rx_agg_buf->page = page; |
| 592 | rx_agg_buf->mapping = mapping; |
| 593 | rxbd->rx_bd_haddr = cpu_to_le64(mapping); |
| 594 | rxbd->rx_bd_opaque = sw_prod; |
| 595 | return 0; |
| 596 | } |
| 597 | |
| 598 | static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons, |
| 599 | u32 agg_bufs) |
| 600 | { |
| 601 | struct bnxt *bp = bnapi->bp; |
| 602 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 603 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 604 | u16 prod = rxr->rx_agg_prod; |
| 605 | u16 sw_prod = rxr->rx_sw_agg_prod; |
| 606 | u32 i; |
| 607 | |
| 608 | for (i = 0; i < agg_bufs; i++) { |
| 609 | u16 cons; |
| 610 | struct rx_agg_cmp *agg; |
| 611 | struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf; |
| 612 | struct rx_bd *prod_bd; |
| 613 | struct page *page; |
| 614 | |
| 615 | agg = (struct rx_agg_cmp *) |
| 616 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; |
| 617 | cons = agg->rx_agg_cmp_opaque; |
| 618 | __clear_bit(cons, rxr->rx_agg_bmap); |
| 619 | |
| 620 | if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap))) |
| 621 | sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod); |
| 622 | |
| 623 | __set_bit(sw_prod, rxr->rx_agg_bmap); |
| 624 | prod_rx_buf = &rxr->rx_agg_ring[sw_prod]; |
| 625 | cons_rx_buf = &rxr->rx_agg_ring[cons]; |
| 626 | |
| 627 | /* It is possible for sw_prod to be equal to cons, so |
| 628 | * set cons_rx_buf->page to NULL first. |
| 629 | */ |
| 630 | page = cons_rx_buf->page; |
| 631 | cons_rx_buf->page = NULL; |
| 632 | prod_rx_buf->page = page; |
| 633 | |
| 634 | prod_rx_buf->mapping = cons_rx_buf->mapping; |
| 635 | |
| 636 | prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)]; |
| 637 | |
| 638 | prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping); |
| 639 | prod_bd->rx_bd_opaque = sw_prod; |
| 640 | |
| 641 | prod = NEXT_RX_AGG(prod); |
| 642 | sw_prod = NEXT_RX_AGG(sw_prod); |
| 643 | cp_cons = NEXT_CMP(cp_cons); |
| 644 | } |
| 645 | rxr->rx_agg_prod = prod; |
| 646 | rxr->rx_sw_agg_prod = sw_prod; |
| 647 | } |
| 648 | |
| 649 | static struct sk_buff *bnxt_rx_skb(struct bnxt *bp, |
| 650 | struct bnxt_rx_ring_info *rxr, u16 cons, |
| 651 | u16 prod, u8 *data, dma_addr_t dma_addr, |
| 652 | unsigned int len) |
| 653 | { |
| 654 | int err; |
| 655 | struct sk_buff *skb; |
| 656 | |
| 657 | err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC); |
| 658 | if (unlikely(err)) { |
| 659 | bnxt_reuse_rx_data(rxr, cons, data); |
| 660 | return NULL; |
| 661 | } |
| 662 | |
| 663 | skb = build_skb(data, 0); |
| 664 | dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size, |
| 665 | PCI_DMA_FROMDEVICE); |
| 666 | if (!skb) { |
| 667 | kfree(data); |
| 668 | return NULL; |
| 669 | } |
| 670 | |
| 671 | skb_reserve(skb, BNXT_RX_OFFSET); |
| 672 | skb_put(skb, len); |
| 673 | return skb; |
| 674 | } |
| 675 | |
| 676 | static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi, |
| 677 | struct sk_buff *skb, u16 cp_cons, |
| 678 | u32 agg_bufs) |
| 679 | { |
| 680 | struct pci_dev *pdev = bp->pdev; |
| 681 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 682 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 683 | u16 prod = rxr->rx_agg_prod; |
| 684 | u32 i; |
| 685 | |
| 686 | for (i = 0; i < agg_bufs; i++) { |
| 687 | u16 cons, frag_len; |
| 688 | struct rx_agg_cmp *agg; |
| 689 | struct bnxt_sw_rx_agg_bd *cons_rx_buf; |
| 690 | struct page *page; |
| 691 | dma_addr_t mapping; |
| 692 | |
| 693 | agg = (struct rx_agg_cmp *) |
| 694 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; |
| 695 | cons = agg->rx_agg_cmp_opaque; |
| 696 | frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) & |
| 697 | RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT; |
| 698 | |
| 699 | cons_rx_buf = &rxr->rx_agg_ring[cons]; |
| 700 | skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len); |
| 701 | __clear_bit(cons, rxr->rx_agg_bmap); |
| 702 | |
| 703 | /* It is possible for bnxt_alloc_rx_page() to allocate |
| 704 | * a sw_prod index that equals the cons index, so we |
| 705 | * need to clear the cons entry now. |
| 706 | */ |
| 707 | mapping = dma_unmap_addr(cons_rx_buf, mapping); |
| 708 | page = cons_rx_buf->page; |
| 709 | cons_rx_buf->page = NULL; |
| 710 | |
| 711 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) { |
| 712 | struct skb_shared_info *shinfo; |
| 713 | unsigned int nr_frags; |
| 714 | |
| 715 | shinfo = skb_shinfo(skb); |
| 716 | nr_frags = --shinfo->nr_frags; |
| 717 | __skb_frag_set_page(&shinfo->frags[nr_frags], NULL); |
| 718 | |
| 719 | dev_kfree_skb(skb); |
| 720 | |
| 721 | cons_rx_buf->page = page; |
| 722 | |
| 723 | /* Update prod since possibly some pages have been |
| 724 | * allocated already. |
| 725 | */ |
| 726 | rxr->rx_agg_prod = prod; |
| 727 | bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i); |
| 728 | return NULL; |
| 729 | } |
| 730 | |
| 731 | dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE, |
| 732 | PCI_DMA_FROMDEVICE); |
| 733 | |
| 734 | skb->data_len += frag_len; |
| 735 | skb->len += frag_len; |
| 736 | skb->truesize += PAGE_SIZE; |
| 737 | |
| 738 | prod = NEXT_RX_AGG(prod); |
| 739 | cp_cons = NEXT_CMP(cp_cons); |
| 740 | } |
| 741 | rxr->rx_agg_prod = prod; |
| 742 | return skb; |
| 743 | } |
| 744 | |
| 745 | static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr, |
| 746 | u8 agg_bufs, u32 *raw_cons) |
| 747 | { |
| 748 | u16 last; |
| 749 | struct rx_agg_cmp *agg; |
| 750 | |
| 751 | *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs); |
| 752 | last = RING_CMP(*raw_cons); |
| 753 | agg = (struct rx_agg_cmp *) |
| 754 | &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)]; |
| 755 | return RX_AGG_CMP_VALID(agg, *raw_cons); |
| 756 | } |
| 757 | |
| 758 | static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data, |
| 759 | unsigned int len, |
| 760 | dma_addr_t mapping) |
| 761 | { |
| 762 | struct bnxt *bp = bnapi->bp; |
| 763 | struct pci_dev *pdev = bp->pdev; |
| 764 | struct sk_buff *skb; |
| 765 | |
| 766 | skb = napi_alloc_skb(&bnapi->napi, len); |
| 767 | if (!skb) |
| 768 | return NULL; |
| 769 | |
| 770 | dma_sync_single_for_cpu(&pdev->dev, mapping, |
| 771 | bp->rx_copy_thresh, PCI_DMA_FROMDEVICE); |
| 772 | |
| 773 | memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET); |
| 774 | |
| 775 | dma_sync_single_for_device(&pdev->dev, mapping, |
| 776 | bp->rx_copy_thresh, |
| 777 | PCI_DMA_FROMDEVICE); |
| 778 | |
| 779 | skb_put(skb, len); |
| 780 | return skb; |
| 781 | } |
| 782 | |
| 783 | static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr, |
| 784 | struct rx_tpa_start_cmp *tpa_start, |
| 785 | struct rx_tpa_start_cmp_ext *tpa_start1) |
| 786 | { |
| 787 | u8 agg_id = TPA_START_AGG_ID(tpa_start); |
| 788 | u16 cons, prod; |
| 789 | struct bnxt_tpa_info *tpa_info; |
| 790 | struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf; |
| 791 | struct rx_bd *prod_bd; |
| 792 | dma_addr_t mapping; |
| 793 | |
| 794 | cons = tpa_start->rx_tpa_start_cmp_opaque; |
| 795 | prod = rxr->rx_prod; |
| 796 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
| 797 | prod_rx_buf = &rxr->rx_buf_ring[prod]; |
| 798 | tpa_info = &rxr->rx_tpa[agg_id]; |
| 799 | |
| 800 | prod_rx_buf->data = tpa_info->data; |
| 801 | |
| 802 | mapping = tpa_info->mapping; |
| 803 | dma_unmap_addr_set(prod_rx_buf, mapping, mapping); |
| 804 | |
| 805 | prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)]; |
| 806 | |
| 807 | prod_bd->rx_bd_haddr = cpu_to_le64(mapping); |
| 808 | |
| 809 | tpa_info->data = cons_rx_buf->data; |
| 810 | cons_rx_buf->data = NULL; |
| 811 | tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping); |
| 812 | |
| 813 | tpa_info->len = |
| 814 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >> |
| 815 | RX_TPA_START_CMP_LEN_SHIFT; |
| 816 | if (likely(TPA_START_HASH_VALID(tpa_start))) { |
| 817 | u32 hash_type = TPA_START_HASH_TYPE(tpa_start); |
| 818 | |
| 819 | tpa_info->hash_type = PKT_HASH_TYPE_L4; |
| 820 | tpa_info->gso_type = SKB_GSO_TCPV4; |
| 821 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ |
| 822 | if (hash_type == 3) |
| 823 | tpa_info->gso_type = SKB_GSO_TCPV6; |
| 824 | tpa_info->rss_hash = |
| 825 | le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash); |
| 826 | } else { |
| 827 | tpa_info->hash_type = PKT_HASH_TYPE_NONE; |
| 828 | tpa_info->gso_type = 0; |
| 829 | if (netif_msg_rx_err(bp)) |
| 830 | netdev_warn(bp->dev, "TPA packet without valid hash\n"); |
| 831 | } |
| 832 | tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2); |
| 833 | tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata); |
| 834 | |
| 835 | rxr->rx_prod = NEXT_RX(prod); |
| 836 | cons = NEXT_RX(cons); |
| 837 | cons_rx_buf = &rxr->rx_buf_ring[cons]; |
| 838 | |
| 839 | bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data); |
| 840 | rxr->rx_prod = NEXT_RX(rxr->rx_prod); |
| 841 | cons_rx_buf->data = NULL; |
| 842 | } |
| 843 | |
| 844 | static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi, |
| 845 | u16 cp_cons, u32 agg_bufs) |
| 846 | { |
| 847 | if (agg_bufs) |
| 848 | bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); |
| 849 | } |
| 850 | |
| 851 | #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr)) |
| 852 | #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr)) |
| 853 | |
| 854 | static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info, |
| 855 | struct rx_tpa_end_cmp *tpa_end, |
| 856 | struct rx_tpa_end_cmp_ext *tpa_end1, |
| 857 | struct sk_buff *skb) |
| 858 | { |
Michael Chan | d1611c3 | 2015-10-25 22:27:57 -0400 | [diff] [blame] | 859 | #ifdef CONFIG_INET |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 860 | struct tcphdr *th; |
| 861 | int payload_off, tcp_opt_len = 0; |
| 862 | int len, nw_off; |
Michael Chan | 27e2418 | 2015-12-27 18:19:23 -0500 | [diff] [blame] | 863 | u16 segs; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 864 | |
Michael Chan | 27e2418 | 2015-12-27 18:19:23 -0500 | [diff] [blame] | 865 | segs = TPA_END_TPA_SEGS(tpa_end); |
| 866 | if (segs == 1) |
| 867 | return skb; |
| 868 | |
| 869 | NAPI_GRO_CB(skb)->count = segs; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 870 | skb_shinfo(skb)->gso_size = |
| 871 | le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len); |
| 872 | skb_shinfo(skb)->gso_type = tpa_info->gso_type; |
| 873 | payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & |
| 874 | RX_TPA_END_CMP_PAYLOAD_OFFSET) >> |
| 875 | RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT; |
| 876 | if (TPA_END_GRO_TS(tpa_end)) |
| 877 | tcp_opt_len = 12; |
| 878 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 879 | if (tpa_info->gso_type == SKB_GSO_TCPV4) { |
| 880 | struct iphdr *iph; |
| 881 | |
| 882 | nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len - |
| 883 | ETH_HLEN; |
| 884 | skb_set_network_header(skb, nw_off); |
| 885 | iph = ip_hdr(skb); |
| 886 | skb_set_transport_header(skb, nw_off + sizeof(struct iphdr)); |
| 887 | len = skb->len - skb_transport_offset(skb); |
| 888 | th = tcp_hdr(skb); |
| 889 | th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0); |
| 890 | } else if (tpa_info->gso_type == SKB_GSO_TCPV6) { |
| 891 | struct ipv6hdr *iph; |
| 892 | |
| 893 | nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len - |
| 894 | ETH_HLEN; |
| 895 | skb_set_network_header(skb, nw_off); |
| 896 | iph = ipv6_hdr(skb); |
| 897 | skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr)); |
| 898 | len = skb->len - skb_transport_offset(skb); |
| 899 | th = tcp_hdr(skb); |
| 900 | th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0); |
| 901 | } else { |
| 902 | dev_kfree_skb_any(skb); |
| 903 | return NULL; |
| 904 | } |
| 905 | tcp_gro_complete(skb); |
| 906 | |
| 907 | if (nw_off) { /* tunnel */ |
| 908 | struct udphdr *uh = NULL; |
| 909 | |
| 910 | if (skb->protocol == htons(ETH_P_IP)) { |
| 911 | struct iphdr *iph = (struct iphdr *)skb->data; |
| 912 | |
| 913 | if (iph->protocol == IPPROTO_UDP) |
| 914 | uh = (struct udphdr *)(iph + 1); |
| 915 | } else { |
| 916 | struct ipv6hdr *iph = (struct ipv6hdr *)skb->data; |
| 917 | |
| 918 | if (iph->nexthdr == IPPROTO_UDP) |
| 919 | uh = (struct udphdr *)(iph + 1); |
| 920 | } |
| 921 | if (uh) { |
| 922 | if (uh->check) |
| 923 | skb_shinfo(skb)->gso_type |= |
| 924 | SKB_GSO_UDP_TUNNEL_CSUM; |
| 925 | else |
| 926 | skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL; |
| 927 | } |
| 928 | } |
| 929 | #endif |
| 930 | return skb; |
| 931 | } |
| 932 | |
| 933 | static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp, |
| 934 | struct bnxt_napi *bnapi, |
| 935 | u32 *raw_cons, |
| 936 | struct rx_tpa_end_cmp *tpa_end, |
| 937 | struct rx_tpa_end_cmp_ext *tpa_end1, |
| 938 | bool *agg_event) |
| 939 | { |
| 940 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 941 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 942 | u8 agg_id = TPA_END_AGG_ID(tpa_end); |
| 943 | u8 *data, agg_bufs; |
| 944 | u16 cp_cons = RING_CMP(*raw_cons); |
| 945 | unsigned int len; |
| 946 | struct bnxt_tpa_info *tpa_info; |
| 947 | dma_addr_t mapping; |
| 948 | struct sk_buff *skb; |
| 949 | |
| 950 | tpa_info = &rxr->rx_tpa[agg_id]; |
| 951 | data = tpa_info->data; |
| 952 | prefetch(data); |
| 953 | len = tpa_info->len; |
| 954 | mapping = tpa_info->mapping; |
| 955 | |
| 956 | agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) & |
| 957 | RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT; |
| 958 | |
| 959 | if (agg_bufs) { |
| 960 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons)) |
| 961 | return ERR_PTR(-EBUSY); |
| 962 | |
| 963 | *agg_event = true; |
| 964 | cp_cons = NEXT_CMP(cp_cons); |
| 965 | } |
| 966 | |
| 967 | if (unlikely(agg_bufs > MAX_SKB_FRAGS)) { |
| 968 | bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); |
| 969 | netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n", |
| 970 | agg_bufs, (int)MAX_SKB_FRAGS); |
| 971 | return NULL; |
| 972 | } |
| 973 | |
| 974 | if (len <= bp->rx_copy_thresh) { |
| 975 | skb = bnxt_copy_skb(bnapi, data, len, mapping); |
| 976 | if (!skb) { |
| 977 | bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); |
| 978 | return NULL; |
| 979 | } |
| 980 | } else { |
| 981 | u8 *new_data; |
| 982 | dma_addr_t new_mapping; |
| 983 | |
| 984 | new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC); |
| 985 | if (!new_data) { |
| 986 | bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); |
| 987 | return NULL; |
| 988 | } |
| 989 | |
| 990 | tpa_info->data = new_data; |
| 991 | tpa_info->mapping = new_mapping; |
| 992 | |
| 993 | skb = build_skb(data, 0); |
| 994 | dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size, |
| 995 | PCI_DMA_FROMDEVICE); |
| 996 | |
| 997 | if (!skb) { |
| 998 | kfree(data); |
| 999 | bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs); |
| 1000 | return NULL; |
| 1001 | } |
| 1002 | skb_reserve(skb, BNXT_RX_OFFSET); |
| 1003 | skb_put(skb, len); |
| 1004 | } |
| 1005 | |
| 1006 | if (agg_bufs) { |
| 1007 | skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); |
| 1008 | if (!skb) { |
| 1009 | /* Page reuse already handled by bnxt_rx_pages(). */ |
| 1010 | return NULL; |
| 1011 | } |
| 1012 | } |
| 1013 | skb->protocol = eth_type_trans(skb, bp->dev); |
| 1014 | |
| 1015 | if (tpa_info->hash_type != PKT_HASH_TYPE_NONE) |
| 1016 | skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type); |
| 1017 | |
| 1018 | if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) { |
| 1019 | netdev_features_t features = skb->dev->features; |
| 1020 | u16 vlan_proto = tpa_info->metadata >> |
| 1021 | RX_CMP_FLAGS2_METADATA_TPID_SFT; |
| 1022 | |
| 1023 | if (((features & NETIF_F_HW_VLAN_CTAG_RX) && |
| 1024 | vlan_proto == ETH_P_8021Q) || |
| 1025 | ((features & NETIF_F_HW_VLAN_STAG_RX) && |
| 1026 | vlan_proto == ETH_P_8021AD)) { |
| 1027 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), |
| 1028 | tpa_info->metadata & |
| 1029 | RX_CMP_FLAGS2_METADATA_VID_MASK); |
| 1030 | } |
| 1031 | } |
| 1032 | |
| 1033 | skb_checksum_none_assert(skb); |
| 1034 | if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) { |
| 1035 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1036 | skb->csum_level = |
| 1037 | (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3; |
| 1038 | } |
| 1039 | |
| 1040 | if (TPA_END_GRO(tpa_end)) |
| 1041 | skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb); |
| 1042 | |
| 1043 | return skb; |
| 1044 | } |
| 1045 | |
| 1046 | /* returns the following: |
| 1047 | * 1 - 1 packet successfully received |
| 1048 | * 0 - successful TPA_START, packet not completed yet |
| 1049 | * -EBUSY - completion ring does not have all the agg buffers yet |
| 1050 | * -ENOMEM - packet aborted due to out of memory |
| 1051 | * -EIO - packet aborted due to hw error indicated in BD |
| 1052 | */ |
| 1053 | static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons, |
| 1054 | bool *agg_event) |
| 1055 | { |
| 1056 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1057 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1058 | struct net_device *dev = bp->dev; |
| 1059 | struct rx_cmp *rxcmp; |
| 1060 | struct rx_cmp_ext *rxcmp1; |
| 1061 | u32 tmp_raw_cons = *raw_cons; |
| 1062 | u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons); |
| 1063 | struct bnxt_sw_rx_bd *rx_buf; |
| 1064 | unsigned int len; |
| 1065 | u8 *data, agg_bufs, cmp_type; |
| 1066 | dma_addr_t dma_addr; |
| 1067 | struct sk_buff *skb; |
| 1068 | int rc = 0; |
| 1069 | |
| 1070 | rxcmp = (struct rx_cmp *) |
| 1071 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; |
| 1072 | |
| 1073 | tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons); |
| 1074 | cp_cons = RING_CMP(tmp_raw_cons); |
| 1075 | rxcmp1 = (struct rx_cmp_ext *) |
| 1076 | &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)]; |
| 1077 | |
| 1078 | if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons)) |
| 1079 | return -EBUSY; |
| 1080 | |
| 1081 | cmp_type = RX_CMP_TYPE(rxcmp); |
| 1082 | |
| 1083 | prod = rxr->rx_prod; |
| 1084 | |
| 1085 | if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) { |
| 1086 | bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp, |
| 1087 | (struct rx_tpa_start_cmp_ext *)rxcmp1); |
| 1088 | |
| 1089 | goto next_rx_no_prod; |
| 1090 | |
| 1091 | } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) { |
| 1092 | skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons, |
| 1093 | (struct rx_tpa_end_cmp *)rxcmp, |
| 1094 | (struct rx_tpa_end_cmp_ext *)rxcmp1, |
| 1095 | agg_event); |
| 1096 | |
| 1097 | if (unlikely(IS_ERR(skb))) |
| 1098 | return -EBUSY; |
| 1099 | |
| 1100 | rc = -ENOMEM; |
| 1101 | if (likely(skb)) { |
| 1102 | skb_record_rx_queue(skb, bnapi->index); |
| 1103 | skb_mark_napi_id(skb, &bnapi->napi); |
| 1104 | if (bnxt_busy_polling(bnapi)) |
| 1105 | netif_receive_skb(skb); |
| 1106 | else |
| 1107 | napi_gro_receive(&bnapi->napi, skb); |
| 1108 | rc = 1; |
| 1109 | } |
| 1110 | goto next_rx_no_prod; |
| 1111 | } |
| 1112 | |
| 1113 | cons = rxcmp->rx_cmp_opaque; |
| 1114 | rx_buf = &rxr->rx_buf_ring[cons]; |
| 1115 | data = rx_buf->data; |
| 1116 | prefetch(data); |
| 1117 | |
| 1118 | agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >> |
| 1119 | RX_CMP_AGG_BUFS_SHIFT; |
| 1120 | |
| 1121 | if (agg_bufs) { |
| 1122 | if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons)) |
| 1123 | return -EBUSY; |
| 1124 | |
| 1125 | cp_cons = NEXT_CMP(cp_cons); |
| 1126 | *agg_event = true; |
| 1127 | } |
| 1128 | |
| 1129 | rx_buf->data = NULL; |
| 1130 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) { |
| 1131 | bnxt_reuse_rx_data(rxr, cons, data); |
| 1132 | if (agg_bufs) |
| 1133 | bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs); |
| 1134 | |
| 1135 | rc = -EIO; |
| 1136 | goto next_rx; |
| 1137 | } |
| 1138 | |
| 1139 | len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT; |
| 1140 | dma_addr = dma_unmap_addr(rx_buf, mapping); |
| 1141 | |
| 1142 | if (len <= bp->rx_copy_thresh) { |
| 1143 | skb = bnxt_copy_skb(bnapi, data, len, dma_addr); |
| 1144 | bnxt_reuse_rx_data(rxr, cons, data); |
| 1145 | if (!skb) { |
| 1146 | rc = -ENOMEM; |
| 1147 | goto next_rx; |
| 1148 | } |
| 1149 | } else { |
| 1150 | skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len); |
| 1151 | if (!skb) { |
| 1152 | rc = -ENOMEM; |
| 1153 | goto next_rx; |
| 1154 | } |
| 1155 | } |
| 1156 | |
| 1157 | if (agg_bufs) { |
| 1158 | skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs); |
| 1159 | if (!skb) { |
| 1160 | rc = -ENOMEM; |
| 1161 | goto next_rx; |
| 1162 | } |
| 1163 | } |
| 1164 | |
| 1165 | if (RX_CMP_HASH_VALID(rxcmp)) { |
| 1166 | u32 hash_type = RX_CMP_HASH_TYPE(rxcmp); |
| 1167 | enum pkt_hash_types type = PKT_HASH_TYPE_L4; |
| 1168 | |
| 1169 | /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */ |
| 1170 | if (hash_type != 1 && hash_type != 3) |
| 1171 | type = PKT_HASH_TYPE_L3; |
| 1172 | skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type); |
| 1173 | } |
| 1174 | |
| 1175 | skb->protocol = eth_type_trans(skb, dev); |
| 1176 | |
| 1177 | if (rxcmp1->rx_cmp_flags2 & |
| 1178 | cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) { |
| 1179 | netdev_features_t features = skb->dev->features; |
| 1180 | u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data); |
| 1181 | u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT; |
| 1182 | |
| 1183 | if (((features & NETIF_F_HW_VLAN_CTAG_RX) && |
| 1184 | vlan_proto == ETH_P_8021Q) || |
| 1185 | ((features & NETIF_F_HW_VLAN_STAG_RX) && |
| 1186 | vlan_proto == ETH_P_8021AD)) |
| 1187 | __vlan_hwaccel_put_tag(skb, htons(vlan_proto), |
| 1188 | meta_data & |
| 1189 | RX_CMP_FLAGS2_METADATA_VID_MASK); |
| 1190 | } |
| 1191 | |
| 1192 | skb_checksum_none_assert(skb); |
| 1193 | if (RX_CMP_L4_CS_OK(rxcmp1)) { |
| 1194 | if (dev->features & NETIF_F_RXCSUM) { |
| 1195 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
| 1196 | skb->csum_level = RX_CMP_ENCAP(rxcmp1); |
| 1197 | } |
| 1198 | } else { |
Satish Baddipadige | 665e350 | 2015-12-27 18:19:21 -0500 | [diff] [blame] | 1199 | if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) { |
| 1200 | if (dev->features & NETIF_F_RXCSUM) |
| 1201 | cpr->rx_l4_csum_errors++; |
| 1202 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1203 | } |
| 1204 | |
| 1205 | skb_record_rx_queue(skb, bnapi->index); |
| 1206 | skb_mark_napi_id(skb, &bnapi->napi); |
| 1207 | if (bnxt_busy_polling(bnapi)) |
| 1208 | netif_receive_skb(skb); |
| 1209 | else |
| 1210 | napi_gro_receive(&bnapi->napi, skb); |
| 1211 | rc = 1; |
| 1212 | |
| 1213 | next_rx: |
| 1214 | rxr->rx_prod = NEXT_RX(prod); |
| 1215 | |
| 1216 | next_rx_no_prod: |
| 1217 | *raw_cons = tmp_raw_cons; |
| 1218 | |
| 1219 | return rc; |
| 1220 | } |
| 1221 | |
| 1222 | static int bnxt_async_event_process(struct bnxt *bp, |
| 1223 | struct hwrm_async_event_cmpl *cmpl) |
| 1224 | { |
| 1225 | u16 event_id = le16_to_cpu(cmpl->event_id); |
| 1226 | |
| 1227 | /* TODO CHIMP_FW: Define event id's for link change, error etc */ |
| 1228 | switch (event_id) { |
| 1229 | case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE: |
| 1230 | set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event); |
| 1231 | schedule_work(&bp->sp_task); |
| 1232 | break; |
| 1233 | default: |
| 1234 | netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n", |
| 1235 | event_id); |
| 1236 | break; |
| 1237 | } |
| 1238 | return 0; |
| 1239 | } |
| 1240 | |
| 1241 | static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp) |
| 1242 | { |
| 1243 | u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id; |
| 1244 | struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp; |
| 1245 | struct hwrm_fwd_req_cmpl *fwd_req_cmpl = |
| 1246 | (struct hwrm_fwd_req_cmpl *)txcmp; |
| 1247 | |
| 1248 | switch (cmpl_type) { |
| 1249 | case CMPL_BASE_TYPE_HWRM_DONE: |
| 1250 | seq_id = le16_to_cpu(h_cmpl->sequence_id); |
| 1251 | if (seq_id == bp->hwrm_intr_seq_id) |
| 1252 | bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID; |
| 1253 | else |
| 1254 | netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id); |
| 1255 | break; |
| 1256 | |
| 1257 | case CMPL_BASE_TYPE_HWRM_FWD_REQ: |
| 1258 | vf_id = le16_to_cpu(fwd_req_cmpl->source_id); |
| 1259 | |
| 1260 | if ((vf_id < bp->pf.first_vf_id) || |
| 1261 | (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) { |
| 1262 | netdev_err(bp->dev, "Msg contains invalid VF id %x\n", |
| 1263 | vf_id); |
| 1264 | return -EINVAL; |
| 1265 | } |
| 1266 | |
| 1267 | set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap); |
| 1268 | set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event); |
| 1269 | schedule_work(&bp->sp_task); |
| 1270 | break; |
| 1271 | |
| 1272 | case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT: |
| 1273 | bnxt_async_event_process(bp, |
| 1274 | (struct hwrm_async_event_cmpl *)txcmp); |
| 1275 | |
| 1276 | default: |
| 1277 | break; |
| 1278 | } |
| 1279 | |
| 1280 | return 0; |
| 1281 | } |
| 1282 | |
| 1283 | static irqreturn_t bnxt_msix(int irq, void *dev_instance) |
| 1284 | { |
| 1285 | struct bnxt_napi *bnapi = dev_instance; |
| 1286 | struct bnxt *bp = bnapi->bp; |
| 1287 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1288 | u32 cons = RING_CMP(cpr->cp_raw_cons); |
| 1289 | |
| 1290 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
| 1291 | napi_schedule(&bnapi->napi); |
| 1292 | return IRQ_HANDLED; |
| 1293 | } |
| 1294 | |
| 1295 | static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr) |
| 1296 | { |
| 1297 | u32 raw_cons = cpr->cp_raw_cons; |
| 1298 | u16 cons = RING_CMP(raw_cons); |
| 1299 | struct tx_cmp *txcmp; |
| 1300 | |
| 1301 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; |
| 1302 | |
| 1303 | return TX_CMP_VALID(txcmp, raw_cons); |
| 1304 | } |
| 1305 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1306 | static irqreturn_t bnxt_inta(int irq, void *dev_instance) |
| 1307 | { |
| 1308 | struct bnxt_napi *bnapi = dev_instance; |
| 1309 | struct bnxt *bp = bnapi->bp; |
| 1310 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1311 | u32 cons = RING_CMP(cpr->cp_raw_cons); |
| 1312 | u32 int_status; |
| 1313 | |
| 1314 | prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]); |
| 1315 | |
| 1316 | if (!bnxt_has_work(bp, cpr)) { |
Jeffrey Huang | 1180949 | 2015-11-05 16:25:49 -0500 | [diff] [blame] | 1317 | int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1318 | /* return if erroneous interrupt */ |
| 1319 | if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id))) |
| 1320 | return IRQ_NONE; |
| 1321 | } |
| 1322 | |
| 1323 | /* disable ring IRQ */ |
| 1324 | BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell); |
| 1325 | |
| 1326 | /* Return here if interrupt is shared and is disabled. */ |
| 1327 | if (unlikely(atomic_read(&bp->intr_sem) != 0)) |
| 1328 | return IRQ_HANDLED; |
| 1329 | |
| 1330 | napi_schedule(&bnapi->napi); |
| 1331 | return IRQ_HANDLED; |
| 1332 | } |
| 1333 | |
| 1334 | static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget) |
| 1335 | { |
| 1336 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1337 | u32 raw_cons = cpr->cp_raw_cons; |
| 1338 | u32 cons; |
| 1339 | int tx_pkts = 0; |
| 1340 | int rx_pkts = 0; |
| 1341 | bool rx_event = false; |
| 1342 | bool agg_event = false; |
| 1343 | struct tx_cmp *txcmp; |
| 1344 | |
| 1345 | while (1) { |
| 1346 | int rc; |
| 1347 | |
| 1348 | cons = RING_CMP(raw_cons); |
| 1349 | txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]; |
| 1350 | |
| 1351 | if (!TX_CMP_VALID(txcmp, raw_cons)) |
| 1352 | break; |
| 1353 | |
| 1354 | if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) { |
| 1355 | tx_pkts++; |
| 1356 | /* return full budget so NAPI will complete. */ |
| 1357 | if (unlikely(tx_pkts > bp->tx_wake_thresh)) |
| 1358 | rx_pkts = budget; |
| 1359 | } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) { |
| 1360 | rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event); |
| 1361 | if (likely(rc >= 0)) |
| 1362 | rx_pkts += rc; |
| 1363 | else if (rc == -EBUSY) /* partial completion */ |
| 1364 | break; |
| 1365 | rx_event = true; |
| 1366 | } else if (unlikely((TX_CMP_TYPE(txcmp) == |
| 1367 | CMPL_BASE_TYPE_HWRM_DONE) || |
| 1368 | (TX_CMP_TYPE(txcmp) == |
| 1369 | CMPL_BASE_TYPE_HWRM_FWD_REQ) || |
| 1370 | (TX_CMP_TYPE(txcmp) == |
| 1371 | CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) { |
| 1372 | bnxt_hwrm_handler(bp, txcmp); |
| 1373 | } |
| 1374 | raw_cons = NEXT_RAW_CMP(raw_cons); |
| 1375 | |
| 1376 | if (rx_pkts == budget) |
| 1377 | break; |
| 1378 | } |
| 1379 | |
| 1380 | cpr->cp_raw_cons = raw_cons; |
| 1381 | /* ACK completion ring before freeing tx ring and producing new |
| 1382 | * buffers in rx/agg rings to prevent overflowing the completion |
| 1383 | * ring. |
| 1384 | */ |
| 1385 | BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 1386 | |
| 1387 | if (tx_pkts) |
| 1388 | bnxt_tx_int(bp, bnapi, tx_pkts); |
| 1389 | |
| 1390 | if (rx_event) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1391 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1392 | |
| 1393 | writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); |
| 1394 | writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); |
| 1395 | if (agg_event) { |
| 1396 | writel(DB_KEY_RX | rxr->rx_agg_prod, |
| 1397 | rxr->rx_agg_doorbell); |
| 1398 | writel(DB_KEY_RX | rxr->rx_agg_prod, |
| 1399 | rxr->rx_agg_doorbell); |
| 1400 | } |
| 1401 | } |
| 1402 | return rx_pkts; |
| 1403 | } |
| 1404 | |
| 1405 | static int bnxt_poll(struct napi_struct *napi, int budget) |
| 1406 | { |
| 1407 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); |
| 1408 | struct bnxt *bp = bnapi->bp; |
| 1409 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1410 | int work_done = 0; |
| 1411 | |
| 1412 | if (!bnxt_lock_napi(bnapi)) |
| 1413 | return budget; |
| 1414 | |
| 1415 | while (1) { |
| 1416 | work_done += bnxt_poll_work(bp, bnapi, budget - work_done); |
| 1417 | |
| 1418 | if (work_done >= budget) |
| 1419 | break; |
| 1420 | |
| 1421 | if (!bnxt_has_work(bp, cpr)) { |
| 1422 | napi_complete(napi); |
| 1423 | BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 1424 | break; |
| 1425 | } |
| 1426 | } |
| 1427 | mmiowb(); |
| 1428 | bnxt_unlock_napi(bnapi); |
| 1429 | return work_done; |
| 1430 | } |
| 1431 | |
| 1432 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 1433 | static int bnxt_busy_poll(struct napi_struct *napi) |
| 1434 | { |
| 1435 | struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi); |
| 1436 | struct bnxt *bp = bnapi->bp; |
| 1437 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 1438 | int rx_work, budget = 4; |
| 1439 | |
| 1440 | if (atomic_read(&bp->intr_sem) != 0) |
| 1441 | return LL_FLUSH_FAILED; |
| 1442 | |
| 1443 | if (!bnxt_lock_poll(bnapi)) |
| 1444 | return LL_FLUSH_BUSY; |
| 1445 | |
| 1446 | rx_work = bnxt_poll_work(bp, bnapi, budget); |
| 1447 | |
| 1448 | BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 1449 | |
| 1450 | bnxt_unlock_poll(bnapi); |
| 1451 | return rx_work; |
| 1452 | } |
| 1453 | #endif |
| 1454 | |
| 1455 | static void bnxt_free_tx_skbs(struct bnxt *bp) |
| 1456 | { |
| 1457 | int i, max_idx; |
| 1458 | struct pci_dev *pdev = bp->pdev; |
| 1459 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1460 | if (!bp->tx_ring) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1461 | return; |
| 1462 | |
| 1463 | max_idx = bp->tx_nr_pages * TX_DESC_CNT; |
| 1464 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1465 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1466 | int j; |
| 1467 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1468 | for (j = 0; j < max_idx;) { |
| 1469 | struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j]; |
| 1470 | struct sk_buff *skb = tx_buf->skb; |
| 1471 | int k, last; |
| 1472 | |
| 1473 | if (!skb) { |
| 1474 | j++; |
| 1475 | continue; |
| 1476 | } |
| 1477 | |
| 1478 | tx_buf->skb = NULL; |
| 1479 | |
| 1480 | if (tx_buf->is_push) { |
| 1481 | dev_kfree_skb(skb); |
| 1482 | j += 2; |
| 1483 | continue; |
| 1484 | } |
| 1485 | |
| 1486 | dma_unmap_single(&pdev->dev, |
| 1487 | dma_unmap_addr(tx_buf, mapping), |
| 1488 | skb_headlen(skb), |
| 1489 | PCI_DMA_TODEVICE); |
| 1490 | |
| 1491 | last = tx_buf->nr_frags; |
| 1492 | j += 2; |
| 1493 | for (k = 0; k < last; k++, j = NEXT_TX(j)) { |
| 1494 | skb_frag_t *frag = &skb_shinfo(skb)->frags[k]; |
| 1495 | |
| 1496 | tx_buf = &txr->tx_buf_ring[j]; |
| 1497 | dma_unmap_page( |
| 1498 | &pdev->dev, |
| 1499 | dma_unmap_addr(tx_buf, mapping), |
| 1500 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
| 1501 | } |
| 1502 | dev_kfree_skb(skb); |
| 1503 | } |
| 1504 | netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i)); |
| 1505 | } |
| 1506 | } |
| 1507 | |
| 1508 | static void bnxt_free_rx_skbs(struct bnxt *bp) |
| 1509 | { |
| 1510 | int i, max_idx, max_agg_idx; |
| 1511 | struct pci_dev *pdev = bp->pdev; |
| 1512 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1513 | if (!bp->rx_ring) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1514 | return; |
| 1515 | |
| 1516 | max_idx = bp->rx_nr_pages * RX_DESC_CNT; |
| 1517 | max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT; |
| 1518 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1519 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1520 | int j; |
| 1521 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1522 | if (rxr->rx_tpa) { |
| 1523 | for (j = 0; j < MAX_TPA; j++) { |
| 1524 | struct bnxt_tpa_info *tpa_info = |
| 1525 | &rxr->rx_tpa[j]; |
| 1526 | u8 *data = tpa_info->data; |
| 1527 | |
| 1528 | if (!data) |
| 1529 | continue; |
| 1530 | |
| 1531 | dma_unmap_single( |
| 1532 | &pdev->dev, |
| 1533 | dma_unmap_addr(tpa_info, mapping), |
| 1534 | bp->rx_buf_use_size, |
| 1535 | PCI_DMA_FROMDEVICE); |
| 1536 | |
| 1537 | tpa_info->data = NULL; |
| 1538 | |
| 1539 | kfree(data); |
| 1540 | } |
| 1541 | } |
| 1542 | |
| 1543 | for (j = 0; j < max_idx; j++) { |
| 1544 | struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j]; |
| 1545 | u8 *data = rx_buf->data; |
| 1546 | |
| 1547 | if (!data) |
| 1548 | continue; |
| 1549 | |
| 1550 | dma_unmap_single(&pdev->dev, |
| 1551 | dma_unmap_addr(rx_buf, mapping), |
| 1552 | bp->rx_buf_use_size, |
| 1553 | PCI_DMA_FROMDEVICE); |
| 1554 | |
| 1555 | rx_buf->data = NULL; |
| 1556 | |
| 1557 | kfree(data); |
| 1558 | } |
| 1559 | |
| 1560 | for (j = 0; j < max_agg_idx; j++) { |
| 1561 | struct bnxt_sw_rx_agg_bd *rx_agg_buf = |
| 1562 | &rxr->rx_agg_ring[j]; |
| 1563 | struct page *page = rx_agg_buf->page; |
| 1564 | |
| 1565 | if (!page) |
| 1566 | continue; |
| 1567 | |
| 1568 | dma_unmap_page(&pdev->dev, |
| 1569 | dma_unmap_addr(rx_agg_buf, mapping), |
| 1570 | PAGE_SIZE, PCI_DMA_FROMDEVICE); |
| 1571 | |
| 1572 | rx_agg_buf->page = NULL; |
| 1573 | __clear_bit(j, rxr->rx_agg_bmap); |
| 1574 | |
| 1575 | __free_page(page); |
| 1576 | } |
| 1577 | } |
| 1578 | } |
| 1579 | |
| 1580 | static void bnxt_free_skbs(struct bnxt *bp) |
| 1581 | { |
| 1582 | bnxt_free_tx_skbs(bp); |
| 1583 | bnxt_free_rx_skbs(bp); |
| 1584 | } |
| 1585 | |
| 1586 | static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) |
| 1587 | { |
| 1588 | struct pci_dev *pdev = bp->pdev; |
| 1589 | int i; |
| 1590 | |
| 1591 | for (i = 0; i < ring->nr_pages; i++) { |
| 1592 | if (!ring->pg_arr[i]) |
| 1593 | continue; |
| 1594 | |
| 1595 | dma_free_coherent(&pdev->dev, ring->page_size, |
| 1596 | ring->pg_arr[i], ring->dma_arr[i]); |
| 1597 | |
| 1598 | ring->pg_arr[i] = NULL; |
| 1599 | } |
| 1600 | if (ring->pg_tbl) { |
| 1601 | dma_free_coherent(&pdev->dev, ring->nr_pages * 8, |
| 1602 | ring->pg_tbl, ring->pg_tbl_map); |
| 1603 | ring->pg_tbl = NULL; |
| 1604 | } |
| 1605 | if (ring->vmem_size && *ring->vmem) { |
| 1606 | vfree(*ring->vmem); |
| 1607 | *ring->vmem = NULL; |
| 1608 | } |
| 1609 | } |
| 1610 | |
| 1611 | static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring) |
| 1612 | { |
| 1613 | int i; |
| 1614 | struct pci_dev *pdev = bp->pdev; |
| 1615 | |
| 1616 | if (ring->nr_pages > 1) { |
| 1617 | ring->pg_tbl = dma_alloc_coherent(&pdev->dev, |
| 1618 | ring->nr_pages * 8, |
| 1619 | &ring->pg_tbl_map, |
| 1620 | GFP_KERNEL); |
| 1621 | if (!ring->pg_tbl) |
| 1622 | return -ENOMEM; |
| 1623 | } |
| 1624 | |
| 1625 | for (i = 0; i < ring->nr_pages; i++) { |
| 1626 | ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev, |
| 1627 | ring->page_size, |
| 1628 | &ring->dma_arr[i], |
| 1629 | GFP_KERNEL); |
| 1630 | if (!ring->pg_arr[i]) |
| 1631 | return -ENOMEM; |
| 1632 | |
| 1633 | if (ring->nr_pages > 1) |
| 1634 | ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]); |
| 1635 | } |
| 1636 | |
| 1637 | if (ring->vmem_size) { |
| 1638 | *ring->vmem = vzalloc(ring->vmem_size); |
| 1639 | if (!(*ring->vmem)) |
| 1640 | return -ENOMEM; |
| 1641 | } |
| 1642 | return 0; |
| 1643 | } |
| 1644 | |
| 1645 | static void bnxt_free_rx_rings(struct bnxt *bp) |
| 1646 | { |
| 1647 | int i; |
| 1648 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1649 | if (!bp->rx_ring) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1650 | return; |
| 1651 | |
| 1652 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1653 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1654 | struct bnxt_ring_struct *ring; |
| 1655 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1656 | kfree(rxr->rx_tpa); |
| 1657 | rxr->rx_tpa = NULL; |
| 1658 | |
| 1659 | kfree(rxr->rx_agg_bmap); |
| 1660 | rxr->rx_agg_bmap = NULL; |
| 1661 | |
| 1662 | ring = &rxr->rx_ring_struct; |
| 1663 | bnxt_free_ring(bp, ring); |
| 1664 | |
| 1665 | ring = &rxr->rx_agg_ring_struct; |
| 1666 | bnxt_free_ring(bp, ring); |
| 1667 | } |
| 1668 | } |
| 1669 | |
| 1670 | static int bnxt_alloc_rx_rings(struct bnxt *bp) |
| 1671 | { |
| 1672 | int i, rc, agg_rings = 0, tpa_rings = 0; |
| 1673 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1674 | if (!bp->rx_ring) |
| 1675 | return -ENOMEM; |
| 1676 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1677 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
| 1678 | agg_rings = 1; |
| 1679 | |
| 1680 | if (bp->flags & BNXT_FLAG_TPA) |
| 1681 | tpa_rings = 1; |
| 1682 | |
| 1683 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1684 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1685 | struct bnxt_ring_struct *ring; |
| 1686 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1687 | ring = &rxr->rx_ring_struct; |
| 1688 | |
| 1689 | rc = bnxt_alloc_ring(bp, ring); |
| 1690 | if (rc) |
| 1691 | return rc; |
| 1692 | |
| 1693 | if (agg_rings) { |
| 1694 | u16 mem_size; |
| 1695 | |
| 1696 | ring = &rxr->rx_agg_ring_struct; |
| 1697 | rc = bnxt_alloc_ring(bp, ring); |
| 1698 | if (rc) |
| 1699 | return rc; |
| 1700 | |
| 1701 | rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1; |
| 1702 | mem_size = rxr->rx_agg_bmap_size / 8; |
| 1703 | rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL); |
| 1704 | if (!rxr->rx_agg_bmap) |
| 1705 | return -ENOMEM; |
| 1706 | |
| 1707 | if (tpa_rings) { |
| 1708 | rxr->rx_tpa = kcalloc(MAX_TPA, |
| 1709 | sizeof(struct bnxt_tpa_info), |
| 1710 | GFP_KERNEL); |
| 1711 | if (!rxr->rx_tpa) |
| 1712 | return -ENOMEM; |
| 1713 | } |
| 1714 | } |
| 1715 | } |
| 1716 | return 0; |
| 1717 | } |
| 1718 | |
| 1719 | static void bnxt_free_tx_rings(struct bnxt *bp) |
| 1720 | { |
| 1721 | int i; |
| 1722 | struct pci_dev *pdev = bp->pdev; |
| 1723 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1724 | if (!bp->tx_ring) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1725 | return; |
| 1726 | |
| 1727 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1728 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1729 | struct bnxt_ring_struct *ring; |
| 1730 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1731 | if (txr->tx_push) { |
| 1732 | dma_free_coherent(&pdev->dev, bp->tx_push_size, |
| 1733 | txr->tx_push, txr->tx_push_mapping); |
| 1734 | txr->tx_push = NULL; |
| 1735 | } |
| 1736 | |
| 1737 | ring = &txr->tx_ring_struct; |
| 1738 | |
| 1739 | bnxt_free_ring(bp, ring); |
| 1740 | } |
| 1741 | } |
| 1742 | |
| 1743 | static int bnxt_alloc_tx_rings(struct bnxt *bp) |
| 1744 | { |
| 1745 | int i, j, rc; |
| 1746 | struct pci_dev *pdev = bp->pdev; |
| 1747 | |
| 1748 | bp->tx_push_size = 0; |
| 1749 | if (bp->tx_push_thresh) { |
| 1750 | int push_size; |
| 1751 | |
| 1752 | push_size = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) + |
| 1753 | bp->tx_push_thresh); |
| 1754 | |
| 1755 | if (push_size > 128) { |
| 1756 | push_size = 0; |
| 1757 | bp->tx_push_thresh = 0; |
| 1758 | } |
| 1759 | |
| 1760 | bp->tx_push_size = push_size; |
| 1761 | } |
| 1762 | |
| 1763 | for (i = 0, j = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1764 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1765 | struct bnxt_ring_struct *ring; |
| 1766 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1767 | ring = &txr->tx_ring_struct; |
| 1768 | |
| 1769 | rc = bnxt_alloc_ring(bp, ring); |
| 1770 | if (rc) |
| 1771 | return rc; |
| 1772 | |
| 1773 | if (bp->tx_push_size) { |
| 1774 | struct tx_bd *txbd; |
| 1775 | dma_addr_t mapping; |
| 1776 | |
| 1777 | /* One pre-allocated DMA buffer to backup |
| 1778 | * TX push operation |
| 1779 | */ |
| 1780 | txr->tx_push = dma_alloc_coherent(&pdev->dev, |
| 1781 | bp->tx_push_size, |
| 1782 | &txr->tx_push_mapping, |
| 1783 | GFP_KERNEL); |
| 1784 | |
| 1785 | if (!txr->tx_push) |
| 1786 | return -ENOMEM; |
| 1787 | |
| 1788 | txbd = &txr->tx_push->txbd1; |
| 1789 | |
| 1790 | mapping = txr->tx_push_mapping + |
| 1791 | sizeof(struct tx_push_bd); |
| 1792 | txbd->tx_bd_haddr = cpu_to_le64(mapping); |
| 1793 | |
| 1794 | memset(txbd + 1, 0, sizeof(struct tx_bd_ext)); |
| 1795 | } |
| 1796 | ring->queue_id = bp->q_info[j].queue_id; |
| 1797 | if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1)) |
| 1798 | j++; |
| 1799 | } |
| 1800 | return 0; |
| 1801 | } |
| 1802 | |
| 1803 | static void bnxt_free_cp_rings(struct bnxt *bp) |
| 1804 | { |
| 1805 | int i; |
| 1806 | |
| 1807 | if (!bp->bnapi) |
| 1808 | return; |
| 1809 | |
| 1810 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 1811 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 1812 | struct bnxt_cp_ring_info *cpr; |
| 1813 | struct bnxt_ring_struct *ring; |
| 1814 | |
| 1815 | if (!bnapi) |
| 1816 | continue; |
| 1817 | |
| 1818 | cpr = &bnapi->cp_ring; |
| 1819 | ring = &cpr->cp_ring_struct; |
| 1820 | |
| 1821 | bnxt_free_ring(bp, ring); |
| 1822 | } |
| 1823 | } |
| 1824 | |
| 1825 | static int bnxt_alloc_cp_rings(struct bnxt *bp) |
| 1826 | { |
| 1827 | int i, rc; |
| 1828 | |
| 1829 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 1830 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 1831 | struct bnxt_cp_ring_info *cpr; |
| 1832 | struct bnxt_ring_struct *ring; |
| 1833 | |
| 1834 | if (!bnapi) |
| 1835 | continue; |
| 1836 | |
| 1837 | cpr = &bnapi->cp_ring; |
| 1838 | ring = &cpr->cp_ring_struct; |
| 1839 | |
| 1840 | rc = bnxt_alloc_ring(bp, ring); |
| 1841 | if (rc) |
| 1842 | return rc; |
| 1843 | } |
| 1844 | return 0; |
| 1845 | } |
| 1846 | |
| 1847 | static void bnxt_init_ring_struct(struct bnxt *bp) |
| 1848 | { |
| 1849 | int i; |
| 1850 | |
| 1851 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 1852 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 1853 | struct bnxt_cp_ring_info *cpr; |
| 1854 | struct bnxt_rx_ring_info *rxr; |
| 1855 | struct bnxt_tx_ring_info *txr; |
| 1856 | struct bnxt_ring_struct *ring; |
| 1857 | |
| 1858 | if (!bnapi) |
| 1859 | continue; |
| 1860 | |
| 1861 | cpr = &bnapi->cp_ring; |
| 1862 | ring = &cpr->cp_ring_struct; |
| 1863 | ring->nr_pages = bp->cp_nr_pages; |
| 1864 | ring->page_size = HW_CMPD_RING_SIZE; |
| 1865 | ring->pg_arr = (void **)cpr->cp_desc_ring; |
| 1866 | ring->dma_arr = cpr->cp_desc_mapping; |
| 1867 | ring->vmem_size = 0; |
| 1868 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1869 | rxr = bnapi->rx_ring; |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 1870 | if (!rxr) |
| 1871 | goto skip_rx; |
| 1872 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1873 | ring = &rxr->rx_ring_struct; |
| 1874 | ring->nr_pages = bp->rx_nr_pages; |
| 1875 | ring->page_size = HW_RXBD_RING_SIZE; |
| 1876 | ring->pg_arr = (void **)rxr->rx_desc_ring; |
| 1877 | ring->dma_arr = rxr->rx_desc_mapping; |
| 1878 | ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages; |
| 1879 | ring->vmem = (void **)&rxr->rx_buf_ring; |
| 1880 | |
| 1881 | ring = &rxr->rx_agg_ring_struct; |
| 1882 | ring->nr_pages = bp->rx_agg_nr_pages; |
| 1883 | ring->page_size = HW_RXBD_RING_SIZE; |
| 1884 | ring->pg_arr = (void **)rxr->rx_agg_desc_ring; |
| 1885 | ring->dma_arr = rxr->rx_agg_desc_mapping; |
| 1886 | ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages; |
| 1887 | ring->vmem = (void **)&rxr->rx_agg_ring; |
| 1888 | |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 1889 | skip_rx: |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1890 | txr = bnapi->tx_ring; |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 1891 | if (!txr) |
| 1892 | continue; |
| 1893 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1894 | ring = &txr->tx_ring_struct; |
| 1895 | ring->nr_pages = bp->tx_nr_pages; |
| 1896 | ring->page_size = HW_RXBD_RING_SIZE; |
| 1897 | ring->pg_arr = (void **)txr->tx_desc_ring; |
| 1898 | ring->dma_arr = txr->tx_desc_mapping; |
| 1899 | ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages; |
| 1900 | ring->vmem = (void **)&txr->tx_buf_ring; |
| 1901 | } |
| 1902 | } |
| 1903 | |
| 1904 | static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type) |
| 1905 | { |
| 1906 | int i; |
| 1907 | u32 prod; |
| 1908 | struct rx_bd **rx_buf_ring; |
| 1909 | |
| 1910 | rx_buf_ring = (struct rx_bd **)ring->pg_arr; |
| 1911 | for (i = 0, prod = 0; i < ring->nr_pages; i++) { |
| 1912 | int j; |
| 1913 | struct rx_bd *rxbd; |
| 1914 | |
| 1915 | rxbd = rx_buf_ring[i]; |
| 1916 | if (!rxbd) |
| 1917 | continue; |
| 1918 | |
| 1919 | for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) { |
| 1920 | rxbd->rx_bd_len_flags_type = cpu_to_le32(type); |
| 1921 | rxbd->rx_bd_opaque = prod; |
| 1922 | } |
| 1923 | } |
| 1924 | } |
| 1925 | |
| 1926 | static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr) |
| 1927 | { |
| 1928 | struct net_device *dev = bp->dev; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1929 | struct bnxt_rx_ring_info *rxr; |
| 1930 | struct bnxt_ring_struct *ring; |
| 1931 | u32 prod, type; |
| 1932 | int i; |
| 1933 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1934 | type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) | |
| 1935 | RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP; |
| 1936 | |
| 1937 | if (NET_IP_ALIGN == 2) |
| 1938 | type |= RX_BD_FLAGS_SOP; |
| 1939 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 1940 | rxr = &bp->rx_ring[ring_nr]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1941 | ring = &rxr->rx_ring_struct; |
| 1942 | bnxt_init_rxbd_pages(ring, type); |
| 1943 | |
| 1944 | prod = rxr->rx_prod; |
| 1945 | for (i = 0; i < bp->rx_ring_size; i++) { |
| 1946 | if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) { |
| 1947 | netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n", |
| 1948 | ring_nr, i, bp->rx_ring_size); |
| 1949 | break; |
| 1950 | } |
| 1951 | prod = NEXT_RX(prod); |
| 1952 | } |
| 1953 | rxr->rx_prod = prod; |
| 1954 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| 1955 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 1956 | ring = &rxr->rx_agg_ring_struct; |
| 1957 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| 1958 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1959 | if (!(bp->flags & BNXT_FLAG_AGG_RINGS)) |
| 1960 | return 0; |
| 1961 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1962 | type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) | |
| 1963 | RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP; |
| 1964 | |
| 1965 | bnxt_init_rxbd_pages(ring, type); |
| 1966 | |
| 1967 | prod = rxr->rx_agg_prod; |
| 1968 | for (i = 0; i < bp->rx_agg_ring_size; i++) { |
| 1969 | if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) { |
| 1970 | netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n", |
| 1971 | ring_nr, i, bp->rx_ring_size); |
| 1972 | break; |
| 1973 | } |
| 1974 | prod = NEXT_RX_AGG(prod); |
| 1975 | } |
| 1976 | rxr->rx_agg_prod = prod; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 1977 | |
| 1978 | if (bp->flags & BNXT_FLAG_TPA) { |
| 1979 | if (rxr->rx_tpa) { |
| 1980 | u8 *data; |
| 1981 | dma_addr_t mapping; |
| 1982 | |
| 1983 | for (i = 0; i < MAX_TPA; i++) { |
| 1984 | data = __bnxt_alloc_rx_data(bp, &mapping, |
| 1985 | GFP_KERNEL); |
| 1986 | if (!data) |
| 1987 | return -ENOMEM; |
| 1988 | |
| 1989 | rxr->rx_tpa[i].data = data; |
| 1990 | rxr->rx_tpa[i].mapping = mapping; |
| 1991 | } |
| 1992 | } else { |
| 1993 | netdev_err(bp->dev, "No resource allocated for LRO/GRO\n"); |
| 1994 | return -ENOMEM; |
| 1995 | } |
| 1996 | } |
| 1997 | |
| 1998 | return 0; |
| 1999 | } |
| 2000 | |
| 2001 | static int bnxt_init_rx_rings(struct bnxt *bp) |
| 2002 | { |
| 2003 | int i, rc = 0; |
| 2004 | |
| 2005 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 2006 | rc = bnxt_init_one_rx_ring(bp, i); |
| 2007 | if (rc) |
| 2008 | break; |
| 2009 | } |
| 2010 | |
| 2011 | return rc; |
| 2012 | } |
| 2013 | |
| 2014 | static int bnxt_init_tx_rings(struct bnxt *bp) |
| 2015 | { |
| 2016 | u16 i; |
| 2017 | |
| 2018 | bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2, |
| 2019 | MAX_SKB_FRAGS + 1); |
| 2020 | |
| 2021 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2022 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2023 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
| 2024 | |
| 2025 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| 2026 | } |
| 2027 | |
| 2028 | return 0; |
| 2029 | } |
| 2030 | |
| 2031 | static void bnxt_free_ring_grps(struct bnxt *bp) |
| 2032 | { |
| 2033 | kfree(bp->grp_info); |
| 2034 | bp->grp_info = NULL; |
| 2035 | } |
| 2036 | |
| 2037 | static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init) |
| 2038 | { |
| 2039 | int i; |
| 2040 | |
| 2041 | if (irq_re_init) { |
| 2042 | bp->grp_info = kcalloc(bp->cp_nr_rings, |
| 2043 | sizeof(struct bnxt_ring_grp_info), |
| 2044 | GFP_KERNEL); |
| 2045 | if (!bp->grp_info) |
| 2046 | return -ENOMEM; |
| 2047 | } |
| 2048 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 2049 | if (irq_re_init) |
| 2050 | bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID; |
| 2051 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
| 2052 | bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID; |
| 2053 | bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID; |
| 2054 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; |
| 2055 | } |
| 2056 | return 0; |
| 2057 | } |
| 2058 | |
| 2059 | static void bnxt_free_vnics(struct bnxt *bp) |
| 2060 | { |
| 2061 | kfree(bp->vnic_info); |
| 2062 | bp->vnic_info = NULL; |
| 2063 | bp->nr_vnics = 0; |
| 2064 | } |
| 2065 | |
| 2066 | static int bnxt_alloc_vnics(struct bnxt *bp) |
| 2067 | { |
| 2068 | int num_vnics = 1; |
| 2069 | |
| 2070 | #ifdef CONFIG_RFS_ACCEL |
| 2071 | if (bp->flags & BNXT_FLAG_RFS) |
| 2072 | num_vnics += bp->rx_nr_rings; |
| 2073 | #endif |
| 2074 | |
| 2075 | bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info), |
| 2076 | GFP_KERNEL); |
| 2077 | if (!bp->vnic_info) |
| 2078 | return -ENOMEM; |
| 2079 | |
| 2080 | bp->nr_vnics = num_vnics; |
| 2081 | return 0; |
| 2082 | } |
| 2083 | |
| 2084 | static void bnxt_init_vnics(struct bnxt *bp) |
| 2085 | { |
| 2086 | int i; |
| 2087 | |
| 2088 | for (i = 0; i < bp->nr_vnics; i++) { |
| 2089 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; |
| 2090 | |
| 2091 | vnic->fw_vnic_id = INVALID_HW_RING_ID; |
| 2092 | vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; |
| 2093 | vnic->fw_l2_ctx_id = INVALID_HW_RING_ID; |
| 2094 | |
| 2095 | if (bp->vnic_info[i].rss_hash_key) { |
| 2096 | if (i == 0) |
| 2097 | prandom_bytes(vnic->rss_hash_key, |
| 2098 | HW_HASH_KEY_SIZE); |
| 2099 | else |
| 2100 | memcpy(vnic->rss_hash_key, |
| 2101 | bp->vnic_info[0].rss_hash_key, |
| 2102 | HW_HASH_KEY_SIZE); |
| 2103 | } |
| 2104 | } |
| 2105 | } |
| 2106 | |
| 2107 | static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg) |
| 2108 | { |
| 2109 | int pages; |
| 2110 | |
| 2111 | pages = ring_size / desc_per_pg; |
| 2112 | |
| 2113 | if (!pages) |
| 2114 | return 1; |
| 2115 | |
| 2116 | pages++; |
| 2117 | |
| 2118 | while (pages & (pages - 1)) |
| 2119 | pages++; |
| 2120 | |
| 2121 | return pages; |
| 2122 | } |
| 2123 | |
| 2124 | static void bnxt_set_tpa_flags(struct bnxt *bp) |
| 2125 | { |
| 2126 | bp->flags &= ~BNXT_FLAG_TPA; |
| 2127 | if (bp->dev->features & NETIF_F_LRO) |
| 2128 | bp->flags |= BNXT_FLAG_LRO; |
| 2129 | if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0)) |
| 2130 | bp->flags |= BNXT_FLAG_GRO; |
| 2131 | } |
| 2132 | |
| 2133 | /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must |
| 2134 | * be set on entry. |
| 2135 | */ |
| 2136 | void bnxt_set_ring_params(struct bnxt *bp) |
| 2137 | { |
| 2138 | u32 ring_size, rx_size, rx_space; |
| 2139 | u32 agg_factor = 0, agg_ring_size = 0; |
| 2140 | |
| 2141 | /* 8 for CRC and VLAN */ |
| 2142 | rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8); |
| 2143 | |
| 2144 | rx_space = rx_size + NET_SKB_PAD + |
| 2145 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 2146 | |
| 2147 | bp->rx_copy_thresh = BNXT_RX_COPY_THRESH; |
| 2148 | ring_size = bp->rx_ring_size; |
| 2149 | bp->rx_agg_ring_size = 0; |
| 2150 | bp->rx_agg_nr_pages = 0; |
| 2151 | |
| 2152 | if (bp->flags & BNXT_FLAG_TPA) |
| 2153 | agg_factor = 4; |
| 2154 | |
| 2155 | bp->flags &= ~BNXT_FLAG_JUMBO; |
| 2156 | if (rx_space > PAGE_SIZE) { |
| 2157 | u32 jumbo_factor; |
| 2158 | |
| 2159 | bp->flags |= BNXT_FLAG_JUMBO; |
| 2160 | jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT; |
| 2161 | if (jumbo_factor > agg_factor) |
| 2162 | agg_factor = jumbo_factor; |
| 2163 | } |
| 2164 | agg_ring_size = ring_size * agg_factor; |
| 2165 | |
| 2166 | if (agg_ring_size) { |
| 2167 | bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size, |
| 2168 | RX_DESC_CNT); |
| 2169 | if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) { |
| 2170 | u32 tmp = agg_ring_size; |
| 2171 | |
| 2172 | bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES; |
| 2173 | agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1; |
| 2174 | netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n", |
| 2175 | tmp, agg_ring_size); |
| 2176 | } |
| 2177 | bp->rx_agg_ring_size = agg_ring_size; |
| 2178 | bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1; |
| 2179 | rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN); |
| 2180 | rx_space = rx_size + NET_SKB_PAD + |
| 2181 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); |
| 2182 | } |
| 2183 | |
| 2184 | bp->rx_buf_use_size = rx_size; |
| 2185 | bp->rx_buf_size = rx_space; |
| 2186 | |
| 2187 | bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT); |
| 2188 | bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1; |
| 2189 | |
| 2190 | ring_size = bp->tx_ring_size; |
| 2191 | bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT); |
| 2192 | bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1; |
| 2193 | |
| 2194 | ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size; |
| 2195 | bp->cp_ring_size = ring_size; |
| 2196 | |
| 2197 | bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT); |
| 2198 | if (bp->cp_nr_pages > MAX_CP_PAGES) { |
| 2199 | bp->cp_nr_pages = MAX_CP_PAGES; |
| 2200 | bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1; |
| 2201 | netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n", |
| 2202 | ring_size, bp->cp_ring_size); |
| 2203 | } |
| 2204 | bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT; |
| 2205 | bp->cp_ring_mask = bp->cp_bit - 1; |
| 2206 | } |
| 2207 | |
| 2208 | static void bnxt_free_vnic_attributes(struct bnxt *bp) |
| 2209 | { |
| 2210 | int i; |
| 2211 | struct bnxt_vnic_info *vnic; |
| 2212 | struct pci_dev *pdev = bp->pdev; |
| 2213 | |
| 2214 | if (!bp->vnic_info) |
| 2215 | return; |
| 2216 | |
| 2217 | for (i = 0; i < bp->nr_vnics; i++) { |
| 2218 | vnic = &bp->vnic_info[i]; |
| 2219 | |
| 2220 | kfree(vnic->fw_grp_ids); |
| 2221 | vnic->fw_grp_ids = NULL; |
| 2222 | |
| 2223 | kfree(vnic->uc_list); |
| 2224 | vnic->uc_list = NULL; |
| 2225 | |
| 2226 | if (vnic->mc_list) { |
| 2227 | dma_free_coherent(&pdev->dev, vnic->mc_list_size, |
| 2228 | vnic->mc_list, vnic->mc_list_mapping); |
| 2229 | vnic->mc_list = NULL; |
| 2230 | } |
| 2231 | |
| 2232 | if (vnic->rss_table) { |
| 2233 | dma_free_coherent(&pdev->dev, PAGE_SIZE, |
| 2234 | vnic->rss_table, |
| 2235 | vnic->rss_table_dma_addr); |
| 2236 | vnic->rss_table = NULL; |
| 2237 | } |
| 2238 | |
| 2239 | vnic->rss_hash_key = NULL; |
| 2240 | vnic->flags = 0; |
| 2241 | } |
| 2242 | } |
| 2243 | |
| 2244 | static int bnxt_alloc_vnic_attributes(struct bnxt *bp) |
| 2245 | { |
| 2246 | int i, rc = 0, size; |
| 2247 | struct bnxt_vnic_info *vnic; |
| 2248 | struct pci_dev *pdev = bp->pdev; |
| 2249 | int max_rings; |
| 2250 | |
| 2251 | for (i = 0; i < bp->nr_vnics; i++) { |
| 2252 | vnic = &bp->vnic_info[i]; |
| 2253 | |
| 2254 | if (vnic->flags & BNXT_VNIC_UCAST_FLAG) { |
| 2255 | int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN; |
| 2256 | |
| 2257 | if (mem_size > 0) { |
| 2258 | vnic->uc_list = kmalloc(mem_size, GFP_KERNEL); |
| 2259 | if (!vnic->uc_list) { |
| 2260 | rc = -ENOMEM; |
| 2261 | goto out; |
| 2262 | } |
| 2263 | } |
| 2264 | } |
| 2265 | |
| 2266 | if (vnic->flags & BNXT_VNIC_MCAST_FLAG) { |
| 2267 | vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN; |
| 2268 | vnic->mc_list = |
| 2269 | dma_alloc_coherent(&pdev->dev, |
| 2270 | vnic->mc_list_size, |
| 2271 | &vnic->mc_list_mapping, |
| 2272 | GFP_KERNEL); |
| 2273 | if (!vnic->mc_list) { |
| 2274 | rc = -ENOMEM; |
| 2275 | goto out; |
| 2276 | } |
| 2277 | } |
| 2278 | |
| 2279 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
| 2280 | max_rings = bp->rx_nr_rings; |
| 2281 | else |
| 2282 | max_rings = 1; |
| 2283 | |
| 2284 | vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL); |
| 2285 | if (!vnic->fw_grp_ids) { |
| 2286 | rc = -ENOMEM; |
| 2287 | goto out; |
| 2288 | } |
| 2289 | |
| 2290 | /* Allocate rss table and hash key */ |
| 2291 | vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, |
| 2292 | &vnic->rss_table_dma_addr, |
| 2293 | GFP_KERNEL); |
| 2294 | if (!vnic->rss_table) { |
| 2295 | rc = -ENOMEM; |
| 2296 | goto out; |
| 2297 | } |
| 2298 | |
| 2299 | size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16)); |
| 2300 | |
| 2301 | vnic->rss_hash_key = ((void *)vnic->rss_table) + size; |
| 2302 | vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size; |
| 2303 | } |
| 2304 | return 0; |
| 2305 | |
| 2306 | out: |
| 2307 | return rc; |
| 2308 | } |
| 2309 | |
| 2310 | static void bnxt_free_hwrm_resources(struct bnxt *bp) |
| 2311 | { |
| 2312 | struct pci_dev *pdev = bp->pdev; |
| 2313 | |
| 2314 | dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr, |
| 2315 | bp->hwrm_cmd_resp_dma_addr); |
| 2316 | |
| 2317 | bp->hwrm_cmd_resp_addr = NULL; |
| 2318 | if (bp->hwrm_dbg_resp_addr) { |
| 2319 | dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE, |
| 2320 | bp->hwrm_dbg_resp_addr, |
| 2321 | bp->hwrm_dbg_resp_dma_addr); |
| 2322 | |
| 2323 | bp->hwrm_dbg_resp_addr = NULL; |
| 2324 | } |
| 2325 | } |
| 2326 | |
| 2327 | static int bnxt_alloc_hwrm_resources(struct bnxt *bp) |
| 2328 | { |
| 2329 | struct pci_dev *pdev = bp->pdev; |
| 2330 | |
| 2331 | bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, |
| 2332 | &bp->hwrm_cmd_resp_dma_addr, |
| 2333 | GFP_KERNEL); |
| 2334 | if (!bp->hwrm_cmd_resp_addr) |
| 2335 | return -ENOMEM; |
| 2336 | bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev, |
| 2337 | HWRM_DBG_REG_BUF_SIZE, |
| 2338 | &bp->hwrm_dbg_resp_dma_addr, |
| 2339 | GFP_KERNEL); |
| 2340 | if (!bp->hwrm_dbg_resp_addr) |
| 2341 | netdev_warn(bp->dev, "fail to alloc debug register dma mem\n"); |
| 2342 | |
| 2343 | return 0; |
| 2344 | } |
| 2345 | |
| 2346 | static void bnxt_free_stats(struct bnxt *bp) |
| 2347 | { |
| 2348 | u32 size, i; |
| 2349 | struct pci_dev *pdev = bp->pdev; |
| 2350 | |
| 2351 | if (!bp->bnapi) |
| 2352 | return; |
| 2353 | |
| 2354 | size = sizeof(struct ctx_hw_stats); |
| 2355 | |
| 2356 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 2357 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 2358 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 2359 | |
| 2360 | if (cpr->hw_stats) { |
| 2361 | dma_free_coherent(&pdev->dev, size, cpr->hw_stats, |
| 2362 | cpr->hw_stats_map); |
| 2363 | cpr->hw_stats = NULL; |
| 2364 | } |
| 2365 | } |
| 2366 | } |
| 2367 | |
| 2368 | static int bnxt_alloc_stats(struct bnxt *bp) |
| 2369 | { |
| 2370 | u32 size, i; |
| 2371 | struct pci_dev *pdev = bp->pdev; |
| 2372 | |
| 2373 | size = sizeof(struct ctx_hw_stats); |
| 2374 | |
| 2375 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 2376 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 2377 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 2378 | |
| 2379 | cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size, |
| 2380 | &cpr->hw_stats_map, |
| 2381 | GFP_KERNEL); |
| 2382 | if (!cpr->hw_stats) |
| 2383 | return -ENOMEM; |
| 2384 | |
| 2385 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; |
| 2386 | } |
| 2387 | return 0; |
| 2388 | } |
| 2389 | |
| 2390 | static void bnxt_clear_ring_indices(struct bnxt *bp) |
| 2391 | { |
| 2392 | int i; |
| 2393 | |
| 2394 | if (!bp->bnapi) |
| 2395 | return; |
| 2396 | |
| 2397 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 2398 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 2399 | struct bnxt_cp_ring_info *cpr; |
| 2400 | struct bnxt_rx_ring_info *rxr; |
| 2401 | struct bnxt_tx_ring_info *txr; |
| 2402 | |
| 2403 | if (!bnapi) |
| 2404 | continue; |
| 2405 | |
| 2406 | cpr = &bnapi->cp_ring; |
| 2407 | cpr->cp_raw_cons = 0; |
| 2408 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2409 | txr = bnapi->tx_ring; |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 2410 | if (txr) { |
| 2411 | txr->tx_prod = 0; |
| 2412 | txr->tx_cons = 0; |
| 2413 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2414 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2415 | rxr = bnapi->rx_ring; |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 2416 | if (rxr) { |
| 2417 | rxr->rx_prod = 0; |
| 2418 | rxr->rx_agg_prod = 0; |
| 2419 | rxr->rx_sw_agg_prod = 0; |
| 2420 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2421 | } |
| 2422 | } |
| 2423 | |
| 2424 | static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit) |
| 2425 | { |
| 2426 | #ifdef CONFIG_RFS_ACCEL |
| 2427 | int i; |
| 2428 | |
| 2429 | /* Under rtnl_lock and all our NAPIs have been disabled. It's |
| 2430 | * safe to delete the hash table. |
| 2431 | */ |
| 2432 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { |
| 2433 | struct hlist_head *head; |
| 2434 | struct hlist_node *tmp; |
| 2435 | struct bnxt_ntuple_filter *fltr; |
| 2436 | |
| 2437 | head = &bp->ntp_fltr_hash_tbl[i]; |
| 2438 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { |
| 2439 | hlist_del(&fltr->hash); |
| 2440 | kfree(fltr); |
| 2441 | } |
| 2442 | } |
| 2443 | if (irq_reinit) { |
| 2444 | kfree(bp->ntp_fltr_bmap); |
| 2445 | bp->ntp_fltr_bmap = NULL; |
| 2446 | } |
| 2447 | bp->ntp_fltr_count = 0; |
| 2448 | #endif |
| 2449 | } |
| 2450 | |
| 2451 | static int bnxt_alloc_ntp_fltrs(struct bnxt *bp) |
| 2452 | { |
| 2453 | #ifdef CONFIG_RFS_ACCEL |
| 2454 | int i, rc = 0; |
| 2455 | |
| 2456 | if (!(bp->flags & BNXT_FLAG_RFS)) |
| 2457 | return 0; |
| 2458 | |
| 2459 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) |
| 2460 | INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]); |
| 2461 | |
| 2462 | bp->ntp_fltr_count = 0; |
| 2463 | bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR), |
| 2464 | GFP_KERNEL); |
| 2465 | |
| 2466 | if (!bp->ntp_fltr_bmap) |
| 2467 | rc = -ENOMEM; |
| 2468 | |
| 2469 | return rc; |
| 2470 | #else |
| 2471 | return 0; |
| 2472 | #endif |
| 2473 | } |
| 2474 | |
| 2475 | static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init) |
| 2476 | { |
| 2477 | bnxt_free_vnic_attributes(bp); |
| 2478 | bnxt_free_tx_rings(bp); |
| 2479 | bnxt_free_rx_rings(bp); |
| 2480 | bnxt_free_cp_rings(bp); |
| 2481 | bnxt_free_ntp_fltrs(bp, irq_re_init); |
| 2482 | if (irq_re_init) { |
| 2483 | bnxt_free_stats(bp); |
| 2484 | bnxt_free_ring_grps(bp); |
| 2485 | bnxt_free_vnics(bp); |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2486 | kfree(bp->tx_ring); |
| 2487 | bp->tx_ring = NULL; |
| 2488 | kfree(bp->rx_ring); |
| 2489 | bp->rx_ring = NULL; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2490 | kfree(bp->bnapi); |
| 2491 | bp->bnapi = NULL; |
| 2492 | } else { |
| 2493 | bnxt_clear_ring_indices(bp); |
| 2494 | } |
| 2495 | } |
| 2496 | |
| 2497 | static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init) |
| 2498 | { |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 2499 | int i, j, rc, size, arr_size; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2500 | void *bnapi; |
| 2501 | |
| 2502 | if (irq_re_init) { |
| 2503 | /* Allocate bnapi mem pointer array and mem block for |
| 2504 | * all queues |
| 2505 | */ |
| 2506 | arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) * |
| 2507 | bp->cp_nr_rings); |
| 2508 | size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi)); |
| 2509 | bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL); |
| 2510 | if (!bnapi) |
| 2511 | return -ENOMEM; |
| 2512 | |
| 2513 | bp->bnapi = bnapi; |
| 2514 | bnapi += arr_size; |
| 2515 | for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) { |
| 2516 | bp->bnapi[i] = bnapi; |
| 2517 | bp->bnapi[i]->index = i; |
| 2518 | bp->bnapi[i]->bp = bp; |
| 2519 | } |
| 2520 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2521 | bp->rx_ring = kcalloc(bp->rx_nr_rings, |
| 2522 | sizeof(struct bnxt_rx_ring_info), |
| 2523 | GFP_KERNEL); |
| 2524 | if (!bp->rx_ring) |
| 2525 | return -ENOMEM; |
| 2526 | |
| 2527 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 2528 | bp->rx_ring[i].bnapi = bp->bnapi[i]; |
| 2529 | bp->bnapi[i]->rx_ring = &bp->rx_ring[i]; |
| 2530 | } |
| 2531 | |
| 2532 | bp->tx_ring = kcalloc(bp->tx_nr_rings, |
| 2533 | sizeof(struct bnxt_tx_ring_info), |
| 2534 | GFP_KERNEL); |
| 2535 | if (!bp->tx_ring) |
| 2536 | return -ENOMEM; |
| 2537 | |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 2538 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
| 2539 | j = 0; |
| 2540 | else |
| 2541 | j = bp->rx_nr_rings; |
| 2542 | |
| 2543 | for (i = 0; i < bp->tx_nr_rings; i++, j++) { |
| 2544 | bp->tx_ring[i].bnapi = bp->bnapi[j]; |
| 2545 | bp->bnapi[j]->tx_ring = &bp->tx_ring[i]; |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 2546 | } |
| 2547 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2548 | rc = bnxt_alloc_stats(bp); |
| 2549 | if (rc) |
| 2550 | goto alloc_mem_err; |
| 2551 | |
| 2552 | rc = bnxt_alloc_ntp_fltrs(bp); |
| 2553 | if (rc) |
| 2554 | goto alloc_mem_err; |
| 2555 | |
| 2556 | rc = bnxt_alloc_vnics(bp); |
| 2557 | if (rc) |
| 2558 | goto alloc_mem_err; |
| 2559 | } |
| 2560 | |
| 2561 | bnxt_init_ring_struct(bp); |
| 2562 | |
| 2563 | rc = bnxt_alloc_rx_rings(bp); |
| 2564 | if (rc) |
| 2565 | goto alloc_mem_err; |
| 2566 | |
| 2567 | rc = bnxt_alloc_tx_rings(bp); |
| 2568 | if (rc) |
| 2569 | goto alloc_mem_err; |
| 2570 | |
| 2571 | rc = bnxt_alloc_cp_rings(bp); |
| 2572 | if (rc) |
| 2573 | goto alloc_mem_err; |
| 2574 | |
| 2575 | bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG | |
| 2576 | BNXT_VNIC_UCAST_FLAG; |
| 2577 | rc = bnxt_alloc_vnic_attributes(bp); |
| 2578 | if (rc) |
| 2579 | goto alloc_mem_err; |
| 2580 | return 0; |
| 2581 | |
| 2582 | alloc_mem_err: |
| 2583 | bnxt_free_mem(bp, true); |
| 2584 | return rc; |
| 2585 | } |
| 2586 | |
| 2587 | void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type, |
| 2588 | u16 cmpl_ring, u16 target_id) |
| 2589 | { |
| 2590 | struct hwrm_cmd_req_hdr *req = request; |
| 2591 | |
| 2592 | req->cmpl_ring_req_type = |
| 2593 | cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT)); |
| 2594 | req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT); |
| 2595 | req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr); |
| 2596 | } |
| 2597 | |
| 2598 | int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
| 2599 | { |
| 2600 | int i, intr_process, rc; |
| 2601 | struct hwrm_cmd_req_hdr *req = msg; |
| 2602 | u32 *data = msg; |
| 2603 | __le32 *resp_len, *valid; |
| 2604 | u16 cp_ring_id, len = 0; |
| 2605 | struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr; |
| 2606 | |
| 2607 | req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++); |
| 2608 | memset(resp, 0, PAGE_SIZE); |
| 2609 | cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) & |
| 2610 | HWRM_CMPL_RING_MASK) >> |
| 2611 | HWRM_CMPL_RING_SFT; |
| 2612 | intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1; |
| 2613 | |
| 2614 | /* Write request msg to hwrm channel */ |
| 2615 | __iowrite32_copy(bp->bar0, data, msg_len / 4); |
| 2616 | |
| 2617 | /* currently supports only one outstanding message */ |
| 2618 | if (intr_process) |
| 2619 | bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) & |
| 2620 | HWRM_SEQ_ID_MASK; |
| 2621 | |
| 2622 | /* Ring channel doorbell */ |
| 2623 | writel(1, bp->bar0 + 0x100); |
| 2624 | |
| 2625 | i = 0; |
| 2626 | if (intr_process) { |
| 2627 | /* Wait until hwrm response cmpl interrupt is processed */ |
| 2628 | while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID && |
| 2629 | i++ < timeout) { |
| 2630 | usleep_range(600, 800); |
| 2631 | } |
| 2632 | |
| 2633 | if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) { |
| 2634 | netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n", |
| 2635 | req->cmpl_ring_req_type); |
| 2636 | return -1; |
| 2637 | } |
| 2638 | } else { |
| 2639 | /* Check if response len is updated */ |
| 2640 | resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET; |
| 2641 | for (i = 0; i < timeout; i++) { |
| 2642 | len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >> |
| 2643 | HWRM_RESP_LEN_SFT; |
| 2644 | if (len) |
| 2645 | break; |
| 2646 | usleep_range(600, 800); |
| 2647 | } |
| 2648 | |
| 2649 | if (i >= timeout) { |
| 2650 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n", |
| 2651 | timeout, req->cmpl_ring_req_type, |
| 2652 | req->target_id_seq_id, *resp_len); |
| 2653 | return -1; |
| 2654 | } |
| 2655 | |
| 2656 | /* Last word of resp contains valid bit */ |
| 2657 | valid = bp->hwrm_cmd_resp_addr + len - 4; |
| 2658 | for (i = 0; i < timeout; i++) { |
| 2659 | if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK) |
| 2660 | break; |
| 2661 | usleep_range(600, 800); |
| 2662 | } |
| 2663 | |
| 2664 | if (i >= timeout) { |
| 2665 | netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n", |
| 2666 | timeout, req->cmpl_ring_req_type, |
| 2667 | req->target_id_seq_id, len, *valid); |
| 2668 | return -1; |
| 2669 | } |
| 2670 | } |
| 2671 | |
| 2672 | rc = le16_to_cpu(resp->error_code); |
| 2673 | if (rc) { |
| 2674 | netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n", |
| 2675 | le16_to_cpu(resp->req_type), |
| 2676 | le16_to_cpu(resp->seq_id), rc); |
| 2677 | return rc; |
| 2678 | } |
| 2679 | return 0; |
| 2680 | } |
| 2681 | |
| 2682 | int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout) |
| 2683 | { |
| 2684 | int rc; |
| 2685 | |
| 2686 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2687 | rc = _hwrm_send_message(bp, msg, msg_len, timeout); |
| 2688 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 2689 | return rc; |
| 2690 | } |
| 2691 | |
| 2692 | static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp) |
| 2693 | { |
| 2694 | struct hwrm_func_drv_rgtr_input req = {0}; |
| 2695 | int i; |
| 2696 | |
| 2697 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1); |
| 2698 | |
| 2699 | req.enables = |
| 2700 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE | |
| 2701 | FUNC_DRV_RGTR_REQ_ENABLES_VER | |
| 2702 | FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD); |
| 2703 | |
| 2704 | /* TODO: current async event fwd bits are not defined and the firmware |
| 2705 | * only checks if it is non-zero to enable async event forwarding |
| 2706 | */ |
| 2707 | req.async_event_fwd[0] |= cpu_to_le32(1); |
| 2708 | req.os_type = cpu_to_le16(1); |
| 2709 | req.ver_maj = DRV_VER_MAJ; |
| 2710 | req.ver_min = DRV_VER_MIN; |
| 2711 | req.ver_upd = DRV_VER_UPD; |
| 2712 | |
| 2713 | if (BNXT_PF(bp)) { |
Michael Chan | de68f5de | 2015-12-09 19:35:41 -0500 | [diff] [blame] | 2714 | DECLARE_BITMAP(vf_req_snif_bmap, 256); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2715 | u32 *data = (u32 *)vf_req_snif_bmap; |
| 2716 | |
Michael Chan | de68f5de | 2015-12-09 19:35:41 -0500 | [diff] [blame] | 2717 | memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap)); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2718 | for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++) |
| 2719 | __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap); |
| 2720 | |
Michael Chan | de68f5de | 2015-12-09 19:35:41 -0500 | [diff] [blame] | 2721 | for (i = 0; i < 8; i++) |
| 2722 | req.vf_req_fwd[i] = cpu_to_le32(data[i]); |
| 2723 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2724 | req.enables |= |
| 2725 | cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD); |
| 2726 | } |
| 2727 | |
| 2728 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2729 | } |
| 2730 | |
Jeffrey Huang | be58a0d | 2015-12-27 18:19:18 -0500 | [diff] [blame] | 2731 | static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp) |
| 2732 | { |
| 2733 | struct hwrm_func_drv_unrgtr_input req = {0}; |
| 2734 | |
| 2735 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1); |
| 2736 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2737 | } |
| 2738 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2739 | static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type) |
| 2740 | { |
| 2741 | u32 rc = 0; |
| 2742 | struct hwrm_tunnel_dst_port_free_input req = {0}; |
| 2743 | |
| 2744 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1); |
| 2745 | req.tunnel_type = tunnel_type; |
| 2746 | |
| 2747 | switch (tunnel_type) { |
| 2748 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN: |
| 2749 | req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id; |
| 2750 | break; |
| 2751 | case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE: |
| 2752 | req.tunnel_dst_port_id = bp->nge_fw_dst_port_id; |
| 2753 | break; |
| 2754 | default: |
| 2755 | break; |
| 2756 | } |
| 2757 | |
| 2758 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2759 | if (rc) |
| 2760 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n", |
| 2761 | rc); |
| 2762 | return rc; |
| 2763 | } |
| 2764 | |
| 2765 | static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port, |
| 2766 | u8 tunnel_type) |
| 2767 | { |
| 2768 | u32 rc = 0; |
| 2769 | struct hwrm_tunnel_dst_port_alloc_input req = {0}; |
| 2770 | struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 2771 | |
| 2772 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1); |
| 2773 | |
| 2774 | req.tunnel_type = tunnel_type; |
| 2775 | req.tunnel_dst_port_val = port; |
| 2776 | |
| 2777 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2778 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2779 | if (rc) { |
| 2780 | netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n", |
| 2781 | rc); |
| 2782 | goto err_out; |
| 2783 | } |
| 2784 | |
| 2785 | if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN) |
| 2786 | bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id; |
| 2787 | |
| 2788 | else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE) |
| 2789 | bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id; |
| 2790 | err_out: |
| 2791 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 2792 | return rc; |
| 2793 | } |
| 2794 | |
| 2795 | static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id) |
| 2796 | { |
| 2797 | struct hwrm_cfa_l2_set_rx_mask_input req = {0}; |
| 2798 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 2799 | |
| 2800 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1); |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2801 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2802 | |
| 2803 | req.num_mc_entries = cpu_to_le32(vnic->mc_list_count); |
| 2804 | req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping); |
| 2805 | req.mask = cpu_to_le32(vnic->rx_mask); |
| 2806 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2807 | } |
| 2808 | |
| 2809 | #ifdef CONFIG_RFS_ACCEL |
| 2810 | static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp, |
| 2811 | struct bnxt_ntuple_filter *fltr) |
| 2812 | { |
| 2813 | struct hwrm_cfa_ntuple_filter_free_input req = {0}; |
| 2814 | |
| 2815 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1); |
| 2816 | req.ntuple_filter_id = fltr->filter_id; |
| 2817 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2818 | } |
| 2819 | |
| 2820 | #define BNXT_NTP_FLTR_FLAGS \ |
| 2821 | (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \ |
| 2822 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \ |
| 2823 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \ |
| 2824 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \ |
| 2825 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \ |
| 2826 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \ |
| 2827 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \ |
| 2828 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \ |
| 2829 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \ |
| 2830 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \ |
| 2831 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \ |
| 2832 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \ |
| 2833 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \ |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2834 | CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2835 | |
| 2836 | static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp, |
| 2837 | struct bnxt_ntuple_filter *fltr) |
| 2838 | { |
| 2839 | int rc = 0; |
| 2840 | struct hwrm_cfa_ntuple_filter_alloc_input req = {0}; |
| 2841 | struct hwrm_cfa_ntuple_filter_alloc_output *resp = |
| 2842 | bp->hwrm_cmd_resp_addr; |
| 2843 | struct flow_keys *keys = &fltr->fkeys; |
| 2844 | struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1]; |
| 2845 | |
| 2846 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1); |
| 2847 | req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0]; |
| 2848 | |
| 2849 | req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS); |
| 2850 | |
| 2851 | req.ethertype = htons(ETH_P_IP); |
| 2852 | memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN); |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2853 | req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2854 | req.ip_protocol = keys->basic.ip_proto; |
| 2855 | |
| 2856 | req.src_ipaddr[0] = keys->addrs.v4addrs.src; |
| 2857 | req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff); |
| 2858 | req.dst_ipaddr[0] = keys->addrs.v4addrs.dst; |
| 2859 | req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff); |
| 2860 | |
| 2861 | req.src_port = keys->ports.src; |
| 2862 | req.src_port_mask = cpu_to_be16(0xffff); |
| 2863 | req.dst_port = keys->ports.dst; |
| 2864 | req.dst_port_mask = cpu_to_be16(0xffff); |
| 2865 | |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2866 | req.dst_id = cpu_to_le16(vnic->fw_vnic_id); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2867 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2868 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2869 | if (!rc) |
| 2870 | fltr->filter_id = resp->ntuple_filter_id; |
| 2871 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 2872 | return rc; |
| 2873 | } |
| 2874 | #endif |
| 2875 | |
| 2876 | static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx, |
| 2877 | u8 *mac_addr) |
| 2878 | { |
| 2879 | u32 rc = 0; |
| 2880 | struct hwrm_cfa_l2_filter_alloc_input req = {0}; |
| 2881 | struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 2882 | |
| 2883 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1); |
| 2884 | req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX | |
| 2885 | CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST); |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2886 | req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2887 | req.enables = |
| 2888 | cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR | |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2889 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2890 | CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK); |
| 2891 | memcpy(req.l2_addr, mac_addr, ETH_ALEN); |
| 2892 | req.l2_addr_mask[0] = 0xff; |
| 2893 | req.l2_addr_mask[1] = 0xff; |
| 2894 | req.l2_addr_mask[2] = 0xff; |
| 2895 | req.l2_addr_mask[3] = 0xff; |
| 2896 | req.l2_addr_mask[4] = 0xff; |
| 2897 | req.l2_addr_mask[5] = 0xff; |
| 2898 | |
| 2899 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2900 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2901 | if (!rc) |
| 2902 | bp->vnic_info[vnic_id].fw_l2_filter_id[idx] = |
| 2903 | resp->l2_filter_id; |
| 2904 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 2905 | return rc; |
| 2906 | } |
| 2907 | |
| 2908 | static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp) |
| 2909 | { |
| 2910 | u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */ |
| 2911 | int rc = 0; |
| 2912 | |
| 2913 | /* Any associated ntuple filters will also be cleared by firmware. */ |
| 2914 | mutex_lock(&bp->hwrm_cmd_lock); |
| 2915 | for (i = 0; i < num_of_vnics; i++) { |
| 2916 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; |
| 2917 | |
| 2918 | for (j = 0; j < vnic->uc_filter_count; j++) { |
| 2919 | struct hwrm_cfa_l2_filter_free_input req = {0}; |
| 2920 | |
| 2921 | bnxt_hwrm_cmd_hdr_init(bp, &req, |
| 2922 | HWRM_CFA_L2_FILTER_FREE, -1, -1); |
| 2923 | |
| 2924 | req.l2_filter_id = vnic->fw_l2_filter_id[j]; |
| 2925 | |
| 2926 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 2927 | HWRM_CMD_TIMEOUT); |
| 2928 | } |
| 2929 | vnic->uc_filter_count = 0; |
| 2930 | } |
| 2931 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 2932 | |
| 2933 | return rc; |
| 2934 | } |
| 2935 | |
| 2936 | static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags) |
| 2937 | { |
| 2938 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 2939 | struct hwrm_vnic_tpa_cfg_input req = {0}; |
| 2940 | |
| 2941 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1); |
| 2942 | |
| 2943 | if (tpa_flags) { |
| 2944 | u16 mss = bp->dev->mtu - 40; |
| 2945 | u32 nsegs, n, segs = 0, flags; |
| 2946 | |
| 2947 | flags = VNIC_TPA_CFG_REQ_FLAGS_TPA | |
| 2948 | VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA | |
| 2949 | VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE | |
| 2950 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN | |
| 2951 | VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ; |
| 2952 | if (tpa_flags & BNXT_FLAG_GRO) |
| 2953 | flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO; |
| 2954 | |
| 2955 | req.flags = cpu_to_le32(flags); |
| 2956 | |
| 2957 | req.enables = |
| 2958 | cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS | |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2959 | VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS | |
| 2960 | VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2961 | |
| 2962 | /* Number of segs are log2 units, and first packet is not |
| 2963 | * included as part of this units. |
| 2964 | */ |
| 2965 | if (mss <= PAGE_SIZE) { |
| 2966 | n = PAGE_SIZE / mss; |
| 2967 | nsegs = (MAX_SKB_FRAGS - 1) * n; |
| 2968 | } else { |
| 2969 | n = mss / PAGE_SIZE; |
| 2970 | if (mss & (PAGE_SIZE - 1)) |
| 2971 | n++; |
| 2972 | nsegs = (MAX_SKB_FRAGS - n) / n; |
| 2973 | } |
| 2974 | |
| 2975 | segs = ilog2(nsegs); |
| 2976 | req.max_agg_segs = cpu_to_le16(segs); |
| 2977 | req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX); |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 2978 | |
| 2979 | req.min_agg_len = cpu_to_le32(512); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 2980 | } |
| 2981 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
| 2982 | |
| 2983 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 2984 | } |
| 2985 | |
| 2986 | static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss) |
| 2987 | { |
| 2988 | u32 i, j, max_rings; |
| 2989 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 2990 | struct hwrm_vnic_rss_cfg_input req = {0}; |
| 2991 | |
| 2992 | if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID) |
| 2993 | return 0; |
| 2994 | |
| 2995 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1); |
| 2996 | if (set_rss) { |
| 2997 | vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 | |
| 2998 | BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 | |
| 2999 | BNXT_RSS_HASH_TYPE_FLAG_IPV6 | |
| 3000 | BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6; |
| 3001 | |
| 3002 | req.hash_type = cpu_to_le32(vnic->hash_type); |
| 3003 | |
| 3004 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
| 3005 | max_rings = bp->rx_nr_rings; |
| 3006 | else |
| 3007 | max_rings = 1; |
| 3008 | |
| 3009 | /* Fill the RSS indirection table with ring group ids */ |
| 3010 | for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) { |
| 3011 | if (j == max_rings) |
| 3012 | j = 0; |
| 3013 | vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]); |
| 3014 | } |
| 3015 | |
| 3016 | req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr); |
| 3017 | req.hash_key_tbl_addr = |
| 3018 | cpu_to_le64(vnic->rss_hash_key_dma_addr); |
| 3019 | } |
| 3020 | req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx); |
| 3021 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3022 | } |
| 3023 | |
| 3024 | static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id) |
| 3025 | { |
| 3026 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 3027 | struct hwrm_vnic_plcmodes_cfg_input req = {0}; |
| 3028 | |
| 3029 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1); |
| 3030 | req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT | |
| 3031 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 | |
| 3032 | VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6); |
| 3033 | req.enables = |
| 3034 | cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID | |
| 3035 | VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID); |
| 3036 | /* thresholds not implemented in firmware yet */ |
| 3037 | req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh); |
| 3038 | req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh); |
| 3039 | req.vnic_id = cpu_to_le32(vnic->fw_vnic_id); |
| 3040 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3041 | } |
| 3042 | |
| 3043 | static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id) |
| 3044 | { |
| 3045 | struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0}; |
| 3046 | |
| 3047 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1); |
| 3048 | req.rss_cos_lb_ctx_id = |
| 3049 | cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx); |
| 3050 | |
| 3051 | hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3052 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; |
| 3053 | } |
| 3054 | |
| 3055 | static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp) |
| 3056 | { |
| 3057 | int i; |
| 3058 | |
| 3059 | for (i = 0; i < bp->nr_vnics; i++) { |
| 3060 | struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; |
| 3061 | |
| 3062 | if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID) |
| 3063 | bnxt_hwrm_vnic_ctx_free_one(bp, i); |
| 3064 | } |
| 3065 | bp->rsscos_nr_ctxs = 0; |
| 3066 | } |
| 3067 | |
| 3068 | static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id) |
| 3069 | { |
| 3070 | int rc; |
| 3071 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0}; |
| 3072 | struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp = |
| 3073 | bp->hwrm_cmd_resp_addr; |
| 3074 | |
| 3075 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1, |
| 3076 | -1); |
| 3077 | |
| 3078 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3079 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3080 | if (!rc) |
| 3081 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = |
| 3082 | le16_to_cpu(resp->rss_cos_lb_ctx_id); |
| 3083 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3084 | |
| 3085 | return rc; |
| 3086 | } |
| 3087 | |
| 3088 | static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id) |
| 3089 | { |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3090 | unsigned int ring = 0, grp_idx; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3091 | struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; |
| 3092 | struct hwrm_vnic_cfg_input req = {0}; |
| 3093 | |
| 3094 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1); |
| 3095 | /* Only RSS support for now TBD: COS & LB */ |
| 3096 | req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP | |
| 3097 | VNIC_CFG_REQ_ENABLES_RSS_RULE); |
| 3098 | req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx); |
| 3099 | req.cos_rule = cpu_to_le16(0xffff); |
| 3100 | if (vnic->flags & BNXT_VNIC_RSS_FLAG) |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3101 | ring = 0; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3102 | else if (vnic->flags & BNXT_VNIC_RFS_FLAG) |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3103 | ring = vnic_id - 1; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3104 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3105 | grp_idx = bp->rx_ring[ring].bnapi->index; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3106 | req.vnic_id = cpu_to_le16(vnic->fw_vnic_id); |
| 3107 | req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id); |
| 3108 | |
| 3109 | req.lb_rule = cpu_to_le16(0xffff); |
| 3110 | req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + |
| 3111 | VLAN_HLEN); |
| 3112 | |
| 3113 | if (bp->flags & BNXT_FLAG_STRIP_VLAN) |
| 3114 | req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE); |
| 3115 | |
| 3116 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3117 | } |
| 3118 | |
| 3119 | static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id) |
| 3120 | { |
| 3121 | u32 rc = 0; |
| 3122 | |
| 3123 | if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) { |
| 3124 | struct hwrm_vnic_free_input req = {0}; |
| 3125 | |
| 3126 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1); |
| 3127 | req.vnic_id = |
| 3128 | cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id); |
| 3129 | |
| 3130 | rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3131 | if (rc) |
| 3132 | return rc; |
| 3133 | bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID; |
| 3134 | } |
| 3135 | return rc; |
| 3136 | } |
| 3137 | |
| 3138 | static void bnxt_hwrm_vnic_free(struct bnxt *bp) |
| 3139 | { |
| 3140 | u16 i; |
| 3141 | |
| 3142 | for (i = 0; i < bp->nr_vnics; i++) |
| 3143 | bnxt_hwrm_vnic_free_one(bp, i); |
| 3144 | } |
| 3145 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3146 | static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id, |
| 3147 | unsigned int start_rx_ring_idx, |
| 3148 | unsigned int nr_rings) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3149 | { |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3150 | int rc = 0; |
| 3151 | unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3152 | struct hwrm_vnic_alloc_input req = {0}; |
| 3153 | struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 3154 | |
| 3155 | /* map ring groups to this vnic */ |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3156 | for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) { |
| 3157 | grp_idx = bp->rx_ring[i].bnapi->index; |
| 3158 | if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3159 | netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n", |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3160 | j, nr_rings); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3161 | break; |
| 3162 | } |
| 3163 | bp->vnic_info[vnic_id].fw_grp_ids[j] = |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3164 | bp->grp_info[grp_idx].fw_grp_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3165 | } |
| 3166 | |
| 3167 | bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID; |
| 3168 | if (vnic_id == 0) |
| 3169 | req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT); |
| 3170 | |
| 3171 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1); |
| 3172 | |
| 3173 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3174 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3175 | if (!rc) |
| 3176 | bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id); |
| 3177 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3178 | return rc; |
| 3179 | } |
| 3180 | |
| 3181 | static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp) |
| 3182 | { |
| 3183 | u16 i; |
| 3184 | u32 rc = 0; |
| 3185 | |
| 3186 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3187 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 3188 | struct hwrm_ring_grp_alloc_input req = {0}; |
| 3189 | struct hwrm_ring_grp_alloc_output *resp = |
| 3190 | bp->hwrm_cmd_resp_addr; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3191 | unsigned int grp_idx = bp->rx_ring[i].bnapi->index; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3192 | |
| 3193 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1); |
| 3194 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3195 | req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id); |
| 3196 | req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id); |
| 3197 | req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id); |
| 3198 | req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3199 | |
| 3200 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3201 | HWRM_CMD_TIMEOUT); |
| 3202 | if (rc) |
| 3203 | break; |
| 3204 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3205 | bp->grp_info[grp_idx].fw_grp_id = |
| 3206 | le32_to_cpu(resp->ring_group_id); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3207 | } |
| 3208 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3209 | return rc; |
| 3210 | } |
| 3211 | |
| 3212 | static int bnxt_hwrm_ring_grp_free(struct bnxt *bp) |
| 3213 | { |
| 3214 | u16 i; |
| 3215 | u32 rc = 0; |
| 3216 | struct hwrm_ring_grp_free_input req = {0}; |
| 3217 | |
| 3218 | if (!bp->grp_info) |
| 3219 | return 0; |
| 3220 | |
| 3221 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1); |
| 3222 | |
| 3223 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3224 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3225 | if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID) |
| 3226 | continue; |
| 3227 | req.ring_group_id = |
| 3228 | cpu_to_le32(bp->grp_info[i].fw_grp_id); |
| 3229 | |
| 3230 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3231 | HWRM_CMD_TIMEOUT); |
| 3232 | if (rc) |
| 3233 | break; |
| 3234 | bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID; |
| 3235 | } |
| 3236 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3237 | return rc; |
| 3238 | } |
| 3239 | |
| 3240 | static int hwrm_ring_alloc_send_msg(struct bnxt *bp, |
| 3241 | struct bnxt_ring_struct *ring, |
| 3242 | u32 ring_type, u32 map_index, |
| 3243 | u32 stats_ctx_id) |
| 3244 | { |
| 3245 | int rc = 0, err = 0; |
| 3246 | struct hwrm_ring_alloc_input req = {0}; |
| 3247 | struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 3248 | u16 ring_id; |
| 3249 | |
| 3250 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1); |
| 3251 | |
| 3252 | req.enables = 0; |
| 3253 | if (ring->nr_pages > 1) { |
| 3254 | req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map); |
| 3255 | /* Page size is in log2 units */ |
| 3256 | req.page_size = BNXT_PAGE_SHIFT; |
| 3257 | req.page_tbl_depth = 1; |
| 3258 | } else { |
| 3259 | req.page_tbl_addr = cpu_to_le64(ring->dma_arr[0]); |
| 3260 | } |
| 3261 | req.fbo = 0; |
| 3262 | /* Association of ring index with doorbell index and MSIX number */ |
| 3263 | req.logical_id = cpu_to_le16(map_index); |
| 3264 | |
| 3265 | switch (ring_type) { |
| 3266 | case HWRM_RING_ALLOC_TX: |
| 3267 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX; |
| 3268 | /* Association of transmit ring with completion ring */ |
| 3269 | req.cmpl_ring_id = |
| 3270 | cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id); |
| 3271 | req.length = cpu_to_le32(bp->tx_ring_mask + 1); |
| 3272 | req.stat_ctx_id = cpu_to_le32(stats_ctx_id); |
| 3273 | req.queue_id = cpu_to_le16(ring->queue_id); |
| 3274 | break; |
| 3275 | case HWRM_RING_ALLOC_RX: |
| 3276 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; |
| 3277 | req.length = cpu_to_le32(bp->rx_ring_mask + 1); |
| 3278 | break; |
| 3279 | case HWRM_RING_ALLOC_AGG: |
| 3280 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX; |
| 3281 | req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1); |
| 3282 | break; |
| 3283 | case HWRM_RING_ALLOC_CMPL: |
| 3284 | req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL; |
| 3285 | req.length = cpu_to_le32(bp->cp_ring_mask + 1); |
| 3286 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
| 3287 | req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX; |
| 3288 | break; |
| 3289 | default: |
| 3290 | netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n", |
| 3291 | ring_type); |
| 3292 | return -1; |
| 3293 | } |
| 3294 | |
| 3295 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3296 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3297 | err = le16_to_cpu(resp->error_code); |
| 3298 | ring_id = le16_to_cpu(resp->ring_id); |
| 3299 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3300 | |
| 3301 | if (rc || err) { |
| 3302 | switch (ring_type) { |
| 3303 | case RING_FREE_REQ_RING_TYPE_CMPL: |
| 3304 | netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n", |
| 3305 | rc, err); |
| 3306 | return -1; |
| 3307 | |
| 3308 | case RING_FREE_REQ_RING_TYPE_RX: |
| 3309 | netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n", |
| 3310 | rc, err); |
| 3311 | return -1; |
| 3312 | |
| 3313 | case RING_FREE_REQ_RING_TYPE_TX: |
| 3314 | netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n", |
| 3315 | rc, err); |
| 3316 | return -1; |
| 3317 | |
| 3318 | default: |
| 3319 | netdev_err(bp->dev, "Invalid ring\n"); |
| 3320 | return -1; |
| 3321 | } |
| 3322 | } |
| 3323 | ring->fw_ring_id = ring_id; |
| 3324 | return rc; |
| 3325 | } |
| 3326 | |
| 3327 | static int bnxt_hwrm_ring_alloc(struct bnxt *bp) |
| 3328 | { |
| 3329 | int i, rc = 0; |
| 3330 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3331 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3332 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 3333 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 3334 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3335 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3336 | rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i, |
| 3337 | INVALID_STATS_CTX_ID); |
| 3338 | if (rc) |
| 3339 | goto err_out; |
| 3340 | cpr->cp_doorbell = bp->bar1 + i * 0x80; |
| 3341 | BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 3342 | bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3343 | } |
| 3344 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3345 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3346 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3347 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3348 | u32 map_idx = txr->bnapi->index; |
| 3349 | u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3350 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3351 | rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX, |
| 3352 | map_idx, fw_stats_ctx); |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3353 | if (rc) |
| 3354 | goto err_out; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3355 | txr->tx_doorbell = bp->bar1 + map_idx * 0x80; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3356 | } |
| 3357 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3358 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3359 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3360 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3361 | u32 map_idx = rxr->bnapi->index; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3362 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3363 | rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX, |
| 3364 | map_idx, INVALID_STATS_CTX_ID); |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3365 | if (rc) |
| 3366 | goto err_out; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3367 | rxr->rx_doorbell = bp->bar1 + map_idx * 0x80; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3368 | writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell); |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3369 | bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3370 | } |
| 3371 | |
| 3372 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { |
| 3373 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3374 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3375 | struct bnxt_ring_struct *ring = |
| 3376 | &rxr->rx_agg_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3377 | u32 grp_idx = rxr->bnapi->index; |
| 3378 | u32 map_idx = grp_idx + bp->rx_nr_rings; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3379 | |
| 3380 | rc = hwrm_ring_alloc_send_msg(bp, ring, |
| 3381 | HWRM_RING_ALLOC_AGG, |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3382 | map_idx, |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3383 | INVALID_STATS_CTX_ID); |
| 3384 | if (rc) |
| 3385 | goto err_out; |
| 3386 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3387 | rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3388 | writel(DB_KEY_RX | rxr->rx_agg_prod, |
| 3389 | rxr->rx_agg_doorbell); |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3390 | bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3391 | } |
| 3392 | } |
| 3393 | err_out: |
| 3394 | return rc; |
| 3395 | } |
| 3396 | |
| 3397 | static int hwrm_ring_free_send_msg(struct bnxt *bp, |
| 3398 | struct bnxt_ring_struct *ring, |
| 3399 | u32 ring_type, int cmpl_ring_id) |
| 3400 | { |
| 3401 | int rc; |
| 3402 | struct hwrm_ring_free_input req = {0}; |
| 3403 | struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr; |
| 3404 | u16 error_code; |
| 3405 | |
| 3406 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1); |
| 3407 | req.ring_type = ring_type; |
| 3408 | req.ring_id = cpu_to_le16(ring->fw_ring_id); |
| 3409 | |
| 3410 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3411 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3412 | error_code = le16_to_cpu(resp->error_code); |
| 3413 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3414 | |
| 3415 | if (rc || error_code) { |
| 3416 | switch (ring_type) { |
| 3417 | case RING_FREE_REQ_RING_TYPE_CMPL: |
| 3418 | netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n", |
| 3419 | rc); |
| 3420 | return rc; |
| 3421 | case RING_FREE_REQ_RING_TYPE_RX: |
| 3422 | netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n", |
| 3423 | rc); |
| 3424 | return rc; |
| 3425 | case RING_FREE_REQ_RING_TYPE_TX: |
| 3426 | netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n", |
| 3427 | rc); |
| 3428 | return rc; |
| 3429 | default: |
| 3430 | netdev_err(bp->dev, "Invalid ring\n"); |
| 3431 | return -1; |
| 3432 | } |
| 3433 | } |
| 3434 | return 0; |
| 3435 | } |
| 3436 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3437 | static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3438 | { |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3439 | int i; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3440 | |
| 3441 | if (!bp->bnapi) |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3442 | return; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3443 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3444 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3445 | struct bnxt_tx_ring_info *txr = &bp->tx_ring[i]; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3446 | struct bnxt_ring_struct *ring = &txr->tx_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3447 | u32 grp_idx = txr->bnapi->index; |
| 3448 | u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3449 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3450 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
| 3451 | hwrm_ring_free_send_msg(bp, ring, |
| 3452 | RING_FREE_REQ_RING_TYPE_TX, |
| 3453 | close_path ? cmpl_ring_id : |
| 3454 | INVALID_HW_RING_ID); |
| 3455 | ring->fw_ring_id = INVALID_HW_RING_ID; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3456 | } |
| 3457 | } |
| 3458 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3459 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3460 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3461 | struct bnxt_ring_struct *ring = &rxr->rx_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3462 | u32 grp_idx = rxr->bnapi->index; |
| 3463 | u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3464 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3465 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
| 3466 | hwrm_ring_free_send_msg(bp, ring, |
| 3467 | RING_FREE_REQ_RING_TYPE_RX, |
| 3468 | close_path ? cmpl_ring_id : |
| 3469 | INVALID_HW_RING_ID); |
| 3470 | ring->fw_ring_id = INVALID_HW_RING_ID; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3471 | bp->grp_info[grp_idx].rx_fw_ring_id = |
| 3472 | INVALID_HW_RING_ID; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3473 | } |
| 3474 | } |
| 3475 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3476 | for (i = 0; i < bp->rx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 3477 | struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i]; |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3478 | struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3479 | u32 grp_idx = rxr->bnapi->index; |
| 3480 | u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3481 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3482 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
| 3483 | hwrm_ring_free_send_msg(bp, ring, |
| 3484 | RING_FREE_REQ_RING_TYPE_RX, |
| 3485 | close_path ? cmpl_ring_id : |
| 3486 | INVALID_HW_RING_ID); |
| 3487 | ring->fw_ring_id = INVALID_HW_RING_ID; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3488 | bp->grp_info[grp_idx].agg_fw_ring_id = |
| 3489 | INVALID_HW_RING_ID; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3490 | } |
| 3491 | } |
| 3492 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3493 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3494 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 3495 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 3496 | struct bnxt_ring_struct *ring = &cpr->cp_ring_struct; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3497 | |
Michael Chan | edd0c2c | 2015-12-27 18:19:19 -0500 | [diff] [blame] | 3498 | if (ring->fw_ring_id != INVALID_HW_RING_ID) { |
| 3499 | hwrm_ring_free_send_msg(bp, ring, |
| 3500 | RING_FREE_REQ_RING_TYPE_CMPL, |
| 3501 | INVALID_HW_RING_ID); |
| 3502 | ring->fw_ring_id = INVALID_HW_RING_ID; |
| 3503 | bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3504 | } |
| 3505 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3506 | } |
| 3507 | |
| 3508 | int bnxt_hwrm_set_coal(struct bnxt *bp) |
| 3509 | { |
| 3510 | int i, rc = 0; |
| 3511 | struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0}; |
| 3512 | u16 max_buf, max_buf_irq; |
| 3513 | u16 buf_tmr, buf_tmr_irq; |
| 3514 | u32 flags; |
| 3515 | |
| 3516 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, |
| 3517 | -1, -1); |
| 3518 | |
| 3519 | /* Each rx completion (2 records) should be DMAed immediately */ |
| 3520 | max_buf = min_t(u16, bp->coal_bufs / 4, 2); |
| 3521 | /* max_buf must not be zero */ |
| 3522 | max_buf = clamp_t(u16, max_buf, 1, 63); |
| 3523 | max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63); |
| 3524 | buf_tmr = max_t(u16, bp->coal_ticks / 4, 1); |
| 3525 | buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1); |
| 3526 | |
| 3527 | flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET; |
| 3528 | |
| 3529 | /* RING_IDLE generates more IRQs for lower latency. Enable it only |
| 3530 | * if coal_ticks is less than 25 us. |
| 3531 | */ |
| 3532 | if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25) |
| 3533 | flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE; |
| 3534 | |
| 3535 | req.flags = cpu_to_le16(flags); |
| 3536 | req.num_cmpl_dma_aggr = cpu_to_le16(max_buf); |
| 3537 | req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq); |
| 3538 | req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr); |
| 3539 | req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq); |
| 3540 | req.int_lat_tmr_min = cpu_to_le16(buf_tmr); |
| 3541 | req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks); |
| 3542 | req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs); |
| 3543 | |
| 3544 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3545 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3546 | req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id); |
| 3547 | |
| 3548 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3549 | HWRM_CMD_TIMEOUT); |
| 3550 | if (rc) |
| 3551 | break; |
| 3552 | } |
| 3553 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3554 | return rc; |
| 3555 | } |
| 3556 | |
| 3557 | static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp) |
| 3558 | { |
| 3559 | int rc = 0, i; |
| 3560 | struct hwrm_stat_ctx_free_input req = {0}; |
| 3561 | |
| 3562 | if (!bp->bnapi) |
| 3563 | return 0; |
| 3564 | |
| 3565 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1); |
| 3566 | |
| 3567 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3568 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3569 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 3570 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 3571 | |
| 3572 | if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) { |
| 3573 | req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id); |
| 3574 | |
| 3575 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3576 | HWRM_CMD_TIMEOUT); |
| 3577 | if (rc) |
| 3578 | break; |
| 3579 | |
| 3580 | cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID; |
| 3581 | } |
| 3582 | } |
| 3583 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3584 | return rc; |
| 3585 | } |
| 3586 | |
| 3587 | static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp) |
| 3588 | { |
| 3589 | int rc = 0, i; |
| 3590 | struct hwrm_stat_ctx_alloc_input req = {0}; |
| 3591 | struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr; |
| 3592 | |
| 3593 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1); |
| 3594 | |
| 3595 | req.update_period_ms = cpu_to_le32(1000); |
| 3596 | |
| 3597 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3598 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 3599 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 3600 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 3601 | |
| 3602 | req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map); |
| 3603 | |
| 3604 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 3605 | HWRM_CMD_TIMEOUT); |
| 3606 | if (rc) |
| 3607 | break; |
| 3608 | |
| 3609 | cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id); |
| 3610 | |
| 3611 | bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id; |
| 3612 | } |
| 3613 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3614 | return 0; |
| 3615 | } |
| 3616 | |
Michael Chan | 4a21b49 | 2015-12-27 18:19:26 -0500 | [diff] [blame] | 3617 | int bnxt_hwrm_func_qcaps(struct bnxt *bp) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3618 | { |
| 3619 | int rc = 0; |
| 3620 | struct hwrm_func_qcaps_input req = {0}; |
| 3621 | struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr; |
| 3622 | |
| 3623 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1); |
| 3624 | req.fid = cpu_to_le16(0xffff); |
| 3625 | |
| 3626 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3627 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3628 | if (rc) |
| 3629 | goto hwrm_func_qcaps_exit; |
| 3630 | |
| 3631 | if (BNXT_PF(bp)) { |
| 3632 | struct bnxt_pf_info *pf = &bp->pf; |
| 3633 | |
| 3634 | pf->fw_fid = le16_to_cpu(resp->fid); |
| 3635 | pf->port_id = le16_to_cpu(resp->port_id); |
| 3636 | memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN); |
Jeffrey Huang | bdd4347 | 2015-12-02 01:54:07 -0500 | [diff] [blame] | 3637 | memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3638 | pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
| 3639 | pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); |
| 3640 | pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3641 | pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); |
Michael Chan | b72d4a6 | 2015-12-27 18:19:27 -0500 | [diff] [blame] | 3642 | pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); |
| 3643 | if (!pf->max_hw_ring_grps) |
| 3644 | pf->max_hw_ring_grps = pf->max_tx_rings; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3645 | pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); |
| 3646 | pf->max_vnics = le16_to_cpu(resp->max_vnics); |
| 3647 | pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); |
| 3648 | pf->first_vf_id = le16_to_cpu(resp->first_vf_id); |
| 3649 | pf->max_vfs = le16_to_cpu(resp->max_vfs); |
| 3650 | pf->max_encap_records = le32_to_cpu(resp->max_encap_records); |
| 3651 | pf->max_decap_records = le32_to_cpu(resp->max_decap_records); |
| 3652 | pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows); |
| 3653 | pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows); |
| 3654 | pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows); |
| 3655 | pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows); |
| 3656 | } else { |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 3657 | #ifdef CONFIG_BNXT_SRIOV |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3658 | struct bnxt_vf_info *vf = &bp->vf; |
| 3659 | |
| 3660 | vf->fw_fid = le16_to_cpu(resp->fid); |
| 3661 | memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN); |
Jeffrey Huang | bdd4347 | 2015-12-02 01:54:07 -0500 | [diff] [blame] | 3662 | if (is_valid_ether_addr(vf->mac_addr)) |
| 3663 | /* overwrite netdev dev_adr with admin VF MAC */ |
| 3664 | memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN); |
| 3665 | else |
| 3666 | random_ether_addr(bp->dev->dev_addr); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3667 | |
| 3668 | vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx); |
| 3669 | vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings); |
| 3670 | vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings); |
| 3671 | vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings); |
Michael Chan | b72d4a6 | 2015-12-27 18:19:27 -0500 | [diff] [blame] | 3672 | vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps); |
| 3673 | if (!vf->max_hw_ring_grps) |
| 3674 | vf->max_hw_ring_grps = vf->max_tx_rings; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3675 | vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs); |
| 3676 | vf->max_vnics = le16_to_cpu(resp->max_vnics); |
| 3677 | vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx); |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 3678 | #endif |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3679 | } |
| 3680 | |
| 3681 | bp->tx_push_thresh = 0; |
| 3682 | if (resp->flags & |
| 3683 | cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED)) |
| 3684 | bp->tx_push_thresh = BNXT_TX_PUSH_THRESH; |
| 3685 | |
| 3686 | hwrm_func_qcaps_exit: |
| 3687 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3688 | return rc; |
| 3689 | } |
| 3690 | |
| 3691 | static int bnxt_hwrm_func_reset(struct bnxt *bp) |
| 3692 | { |
| 3693 | struct hwrm_func_reset_input req = {0}; |
| 3694 | |
| 3695 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1); |
| 3696 | req.enables = 0; |
| 3697 | |
| 3698 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT); |
| 3699 | } |
| 3700 | |
| 3701 | static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp) |
| 3702 | { |
| 3703 | int rc = 0; |
| 3704 | struct hwrm_queue_qportcfg_input req = {0}; |
| 3705 | struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr; |
| 3706 | u8 i, *qptr; |
| 3707 | |
| 3708 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1); |
| 3709 | |
| 3710 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3711 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3712 | if (rc) |
| 3713 | goto qportcfg_exit; |
| 3714 | |
| 3715 | if (!resp->max_configurable_queues) { |
| 3716 | rc = -EINVAL; |
| 3717 | goto qportcfg_exit; |
| 3718 | } |
| 3719 | bp->max_tc = resp->max_configurable_queues; |
| 3720 | if (bp->max_tc > BNXT_MAX_QUEUE) |
| 3721 | bp->max_tc = BNXT_MAX_QUEUE; |
| 3722 | |
| 3723 | qptr = &resp->queue_id0; |
| 3724 | for (i = 0; i < bp->max_tc; i++) { |
| 3725 | bp->q_info[i].queue_id = *qptr++; |
| 3726 | bp->q_info[i].queue_profile = *qptr++; |
| 3727 | } |
| 3728 | |
| 3729 | qportcfg_exit: |
| 3730 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3731 | return rc; |
| 3732 | } |
| 3733 | |
| 3734 | static int bnxt_hwrm_ver_get(struct bnxt *bp) |
| 3735 | { |
| 3736 | int rc; |
| 3737 | struct hwrm_ver_get_input req = {0}; |
| 3738 | struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr; |
| 3739 | |
| 3740 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1); |
| 3741 | req.hwrm_intf_maj = HWRM_VERSION_MAJOR; |
| 3742 | req.hwrm_intf_min = HWRM_VERSION_MINOR; |
| 3743 | req.hwrm_intf_upd = HWRM_VERSION_UPDATE; |
| 3744 | mutex_lock(&bp->hwrm_cmd_lock); |
| 3745 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 3746 | if (rc) |
| 3747 | goto hwrm_ver_get_exit; |
| 3748 | |
| 3749 | memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output)); |
| 3750 | |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 3751 | if (resp->hwrm_intf_maj < 1) { |
| 3752 | netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n", |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3753 | resp->hwrm_intf_maj, resp->hwrm_intf_min, |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 3754 | resp->hwrm_intf_upd); |
| 3755 | netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n"); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3756 | } |
| 3757 | snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d", |
| 3758 | resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld, |
| 3759 | resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd); |
| 3760 | |
| 3761 | hwrm_ver_get_exit: |
| 3762 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 3763 | return rc; |
| 3764 | } |
| 3765 | |
| 3766 | static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp) |
| 3767 | { |
| 3768 | if (bp->vxlan_port_cnt) { |
| 3769 | bnxt_hwrm_tunnel_dst_port_free( |
| 3770 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); |
| 3771 | } |
| 3772 | bp->vxlan_port_cnt = 0; |
| 3773 | if (bp->nge_port_cnt) { |
| 3774 | bnxt_hwrm_tunnel_dst_port_free( |
| 3775 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE); |
| 3776 | } |
| 3777 | bp->nge_port_cnt = 0; |
| 3778 | } |
| 3779 | |
| 3780 | static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa) |
| 3781 | { |
| 3782 | int rc, i; |
| 3783 | u32 tpa_flags = 0; |
| 3784 | |
| 3785 | if (set_tpa) |
| 3786 | tpa_flags = bp->flags & BNXT_FLAG_TPA; |
| 3787 | for (i = 0; i < bp->nr_vnics; i++) { |
| 3788 | rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags); |
| 3789 | if (rc) { |
| 3790 | netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n", |
| 3791 | rc, i); |
| 3792 | return rc; |
| 3793 | } |
| 3794 | } |
| 3795 | return 0; |
| 3796 | } |
| 3797 | |
| 3798 | static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp) |
| 3799 | { |
| 3800 | int i; |
| 3801 | |
| 3802 | for (i = 0; i < bp->nr_vnics; i++) |
| 3803 | bnxt_hwrm_vnic_set_rss(bp, i, false); |
| 3804 | } |
| 3805 | |
| 3806 | static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path, |
| 3807 | bool irq_re_init) |
| 3808 | { |
| 3809 | if (bp->vnic_info) { |
| 3810 | bnxt_hwrm_clear_vnic_filter(bp); |
| 3811 | /* clear all RSS setting before free vnic ctx */ |
| 3812 | bnxt_hwrm_clear_vnic_rss(bp); |
| 3813 | bnxt_hwrm_vnic_ctx_free(bp); |
| 3814 | /* before free the vnic, undo the vnic tpa settings */ |
| 3815 | if (bp->flags & BNXT_FLAG_TPA) |
| 3816 | bnxt_set_tpa(bp, false); |
| 3817 | bnxt_hwrm_vnic_free(bp); |
| 3818 | } |
| 3819 | bnxt_hwrm_ring_free(bp, close_path); |
| 3820 | bnxt_hwrm_ring_grp_free(bp); |
| 3821 | if (irq_re_init) { |
| 3822 | bnxt_hwrm_stat_ctx_free(bp); |
| 3823 | bnxt_hwrm_free_tunnel_ports(bp); |
| 3824 | } |
| 3825 | } |
| 3826 | |
| 3827 | static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id) |
| 3828 | { |
| 3829 | int rc; |
| 3830 | |
| 3831 | /* allocate context for vnic */ |
| 3832 | rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id); |
| 3833 | if (rc) { |
| 3834 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", |
| 3835 | vnic_id, rc); |
| 3836 | goto vnic_setup_err; |
| 3837 | } |
| 3838 | bp->rsscos_nr_ctxs++; |
| 3839 | |
| 3840 | /* configure default vnic, ring grp */ |
| 3841 | rc = bnxt_hwrm_vnic_cfg(bp, vnic_id); |
| 3842 | if (rc) { |
| 3843 | netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n", |
| 3844 | vnic_id, rc); |
| 3845 | goto vnic_setup_err; |
| 3846 | } |
| 3847 | |
| 3848 | /* Enable RSS hashing on vnic */ |
| 3849 | rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true); |
| 3850 | if (rc) { |
| 3851 | netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n", |
| 3852 | vnic_id, rc); |
| 3853 | goto vnic_setup_err; |
| 3854 | } |
| 3855 | |
| 3856 | if (bp->flags & BNXT_FLAG_AGG_RINGS) { |
| 3857 | rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id); |
| 3858 | if (rc) { |
| 3859 | netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n", |
| 3860 | vnic_id, rc); |
| 3861 | } |
| 3862 | } |
| 3863 | |
| 3864 | vnic_setup_err: |
| 3865 | return rc; |
| 3866 | } |
| 3867 | |
| 3868 | static int bnxt_alloc_rfs_vnics(struct bnxt *bp) |
| 3869 | { |
| 3870 | #ifdef CONFIG_RFS_ACCEL |
| 3871 | int i, rc = 0; |
| 3872 | |
| 3873 | for (i = 0; i < bp->rx_nr_rings; i++) { |
| 3874 | u16 vnic_id = i + 1; |
| 3875 | u16 ring_id = i; |
| 3876 | |
| 3877 | if (vnic_id >= bp->nr_vnics) |
| 3878 | break; |
| 3879 | |
| 3880 | bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG; |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 3881 | rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3882 | if (rc) { |
| 3883 | netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n", |
| 3884 | vnic_id, rc); |
| 3885 | break; |
| 3886 | } |
| 3887 | rc = bnxt_setup_vnic(bp, vnic_id); |
| 3888 | if (rc) |
| 3889 | break; |
| 3890 | } |
| 3891 | return rc; |
| 3892 | #else |
| 3893 | return 0; |
| 3894 | #endif |
| 3895 | } |
| 3896 | |
Michael Chan | b664f00 | 2015-12-02 01:54:08 -0500 | [diff] [blame] | 3897 | static int bnxt_cfg_rx_mode(struct bnxt *); |
| 3898 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3899 | static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init) |
| 3900 | { |
| 3901 | int rc = 0; |
| 3902 | |
| 3903 | if (irq_re_init) { |
| 3904 | rc = bnxt_hwrm_stat_ctx_alloc(bp); |
| 3905 | if (rc) { |
| 3906 | netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n", |
| 3907 | rc); |
| 3908 | goto err_out; |
| 3909 | } |
| 3910 | } |
| 3911 | |
| 3912 | rc = bnxt_hwrm_ring_alloc(bp); |
| 3913 | if (rc) { |
| 3914 | netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc); |
| 3915 | goto err_out; |
| 3916 | } |
| 3917 | |
| 3918 | rc = bnxt_hwrm_ring_grp_alloc(bp); |
| 3919 | if (rc) { |
| 3920 | netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc); |
| 3921 | goto err_out; |
| 3922 | } |
| 3923 | |
| 3924 | /* default vnic 0 */ |
| 3925 | rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings); |
| 3926 | if (rc) { |
| 3927 | netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc); |
| 3928 | goto err_out; |
| 3929 | } |
| 3930 | |
| 3931 | rc = bnxt_setup_vnic(bp, 0); |
| 3932 | if (rc) |
| 3933 | goto err_out; |
| 3934 | |
| 3935 | if (bp->flags & BNXT_FLAG_RFS) { |
| 3936 | rc = bnxt_alloc_rfs_vnics(bp); |
| 3937 | if (rc) |
| 3938 | goto err_out; |
| 3939 | } |
| 3940 | |
| 3941 | if (bp->flags & BNXT_FLAG_TPA) { |
| 3942 | rc = bnxt_set_tpa(bp, true); |
| 3943 | if (rc) |
| 3944 | goto err_out; |
| 3945 | } |
| 3946 | |
| 3947 | if (BNXT_VF(bp)) |
| 3948 | bnxt_update_vf_mac(bp); |
| 3949 | |
| 3950 | /* Filter for default vnic 0 */ |
| 3951 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr); |
| 3952 | if (rc) { |
| 3953 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc); |
| 3954 | goto err_out; |
| 3955 | } |
| 3956 | bp->vnic_info[0].uc_filter_count = 1; |
| 3957 | |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 3958 | bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3959 | |
| 3960 | if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp)) |
| 3961 | bp->vnic_info[0].rx_mask |= |
| 3962 | CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
| 3963 | |
Michael Chan | b664f00 | 2015-12-02 01:54:08 -0500 | [diff] [blame] | 3964 | rc = bnxt_cfg_rx_mode(bp); |
| 3965 | if (rc) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3966 | goto err_out; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 3967 | |
| 3968 | rc = bnxt_hwrm_set_coal(bp); |
| 3969 | if (rc) |
| 3970 | netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n", |
| 3971 | rc); |
| 3972 | |
| 3973 | return 0; |
| 3974 | |
| 3975 | err_out: |
| 3976 | bnxt_hwrm_resource_free(bp, 0, true); |
| 3977 | |
| 3978 | return rc; |
| 3979 | } |
| 3980 | |
| 3981 | static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init) |
| 3982 | { |
| 3983 | bnxt_hwrm_resource_free(bp, 1, irq_re_init); |
| 3984 | return 0; |
| 3985 | } |
| 3986 | |
| 3987 | static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init) |
| 3988 | { |
| 3989 | bnxt_init_rx_rings(bp); |
| 3990 | bnxt_init_tx_rings(bp); |
| 3991 | bnxt_init_ring_grps(bp, irq_re_init); |
| 3992 | bnxt_init_vnics(bp); |
| 3993 | |
| 3994 | return bnxt_init_chip(bp, irq_re_init); |
| 3995 | } |
| 3996 | |
| 3997 | static void bnxt_disable_int(struct bnxt *bp) |
| 3998 | { |
| 3999 | int i; |
| 4000 | |
| 4001 | if (!bp->bnapi) |
| 4002 | return; |
| 4003 | |
| 4004 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4005 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 4006 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 4007 | |
| 4008 | BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 4009 | } |
| 4010 | } |
| 4011 | |
| 4012 | static void bnxt_enable_int(struct bnxt *bp) |
| 4013 | { |
| 4014 | int i; |
| 4015 | |
| 4016 | atomic_set(&bp->intr_sem, 0); |
| 4017 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4018 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 4019 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 4020 | |
| 4021 | BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons); |
| 4022 | } |
| 4023 | } |
| 4024 | |
| 4025 | static int bnxt_set_real_num_queues(struct bnxt *bp) |
| 4026 | { |
| 4027 | int rc; |
| 4028 | struct net_device *dev = bp->dev; |
| 4029 | |
| 4030 | rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings); |
| 4031 | if (rc) |
| 4032 | return rc; |
| 4033 | |
| 4034 | rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings); |
| 4035 | if (rc) |
| 4036 | return rc; |
| 4037 | |
| 4038 | #ifdef CONFIG_RFS_ACCEL |
Michael Chan | 45019a1 | 2015-12-27 18:19:22 -0500 | [diff] [blame] | 4039 | if (bp->flags & BNXT_FLAG_RFS) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4040 | dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4041 | #endif |
| 4042 | |
| 4043 | return rc; |
| 4044 | } |
| 4045 | |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 4046 | static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max, |
| 4047 | bool shared) |
| 4048 | { |
| 4049 | int _rx = *rx, _tx = *tx; |
| 4050 | |
| 4051 | if (shared) { |
| 4052 | *rx = min_t(int, _rx, max); |
| 4053 | *tx = min_t(int, _tx, max); |
| 4054 | } else { |
| 4055 | if (max < 2) |
| 4056 | return -ENOMEM; |
| 4057 | |
| 4058 | while (_rx + _tx > max) { |
| 4059 | if (_rx > _tx && _rx > 1) |
| 4060 | _rx--; |
| 4061 | else if (_tx > 1) |
| 4062 | _tx--; |
| 4063 | } |
| 4064 | *rx = _rx; |
| 4065 | *tx = _tx; |
| 4066 | } |
| 4067 | return 0; |
| 4068 | } |
| 4069 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4070 | static int bnxt_setup_msix(struct bnxt *bp) |
| 4071 | { |
| 4072 | struct msix_entry *msix_ent; |
| 4073 | struct net_device *dev = bp->dev; |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4074 | int i, total_vecs, rc = 0, min = 1; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4075 | const int len = sizeof(bp->irq_tbl[0].name); |
| 4076 | |
| 4077 | bp->flags &= ~BNXT_FLAG_USING_MSIX; |
| 4078 | total_vecs = bp->cp_nr_rings; |
| 4079 | |
| 4080 | msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL); |
| 4081 | if (!msix_ent) |
| 4082 | return -ENOMEM; |
| 4083 | |
| 4084 | for (i = 0; i < total_vecs; i++) { |
| 4085 | msix_ent[i].entry = i; |
| 4086 | msix_ent[i].vector = 0; |
| 4087 | } |
| 4088 | |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4089 | if (!(bp->flags & BNXT_FLAG_SHARED_RINGS)) |
| 4090 | min = 2; |
| 4091 | |
| 4092 | total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4093 | if (total_vecs < 0) { |
| 4094 | rc = -ENODEV; |
| 4095 | goto msix_setup_exit; |
| 4096 | } |
| 4097 | |
| 4098 | bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL); |
| 4099 | if (bp->irq_tbl) { |
| 4100 | int tcs; |
| 4101 | |
| 4102 | /* Trim rings based upon num of vectors allocated */ |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 4103 | rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings, |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4104 | total_vecs, min == 1); |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 4105 | if (rc) |
| 4106 | goto msix_setup_exit; |
| 4107 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4108 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
| 4109 | tcs = netdev_get_num_tc(dev); |
| 4110 | if (tcs > 1) { |
| 4111 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs; |
| 4112 | if (bp->tx_nr_rings_per_tc == 0) { |
| 4113 | netdev_reset_tc(dev); |
| 4114 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
| 4115 | } else { |
| 4116 | int i, off, count; |
| 4117 | |
| 4118 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs; |
| 4119 | for (i = 0; i < tcs; i++) { |
| 4120 | count = bp->tx_nr_rings_per_tc; |
| 4121 | off = i * count; |
| 4122 | netdev_set_tc_queue(dev, i, count, off); |
| 4123 | } |
| 4124 | } |
| 4125 | } |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4126 | bp->cp_nr_rings = total_vecs; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4127 | |
| 4128 | for (i = 0; i < bp->cp_nr_rings; i++) { |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4129 | char *attr; |
| 4130 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4131 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4132 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
| 4133 | attr = "TxRx"; |
| 4134 | else if (i < bp->rx_nr_rings) |
| 4135 | attr = "rx"; |
| 4136 | else |
| 4137 | attr = "tx"; |
| 4138 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4139 | snprintf(bp->irq_tbl[i].name, len, |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4140 | "%s-%s-%d", dev->name, attr, i); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4141 | bp->irq_tbl[i].handler = bnxt_msix; |
| 4142 | } |
| 4143 | rc = bnxt_set_real_num_queues(bp); |
| 4144 | if (rc) |
| 4145 | goto msix_setup_exit; |
| 4146 | } else { |
| 4147 | rc = -ENOMEM; |
| 4148 | goto msix_setup_exit; |
| 4149 | } |
| 4150 | bp->flags |= BNXT_FLAG_USING_MSIX; |
| 4151 | kfree(msix_ent); |
| 4152 | return 0; |
| 4153 | |
| 4154 | msix_setup_exit: |
| 4155 | netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc); |
| 4156 | pci_disable_msix(bp->pdev); |
| 4157 | kfree(msix_ent); |
| 4158 | return rc; |
| 4159 | } |
| 4160 | |
| 4161 | static int bnxt_setup_inta(struct bnxt *bp) |
| 4162 | { |
| 4163 | int rc; |
| 4164 | const int len = sizeof(bp->irq_tbl[0].name); |
| 4165 | |
| 4166 | if (netdev_get_num_tc(bp->dev)) |
| 4167 | netdev_reset_tc(bp->dev); |
| 4168 | |
| 4169 | bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL); |
| 4170 | if (!bp->irq_tbl) { |
| 4171 | rc = -ENOMEM; |
| 4172 | return rc; |
| 4173 | } |
| 4174 | bp->rx_nr_rings = 1; |
| 4175 | bp->tx_nr_rings = 1; |
| 4176 | bp->cp_nr_rings = 1; |
| 4177 | bp->tx_nr_rings_per_tc = bp->tx_nr_rings; |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 4178 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4179 | bp->irq_tbl[0].vector = bp->pdev->irq; |
| 4180 | snprintf(bp->irq_tbl[0].name, len, |
| 4181 | "%s-%s-%d", bp->dev->name, "TxRx", 0); |
| 4182 | bp->irq_tbl[0].handler = bnxt_inta; |
| 4183 | rc = bnxt_set_real_num_queues(bp); |
| 4184 | return rc; |
| 4185 | } |
| 4186 | |
| 4187 | static int bnxt_setup_int_mode(struct bnxt *bp) |
| 4188 | { |
| 4189 | int rc = 0; |
| 4190 | |
| 4191 | if (bp->flags & BNXT_FLAG_MSIX_CAP) |
| 4192 | rc = bnxt_setup_msix(bp); |
| 4193 | |
| 4194 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) { |
| 4195 | /* fallback to INTA */ |
| 4196 | rc = bnxt_setup_inta(bp); |
| 4197 | } |
| 4198 | return rc; |
| 4199 | } |
| 4200 | |
| 4201 | static void bnxt_free_irq(struct bnxt *bp) |
| 4202 | { |
| 4203 | struct bnxt_irq *irq; |
| 4204 | int i; |
| 4205 | |
| 4206 | #ifdef CONFIG_RFS_ACCEL |
| 4207 | free_irq_cpu_rmap(bp->dev->rx_cpu_rmap); |
| 4208 | bp->dev->rx_cpu_rmap = NULL; |
| 4209 | #endif |
| 4210 | if (!bp->irq_tbl) |
| 4211 | return; |
| 4212 | |
| 4213 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4214 | irq = &bp->irq_tbl[i]; |
| 4215 | if (irq->requested) |
| 4216 | free_irq(irq->vector, bp->bnapi[i]); |
| 4217 | irq->requested = 0; |
| 4218 | } |
| 4219 | if (bp->flags & BNXT_FLAG_USING_MSIX) |
| 4220 | pci_disable_msix(bp->pdev); |
| 4221 | kfree(bp->irq_tbl); |
| 4222 | bp->irq_tbl = NULL; |
| 4223 | } |
| 4224 | |
| 4225 | static int bnxt_request_irq(struct bnxt *bp) |
| 4226 | { |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 4227 | int i, j, rc = 0; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4228 | unsigned long flags = 0; |
| 4229 | #ifdef CONFIG_RFS_ACCEL |
| 4230 | struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap; |
| 4231 | #endif |
| 4232 | |
| 4233 | if (!(bp->flags & BNXT_FLAG_USING_MSIX)) |
| 4234 | flags = IRQF_SHARED; |
| 4235 | |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 4236 | for (i = 0, j = 0; i < bp->cp_nr_rings; i++) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4237 | struct bnxt_irq *irq = &bp->irq_tbl[i]; |
| 4238 | #ifdef CONFIG_RFS_ACCEL |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 4239 | if (rmap && bp->bnapi[i]->rx_ring) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4240 | rc = irq_cpu_rmap_add(rmap, irq->vector); |
| 4241 | if (rc) |
| 4242 | netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n", |
Michael Chan | b81a90d | 2016-01-02 23:45:01 -0500 | [diff] [blame] | 4243 | j); |
| 4244 | j++; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4245 | } |
| 4246 | #endif |
| 4247 | rc = request_irq(irq->vector, irq->handler, flags, irq->name, |
| 4248 | bp->bnapi[i]); |
| 4249 | if (rc) |
| 4250 | break; |
| 4251 | |
| 4252 | irq->requested = 1; |
| 4253 | } |
| 4254 | return rc; |
| 4255 | } |
| 4256 | |
| 4257 | static void bnxt_del_napi(struct bnxt *bp) |
| 4258 | { |
| 4259 | int i; |
| 4260 | |
| 4261 | if (!bp->bnapi) |
| 4262 | return; |
| 4263 | |
| 4264 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4265 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 4266 | |
| 4267 | napi_hash_del(&bnapi->napi); |
| 4268 | netif_napi_del(&bnapi->napi); |
| 4269 | } |
| 4270 | } |
| 4271 | |
| 4272 | static void bnxt_init_napi(struct bnxt *bp) |
| 4273 | { |
| 4274 | int i; |
| 4275 | struct bnxt_napi *bnapi; |
| 4276 | |
| 4277 | if (bp->flags & BNXT_FLAG_USING_MSIX) { |
| 4278 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4279 | bnapi = bp->bnapi[i]; |
| 4280 | netif_napi_add(bp->dev, &bnapi->napi, |
| 4281 | bnxt_poll, 64); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4282 | } |
| 4283 | } else { |
| 4284 | bnapi = bp->bnapi[0]; |
| 4285 | netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4286 | } |
| 4287 | } |
| 4288 | |
| 4289 | static void bnxt_disable_napi(struct bnxt *bp) |
| 4290 | { |
| 4291 | int i; |
| 4292 | |
| 4293 | if (!bp->bnapi) |
| 4294 | return; |
| 4295 | |
| 4296 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4297 | napi_disable(&bp->bnapi[i]->napi); |
| 4298 | bnxt_disable_poll(bp->bnapi[i]); |
| 4299 | } |
| 4300 | } |
| 4301 | |
| 4302 | static void bnxt_enable_napi(struct bnxt *bp) |
| 4303 | { |
| 4304 | int i; |
| 4305 | |
| 4306 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4307 | bnxt_enable_poll(bp->bnapi[i]); |
| 4308 | napi_enable(&bp->bnapi[i]->napi); |
| 4309 | } |
| 4310 | } |
| 4311 | |
| 4312 | static void bnxt_tx_disable(struct bnxt *bp) |
| 4313 | { |
| 4314 | int i; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4315 | struct bnxt_tx_ring_info *txr; |
| 4316 | struct netdev_queue *txq; |
| 4317 | |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 4318 | if (bp->tx_ring) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4319 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 4320 | txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4321 | txq = netdev_get_tx_queue(bp->dev, i); |
| 4322 | __netif_tx_lock(txq, smp_processor_id()); |
| 4323 | txr->dev_state = BNXT_DEV_STATE_CLOSING; |
| 4324 | __netif_tx_unlock(txq); |
| 4325 | } |
| 4326 | } |
| 4327 | /* Stop all TX queues */ |
| 4328 | netif_tx_disable(bp->dev); |
| 4329 | netif_carrier_off(bp->dev); |
| 4330 | } |
| 4331 | |
| 4332 | static void bnxt_tx_enable(struct bnxt *bp) |
| 4333 | { |
| 4334 | int i; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4335 | struct bnxt_tx_ring_info *txr; |
| 4336 | struct netdev_queue *txq; |
| 4337 | |
| 4338 | for (i = 0; i < bp->tx_nr_rings; i++) { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 4339 | txr = &bp->tx_ring[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4340 | txq = netdev_get_tx_queue(bp->dev, i); |
| 4341 | txr->dev_state = 0; |
| 4342 | } |
| 4343 | netif_tx_wake_all_queues(bp->dev); |
| 4344 | if (bp->link_info.link_up) |
| 4345 | netif_carrier_on(bp->dev); |
| 4346 | } |
| 4347 | |
| 4348 | static void bnxt_report_link(struct bnxt *bp) |
| 4349 | { |
| 4350 | if (bp->link_info.link_up) { |
| 4351 | const char *duplex; |
| 4352 | const char *flow_ctrl; |
| 4353 | u16 speed; |
| 4354 | |
| 4355 | netif_carrier_on(bp->dev); |
| 4356 | if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL) |
| 4357 | duplex = "full"; |
| 4358 | else |
| 4359 | duplex = "half"; |
| 4360 | if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH) |
| 4361 | flow_ctrl = "ON - receive & transmit"; |
| 4362 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX) |
| 4363 | flow_ctrl = "ON - transmit"; |
| 4364 | else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX) |
| 4365 | flow_ctrl = "ON - receive"; |
| 4366 | else |
| 4367 | flow_ctrl = "none"; |
| 4368 | speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed); |
| 4369 | netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", |
| 4370 | speed, duplex, flow_ctrl); |
| 4371 | } else { |
| 4372 | netif_carrier_off(bp->dev); |
| 4373 | netdev_err(bp->dev, "NIC Link is Down\n"); |
| 4374 | } |
| 4375 | } |
| 4376 | |
| 4377 | static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) |
| 4378 | { |
| 4379 | int rc = 0; |
| 4380 | struct bnxt_link_info *link_info = &bp->link_info; |
| 4381 | struct hwrm_port_phy_qcfg_input req = {0}; |
| 4382 | struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr; |
| 4383 | u8 link_up = link_info->link_up; |
| 4384 | |
| 4385 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1); |
| 4386 | |
| 4387 | mutex_lock(&bp->hwrm_cmd_lock); |
| 4388 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 4389 | if (rc) { |
| 4390 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 4391 | return rc; |
| 4392 | } |
| 4393 | |
| 4394 | memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp)); |
| 4395 | link_info->phy_link_status = resp->link; |
| 4396 | link_info->duplex = resp->duplex; |
| 4397 | link_info->pause = resp->pause; |
| 4398 | link_info->auto_mode = resp->auto_mode; |
| 4399 | link_info->auto_pause_setting = resp->auto_pause; |
| 4400 | link_info->force_pause_setting = resp->force_pause; |
Michael Chan | c193554 | 2015-12-27 18:19:28 -0500 | [diff] [blame] | 4401 | link_info->duplex_setting = resp->duplex; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4402 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
| 4403 | link_info->link_speed = le16_to_cpu(resp->link_speed); |
| 4404 | else |
| 4405 | link_info->link_speed = 0; |
| 4406 | link_info->force_link_speed = le16_to_cpu(resp->force_link_speed); |
| 4407 | link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed); |
| 4408 | link_info->support_speeds = le16_to_cpu(resp->support_speeds); |
| 4409 | link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask); |
| 4410 | link_info->preemphasis = le32_to_cpu(resp->preemphasis); |
| 4411 | link_info->phy_ver[0] = resp->phy_maj; |
| 4412 | link_info->phy_ver[1] = resp->phy_min; |
| 4413 | link_info->phy_ver[2] = resp->phy_bld; |
| 4414 | link_info->media_type = resp->media_type; |
| 4415 | link_info->transceiver = resp->transceiver_type; |
| 4416 | link_info->phy_addr = resp->phy_addr; |
| 4417 | |
| 4418 | /* TODO: need to add more logic to report VF link */ |
| 4419 | if (chng_link_state) { |
| 4420 | if (link_info->phy_link_status == BNXT_LINK_LINK) |
| 4421 | link_info->link_up = 1; |
| 4422 | else |
| 4423 | link_info->link_up = 0; |
| 4424 | if (link_up != link_info->link_up) |
| 4425 | bnxt_report_link(bp); |
| 4426 | } else { |
| 4427 | /* alwasy link down if not require to update link state */ |
| 4428 | link_info->link_up = 0; |
| 4429 | } |
| 4430 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 4431 | return 0; |
| 4432 | } |
| 4433 | |
| 4434 | static void |
| 4435 | bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) |
| 4436 | { |
| 4437 | if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) { |
| 4438 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
| 4439 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; |
| 4440 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) |
| 4441 | req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX; |
| 4442 | req->enables |= |
| 4443 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE); |
| 4444 | } else { |
| 4445 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX) |
| 4446 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX; |
| 4447 | if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX) |
| 4448 | req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX; |
| 4449 | req->enables |= |
| 4450 | cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE); |
| 4451 | } |
| 4452 | } |
| 4453 | |
| 4454 | static void bnxt_hwrm_set_link_common(struct bnxt *bp, |
| 4455 | struct hwrm_port_phy_cfg_input *req) |
| 4456 | { |
| 4457 | u8 autoneg = bp->link_info.autoneg; |
| 4458 | u16 fw_link_speed = bp->link_info.req_link_speed; |
| 4459 | u32 advertising = bp->link_info.advertising; |
| 4460 | |
| 4461 | if (autoneg & BNXT_AUTONEG_SPEED) { |
| 4462 | req->auto_mode |= |
| 4463 | PORT_PHY_CFG_REQ_AUTO_MODE_MASK; |
| 4464 | |
| 4465 | req->enables |= cpu_to_le32( |
| 4466 | PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK); |
| 4467 | req->auto_link_speed_mask = cpu_to_le16(advertising); |
| 4468 | |
| 4469 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE); |
| 4470 | req->flags |= |
| 4471 | cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG); |
| 4472 | } else { |
| 4473 | req->force_link_speed = cpu_to_le16(fw_link_speed); |
| 4474 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE); |
| 4475 | } |
| 4476 | |
| 4477 | /* currently don't support half duplex */ |
| 4478 | req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL; |
| 4479 | req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX); |
| 4480 | /* tell chimp that the setting takes effect immediately */ |
| 4481 | req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY); |
| 4482 | } |
| 4483 | |
| 4484 | int bnxt_hwrm_set_pause(struct bnxt *bp) |
| 4485 | { |
| 4486 | struct hwrm_port_phy_cfg_input req = {0}; |
| 4487 | int rc; |
| 4488 | |
| 4489 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); |
| 4490 | bnxt_hwrm_set_pause_common(bp, &req); |
| 4491 | |
| 4492 | if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) || |
| 4493 | bp->link_info.force_link_chng) |
| 4494 | bnxt_hwrm_set_link_common(bp, &req); |
| 4495 | |
| 4496 | mutex_lock(&bp->hwrm_cmd_lock); |
| 4497 | rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 4498 | if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) { |
| 4499 | /* since changing of pause setting doesn't trigger any link |
| 4500 | * change event, the driver needs to update the current pause |
| 4501 | * result upon successfully return of the phy_cfg command |
| 4502 | */ |
| 4503 | bp->link_info.pause = |
| 4504 | bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl; |
| 4505 | bp->link_info.auto_pause_setting = 0; |
| 4506 | if (!bp->link_info.force_link_chng) |
| 4507 | bnxt_report_link(bp); |
| 4508 | } |
| 4509 | bp->link_info.force_link_chng = false; |
| 4510 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 4511 | return rc; |
| 4512 | } |
| 4513 | |
| 4514 | int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause) |
| 4515 | { |
| 4516 | struct hwrm_port_phy_cfg_input req = {0}; |
| 4517 | |
| 4518 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1); |
| 4519 | if (set_pause) |
| 4520 | bnxt_hwrm_set_pause_common(bp, &req); |
| 4521 | |
| 4522 | bnxt_hwrm_set_link_common(bp, &req); |
| 4523 | return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); |
| 4524 | } |
| 4525 | |
| 4526 | static int bnxt_update_phy_setting(struct bnxt *bp) |
| 4527 | { |
| 4528 | int rc; |
| 4529 | bool update_link = false; |
| 4530 | bool update_pause = false; |
| 4531 | struct bnxt_link_info *link_info = &bp->link_info; |
| 4532 | |
| 4533 | rc = bnxt_update_link(bp, true); |
| 4534 | if (rc) { |
| 4535 | netdev_err(bp->dev, "failed to update link (rc: %x)\n", |
| 4536 | rc); |
| 4537 | return rc; |
| 4538 | } |
| 4539 | if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
| 4540 | link_info->auto_pause_setting != link_info->req_flow_ctrl) |
| 4541 | update_pause = true; |
| 4542 | if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) && |
| 4543 | link_info->force_pause_setting != link_info->req_flow_ctrl) |
| 4544 | update_pause = true; |
| 4545 | if (link_info->req_duplex != link_info->duplex_setting) |
| 4546 | update_link = true; |
| 4547 | if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) { |
| 4548 | if (BNXT_AUTO_MODE(link_info->auto_mode)) |
| 4549 | update_link = true; |
| 4550 | if (link_info->req_link_speed != link_info->force_link_speed) |
| 4551 | update_link = true; |
| 4552 | } else { |
| 4553 | if (link_info->auto_mode == BNXT_LINK_AUTO_NONE) |
| 4554 | update_link = true; |
| 4555 | if (link_info->advertising != link_info->auto_link_speeds) |
| 4556 | update_link = true; |
| 4557 | if (link_info->req_link_speed != link_info->auto_link_speed) |
| 4558 | update_link = true; |
| 4559 | } |
| 4560 | |
| 4561 | if (update_link) |
| 4562 | rc = bnxt_hwrm_set_link_setting(bp, update_pause); |
| 4563 | else if (update_pause) |
| 4564 | rc = bnxt_hwrm_set_pause(bp); |
| 4565 | if (rc) { |
| 4566 | netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n", |
| 4567 | rc); |
| 4568 | return rc; |
| 4569 | } |
| 4570 | |
| 4571 | return rc; |
| 4572 | } |
| 4573 | |
Jeffrey Huang | 1180949 | 2015-11-05 16:25:49 -0500 | [diff] [blame] | 4574 | /* Common routine to pre-map certain register block to different GRC window. |
| 4575 | * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows |
| 4576 | * in PF and 3 windows in VF that can be customized to map in different |
| 4577 | * register blocks. |
| 4578 | */ |
| 4579 | static void bnxt_preset_reg_win(struct bnxt *bp) |
| 4580 | { |
| 4581 | if (BNXT_PF(bp)) { |
| 4582 | /* CAG registers map to GRC window #4 */ |
| 4583 | writel(BNXT_CAG_REG_BASE, |
| 4584 | bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12); |
| 4585 | } |
| 4586 | } |
| 4587 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4588 | static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
| 4589 | { |
| 4590 | int rc = 0; |
| 4591 | |
Jeffrey Huang | 1180949 | 2015-11-05 16:25:49 -0500 | [diff] [blame] | 4592 | bnxt_preset_reg_win(bp); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4593 | netif_carrier_off(bp->dev); |
| 4594 | if (irq_re_init) { |
| 4595 | rc = bnxt_setup_int_mode(bp); |
| 4596 | if (rc) { |
| 4597 | netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n", |
| 4598 | rc); |
| 4599 | return rc; |
| 4600 | } |
| 4601 | } |
| 4602 | if ((bp->flags & BNXT_FLAG_RFS) && |
| 4603 | !(bp->flags & BNXT_FLAG_USING_MSIX)) { |
| 4604 | /* disable RFS if falling back to INTA */ |
| 4605 | bp->dev->hw_features &= ~NETIF_F_NTUPLE; |
| 4606 | bp->flags &= ~BNXT_FLAG_RFS; |
| 4607 | } |
| 4608 | |
| 4609 | rc = bnxt_alloc_mem(bp, irq_re_init); |
| 4610 | if (rc) { |
| 4611 | netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc); |
| 4612 | goto open_err_free_mem; |
| 4613 | } |
| 4614 | |
| 4615 | if (irq_re_init) { |
| 4616 | bnxt_init_napi(bp); |
| 4617 | rc = bnxt_request_irq(bp); |
| 4618 | if (rc) { |
| 4619 | netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc); |
| 4620 | goto open_err; |
| 4621 | } |
| 4622 | } |
| 4623 | |
| 4624 | bnxt_enable_napi(bp); |
| 4625 | |
| 4626 | rc = bnxt_init_nic(bp, irq_re_init); |
| 4627 | if (rc) { |
| 4628 | netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc); |
| 4629 | goto open_err; |
| 4630 | } |
| 4631 | |
| 4632 | if (link_re_init) { |
| 4633 | rc = bnxt_update_phy_setting(bp); |
| 4634 | if (rc) |
| 4635 | goto open_err; |
| 4636 | } |
| 4637 | |
| 4638 | if (irq_re_init) { |
| 4639 | #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE) |
| 4640 | vxlan_get_rx_port(bp->dev); |
| 4641 | #endif |
| 4642 | if (!bnxt_hwrm_tunnel_dst_port_alloc( |
| 4643 | bp, htons(0x17c1), |
| 4644 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE)) |
| 4645 | bp->nge_port_cnt = 1; |
| 4646 | } |
| 4647 | |
Michael Chan | caefe52 | 2015-12-09 19:35:42 -0500 | [diff] [blame] | 4648 | set_bit(BNXT_STATE_OPEN, &bp->state); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4649 | bnxt_enable_int(bp); |
| 4650 | /* Enable TX queues */ |
| 4651 | bnxt_tx_enable(bp); |
| 4652 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
| 4653 | |
| 4654 | return 0; |
| 4655 | |
| 4656 | open_err: |
| 4657 | bnxt_disable_napi(bp); |
| 4658 | bnxt_del_napi(bp); |
| 4659 | |
| 4660 | open_err_free_mem: |
| 4661 | bnxt_free_skbs(bp); |
| 4662 | bnxt_free_irq(bp); |
| 4663 | bnxt_free_mem(bp, true); |
| 4664 | return rc; |
| 4665 | } |
| 4666 | |
| 4667 | /* rtnl_lock held */ |
| 4668 | int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
| 4669 | { |
| 4670 | int rc = 0; |
| 4671 | |
| 4672 | rc = __bnxt_open_nic(bp, irq_re_init, link_re_init); |
| 4673 | if (rc) { |
| 4674 | netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc); |
| 4675 | dev_close(bp->dev); |
| 4676 | } |
| 4677 | return rc; |
| 4678 | } |
| 4679 | |
| 4680 | static int bnxt_open(struct net_device *dev) |
| 4681 | { |
| 4682 | struct bnxt *bp = netdev_priv(dev); |
| 4683 | int rc = 0; |
| 4684 | |
| 4685 | rc = bnxt_hwrm_func_reset(bp); |
| 4686 | if (rc) { |
| 4687 | netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n", |
| 4688 | rc); |
| 4689 | rc = -1; |
| 4690 | return rc; |
| 4691 | } |
| 4692 | return __bnxt_open_nic(bp, true, true); |
| 4693 | } |
| 4694 | |
| 4695 | static void bnxt_disable_int_sync(struct bnxt *bp) |
| 4696 | { |
| 4697 | int i; |
| 4698 | |
| 4699 | atomic_inc(&bp->intr_sem); |
| 4700 | if (!netif_running(bp->dev)) |
| 4701 | return; |
| 4702 | |
| 4703 | bnxt_disable_int(bp); |
| 4704 | for (i = 0; i < bp->cp_nr_rings; i++) |
| 4705 | synchronize_irq(bp->irq_tbl[i].vector); |
| 4706 | } |
| 4707 | |
| 4708 | int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) |
| 4709 | { |
| 4710 | int rc = 0; |
| 4711 | |
| 4712 | #ifdef CONFIG_BNXT_SRIOV |
| 4713 | if (bp->sriov_cfg) { |
| 4714 | rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait, |
| 4715 | !bp->sriov_cfg, |
| 4716 | BNXT_SRIOV_CFG_WAIT_TMO); |
| 4717 | if (rc) |
| 4718 | netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n"); |
| 4719 | } |
| 4720 | #endif |
| 4721 | /* Change device state to avoid TX queue wake up's */ |
| 4722 | bnxt_tx_disable(bp); |
| 4723 | |
Michael Chan | caefe52 | 2015-12-09 19:35:42 -0500 | [diff] [blame] | 4724 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
Michael Chan | 4cebdce | 2015-12-09 19:35:43 -0500 | [diff] [blame] | 4725 | smp_mb__after_atomic(); |
| 4726 | while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state)) |
| 4727 | msleep(20); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4728 | |
| 4729 | /* Flush rings before disabling interrupts */ |
| 4730 | bnxt_shutdown_nic(bp, irq_re_init); |
| 4731 | |
| 4732 | /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */ |
| 4733 | |
| 4734 | bnxt_disable_napi(bp); |
| 4735 | bnxt_disable_int_sync(bp); |
| 4736 | del_timer_sync(&bp->timer); |
| 4737 | bnxt_free_skbs(bp); |
| 4738 | |
| 4739 | if (irq_re_init) { |
| 4740 | bnxt_free_irq(bp); |
| 4741 | bnxt_del_napi(bp); |
| 4742 | } |
| 4743 | bnxt_free_mem(bp, irq_re_init); |
| 4744 | return rc; |
| 4745 | } |
| 4746 | |
| 4747 | static int bnxt_close(struct net_device *dev) |
| 4748 | { |
| 4749 | struct bnxt *bp = netdev_priv(dev); |
| 4750 | |
| 4751 | bnxt_close_nic(bp, true, true); |
| 4752 | return 0; |
| 4753 | } |
| 4754 | |
| 4755 | /* rtnl_lock held */ |
| 4756 | static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
| 4757 | { |
| 4758 | switch (cmd) { |
| 4759 | case SIOCGMIIPHY: |
| 4760 | /* fallthru */ |
| 4761 | case SIOCGMIIREG: { |
| 4762 | if (!netif_running(dev)) |
| 4763 | return -EAGAIN; |
| 4764 | |
| 4765 | return 0; |
| 4766 | } |
| 4767 | |
| 4768 | case SIOCSMIIREG: |
| 4769 | if (!netif_running(dev)) |
| 4770 | return -EAGAIN; |
| 4771 | |
| 4772 | return 0; |
| 4773 | |
| 4774 | default: |
| 4775 | /* do nothing */ |
| 4776 | break; |
| 4777 | } |
| 4778 | return -EOPNOTSUPP; |
| 4779 | } |
| 4780 | |
| 4781 | static struct rtnl_link_stats64 * |
| 4782 | bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) |
| 4783 | { |
| 4784 | u32 i; |
| 4785 | struct bnxt *bp = netdev_priv(dev); |
| 4786 | |
| 4787 | memset(stats, 0, sizeof(struct rtnl_link_stats64)); |
| 4788 | |
| 4789 | if (!bp->bnapi) |
| 4790 | return stats; |
| 4791 | |
| 4792 | /* TODO check if we need to synchronize with bnxt_close path */ |
| 4793 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 4794 | struct bnxt_napi *bnapi = bp->bnapi[i]; |
| 4795 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 4796 | struct ctx_hw_stats *hw_stats = cpr->hw_stats; |
| 4797 | |
| 4798 | stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts); |
| 4799 | stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts); |
| 4800 | stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts); |
| 4801 | |
| 4802 | stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts); |
| 4803 | stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts); |
| 4804 | stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts); |
| 4805 | |
| 4806 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes); |
| 4807 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes); |
| 4808 | stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes); |
| 4809 | |
| 4810 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes); |
| 4811 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes); |
| 4812 | stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes); |
| 4813 | |
| 4814 | stats->rx_missed_errors += |
| 4815 | le64_to_cpu(hw_stats->rx_discard_pkts); |
| 4816 | |
| 4817 | stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts); |
| 4818 | |
| 4819 | stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts); |
| 4820 | |
| 4821 | stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts); |
| 4822 | } |
| 4823 | |
| 4824 | return stats; |
| 4825 | } |
| 4826 | |
| 4827 | static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask) |
| 4828 | { |
| 4829 | struct net_device *dev = bp->dev; |
| 4830 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
| 4831 | struct netdev_hw_addr *ha; |
| 4832 | u8 *haddr; |
| 4833 | int mc_count = 0; |
| 4834 | bool update = false; |
| 4835 | int off = 0; |
| 4836 | |
| 4837 | netdev_for_each_mc_addr(ha, dev) { |
| 4838 | if (mc_count >= BNXT_MAX_MC_ADDRS) { |
| 4839 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; |
| 4840 | vnic->mc_list_count = 0; |
| 4841 | return false; |
| 4842 | } |
| 4843 | haddr = ha->addr; |
| 4844 | if (!ether_addr_equal(haddr, vnic->mc_list + off)) { |
| 4845 | memcpy(vnic->mc_list + off, haddr, ETH_ALEN); |
| 4846 | update = true; |
| 4847 | } |
| 4848 | off += ETH_ALEN; |
| 4849 | mc_count++; |
| 4850 | } |
| 4851 | if (mc_count) |
| 4852 | *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST; |
| 4853 | |
| 4854 | if (mc_count != vnic->mc_list_count) { |
| 4855 | vnic->mc_list_count = mc_count; |
| 4856 | update = true; |
| 4857 | } |
| 4858 | return update; |
| 4859 | } |
| 4860 | |
| 4861 | static bool bnxt_uc_list_updated(struct bnxt *bp) |
| 4862 | { |
| 4863 | struct net_device *dev = bp->dev; |
| 4864 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
| 4865 | struct netdev_hw_addr *ha; |
| 4866 | int off = 0; |
| 4867 | |
| 4868 | if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1)) |
| 4869 | return true; |
| 4870 | |
| 4871 | netdev_for_each_uc_addr(ha, dev) { |
| 4872 | if (!ether_addr_equal(ha->addr, vnic->uc_list + off)) |
| 4873 | return true; |
| 4874 | |
| 4875 | off += ETH_ALEN; |
| 4876 | } |
| 4877 | return false; |
| 4878 | } |
| 4879 | |
| 4880 | static void bnxt_set_rx_mode(struct net_device *dev) |
| 4881 | { |
| 4882 | struct bnxt *bp = netdev_priv(dev); |
| 4883 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
| 4884 | u32 mask = vnic->rx_mask; |
| 4885 | bool mc_update = false; |
| 4886 | bool uc_update; |
| 4887 | |
| 4888 | if (!netif_running(dev)) |
| 4889 | return; |
| 4890 | |
| 4891 | mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS | |
| 4892 | CFA_L2_SET_RX_MASK_REQ_MASK_MCAST | |
| 4893 | CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST); |
| 4894 | |
| 4895 | /* Only allow PF to be in promiscuous mode */ |
| 4896 | if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp)) |
| 4897 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
| 4898 | |
| 4899 | uc_update = bnxt_uc_list_updated(bp); |
| 4900 | |
| 4901 | if (dev->flags & IFF_ALLMULTI) { |
| 4902 | mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST; |
| 4903 | vnic->mc_list_count = 0; |
| 4904 | } else { |
| 4905 | mc_update = bnxt_mc_list_updated(bp, &mask); |
| 4906 | } |
| 4907 | |
| 4908 | if (mask != vnic->rx_mask || uc_update || mc_update) { |
| 4909 | vnic->rx_mask = mask; |
| 4910 | |
| 4911 | set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event); |
| 4912 | schedule_work(&bp->sp_task); |
| 4913 | } |
| 4914 | } |
| 4915 | |
Michael Chan | b664f00 | 2015-12-02 01:54:08 -0500 | [diff] [blame] | 4916 | static int bnxt_cfg_rx_mode(struct bnxt *bp) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4917 | { |
| 4918 | struct net_device *dev = bp->dev; |
| 4919 | struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; |
| 4920 | struct netdev_hw_addr *ha; |
| 4921 | int i, off = 0, rc; |
| 4922 | bool uc_update; |
| 4923 | |
| 4924 | netif_addr_lock_bh(dev); |
| 4925 | uc_update = bnxt_uc_list_updated(bp); |
| 4926 | netif_addr_unlock_bh(dev); |
| 4927 | |
| 4928 | if (!uc_update) |
| 4929 | goto skip_uc; |
| 4930 | |
| 4931 | mutex_lock(&bp->hwrm_cmd_lock); |
| 4932 | for (i = 1; i < vnic->uc_filter_count; i++) { |
| 4933 | struct hwrm_cfa_l2_filter_free_input req = {0}; |
| 4934 | |
| 4935 | bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1, |
| 4936 | -1); |
| 4937 | |
| 4938 | req.l2_filter_id = vnic->fw_l2_filter_id[i]; |
| 4939 | |
| 4940 | rc = _hwrm_send_message(bp, &req, sizeof(req), |
| 4941 | HWRM_CMD_TIMEOUT); |
| 4942 | } |
| 4943 | mutex_unlock(&bp->hwrm_cmd_lock); |
| 4944 | |
| 4945 | vnic->uc_filter_count = 1; |
| 4946 | |
| 4947 | netif_addr_lock_bh(dev); |
| 4948 | if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) { |
| 4949 | vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS; |
| 4950 | } else { |
| 4951 | netdev_for_each_uc_addr(ha, dev) { |
| 4952 | memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN); |
| 4953 | off += ETH_ALEN; |
| 4954 | vnic->uc_filter_count++; |
| 4955 | } |
| 4956 | } |
| 4957 | netif_addr_unlock_bh(dev); |
| 4958 | |
| 4959 | for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) { |
| 4960 | rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off); |
| 4961 | if (rc) { |
| 4962 | netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", |
| 4963 | rc); |
| 4964 | vnic->uc_filter_count = i; |
Michael Chan | b664f00 | 2015-12-02 01:54:08 -0500 | [diff] [blame] | 4965 | return rc; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4966 | } |
| 4967 | } |
| 4968 | |
| 4969 | skip_uc: |
| 4970 | rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0); |
| 4971 | if (rc) |
| 4972 | netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n", |
| 4973 | rc); |
Michael Chan | b664f00 | 2015-12-02 01:54:08 -0500 | [diff] [blame] | 4974 | |
| 4975 | return rc; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4976 | } |
| 4977 | |
Michael Chan | 2bcfa6f | 2015-12-27 18:19:24 -0500 | [diff] [blame] | 4978 | static bool bnxt_rfs_capable(struct bnxt *bp) |
| 4979 | { |
| 4980 | #ifdef CONFIG_RFS_ACCEL |
| 4981 | struct bnxt_pf_info *pf = &bp->pf; |
| 4982 | int vnics; |
| 4983 | |
| 4984 | if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP)) |
| 4985 | return false; |
| 4986 | |
| 4987 | vnics = 1 + bp->rx_nr_rings; |
| 4988 | if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics) |
| 4989 | return false; |
| 4990 | |
| 4991 | return true; |
| 4992 | #else |
| 4993 | return false; |
| 4994 | #endif |
| 4995 | } |
| 4996 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 4997 | static netdev_features_t bnxt_fix_features(struct net_device *dev, |
| 4998 | netdev_features_t features) |
| 4999 | { |
Michael Chan | 2bcfa6f | 2015-12-27 18:19:24 -0500 | [diff] [blame] | 5000 | struct bnxt *bp = netdev_priv(dev); |
| 5001 | |
| 5002 | if (!bnxt_rfs_capable(bp)) |
| 5003 | features &= ~NETIF_F_NTUPLE; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5004 | return features; |
| 5005 | } |
| 5006 | |
| 5007 | static int bnxt_set_features(struct net_device *dev, netdev_features_t features) |
| 5008 | { |
| 5009 | struct bnxt *bp = netdev_priv(dev); |
| 5010 | u32 flags = bp->flags; |
| 5011 | u32 changes; |
| 5012 | int rc = 0; |
| 5013 | bool re_init = false; |
| 5014 | bool update_tpa = false; |
| 5015 | |
| 5016 | flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS; |
| 5017 | if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0)) |
| 5018 | flags |= BNXT_FLAG_GRO; |
| 5019 | if (features & NETIF_F_LRO) |
| 5020 | flags |= BNXT_FLAG_LRO; |
| 5021 | |
| 5022 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
| 5023 | flags |= BNXT_FLAG_STRIP_VLAN; |
| 5024 | |
| 5025 | if (features & NETIF_F_NTUPLE) |
| 5026 | flags |= BNXT_FLAG_RFS; |
| 5027 | |
| 5028 | changes = flags ^ bp->flags; |
| 5029 | if (changes & BNXT_FLAG_TPA) { |
| 5030 | update_tpa = true; |
| 5031 | if ((bp->flags & BNXT_FLAG_TPA) == 0 || |
| 5032 | (flags & BNXT_FLAG_TPA) == 0) |
| 5033 | re_init = true; |
| 5034 | } |
| 5035 | |
| 5036 | if (changes & ~BNXT_FLAG_TPA) |
| 5037 | re_init = true; |
| 5038 | |
| 5039 | if (flags != bp->flags) { |
| 5040 | u32 old_flags = bp->flags; |
| 5041 | |
| 5042 | bp->flags = flags; |
| 5043 | |
Michael Chan | 2bcfa6f | 2015-12-27 18:19:24 -0500 | [diff] [blame] | 5044 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5045 | if (update_tpa) |
| 5046 | bnxt_set_ring_params(bp); |
| 5047 | return rc; |
| 5048 | } |
| 5049 | |
| 5050 | if (re_init) { |
| 5051 | bnxt_close_nic(bp, false, false); |
| 5052 | if (update_tpa) |
| 5053 | bnxt_set_ring_params(bp); |
| 5054 | |
| 5055 | return bnxt_open_nic(bp, false, false); |
| 5056 | } |
| 5057 | if (update_tpa) { |
| 5058 | rc = bnxt_set_tpa(bp, |
| 5059 | (flags & BNXT_FLAG_TPA) ? |
| 5060 | true : false); |
| 5061 | if (rc) |
| 5062 | bp->flags = old_flags; |
| 5063 | } |
| 5064 | } |
| 5065 | return rc; |
| 5066 | } |
| 5067 | |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5068 | static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi) |
| 5069 | { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 5070 | struct bnxt_tx_ring_info *txr = bnapi->tx_ring; |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5071 | int i = bnapi->index; |
| 5072 | |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 5073 | if (!txr) |
| 5074 | return; |
| 5075 | |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5076 | netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n", |
| 5077 | i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod, |
| 5078 | txr->tx_cons); |
| 5079 | } |
| 5080 | |
| 5081 | static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi) |
| 5082 | { |
Michael Chan | b6ab4b0 | 2016-01-02 23:44:59 -0500 | [diff] [blame] | 5083 | struct bnxt_rx_ring_info *rxr = bnapi->rx_ring; |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5084 | int i = bnapi->index; |
| 5085 | |
Michael Chan | 3b2b7d9 | 2016-01-02 23:45:00 -0500 | [diff] [blame] | 5086 | if (!rxr) |
| 5087 | return; |
| 5088 | |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5089 | netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n", |
| 5090 | i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod, |
| 5091 | rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod, |
| 5092 | rxr->rx_sw_agg_prod); |
| 5093 | } |
| 5094 | |
| 5095 | static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi) |
| 5096 | { |
| 5097 | struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; |
| 5098 | int i = bnapi->index; |
| 5099 | |
| 5100 | netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n", |
| 5101 | i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons); |
| 5102 | } |
| 5103 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5104 | static void bnxt_dbg_dump_states(struct bnxt *bp) |
| 5105 | { |
| 5106 | int i; |
| 5107 | struct bnxt_napi *bnapi; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5108 | |
| 5109 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 5110 | bnapi = bp->bnapi[i]; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5111 | if (netif_msg_drv(bp)) { |
Michael Chan | 9f55459 | 2016-01-02 23:44:58 -0500 | [diff] [blame] | 5112 | bnxt_dump_tx_sw_state(bnapi); |
| 5113 | bnxt_dump_rx_sw_state(bnapi); |
| 5114 | bnxt_dump_cp_sw_state(bnapi); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5115 | } |
| 5116 | } |
| 5117 | } |
| 5118 | |
| 5119 | static void bnxt_reset_task(struct bnxt *bp) |
| 5120 | { |
| 5121 | bnxt_dbg_dump_states(bp); |
Michael Chan | 028de14 | 2015-12-09 19:35:44 -0500 | [diff] [blame] | 5122 | if (netif_running(bp->dev)) { |
| 5123 | bnxt_close_nic(bp, false, false); |
| 5124 | bnxt_open_nic(bp, false, false); |
| 5125 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5126 | } |
| 5127 | |
| 5128 | static void bnxt_tx_timeout(struct net_device *dev) |
| 5129 | { |
| 5130 | struct bnxt *bp = netdev_priv(dev); |
| 5131 | |
| 5132 | netdev_err(bp->dev, "TX timeout detected, starting reset task!\n"); |
| 5133 | set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event); |
| 5134 | schedule_work(&bp->sp_task); |
| 5135 | } |
| 5136 | |
| 5137 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 5138 | static void bnxt_poll_controller(struct net_device *dev) |
| 5139 | { |
| 5140 | struct bnxt *bp = netdev_priv(dev); |
| 5141 | int i; |
| 5142 | |
| 5143 | for (i = 0; i < bp->cp_nr_rings; i++) { |
| 5144 | struct bnxt_irq *irq = &bp->irq_tbl[i]; |
| 5145 | |
| 5146 | disable_irq(irq->vector); |
| 5147 | irq->handler(irq->vector, bp->bnapi[i]); |
| 5148 | enable_irq(irq->vector); |
| 5149 | } |
| 5150 | } |
| 5151 | #endif |
| 5152 | |
| 5153 | static void bnxt_timer(unsigned long data) |
| 5154 | { |
| 5155 | struct bnxt *bp = (struct bnxt *)data; |
| 5156 | struct net_device *dev = bp->dev; |
| 5157 | |
| 5158 | if (!netif_running(dev)) |
| 5159 | return; |
| 5160 | |
| 5161 | if (atomic_read(&bp->intr_sem) != 0) |
| 5162 | goto bnxt_restart_timer; |
| 5163 | |
| 5164 | bnxt_restart_timer: |
| 5165 | mod_timer(&bp->timer, jiffies + bp->current_interval); |
| 5166 | } |
| 5167 | |
| 5168 | static void bnxt_cfg_ntp_filters(struct bnxt *); |
| 5169 | |
| 5170 | static void bnxt_sp_task(struct work_struct *work) |
| 5171 | { |
| 5172 | struct bnxt *bp = container_of(work, struct bnxt, sp_task); |
| 5173 | int rc; |
| 5174 | |
Michael Chan | 4cebdce | 2015-12-09 19:35:43 -0500 | [diff] [blame] | 5175 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
| 5176 | smp_mb__after_atomic(); |
| 5177 | if (!test_bit(BNXT_STATE_OPEN, &bp->state)) { |
| 5178 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5179 | return; |
Michael Chan | 4cebdce | 2015-12-09 19:35:43 -0500 | [diff] [blame] | 5180 | } |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5181 | |
| 5182 | if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) |
| 5183 | bnxt_cfg_rx_mode(bp); |
| 5184 | |
| 5185 | if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event)) |
| 5186 | bnxt_cfg_ntp_filters(bp); |
| 5187 | if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) { |
| 5188 | rc = bnxt_update_link(bp, true); |
| 5189 | if (rc) |
| 5190 | netdev_err(bp->dev, "SP task can't update link (rc: %x)\n", |
| 5191 | rc); |
| 5192 | } |
| 5193 | if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event)) |
| 5194 | bnxt_hwrm_exec_fwd_req(bp); |
| 5195 | if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) { |
| 5196 | bnxt_hwrm_tunnel_dst_port_alloc( |
| 5197 | bp, bp->vxlan_port, |
| 5198 | TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); |
| 5199 | } |
| 5200 | if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) { |
| 5201 | bnxt_hwrm_tunnel_dst_port_free( |
| 5202 | bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN); |
| 5203 | } |
Michael Chan | 028de14 | 2015-12-09 19:35:44 -0500 | [diff] [blame] | 5204 | if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) { |
| 5205 | /* bnxt_reset_task() calls bnxt_close_nic() which waits |
| 5206 | * for BNXT_STATE_IN_SP_TASK to clear. |
| 5207 | */ |
| 5208 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
| 5209 | rtnl_lock(); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5210 | bnxt_reset_task(bp); |
Michael Chan | 028de14 | 2015-12-09 19:35:44 -0500 | [diff] [blame] | 5211 | set_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
| 5212 | rtnl_unlock(); |
| 5213 | } |
Michael Chan | 4cebdce | 2015-12-09 19:35:43 -0500 | [diff] [blame] | 5214 | |
| 5215 | smp_mb__before_atomic(); |
| 5216 | clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5217 | } |
| 5218 | |
| 5219 | static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev) |
| 5220 | { |
| 5221 | int rc; |
| 5222 | struct bnxt *bp = netdev_priv(dev); |
| 5223 | |
| 5224 | SET_NETDEV_DEV(dev, &pdev->dev); |
| 5225 | |
| 5226 | /* enable device (incl. PCI PM wakeup), and bus-mastering */ |
| 5227 | rc = pci_enable_device(pdev); |
| 5228 | if (rc) { |
| 5229 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
| 5230 | goto init_err; |
| 5231 | } |
| 5232 | |
| 5233 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
| 5234 | dev_err(&pdev->dev, |
| 5235 | "Cannot find PCI device base address, aborting\n"); |
| 5236 | rc = -ENODEV; |
| 5237 | goto init_err_disable; |
| 5238 | } |
| 5239 | |
| 5240 | rc = pci_request_regions(pdev, DRV_MODULE_NAME); |
| 5241 | if (rc) { |
| 5242 | dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); |
| 5243 | goto init_err_disable; |
| 5244 | } |
| 5245 | |
| 5246 | if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 && |
| 5247 | dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) { |
| 5248 | dev_err(&pdev->dev, "System does not support DMA, aborting\n"); |
| 5249 | goto init_err_disable; |
| 5250 | } |
| 5251 | |
| 5252 | pci_set_master(pdev); |
| 5253 | |
| 5254 | bp->dev = dev; |
| 5255 | bp->pdev = pdev; |
| 5256 | |
| 5257 | bp->bar0 = pci_ioremap_bar(pdev, 0); |
| 5258 | if (!bp->bar0) { |
| 5259 | dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); |
| 5260 | rc = -ENOMEM; |
| 5261 | goto init_err_release; |
| 5262 | } |
| 5263 | |
| 5264 | bp->bar1 = pci_ioremap_bar(pdev, 2); |
| 5265 | if (!bp->bar1) { |
| 5266 | dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n"); |
| 5267 | rc = -ENOMEM; |
| 5268 | goto init_err_release; |
| 5269 | } |
| 5270 | |
| 5271 | bp->bar2 = pci_ioremap_bar(pdev, 4); |
| 5272 | if (!bp->bar2) { |
| 5273 | dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n"); |
| 5274 | rc = -ENOMEM; |
| 5275 | goto init_err_release; |
| 5276 | } |
| 5277 | |
| 5278 | INIT_WORK(&bp->sp_task, bnxt_sp_task); |
| 5279 | |
| 5280 | spin_lock_init(&bp->ntp_fltr_lock); |
| 5281 | |
| 5282 | bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE; |
| 5283 | bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE; |
| 5284 | |
| 5285 | bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4); |
| 5286 | bp->coal_bufs = 20; |
| 5287 | bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1); |
| 5288 | bp->coal_bufs_irq = 2; |
| 5289 | |
| 5290 | init_timer(&bp->timer); |
| 5291 | bp->timer.data = (unsigned long)bp; |
| 5292 | bp->timer.function = bnxt_timer; |
| 5293 | bp->current_interval = BNXT_TIMER_INTERVAL; |
| 5294 | |
Michael Chan | caefe52 | 2015-12-09 19:35:42 -0500 | [diff] [blame] | 5295 | clear_bit(BNXT_STATE_OPEN, &bp->state); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5296 | |
| 5297 | return 0; |
| 5298 | |
| 5299 | init_err_release: |
| 5300 | if (bp->bar2) { |
| 5301 | pci_iounmap(pdev, bp->bar2); |
| 5302 | bp->bar2 = NULL; |
| 5303 | } |
| 5304 | |
| 5305 | if (bp->bar1) { |
| 5306 | pci_iounmap(pdev, bp->bar1); |
| 5307 | bp->bar1 = NULL; |
| 5308 | } |
| 5309 | |
| 5310 | if (bp->bar0) { |
| 5311 | pci_iounmap(pdev, bp->bar0); |
| 5312 | bp->bar0 = NULL; |
| 5313 | } |
| 5314 | |
| 5315 | pci_release_regions(pdev); |
| 5316 | |
| 5317 | init_err_disable: |
| 5318 | pci_disable_device(pdev); |
| 5319 | |
| 5320 | init_err: |
| 5321 | return rc; |
| 5322 | } |
| 5323 | |
| 5324 | /* rtnl_lock held */ |
| 5325 | static int bnxt_change_mac_addr(struct net_device *dev, void *p) |
| 5326 | { |
| 5327 | struct sockaddr *addr = p; |
Jeffrey Huang | 1fc2cfd | 2015-12-02 01:54:06 -0500 | [diff] [blame] | 5328 | struct bnxt *bp = netdev_priv(dev); |
| 5329 | int rc = 0; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5330 | |
| 5331 | if (!is_valid_ether_addr(addr->sa_data)) |
| 5332 | return -EADDRNOTAVAIL; |
| 5333 | |
Jeffrey Huang | bdd4347 | 2015-12-02 01:54:07 -0500 | [diff] [blame] | 5334 | #ifdef CONFIG_BNXT_SRIOV |
| 5335 | if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr)) |
| 5336 | return -EADDRNOTAVAIL; |
| 5337 | #endif |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5338 | |
Jeffrey Huang | 1fc2cfd | 2015-12-02 01:54:06 -0500 | [diff] [blame] | 5339 | if (ether_addr_equal(addr->sa_data, dev->dev_addr)) |
| 5340 | return 0; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5341 | |
Jeffrey Huang | 1fc2cfd | 2015-12-02 01:54:06 -0500 | [diff] [blame] | 5342 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); |
| 5343 | if (netif_running(dev)) { |
| 5344 | bnxt_close_nic(bp, false, false); |
| 5345 | rc = bnxt_open_nic(bp, false, false); |
| 5346 | } |
| 5347 | |
| 5348 | return rc; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5349 | } |
| 5350 | |
| 5351 | /* rtnl_lock held */ |
| 5352 | static int bnxt_change_mtu(struct net_device *dev, int new_mtu) |
| 5353 | { |
| 5354 | struct bnxt *bp = netdev_priv(dev); |
| 5355 | |
| 5356 | if (new_mtu < 60 || new_mtu > 9000) |
| 5357 | return -EINVAL; |
| 5358 | |
| 5359 | if (netif_running(dev)) |
| 5360 | bnxt_close_nic(bp, false, false); |
| 5361 | |
| 5362 | dev->mtu = new_mtu; |
| 5363 | bnxt_set_ring_params(bp); |
| 5364 | |
| 5365 | if (netif_running(dev)) |
| 5366 | return bnxt_open_nic(bp, false, false); |
| 5367 | |
| 5368 | return 0; |
| 5369 | } |
| 5370 | |
| 5371 | static int bnxt_setup_tc(struct net_device *dev, u8 tc) |
| 5372 | { |
| 5373 | struct bnxt *bp = netdev_priv(dev); |
| 5374 | |
| 5375 | if (tc > bp->max_tc) { |
| 5376 | netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n", |
| 5377 | tc, bp->max_tc); |
| 5378 | return -EINVAL; |
| 5379 | } |
| 5380 | |
| 5381 | if (netdev_get_num_tc(dev) == tc) |
| 5382 | return 0; |
| 5383 | |
| 5384 | if (tc) { |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5385 | int max_rx_rings, max_tx_rings, rc; |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 5386 | bool sh = false; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5387 | |
Michael Chan | 01657bc | 2016-01-02 23:45:03 -0500 | [diff] [blame] | 5388 | if (bp->flags & BNXT_FLAG_SHARED_RINGS) |
| 5389 | sh = true; |
| 5390 | |
| 5391 | rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5392 | if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5393 | return -ENOMEM; |
| 5394 | } |
| 5395 | |
| 5396 | /* Needs to close the device and do hw resource re-allocations */ |
| 5397 | if (netif_running(bp->dev)) |
| 5398 | bnxt_close_nic(bp, true, false); |
| 5399 | |
| 5400 | if (tc) { |
| 5401 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc; |
| 5402 | netdev_set_num_tc(dev, tc); |
| 5403 | } else { |
| 5404 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; |
| 5405 | netdev_reset_tc(dev); |
| 5406 | } |
| 5407 | bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings); |
| 5408 | bp->num_stat_ctxs = bp->cp_nr_rings; |
| 5409 | |
| 5410 | if (netif_running(bp->dev)) |
| 5411 | return bnxt_open_nic(bp, true, false); |
| 5412 | |
| 5413 | return 0; |
| 5414 | } |
| 5415 | |
| 5416 | #ifdef CONFIG_RFS_ACCEL |
| 5417 | static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1, |
| 5418 | struct bnxt_ntuple_filter *f2) |
| 5419 | { |
| 5420 | struct flow_keys *keys1 = &f1->fkeys; |
| 5421 | struct flow_keys *keys2 = &f2->fkeys; |
| 5422 | |
| 5423 | if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src && |
| 5424 | keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst && |
| 5425 | keys1->ports.ports == keys2->ports.ports && |
| 5426 | keys1->basic.ip_proto == keys2->basic.ip_proto && |
| 5427 | keys1->basic.n_proto == keys2->basic.n_proto && |
| 5428 | ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr)) |
| 5429 | return true; |
| 5430 | |
| 5431 | return false; |
| 5432 | } |
| 5433 | |
| 5434 | static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb, |
| 5435 | u16 rxq_index, u32 flow_id) |
| 5436 | { |
| 5437 | struct bnxt *bp = netdev_priv(dev); |
| 5438 | struct bnxt_ntuple_filter *fltr, *new_fltr; |
| 5439 | struct flow_keys *fkeys; |
| 5440 | struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb); |
Michael Chan | 84e86b9 | 2015-11-05 16:25:50 -0500 | [diff] [blame] | 5441 | int rc = 0, idx, bit_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5442 | struct hlist_head *head; |
| 5443 | |
| 5444 | if (skb->encapsulation) |
| 5445 | return -EPROTONOSUPPORT; |
| 5446 | |
| 5447 | new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC); |
| 5448 | if (!new_fltr) |
| 5449 | return -ENOMEM; |
| 5450 | |
| 5451 | fkeys = &new_fltr->fkeys; |
| 5452 | if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) { |
| 5453 | rc = -EPROTONOSUPPORT; |
| 5454 | goto err_free; |
| 5455 | } |
| 5456 | |
| 5457 | if ((fkeys->basic.n_proto != htons(ETH_P_IP)) || |
| 5458 | ((fkeys->basic.ip_proto != IPPROTO_TCP) && |
| 5459 | (fkeys->basic.ip_proto != IPPROTO_UDP))) { |
| 5460 | rc = -EPROTONOSUPPORT; |
| 5461 | goto err_free; |
| 5462 | } |
| 5463 | |
| 5464 | memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN); |
| 5465 | |
| 5466 | idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK; |
| 5467 | head = &bp->ntp_fltr_hash_tbl[idx]; |
| 5468 | rcu_read_lock(); |
| 5469 | hlist_for_each_entry_rcu(fltr, head, hash) { |
| 5470 | if (bnxt_fltr_match(fltr, new_fltr)) { |
| 5471 | rcu_read_unlock(); |
| 5472 | rc = 0; |
| 5473 | goto err_free; |
| 5474 | } |
| 5475 | } |
| 5476 | rcu_read_unlock(); |
| 5477 | |
| 5478 | spin_lock_bh(&bp->ntp_fltr_lock); |
Michael Chan | 84e86b9 | 2015-11-05 16:25:50 -0500 | [diff] [blame] | 5479 | bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap, |
| 5480 | BNXT_NTP_FLTR_MAX_FLTR, 0); |
| 5481 | if (bit_id < 0) { |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5482 | spin_unlock_bh(&bp->ntp_fltr_lock); |
| 5483 | rc = -ENOMEM; |
| 5484 | goto err_free; |
| 5485 | } |
| 5486 | |
Michael Chan | 84e86b9 | 2015-11-05 16:25:50 -0500 | [diff] [blame] | 5487 | new_fltr->sw_id = (u16)bit_id; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5488 | new_fltr->flow_id = flow_id; |
| 5489 | new_fltr->rxq = rxq_index; |
| 5490 | hlist_add_head_rcu(&new_fltr->hash, head); |
| 5491 | bp->ntp_fltr_count++; |
| 5492 | spin_unlock_bh(&bp->ntp_fltr_lock); |
| 5493 | |
| 5494 | set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event); |
| 5495 | schedule_work(&bp->sp_task); |
| 5496 | |
| 5497 | return new_fltr->sw_id; |
| 5498 | |
| 5499 | err_free: |
| 5500 | kfree(new_fltr); |
| 5501 | return rc; |
| 5502 | } |
| 5503 | |
| 5504 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) |
| 5505 | { |
| 5506 | int i; |
| 5507 | |
| 5508 | for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) { |
| 5509 | struct hlist_head *head; |
| 5510 | struct hlist_node *tmp; |
| 5511 | struct bnxt_ntuple_filter *fltr; |
| 5512 | int rc; |
| 5513 | |
| 5514 | head = &bp->ntp_fltr_hash_tbl[i]; |
| 5515 | hlist_for_each_entry_safe(fltr, tmp, head, hash) { |
| 5516 | bool del = false; |
| 5517 | |
| 5518 | if (test_bit(BNXT_FLTR_VALID, &fltr->state)) { |
| 5519 | if (rps_may_expire_flow(bp->dev, fltr->rxq, |
| 5520 | fltr->flow_id, |
| 5521 | fltr->sw_id)) { |
| 5522 | bnxt_hwrm_cfa_ntuple_filter_free(bp, |
| 5523 | fltr); |
| 5524 | del = true; |
| 5525 | } |
| 5526 | } else { |
| 5527 | rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp, |
| 5528 | fltr); |
| 5529 | if (rc) |
| 5530 | del = true; |
| 5531 | else |
| 5532 | set_bit(BNXT_FLTR_VALID, &fltr->state); |
| 5533 | } |
| 5534 | |
| 5535 | if (del) { |
| 5536 | spin_lock_bh(&bp->ntp_fltr_lock); |
| 5537 | hlist_del_rcu(&fltr->hash); |
| 5538 | bp->ntp_fltr_count--; |
| 5539 | spin_unlock_bh(&bp->ntp_fltr_lock); |
| 5540 | synchronize_rcu(); |
| 5541 | clear_bit(fltr->sw_id, bp->ntp_fltr_bmap); |
| 5542 | kfree(fltr); |
| 5543 | } |
| 5544 | } |
| 5545 | } |
| 5546 | } |
| 5547 | |
| 5548 | #else |
| 5549 | |
| 5550 | static void bnxt_cfg_ntp_filters(struct bnxt *bp) |
| 5551 | { |
| 5552 | } |
| 5553 | |
| 5554 | #endif /* CONFIG_RFS_ACCEL */ |
| 5555 | |
| 5556 | static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family, |
| 5557 | __be16 port) |
| 5558 | { |
| 5559 | struct bnxt *bp = netdev_priv(dev); |
| 5560 | |
| 5561 | if (!netif_running(dev)) |
| 5562 | return; |
| 5563 | |
| 5564 | if (sa_family != AF_INET6 && sa_family != AF_INET) |
| 5565 | return; |
| 5566 | |
| 5567 | if (bp->vxlan_port_cnt && bp->vxlan_port != port) |
| 5568 | return; |
| 5569 | |
| 5570 | bp->vxlan_port_cnt++; |
| 5571 | if (bp->vxlan_port_cnt == 1) { |
| 5572 | bp->vxlan_port = port; |
| 5573 | set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event); |
| 5574 | schedule_work(&bp->sp_task); |
| 5575 | } |
| 5576 | } |
| 5577 | |
| 5578 | static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family, |
| 5579 | __be16 port) |
| 5580 | { |
| 5581 | struct bnxt *bp = netdev_priv(dev); |
| 5582 | |
| 5583 | if (!netif_running(dev)) |
| 5584 | return; |
| 5585 | |
| 5586 | if (sa_family != AF_INET6 && sa_family != AF_INET) |
| 5587 | return; |
| 5588 | |
| 5589 | if (bp->vxlan_port_cnt && bp->vxlan_port == port) { |
| 5590 | bp->vxlan_port_cnt--; |
| 5591 | |
| 5592 | if (bp->vxlan_port_cnt == 0) { |
| 5593 | set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event); |
| 5594 | schedule_work(&bp->sp_task); |
| 5595 | } |
| 5596 | } |
| 5597 | } |
| 5598 | |
| 5599 | static const struct net_device_ops bnxt_netdev_ops = { |
| 5600 | .ndo_open = bnxt_open, |
| 5601 | .ndo_start_xmit = bnxt_start_xmit, |
| 5602 | .ndo_stop = bnxt_close, |
| 5603 | .ndo_get_stats64 = bnxt_get_stats64, |
| 5604 | .ndo_set_rx_mode = bnxt_set_rx_mode, |
| 5605 | .ndo_do_ioctl = bnxt_ioctl, |
| 5606 | .ndo_validate_addr = eth_validate_addr, |
| 5607 | .ndo_set_mac_address = bnxt_change_mac_addr, |
| 5608 | .ndo_change_mtu = bnxt_change_mtu, |
| 5609 | .ndo_fix_features = bnxt_fix_features, |
| 5610 | .ndo_set_features = bnxt_set_features, |
| 5611 | .ndo_tx_timeout = bnxt_tx_timeout, |
| 5612 | #ifdef CONFIG_BNXT_SRIOV |
| 5613 | .ndo_get_vf_config = bnxt_get_vf_config, |
| 5614 | .ndo_set_vf_mac = bnxt_set_vf_mac, |
| 5615 | .ndo_set_vf_vlan = bnxt_set_vf_vlan, |
| 5616 | .ndo_set_vf_rate = bnxt_set_vf_bw, |
| 5617 | .ndo_set_vf_link_state = bnxt_set_vf_link_state, |
| 5618 | .ndo_set_vf_spoofchk = bnxt_set_vf_spoofchk, |
| 5619 | #endif |
| 5620 | #ifdef CONFIG_NET_POLL_CONTROLLER |
| 5621 | .ndo_poll_controller = bnxt_poll_controller, |
| 5622 | #endif |
| 5623 | .ndo_setup_tc = bnxt_setup_tc, |
| 5624 | #ifdef CONFIG_RFS_ACCEL |
| 5625 | .ndo_rx_flow_steer = bnxt_rx_flow_steer, |
| 5626 | #endif |
| 5627 | .ndo_add_vxlan_port = bnxt_add_vxlan_port, |
| 5628 | .ndo_del_vxlan_port = bnxt_del_vxlan_port, |
| 5629 | #ifdef CONFIG_NET_RX_BUSY_POLL |
| 5630 | .ndo_busy_poll = bnxt_busy_poll, |
| 5631 | #endif |
| 5632 | }; |
| 5633 | |
| 5634 | static void bnxt_remove_one(struct pci_dev *pdev) |
| 5635 | { |
| 5636 | struct net_device *dev = pci_get_drvdata(pdev); |
| 5637 | struct bnxt *bp = netdev_priv(dev); |
| 5638 | |
| 5639 | if (BNXT_PF(bp)) |
| 5640 | bnxt_sriov_disable(bp); |
| 5641 | |
| 5642 | unregister_netdev(dev); |
| 5643 | cancel_work_sync(&bp->sp_task); |
| 5644 | bp->sp_event = 0; |
| 5645 | |
Jeffrey Huang | be58a0d | 2015-12-27 18:19:18 -0500 | [diff] [blame] | 5646 | bnxt_hwrm_func_drv_unrgtr(bp); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5647 | bnxt_free_hwrm_resources(bp); |
| 5648 | pci_iounmap(pdev, bp->bar2); |
| 5649 | pci_iounmap(pdev, bp->bar1); |
| 5650 | pci_iounmap(pdev, bp->bar0); |
| 5651 | free_netdev(dev); |
| 5652 | |
| 5653 | pci_release_regions(pdev); |
| 5654 | pci_disable_device(pdev); |
| 5655 | } |
| 5656 | |
| 5657 | static int bnxt_probe_phy(struct bnxt *bp) |
| 5658 | { |
| 5659 | int rc = 0; |
| 5660 | struct bnxt_link_info *link_info = &bp->link_info; |
| 5661 | char phy_ver[PHY_VER_STR_LEN]; |
| 5662 | |
| 5663 | rc = bnxt_update_link(bp, false); |
| 5664 | if (rc) { |
| 5665 | netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n", |
| 5666 | rc); |
| 5667 | return rc; |
| 5668 | } |
| 5669 | |
| 5670 | /*initialize the ethool setting copy with NVM settings */ |
| 5671 | if (BNXT_AUTO_MODE(link_info->auto_mode)) |
| 5672 | link_info->autoneg |= BNXT_AUTONEG_SPEED; |
| 5673 | |
| 5674 | if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) { |
| 5675 | if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH) |
| 5676 | link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL; |
| 5677 | link_info->req_flow_ctrl = link_info->auto_pause_setting; |
| 5678 | } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) { |
| 5679 | link_info->req_flow_ctrl = link_info->force_pause_setting; |
| 5680 | } |
| 5681 | link_info->req_duplex = link_info->duplex_setting; |
| 5682 | if (link_info->autoneg & BNXT_AUTONEG_SPEED) |
| 5683 | link_info->req_link_speed = link_info->auto_link_speed; |
| 5684 | else |
| 5685 | link_info->req_link_speed = link_info->force_link_speed; |
| 5686 | link_info->advertising = link_info->auto_link_speeds; |
| 5687 | snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d", |
| 5688 | link_info->phy_ver[0], |
| 5689 | link_info->phy_ver[1], |
| 5690 | link_info->phy_ver[2]); |
| 5691 | strcat(bp->fw_ver_str, phy_ver); |
| 5692 | return rc; |
| 5693 | } |
| 5694 | |
| 5695 | static int bnxt_get_max_irq(struct pci_dev *pdev) |
| 5696 | { |
| 5697 | u16 ctrl; |
| 5698 | |
| 5699 | if (!pdev->msix_cap) |
| 5700 | return 1; |
| 5701 | |
| 5702 | pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl); |
| 5703 | return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1; |
| 5704 | } |
| 5705 | |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5706 | static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, |
| 5707 | int *max_cp) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5708 | { |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5709 | int max_ring_grps = 0; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5710 | |
| 5711 | if (BNXT_PF(bp)) { |
Michael Chan | 4a21b49 | 2015-12-27 18:19:26 -0500 | [diff] [blame] | 5712 | *max_tx = bp->pf.max_tx_rings; |
| 5713 | *max_rx = bp->pf.max_rx_rings; |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5714 | *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings); |
| 5715 | *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs); |
Michael Chan | b72d4a6 | 2015-12-27 18:19:27 -0500 | [diff] [blame] | 5716 | max_ring_grps = bp->pf.max_hw_ring_grps; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5717 | } else { |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 5718 | #ifdef CONFIG_BNXT_SRIOV |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5719 | *max_tx = bp->vf.max_tx_rings; |
| 5720 | *max_rx = bp->vf.max_rx_rings; |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5721 | *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings); |
| 5722 | *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs); |
Michael Chan | b72d4a6 | 2015-12-27 18:19:27 -0500 | [diff] [blame] | 5723 | max_ring_grps = bp->vf.max_hw_ring_grps; |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 5724 | #endif |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5725 | } |
| 5726 | if (bp->flags & BNXT_FLAG_AGG_RINGS) |
| 5727 | *max_rx >>= 1; |
Michael Chan | b72d4a6 | 2015-12-27 18:19:27 -0500 | [diff] [blame] | 5728 | *max_rx = min_t(int, *max_rx, max_ring_grps); |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5729 | } |
| 5730 | |
| 5731 | int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared) |
| 5732 | { |
| 5733 | int rx, tx, cp; |
| 5734 | |
| 5735 | _bnxt_get_max_rings(bp, &rx, &tx, &cp); |
| 5736 | if (!rx || !tx || !cp) |
| 5737 | return -ENOMEM; |
| 5738 | |
| 5739 | *max_rx = rx; |
| 5740 | *max_tx = tx; |
| 5741 | return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared); |
| 5742 | } |
| 5743 | |
| 5744 | static int bnxt_set_dflt_rings(struct bnxt *bp) |
| 5745 | { |
| 5746 | int dflt_rings, max_rx_rings, max_tx_rings, rc; |
| 5747 | bool sh = true; |
| 5748 | |
| 5749 | if (sh) |
| 5750 | bp->flags |= BNXT_FLAG_SHARED_RINGS; |
| 5751 | dflt_rings = netif_get_num_default_rss_queues(); |
| 5752 | rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh); |
| 5753 | if (rc) |
| 5754 | return rc; |
| 5755 | bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings); |
| 5756 | bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings); |
| 5757 | bp->tx_nr_rings = bp->tx_nr_rings_per_tc; |
| 5758 | bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) : |
| 5759 | bp->tx_nr_rings + bp->rx_nr_rings; |
| 5760 | bp->num_stat_ctxs = bp->cp_nr_rings; |
| 5761 | return rc; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5762 | } |
| 5763 | |
| 5764 | static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 5765 | { |
| 5766 | static int version_printed; |
| 5767 | struct net_device *dev; |
| 5768 | struct bnxt *bp; |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5769 | int rc, max_irqs; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5770 | |
| 5771 | if (version_printed++ == 0) |
| 5772 | pr_info("%s", version); |
| 5773 | |
| 5774 | max_irqs = bnxt_get_max_irq(pdev); |
| 5775 | dev = alloc_etherdev_mq(sizeof(*bp), max_irqs); |
| 5776 | if (!dev) |
| 5777 | return -ENOMEM; |
| 5778 | |
| 5779 | bp = netdev_priv(dev); |
| 5780 | |
| 5781 | if (bnxt_vf_pciid(ent->driver_data)) |
| 5782 | bp->flags |= BNXT_FLAG_VF; |
| 5783 | |
Michael Chan | 2bcfa6f | 2015-12-27 18:19:24 -0500 | [diff] [blame] | 5784 | if (pdev->msix_cap) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5785 | bp->flags |= BNXT_FLAG_MSIX_CAP; |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5786 | |
| 5787 | rc = bnxt_init_board(pdev, dev); |
| 5788 | if (rc < 0) |
| 5789 | goto init_err_free; |
| 5790 | |
| 5791 | dev->netdev_ops = &bnxt_netdev_ops; |
| 5792 | dev->watchdog_timeo = BNXT_TX_TIMEOUT; |
| 5793 | dev->ethtool_ops = &bnxt_ethtool_ops; |
| 5794 | |
| 5795 | pci_set_drvdata(pdev, dev); |
| 5796 | |
| 5797 | dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
| 5798 | NETIF_F_TSO | NETIF_F_TSO6 | |
| 5799 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | |
| 5800 | NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT | |
| 5801 | NETIF_F_RXHASH | |
| 5802 | NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO; |
| 5803 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5804 | dev->hw_enc_features = |
| 5805 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG | |
| 5806 | NETIF_F_TSO | NETIF_F_TSO6 | |
| 5807 | NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE | |
| 5808 | NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT; |
| 5809 | dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA; |
| 5810 | dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | |
| 5811 | NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX; |
| 5812 | dev->features |= dev->hw_features | NETIF_F_HIGHDMA; |
| 5813 | dev->priv_flags |= IFF_UNICAST_FLT; |
| 5814 | |
| 5815 | #ifdef CONFIG_BNXT_SRIOV |
| 5816 | init_waitqueue_head(&bp->sriov_cfg_wait); |
| 5817 | #endif |
| 5818 | rc = bnxt_alloc_hwrm_resources(bp); |
| 5819 | if (rc) |
| 5820 | goto init_err; |
| 5821 | |
| 5822 | mutex_init(&bp->hwrm_cmd_lock); |
| 5823 | bnxt_hwrm_ver_get(bp); |
| 5824 | |
| 5825 | rc = bnxt_hwrm_func_drv_rgtr(bp); |
| 5826 | if (rc) |
| 5827 | goto init_err; |
| 5828 | |
| 5829 | /* Get the MAX capabilities for this function */ |
| 5830 | rc = bnxt_hwrm_func_qcaps(bp); |
| 5831 | if (rc) { |
| 5832 | netdev_err(bp->dev, "hwrm query capability failure rc: %x\n", |
| 5833 | rc); |
| 5834 | rc = -1; |
| 5835 | goto init_err; |
| 5836 | } |
| 5837 | |
| 5838 | rc = bnxt_hwrm_queue_qportcfg(bp); |
| 5839 | if (rc) { |
| 5840 | netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n", |
| 5841 | rc); |
| 5842 | rc = -1; |
| 5843 | goto init_err; |
| 5844 | } |
| 5845 | |
| 5846 | bnxt_set_tpa_flags(bp); |
| 5847 | bnxt_set_ring_params(bp); |
Jeffrey Huang | bdd4347 | 2015-12-02 01:54:07 -0500 | [diff] [blame] | 5848 | if (BNXT_PF(bp)) |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5849 | bp->pf.max_irqs = max_irqs; |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 5850 | #if defined(CONFIG_BNXT_SRIOV) |
Jeffrey Huang | bdd4347 | 2015-12-02 01:54:07 -0500 | [diff] [blame] | 5851 | else |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5852 | bp->vf.max_irqs = max_irqs; |
Michael Chan | 379a80a | 2015-10-23 15:06:19 -0400 | [diff] [blame] | 5853 | #endif |
Michael Chan | 6e6c5a5 | 2016-01-02 23:45:02 -0500 | [diff] [blame] | 5854 | bnxt_set_dflt_rings(bp); |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5855 | |
Michael Chan | 2bcfa6f | 2015-12-27 18:19:24 -0500 | [diff] [blame] | 5856 | if (BNXT_PF(bp)) { |
| 5857 | dev->hw_features |= NETIF_F_NTUPLE; |
| 5858 | if (bnxt_rfs_capable(bp)) { |
| 5859 | bp->flags |= BNXT_FLAG_RFS; |
| 5860 | dev->features |= NETIF_F_NTUPLE; |
| 5861 | } |
| 5862 | } |
| 5863 | |
Michael Chan | c0c050c | 2015-10-22 16:01:17 -0400 | [diff] [blame] | 5864 | if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX) |
| 5865 | bp->flags |= BNXT_FLAG_STRIP_VLAN; |
| 5866 | |
| 5867 | rc = bnxt_probe_phy(bp); |
| 5868 | if (rc) |
| 5869 | goto init_err; |
| 5870 | |
| 5871 | rc = register_netdev(dev); |
| 5872 | if (rc) |
| 5873 | goto init_err; |
| 5874 | |
| 5875 | netdev_info(dev, "%s found at mem %lx, node addr %pM\n", |
| 5876 | board_info[ent->driver_data].name, |
| 5877 | (long)pci_resource_start(pdev, 0), dev->dev_addr); |
| 5878 | |
| 5879 | return 0; |
| 5880 | |
| 5881 | init_err: |
| 5882 | pci_iounmap(pdev, bp->bar0); |
| 5883 | pci_release_regions(pdev); |
| 5884 | pci_disable_device(pdev); |
| 5885 | |
| 5886 | init_err_free: |
| 5887 | free_netdev(dev); |
| 5888 | return rc; |
| 5889 | } |
| 5890 | |
| 5891 | static struct pci_driver bnxt_pci_driver = { |
| 5892 | .name = DRV_MODULE_NAME, |
| 5893 | .id_table = bnxt_pci_tbl, |
| 5894 | .probe = bnxt_init_one, |
| 5895 | .remove = bnxt_remove_one, |
| 5896 | #if defined(CONFIG_BNXT_SRIOV) |
| 5897 | .sriov_configure = bnxt_sriov_configure, |
| 5898 | #endif |
| 5899 | }; |
| 5900 | |
| 5901 | module_pci_driver(bnxt_pci_driver); |