Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 1 | /* linux/arch/arm/mach-s3c2443/clock.c |
| 2 | * |
Ben Dooks | 4bed36b | 2010-01-30 10:25:49 +0200 | [diff] [blame] | 3 | * Copyright (c) 2007, 2010 Simtec Electronics |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * S3C2443 Clock control support |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <linux/init.h> |
Ben Dooks | af337f3 | 2010-04-28 18:03:57 +0900 | [diff] [blame] | 24 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 25 | #include <linux/module.h> |
| 26 | #include <linux/kernel.h> |
| 27 | #include <linux/list.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/err.h> |
Kay Sievers | edbaa60 | 2011-12-21 16:26:03 -0800 | [diff] [blame] | 30 | #include <linux/device.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 31 | #include <linux/clk.h> |
| 32 | #include <linux/mutex.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 33 | #include <linux/serial_core.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 34 | #include <linux/io.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 35 | |
| 36 | #include <asm/mach/map.h> |
| 37 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 38 | #include <mach/hardware.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 39 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 40 | #include <mach/regs-s3c2443-clock.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 41 | |
Ben Dooks | e425382 | 2008-10-21 14:06:38 +0100 | [diff] [blame] | 42 | #include <plat/cpu-freq.h> |
| 43 | |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 44 | #include <plat/s3c2443.h> |
Ben Dooks | d5120ae | 2008-10-07 23:09:51 +0100 | [diff] [blame] | 45 | #include <plat/clock.h> |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 46 | #include <plat/clock-clksrc.h> |
Ben Dooks | a2b7ba9 | 2008-10-07 22:26:09 +0100 | [diff] [blame] | 47 | #include <plat/cpu.h> |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 48 | |
| 49 | /* We currently have to assume that the system is running |
| 50 | * from the XTPll input, and that all ***REFCLKs are being |
| 51 | * fed from it, as we cannot read the state of OM[4] from |
| 52 | * software. |
| 53 | * |
| 54 | * It would be possible for each board initialisation to |
| 55 | * set the correct muxing at initialisation |
| 56 | */ |
| 57 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 58 | /* clock selections */ |
| 59 | |
Ben Dooks | ba7622a | 2008-07-07 18:12:39 +0100 | [diff] [blame] | 60 | /* armdiv |
| 61 | * |
| 62 | * this clock is sourced from msysclk and can have a number of |
| 63 | * divider values applied to it to then be fed into armclk. |
Heiko St?bner | aab08ee | 2011-10-14 15:08:56 +0900 | [diff] [blame] | 64 | * The real clock definition is done in s3c2443-clock.c, |
| 65 | * only the armdiv divisor table must be defined here. |
Ben Dooks | ba7622a | 2008-07-07 18:12:39 +0100 | [diff] [blame] | 66 | */ |
| 67 | |
Ben Dooks | 41f23a0 | 2010-01-30 11:14:14 +0200 | [diff] [blame] | 68 | static unsigned int armdiv[16] = { |
| 69 | [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1, |
| 70 | [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2, |
| 71 | [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3, |
| 72 | [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4, |
| 73 | [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6, |
| 74 | [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8, |
| 75 | [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12, |
| 76 | [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16, |
| 77 | }; |
| 78 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 79 | /* hsspi |
| 80 | * |
| 81 | * high-speed spi clock, sourced from esysclk |
| 82 | */ |
| 83 | |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 84 | static struct clksrc_clk clk_hsspi = { |
| 85 | .clk = { |
Heiko Stuebner | 8b069b7 | 2011-09-27 08:45:23 +0900 | [diff] [blame] | 86 | .name = "hsspi-if", |
Ben Dooks | 4bed36b | 2010-01-30 10:25:49 +0200 | [diff] [blame] | 87 | .parent = &clk_esysclk.clk, |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 88 | .ctrlbit = S3C2443_SCLKCON_HSSPICLK, |
| 89 | .enable = s3c2443_clkcon_enable_s, |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame] | 90 | }, |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 91 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 }, |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 92 | }; |
| 93 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 94 | |
| 95 | /* clk_hsmcc_div |
| 96 | * |
| 97 | * this clock is sourced from epll, and is fed through a divider, |
| 98 | * to a mux controlled by sclkcon where either it or a extclk can |
| 99 | * be fed to the hsmmc block |
| 100 | */ |
| 101 | |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 102 | static struct clksrc_clk clk_hsmmc_div = { |
| 103 | .clk = { |
| 104 | .name = "hsmmc-div", |
Thomas Abraham | e83626f | 2011-06-14 19:12:26 +0900 | [diff] [blame] | 105 | .devname = "s3c-sdhci.1", |
Ben Dooks | 4bed36b | 2010-01-30 10:25:49 +0200 | [diff] [blame] | 106 | .parent = &clk_esysclk.clk, |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame] | 107 | }, |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 108 | .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 }, |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 109 | }; |
| 110 | |
| 111 | static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent) |
| 112 | { |
| 113 | unsigned long clksrc = __raw_readl(S3C2443_SCLKCON); |
| 114 | |
| 115 | clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT | |
| 116 | S3C2443_SCLKCON_HSMMCCLK_EPLL); |
| 117 | |
| 118 | if (parent == &clk_epll) |
| 119 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL; |
| 120 | else if (parent == &clk_ext) |
| 121 | clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT; |
| 122 | else |
| 123 | return -EINVAL; |
| 124 | |
| 125 | if (clk->usage > 0) { |
| 126 | __raw_writel(clksrc, S3C2443_SCLKCON); |
| 127 | } |
| 128 | |
| 129 | clk->parent = parent; |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static int s3c2443_enable_hsmmc(struct clk *clk, int enable) |
| 134 | { |
| 135 | return s3c2443_setparent_hsmmc(clk, clk->parent); |
| 136 | } |
| 137 | |
| 138 | static struct clk clk_hsmmc = { |
| 139 | .name = "hsmmc-if", |
Thomas Abraham | e83626f | 2011-06-14 19:12:26 +0900 | [diff] [blame] | 140 | .devname = "s3c-sdhci.1", |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 141 | .parent = &clk_hsmmc_div.clk, |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 142 | .enable = s3c2443_enable_hsmmc, |
Ben Dooks | b3bf41b | 2009-12-01 01:24:37 +0000 | [diff] [blame] | 143 | .ops = &(struct clk_ops) { |
| 144 | .set_parent = s3c2443_setparent_hsmmc, |
| 145 | }, |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 146 | }; |
| 147 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 148 | /* standard clock definitions */ |
| 149 | |
Ben Dooks | 4e04691 | 2010-04-28 12:58:13 +0900 | [diff] [blame] | 150 | static struct clk init_clocks_off[] = { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 151 | { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 152 | .name = "sdi", |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 153 | .parent = &clk_p, |
| 154 | .enable = s3c2443_clkcon_enable_p, |
| 155 | .ctrlbit = S3C2443_PCLKCON_SDI, |
| 156 | }, { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 157 | .name = "spi", |
Thomas Abraham | e83626f | 2011-06-14 19:12:26 +0900 | [diff] [blame] | 158 | .devname = "s3c2410-spi.0", |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 159 | .parent = &clk_p, |
| 160 | .enable = s3c2443_clkcon_enable_p, |
| 161 | .ctrlbit = S3C2443_PCLKCON_SPI0, |
| 162 | }, { |
| 163 | .name = "spi", |
Thomas Abraham | e83626f | 2011-06-14 19:12:26 +0900 | [diff] [blame] | 164 | .devname = "s3c2410-spi.1", |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 165 | .parent = &clk_p, |
| 166 | .enable = s3c2443_clkcon_enable_p, |
| 167 | .ctrlbit = S3C2443_PCLKCON_SPI1, |
| 168 | } |
| 169 | }; |
| 170 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 171 | /* clocks to add straight away */ |
| 172 | |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 173 | static struct clksrc_clk *clksrcs[] __initdata = { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 174 | &clk_hsspi, |
| 175 | &clk_hsmmc_div, |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 176 | }; |
| 177 | |
| 178 | static struct clk *clks[] __initdata = { |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 179 | &clk_hsmmc, |
| 180 | }; |
| 181 | |
Ben Dooks | e425382 | 2008-10-21 14:06:38 +0100 | [diff] [blame] | 182 | void __init s3c2443_init_clocks(int xtal) |
| 183 | { |
Ben Dooks | e425382 | 2008-10-21 14:06:38 +0100 | [diff] [blame] | 184 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); |
Ben Dooks | e425382 | 2008-10-21 14:06:38 +0100 | [diff] [blame] | 185 | int ptr; |
| 186 | |
Ben Dooks | af337f3 | 2010-04-28 18:03:57 +0900 | [diff] [blame] | 187 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
| 188 | clk_epll.parent = &clk_epllref.clk; |
Ben Dooks | e425382 | 2008-10-21 14:06:38 +0100 | [diff] [blame] | 189 | |
Heiko Stuebner | 33ccedf | 2011-10-14 15:08:57 +0900 | [diff] [blame] | 190 | s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, |
Heiko Stuebner | d9a3bfb | 2011-10-14 15:08:56 +0900 | [diff] [blame] | 191 | armdiv, ARRAY_SIZE(armdiv), |
| 192 | S3C2443_CLKDIV0_ARMDIV_MASK); |
Ben Dooks | af337f3 | 2010-04-28 18:03:57 +0900 | [diff] [blame] | 193 | |
Ben Dooks | 4e04691 | 2010-04-28 12:58:13 +0900 | [diff] [blame] | 194 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 195 | |
Ben Dooks | 9aa753c | 2010-01-30 09:19:59 +0200 | [diff] [blame] | 196 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) |
| 197 | s3c_register_clksrc(clksrcs[ptr], 1); |
| 198 | |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 199 | /* We must be careful disabling the clocks we are not intending to |
Robert P. J. Day | 3a4fa0a | 2007-10-19 23:10:43 +0200 | [diff] [blame] | 200 | * be using at boot time, as subsystems such as the LCD which do |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 201 | * their own DMA requests to the bus can cause the system to lockup |
| 202 | * if they where in the middle of requesting bus access. |
| 203 | * |
| 204 | * Disabling the LCD clock if the LCD is active is very dangerous, |
| 205 | * and therefore the bootloader should be careful to not enable |
| 206 | * the LCD clock if it is not needed. |
| 207 | */ |
| 208 | |
| 209 | /* install (and disable) the clocks we do not need immediately */ |
| 210 | |
Ben Dooks | 4e04691 | 2010-04-28 12:58:13 +0900 | [diff] [blame] | 211 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
| 212 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); |
Ben Dooks | 9d325f2 | 2008-11-21 10:36:05 +0000 | [diff] [blame] | 213 | |
| 214 | s3c_pwmclk_init(); |
Ben Dooks | e4d06e3 | 2007-02-16 12:12:31 +0100 | [diff] [blame] | 215 | } |