| Ira W. Snyder | 3f6ea84 | 2010-04-01 11:43:30 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Read address ranges from a Broadcom CNB20LE Host Bridge |
| 3 | * |
| 4 | * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/dmi.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/init.h> |
| 16 | #include <asm/pci_x86.h> |
| 17 | |
| 18 | #include "bus_numa.h" |
| 19 | |
| 20 | static void __devinit cnb20le_res(struct pci_dev *dev) |
| 21 | { |
| 22 | struct pci_root_info *info; |
| 23 | struct resource res; |
| 24 | u16 word1, word2; |
| 25 | u8 fbus, lbus; |
| 26 | int i; |
| 27 | |
| 28 | /* |
| 29 | * The x86_pci_root_bus_res_quirks() function already refuses to use |
| 30 | * this information if ACPI _CRS was used. Therefore, we don't bother |
| 31 | * checking if ACPI is enabled, and just generate the information |
| 32 | * for both the ACPI _CRS and no ACPI cases. |
| 33 | */ |
| 34 | |
| 35 | info = &pci_root_info[pci_root_num]; |
| 36 | pci_root_num++; |
| 37 | |
| 38 | /* read the PCI bus numbers */ |
| 39 | pci_read_config_byte(dev, 0x44, &fbus); |
| 40 | pci_read_config_byte(dev, 0x45, &lbus); |
| 41 | info->bus_min = fbus; |
| 42 | info->bus_max = lbus; |
| 43 | |
| 44 | /* |
| 45 | * Add the legacy IDE ports on bus 0 |
| 46 | * |
| 47 | * These do not exist anywhere in the bridge registers, AFAICT. I do |
| 48 | * not have the datasheet, so this is the best I can do. |
| 49 | */ |
| 50 | if (fbus == 0) { |
| 51 | update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0); |
| 52 | update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0); |
| 53 | update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0); |
| 54 | update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0); |
| 55 | update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0); |
| 56 | } |
| 57 | |
| 58 | /* read the non-prefetchable memory window */ |
| 59 | pci_read_config_word(dev, 0xc0, &word1); |
| 60 | pci_read_config_word(dev, 0xc2, &word2); |
| 61 | if (word1 != word2) { |
| 62 | res.start = (word1 << 16) | 0x0000; |
| 63 | res.end = (word2 << 16) | 0xffff; |
| 64 | res.flags = IORESOURCE_MEM; |
| 65 | update_res(info, res.start, res.end, res.flags, 0); |
| 66 | } |
| 67 | |
| 68 | /* read the prefetchable memory window */ |
| 69 | pci_read_config_word(dev, 0xc4, &word1); |
| 70 | pci_read_config_word(dev, 0xc6, &word2); |
| 71 | if (word1 != word2) { |
| 72 | res.start = (word1 << 16) | 0x0000; |
| 73 | res.end = (word2 << 16) | 0xffff; |
| 74 | res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
| 75 | update_res(info, res.start, res.end, res.flags, 0); |
| 76 | } |
| 77 | |
| 78 | /* read the IO port window */ |
| 79 | pci_read_config_word(dev, 0xd0, &word1); |
| 80 | pci_read_config_word(dev, 0xd2, &word2); |
| 81 | if (word1 != word2) { |
| 82 | res.start = word1; |
| 83 | res.end = word2; |
| 84 | res.flags = IORESOURCE_IO; |
| 85 | update_res(info, res.start, res.end, res.flags, 0); |
| 86 | } |
| 87 | |
| 88 | /* print information about this host bridge */ |
| 89 | res.start = fbus; |
| 90 | res.end = lbus; |
| 91 | res.flags = IORESOURCE_BUS; |
| 92 | dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n", |
| 93 | pci_domain_nr(dev->bus), &res); |
| 94 | |
| 95 | for (i = 0; i < info->res_num; i++) |
| 96 | dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]); |
| 97 | } |
| 98 | |
| 99 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE, |
| 100 | cnb20le_res); |
| 101 | |