Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
| 3 | * Copyright 2005-2006 Fen Systems Ltd. |
Ben Hutchings | 906bb26 | 2009-11-29 15:16:19 +0000 | [diff] [blame] | 4 | * Copyright 2006-2009 Solarflare Communications Inc. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation, incorporated herein by reference. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/bitops.h> |
| 12 | #include <linux/delay.h> |
| 13 | #include <linux/pci.h> |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/seq_file.h> |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 16 | #include <linux/i2c.h> |
Ben Hutchings | f31a45d | 2008-12-12 21:43:33 -0800 | [diff] [blame] | 17 | #include <linux/mii.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 18 | #include <linux/slab.h> |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 19 | #include "net_driver.h" |
| 20 | #include "bitfield.h" |
| 21 | #include "efx.h" |
| 22 | #include "mac.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 23 | #include "spi.h" |
Ben Hutchings | 744093c | 2009-11-29 15:12:08 +0000 | [diff] [blame] | 24 | #include "nic.h" |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 25 | #include "regs.h" |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 26 | #include "io.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 27 | #include "mdio_10g.h" |
| 28 | #include "phy.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 29 | #include "workarounds.h" |
| 30 | |
Ben Hutchings | 8986352 | 2009-11-25 16:09:04 +0000 | [diff] [blame] | 31 | /* Hardware control for SFC4000 (aka Falcon). */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 32 | |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 33 | static const unsigned int |
| 34 | /* "Large" EEPROM device: Atmel AT25640 or similar |
| 35 | * 8 KB, 16-bit address, 32 B write block */ |
| 36 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) |
| 37 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) |
| 38 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), |
| 39 | /* Default flash device: Atmel AT25F1024 |
| 40 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ |
| 41 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) |
| 42 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) |
| 43 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) |
| 44 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) |
| 45 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); |
| 46 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 47 | /************************************************************************** |
| 48 | * |
| 49 | * I2C bus - this is a bit-bashing interface using GPIO pins |
| 50 | * Note that it uses the output enables to tristate the outputs |
| 51 | * SDA is the data pin and SCL is the clock |
| 52 | * |
| 53 | ************************************************************************** |
| 54 | */ |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 55 | static void falcon_setsda(void *data, int state) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 56 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 57 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 58 | efx_oword_t reg; |
| 59 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 60 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 61 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 62 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 65 | static void falcon_setscl(void *data, int state) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 66 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 67 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 68 | efx_oword_t reg; |
| 69 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 70 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 71 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 72 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static int falcon_getsda(void *data) |
| 76 | { |
| 77 | struct efx_nic *efx = (struct efx_nic *)data; |
| 78 | efx_oword_t reg; |
| 79 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 80 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 81 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 82 | } |
| 83 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 84 | static int falcon_getscl(void *data) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 85 | { |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 86 | struct efx_nic *efx = (struct efx_nic *)data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 87 | efx_oword_t reg; |
| 88 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 89 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 90 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 91 | } |
| 92 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 93 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
| 94 | .setsda = falcon_setsda, |
| 95 | .setscl = falcon_setscl, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 96 | .getsda = falcon_getsda, |
| 97 | .getscl = falcon_getscl, |
Ben Hutchings | 62c7832 | 2008-05-30 22:27:46 +0100 | [diff] [blame] | 98 | .udelay = 5, |
Ben Hutchings | 9dadae6 | 2008-07-18 18:59:12 +0100 | [diff] [blame] | 99 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
| 100 | .timeout = DIV_ROUND_UP(HZ, 20), |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 101 | }; |
| 102 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 103 | static void falcon_push_irq_moderation(struct efx_channel *channel) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 104 | { |
| 105 | efx_dword_t timer_cmd; |
| 106 | struct efx_nic *efx = channel->efx; |
| 107 | |
| 108 | /* Set timer register */ |
| 109 | if (channel->irq_moderation) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 110 | EFX_POPULATE_DWORD_2(timer_cmd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 111 | FRF_AB_TC_TIMER_MODE, |
| 112 | FFE_BB_TIMER_MODE_INT_HLDOFF, |
| 113 | FRF_AB_TC_TIMER_VAL, |
Ben Hutchings | 0d86ebd | 2009-10-23 08:32:13 +0000 | [diff] [blame] | 114 | channel->irq_moderation - 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 115 | } else { |
| 116 | EFX_POPULATE_DWORD_2(timer_cmd, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 117 | FRF_AB_TC_TIMER_MODE, |
| 118 | FFE_BB_TIMER_MODE_DIS, |
| 119 | FRF_AB_TC_TIMER_VAL, 0); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 120 | } |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 121 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 122 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
| 123 | channel->channel); |
Ben Hutchings | 127e6e1 | 2009-11-25 16:09:55 +0000 | [diff] [blame] | 124 | } |
| 125 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 126 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); |
| 127 | |
Ben Hutchings | 127e6e1 | 2009-11-25 16:09:55 +0000 | [diff] [blame] | 128 | static void falcon_prepare_flush(struct efx_nic *efx) |
| 129 | { |
| 130 | falcon_deconfigure_mac_wrapper(efx); |
| 131 | |
| 132 | /* Wait for the tx and rx fifo's to get to the next packet boundary |
| 133 | * (~1ms without back-pressure), then to drain the remainder of the |
| 134 | * fifo's at data path speeds (negligible), with a healthy margin. */ |
| 135 | msleep(10); |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 136 | } |
| 137 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 138 | /* Acknowledge a legacy interrupt from Falcon |
| 139 | * |
| 140 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. |
| 141 | * |
| 142 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the |
| 143 | * BIU. Interrupt acknowledge is read sensitive so must write instead |
| 144 | * (then read to ensure the BIU collector is flushed) |
| 145 | * |
| 146 | * NB most hardware supports MSI interrupts |
| 147 | */ |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 148 | inline void falcon_irq_ack_a1(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 149 | { |
| 150 | efx_dword_t reg; |
| 151 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 152 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 153 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
| 154 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 155 | } |
| 156 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 157 | |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 158 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 159 | { |
Ben Hutchings | d3208b5 | 2008-05-16 21:20:00 +0100 | [diff] [blame] | 160 | struct efx_nic *efx = dev_id; |
| 161 | efx_oword_t *int_ker = efx->irq_status.addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 162 | struct efx_channel *channel; |
| 163 | int syserr; |
| 164 | int queues; |
| 165 | |
| 166 | /* Check to see if this is our interrupt. If it isn't, we |
| 167 | * exit without having touched the hardware. |
| 168 | */ |
| 169 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 170 | netif_vdbg(efx, intr, efx->net_dev, |
| 171 | "IRQ %d on CPU %d not for me\n", irq, |
| 172 | raw_smp_processor_id()); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 173 | return IRQ_NONE; |
| 174 | } |
| 175 | efx->last_irq_cpu = raw_smp_processor_id(); |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 176 | netif_vdbg(efx, intr, efx->net_dev, |
| 177 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", |
| 178 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 179 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 180 | /* Determine interrupting queues, clear interrupt status |
| 181 | * register and acknowledge the device interrupt. |
| 182 | */ |
Ben Hutchings | 674979d | 2009-11-29 03:42:10 +0000 | [diff] [blame] | 183 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); |
| 184 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); |
Steve Hodgson | 6369545 | 2010-04-28 09:27:36 +0000 | [diff] [blame] | 185 | |
| 186 | /* Check to see if we have a serious error condition */ |
| 187 | if (queues & (1U << efx->fatal_irq_level)) { |
| 188 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
| 189 | if (unlikely(syserr)) |
| 190 | return efx_nic_fatal_interrupt(efx); |
| 191 | } |
| 192 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 193 | EFX_ZERO_OWORD(*int_ker); |
| 194 | wmb(); /* Ensure the vector is cleared before interrupt ack */ |
| 195 | falcon_irq_ack_a1(efx); |
| 196 | |
| 197 | /* Schedule processing of any interrupting queues */ |
| 198 | channel = &efx->channel[0]; |
| 199 | while (queues) { |
| 200 | if (queues & 0x01) |
| 201 | efx_schedule_channel(channel); |
| 202 | channel++; |
| 203 | queues >>= 1; |
| 204 | } |
| 205 | |
| 206 | return IRQ_HANDLED; |
| 207 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 208 | /************************************************************************** |
| 209 | * |
| 210 | * EEPROM/flash |
| 211 | * |
| 212 | ************************************************************************** |
| 213 | */ |
| 214 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 215 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 216 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 217 | static int falcon_spi_poll(struct efx_nic *efx) |
| 218 | { |
| 219 | efx_oword_t reg; |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 220 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 221 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 222 | } |
| 223 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 224 | /* Wait for SPI command completion */ |
| 225 | static int falcon_spi_wait(struct efx_nic *efx) |
| 226 | { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 227 | /* Most commands will finish quickly, so we start polling at |
| 228 | * very short intervals. Sometimes the command may have to |
| 229 | * wait for VPD or expansion ROM access outside of our |
| 230 | * control, so we allow up to 100 ms. */ |
| 231 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); |
| 232 | int i; |
| 233 | |
| 234 | for (i = 0; i < 10; i++) { |
| 235 | if (!falcon_spi_poll(efx)) |
| 236 | return 0; |
| 237 | udelay(10); |
| 238 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 239 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 240 | for (;;) { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 241 | if (!falcon_spi_poll(efx)) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 242 | return 0; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 243 | if (time_after_eq(jiffies, timeout)) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 244 | netif_err(efx, hw, efx->net_dev, |
| 245 | "timed out waiting for SPI\n"); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 246 | return -ETIMEDOUT; |
| 247 | } |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 248 | schedule_timeout_uninterruptible(1); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 249 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 250 | } |
| 251 | |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 252 | int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi, |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 253 | unsigned int command, int address, |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 254 | const void *in, void *out, size_t len) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 255 | { |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 256 | bool addressed = (address >= 0); |
| 257 | bool reading = (out != NULL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 258 | efx_oword_t reg; |
| 259 | int rc; |
| 260 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 261 | /* Input validation */ |
| 262 | if (len > FALCON_SPI_MAX_LEN) |
| 263 | return -EINVAL; |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 264 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 265 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 266 | /* Check that previous command is not still running */ |
| 267 | rc = falcon_spi_poll(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 268 | if (rc) |
| 269 | return rc; |
| 270 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 271 | /* Program address register, if we have an address */ |
| 272 | if (addressed) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 273 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 274 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 275 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 276 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 277 | /* Program data register, if we have data */ |
| 278 | if (in != NULL) { |
| 279 | memcpy(®, in, len); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 280 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 281 | } |
| 282 | |
| 283 | /* Issue read/write command */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 284 | EFX_POPULATE_OWORD_7(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 285 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
| 286 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, |
| 287 | FRF_AB_EE_SPI_HCMD_DABCNT, len, |
| 288 | FRF_AB_EE_SPI_HCMD_READ, reading, |
| 289 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, |
| 290 | FRF_AB_EE_SPI_HCMD_ADBCNT, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 291 | (addressed ? spi->addr_len : 0), |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 292 | FRF_AB_EE_SPI_HCMD_ENC, command); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 293 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 294 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 295 | /* Wait for read/write to complete */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 296 | rc = falcon_spi_wait(efx); |
| 297 | if (rc) |
| 298 | return rc; |
| 299 | |
| 300 | /* Read data */ |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 301 | if (out != NULL) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 302 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 303 | memcpy(out, ®, len); |
| 304 | } |
| 305 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 306 | return 0; |
| 307 | } |
| 308 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 309 | static size_t |
| 310 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 311 | { |
| 312 | return min(FALCON_SPI_MAX_LEN, |
| 313 | (spi->block_size - (start & (spi->block_size - 1)))); |
| 314 | } |
| 315 | |
| 316 | static inline u8 |
| 317 | efx_spi_munge_command(const struct efx_spi_device *spi, |
| 318 | const u8 command, const unsigned int address) |
| 319 | { |
| 320 | return command | (((address >> 8) & spi->munge_address) << 3); |
| 321 | } |
| 322 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 323 | /* Wait up to 10 ms for buffered write completion */ |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 324 | int |
| 325 | falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 326 | { |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 327 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 328 | u8 status; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 329 | int rc; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 330 | |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 331 | for (;;) { |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 332 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 333 | &status, sizeof(status)); |
| 334 | if (rc) |
| 335 | return rc; |
| 336 | if (!(status & SPI_STATUS_NRDY)) |
| 337 | return 0; |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 338 | if (time_after_eq(jiffies, timeout)) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 339 | netif_err(efx, hw, efx->net_dev, |
| 340 | "SPI write timeout on device %d" |
| 341 | " last status=0x%02x\n", |
| 342 | spi->device_id, status); |
Ben Hutchings | be4ea89 | 2008-12-12 21:33:50 -0800 | [diff] [blame] | 343 | return -ETIMEDOUT; |
| 344 | } |
| 345 | schedule_timeout_uninterruptible(1); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 346 | } |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 347 | } |
| 348 | |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 349 | int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi, |
| 350 | loff_t start, size_t len, size_t *retlen, u8 *buffer) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 351 | { |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 352 | size_t block_len, pos = 0; |
| 353 | unsigned int command; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 354 | int rc = 0; |
| 355 | |
| 356 | while (pos < len) { |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 357 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 358 | |
| 359 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 360 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 361 | buffer + pos, block_len); |
| 362 | if (rc) |
| 363 | break; |
| 364 | pos += block_len; |
| 365 | |
| 366 | /* Avoid locking up the system */ |
| 367 | cond_resched(); |
| 368 | if (signal_pending(current)) { |
| 369 | rc = -EINTR; |
| 370 | break; |
| 371 | } |
| 372 | } |
| 373 | |
| 374 | if (retlen) |
| 375 | *retlen = pos; |
| 376 | return rc; |
| 377 | } |
| 378 | |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 379 | int |
| 380 | falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi, |
| 381 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 382 | { |
| 383 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 384 | size_t block_len, pos = 0; |
| 385 | unsigned int command; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 386 | int rc = 0; |
| 387 | |
| 388 | while (pos < len) { |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 389 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 390 | if (rc) |
| 391 | break; |
| 392 | |
Ben Hutchings | 23d30f0 | 2008-12-12 21:56:11 -0800 | [diff] [blame] | 393 | block_len = min(len - pos, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 394 | falcon_spi_write_limit(spi, start + pos)); |
| 395 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 396 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 397 | buffer + pos, NULL, block_len); |
| 398 | if (rc) |
| 399 | break; |
| 400 | |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 401 | rc = falcon_spi_wait_write(efx, spi); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 402 | if (rc) |
| 403 | break; |
| 404 | |
| 405 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 406 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 407 | NULL, verify_buffer, block_len); |
| 408 | if (memcmp(verify_buffer, buffer + pos, block_len)) { |
| 409 | rc = -EIO; |
| 410 | break; |
| 411 | } |
| 412 | |
| 413 | pos += block_len; |
| 414 | |
| 415 | /* Avoid locking up the system */ |
| 416 | cond_resched(); |
| 417 | if (signal_pending(current)) { |
| 418 | rc = -EINTR; |
| 419 | break; |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | if (retlen) |
| 424 | *retlen = pos; |
| 425 | return rc; |
| 426 | } |
| 427 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 428 | /************************************************************************** |
| 429 | * |
| 430 | * MAC wrapper |
| 431 | * |
| 432 | ************************************************************************** |
| 433 | */ |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 434 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 435 | static void falcon_push_multicast_hash(struct efx_nic *efx) |
| 436 | { |
| 437 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; |
| 438 | |
| 439 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
| 440 | |
| 441 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
| 442 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); |
| 443 | } |
| 444 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 445 | static void falcon_reset_macs(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 446 | { |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 447 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 448 | efx_oword_t reg, mac_ctrl; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 449 | int count; |
| 450 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 451 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 452 | /* It's not safe to use GLB_CTL_REG to reset the |
| 453 | * macs, so instead use the internal MAC resets |
| 454 | */ |
| 455 | if (!EFX_IS10G(efx)) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 456 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 457 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 458 | udelay(1000); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 459 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 460 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 461 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 462 | udelay(1000); |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 463 | return; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 464 | } else { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 465 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 466 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 467 | |
| 468 | for (count = 0; count < 10000; count++) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 469 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 470 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
| 471 | 0) |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 472 | return; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 473 | udelay(10); |
| 474 | } |
| 475 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 476 | netif_err(efx, hw, efx->net_dev, |
| 477 | "timed out waiting for XMAC core reset\n"); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 478 | } |
| 479 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 480 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 481 | /* Mac stats will fail whist the TX fifo is draining */ |
| 482 | WARN_ON(nic_data->stats_disable_count == 0); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 483 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 484 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
| 485 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); |
| 486 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 487 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 488 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 489 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
| 490 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); |
| 491 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 492 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 493 | |
| 494 | count = 0; |
| 495 | while (1) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 496 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 497 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
| 498 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && |
| 499 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 500 | netif_dbg(efx, hw, efx->net_dev, |
| 501 | "Completed MAC reset after %d loops\n", |
| 502 | count); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 503 | break; |
| 504 | } |
| 505 | if (count > 20) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 506 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 507 | break; |
| 508 | } |
| 509 | count++; |
| 510 | udelay(10); |
| 511 | } |
| 512 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 513 | /* Ensure the correct MAC is selected before statistics |
| 514 | * are re-enabled by the caller */ |
| 515 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
Steve Hodgson | b7b40ee | 2010-04-28 09:28:10 +0000 | [diff] [blame] | 516 | |
| 517 | /* This can run even when the GMAC is selected */ |
| 518 | falcon_setup_xaui(efx); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | void falcon_drain_tx_fifo(struct efx_nic *efx) |
| 522 | { |
| 523 | efx_oword_t reg; |
| 524 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 525 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 526 | (efx->loopback_mode != LOOPBACK_NONE)) |
| 527 | return; |
| 528 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 529 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 530 | /* There is no point in draining more than once */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 531 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 532 | return; |
| 533 | |
| 534 | falcon_reset_macs(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 535 | } |
| 536 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 537 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 538 | { |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 539 | efx_oword_t reg; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 540 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 541 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 542 | return; |
| 543 | |
| 544 | /* Isolate the MAC -> RX */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 545 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 546 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 547 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 548 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 549 | /* Isolate TX -> MAC */ |
| 550 | falcon_drain_tx_fifo(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 551 | } |
| 552 | |
| 553 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) |
| 554 | { |
Ben Hutchings | eb50c0d | 2009-11-23 16:06:30 +0000 | [diff] [blame] | 555 | struct efx_link_state *link_state = &efx->link_state; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 556 | efx_oword_t reg; |
Steve Hodgson | fd371e3 | 2010-06-01 11:17:51 +0000 | [diff] [blame] | 557 | int link_speed, isolate; |
| 558 | |
| 559 | isolate = (efx->reset_pending != RESET_TYPE_NONE); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 560 | |
Ben Hutchings | eb50c0d | 2009-11-23 16:06:30 +0000 | [diff] [blame] | 561 | switch (link_state->speed) { |
Ben Hutchings | f31a45d | 2008-12-12 21:43:33 -0800 | [diff] [blame] | 562 | case 10000: link_speed = 3; break; |
| 563 | case 1000: link_speed = 2; break; |
| 564 | case 100: link_speed = 1; break; |
| 565 | default: link_speed = 0; break; |
| 566 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 567 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
| 568 | * as advertised. Disable to ensure packets are not |
| 569 | * indefinitely held and TX queue can be flushed at any point |
| 570 | * while the link is down. */ |
| 571 | EFX_POPULATE_OWORD_5(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 572 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
| 573 | FRF_AB_MAC_BCAD_ACPT, 1, |
| 574 | FRF_AB_MAC_UC_PROM, efx->promiscuous, |
| 575 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ |
| 576 | FRF_AB_MAC_SPEED, link_speed); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 577 | /* On B0, MAC backpressure can be disabled and packets get |
| 578 | * discarded. */ |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 579 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 580 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
Steve Hodgson | fd371e3 | 2010-06-01 11:17:51 +0000 | [diff] [blame] | 581 | !link_state->up || isolate); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 582 | } |
| 583 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 584 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 585 | |
| 586 | /* Restore the multicast hash registers. */ |
Ben Hutchings | 8be4f3e | 2009-11-25 16:12:16 +0000 | [diff] [blame] | 587 | falcon_push_multicast_hash(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 588 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 589 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 4b0d29d | 2009-11-29 03:42:18 +0000 | [diff] [blame] | 590 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
| 591 | * initialisation but it may read back as 0) */ |
| 592 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 593 | /* Unisolate the MAC -> RX */ |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 594 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
Steve Hodgson | fd371e3 | 2010-06-01 11:17:51 +0000 | [diff] [blame] | 595 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 596 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 597 | } |
| 598 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 599 | static void falcon_stats_request(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 600 | { |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 601 | struct falcon_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 602 | efx_oword_t reg; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 603 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 604 | WARN_ON(nic_data->stats_pending); |
| 605 | WARN_ON(nic_data->stats_disable_count); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 606 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 607 | if (nic_data->stats_dma_done == NULL) |
| 608 | return; /* no mac selected */ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 609 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 610 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
| 611 | nic_data->stats_pending = true; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 612 | wmb(); /* ensure done flag is clear */ |
| 613 | |
| 614 | /* Initiate DMA transfer of stats */ |
| 615 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 616 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
| 617 | FRF_AB_MAC_STAT_DMA_ADR, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 618 | efx->stats_buffer.dma_addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 619 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 620 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 621 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
| 622 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 623 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 624 | static void falcon_stats_complete(struct efx_nic *efx) |
| 625 | { |
| 626 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 627 | |
| 628 | if (!nic_data->stats_pending) |
| 629 | return; |
| 630 | |
| 631 | nic_data->stats_pending = 0; |
| 632 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { |
| 633 | rmb(); /* read the done flag before the stats */ |
| 634 | efx->mac_op->update_stats(efx); |
| 635 | } else { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 636 | netif_err(efx, hw, efx->net_dev, |
| 637 | "timed out waiting for statistics\n"); |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 638 | } |
| 639 | } |
| 640 | |
| 641 | static void falcon_stats_timer_func(unsigned long context) |
| 642 | { |
| 643 | struct efx_nic *efx = (struct efx_nic *)context; |
| 644 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 645 | |
| 646 | spin_lock(&efx->stats_lock); |
| 647 | |
| 648 | falcon_stats_complete(efx); |
| 649 | if (nic_data->stats_disable_count == 0) |
| 650 | falcon_stats_request(efx); |
| 651 | |
| 652 | spin_unlock(&efx->stats_lock); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 653 | } |
| 654 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 655 | static void falcon_switch_mac(struct efx_nic *efx); |
| 656 | |
Steve Hodgson | fdaa9ae | 2009-11-28 05:34:05 +0000 | [diff] [blame] | 657 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
| 658 | { |
| 659 | struct efx_link_state old_state = efx->link_state; |
| 660 | |
| 661 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
| 662 | WARN_ON(!LOOPBACK_INTERNAL(efx)); |
| 663 | |
| 664 | efx->link_state.fd = true; |
| 665 | efx->link_state.fc = efx->wanted_fc; |
| 666 | efx->link_state.up = true; |
| 667 | |
| 668 | if (efx->loopback_mode == LOOPBACK_GMAC) |
| 669 | efx->link_state.speed = 1000; |
| 670 | else |
| 671 | efx->link_state.speed = 10000; |
| 672 | |
| 673 | return !efx_link_state_equal(&efx->link_state, &old_state); |
| 674 | } |
| 675 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 676 | static int falcon_reconfigure_port(struct efx_nic *efx) |
| 677 | { |
| 678 | int rc; |
| 679 | |
| 680 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); |
| 681 | |
| 682 | /* Poll the PHY link state *before* reconfiguring it. This means we |
| 683 | * will pick up the correct speed (in loopback) to select the correct |
| 684 | * MAC. |
| 685 | */ |
| 686 | if (LOOPBACK_INTERNAL(efx)) |
| 687 | falcon_loopback_link_poll(efx); |
| 688 | else |
| 689 | efx->phy_op->poll(efx); |
| 690 | |
| 691 | falcon_stop_nic_stats(efx); |
| 692 | falcon_deconfigure_mac_wrapper(efx); |
| 693 | |
| 694 | falcon_switch_mac(efx); |
| 695 | |
| 696 | efx->phy_op->reconfigure(efx); |
| 697 | rc = efx->mac_op->reconfigure(efx); |
| 698 | BUG_ON(rc); |
| 699 | |
| 700 | falcon_start_nic_stats(efx); |
| 701 | |
| 702 | /* Synchronise efx->link_state with the kernel */ |
| 703 | efx_link_status_changed(efx); |
| 704 | |
| 705 | return 0; |
| 706 | } |
| 707 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 708 | /************************************************************************** |
| 709 | * |
| 710 | * PHY access via GMII |
| 711 | * |
| 712 | ************************************************************************** |
| 713 | */ |
| 714 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 715 | /* Wait for GMII access to complete */ |
| 716 | static int falcon_gmii_wait(struct efx_nic *efx) |
| 717 | { |
Ben Hutchings | 80cb9a0 | 2009-11-25 16:08:41 +0000 | [diff] [blame] | 718 | efx_oword_t md_stat; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 719 | int count; |
| 720 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 721 | /* wait upto 50ms - taken max from datasheet */ |
| 722 | for (count = 0; count < 5000; count++) { |
Ben Hutchings | 80cb9a0 | 2009-11-25 16:08:41 +0000 | [diff] [blame] | 723 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
| 724 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { |
| 725 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || |
| 726 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 727 | netif_err(efx, hw, efx->net_dev, |
| 728 | "error from GMII access " |
| 729 | EFX_OWORD_FMT"\n", |
| 730 | EFX_OWORD_VAL(md_stat)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 731 | return -EIO; |
| 732 | } |
| 733 | return 0; |
| 734 | } |
| 735 | udelay(10); |
| 736 | } |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 737 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 738 | return -ETIMEDOUT; |
| 739 | } |
| 740 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 741 | /* Write an MDIO register of a PHY connected to Falcon. */ |
| 742 | static int falcon_mdio_write(struct net_device *net_dev, |
| 743 | int prtad, int devad, u16 addr, u16 value) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 744 | { |
Ben Hutchings | 767e468 | 2008-09-01 12:43:14 +0100 | [diff] [blame] | 745 | struct efx_nic *efx = netdev_priv(net_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 746 | efx_oword_t reg; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 747 | int rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 748 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 749 | netif_vdbg(efx, hw, efx->net_dev, |
| 750 | "writing MDIO %d register %d.%d with 0x%04x\n", |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 751 | prtad, devad, addr, value); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 752 | |
Steve Hodgson | ab86746 | 2009-11-28 05:34:44 +0000 | [diff] [blame] | 753 | mutex_lock(&efx->mdio_lock); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 754 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 755 | /* Check MDIO not currently being accessed */ |
| 756 | rc = falcon_gmii_wait(efx); |
| 757 | if (rc) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 758 | goto out; |
| 759 | |
| 760 | /* Write the address/ID register */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 761 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 762 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 763 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 764 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
| 765 | FRF_AB_MD_DEV_ADR, devad); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 766 | efx_writeo(efx, ®, FR_AB_MD_ID); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 767 | |
| 768 | /* Write data */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 769 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 770 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 771 | |
| 772 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 773 | FRF_AB_MD_WRC, 1, |
| 774 | FRF_AB_MD_GC, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 775 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 776 | |
| 777 | /* Wait for data to be written */ |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 778 | rc = falcon_gmii_wait(efx); |
| 779 | if (rc) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 780 | /* Abort the write operation */ |
| 781 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 782 | FRF_AB_MD_WRC, 0, |
| 783 | FRF_AB_MD_GC, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 784 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 785 | udelay(10); |
| 786 | } |
| 787 | |
Steve Hodgson | ab86746 | 2009-11-28 05:34:44 +0000 | [diff] [blame] | 788 | out: |
| 789 | mutex_unlock(&efx->mdio_lock); |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 790 | return rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 791 | } |
| 792 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 793 | /* Read an MDIO register of a PHY connected to Falcon. */ |
| 794 | static int falcon_mdio_read(struct net_device *net_dev, |
| 795 | int prtad, int devad, u16 addr) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 796 | { |
Ben Hutchings | 767e468 | 2008-09-01 12:43:14 +0100 | [diff] [blame] | 797 | struct efx_nic *efx = netdev_priv(net_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 798 | efx_oword_t reg; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 799 | int rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 800 | |
Steve Hodgson | ab86746 | 2009-11-28 05:34:44 +0000 | [diff] [blame] | 801 | mutex_lock(&efx->mdio_lock); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 802 | |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 803 | /* Check MDIO not currently being accessed */ |
| 804 | rc = falcon_gmii_wait(efx); |
| 805 | if (rc) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 806 | goto out; |
| 807 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 808 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 809 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 810 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 811 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
| 812 | FRF_AB_MD_DEV_ADR, devad); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 813 | efx_writeo(efx, ®, FR_AB_MD_ID); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 814 | |
| 815 | /* Request data to be read */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 816 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 817 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 818 | |
| 819 | /* Wait for data to become available */ |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 820 | rc = falcon_gmii_wait(efx); |
| 821 | if (rc == 0) { |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 822 | efx_reado(efx, ®, FR_AB_MD_RXD); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 823 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 824 | netif_vdbg(efx, hw, efx->net_dev, |
| 825 | "read from MDIO %d register %d.%d, got %04x\n", |
| 826 | prtad, devad, addr, rc); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 827 | } else { |
| 828 | /* Abort the read operation */ |
| 829 | EFX_POPULATE_OWORD_2(reg, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 830 | FRF_AB_MD_RIC, 0, |
| 831 | FRF_AB_MD_GC, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 832 | efx_writeo(efx, ®, FR_AB_MD_CS); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 833 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 834 | netif_dbg(efx, hw, efx->net_dev, |
| 835 | "read from MDIO %d register %d.%d, got error %d\n", |
| 836 | prtad, devad, addr, rc); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 837 | } |
| 838 | |
Steve Hodgson | ab86746 | 2009-11-28 05:34:44 +0000 | [diff] [blame] | 839 | out: |
| 840 | mutex_unlock(&efx->mdio_lock); |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 841 | return rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 842 | } |
| 843 | |
Steve Hodgson | 26deba5 | 2009-11-25 16:11:03 +0000 | [diff] [blame] | 844 | static void falcon_clock_mac(struct efx_nic *efx) |
| 845 | { |
| 846 | unsigned strap_val; |
| 847 | efx_oword_t nic_stat; |
| 848 | |
| 849 | /* Configure the NIC generated MAC clock correctly */ |
| 850 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
| 851 | strap_val = EFX_IS10G(efx) ? 5 : 3; |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 852 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
Steve Hodgson | 26deba5 | 2009-11-25 16:11:03 +0000 | [diff] [blame] | 853 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); |
| 854 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); |
| 855 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); |
| 856 | } else { |
| 857 | /* Falcon A1 does not support 1G/10G speed switching |
| 858 | * and must not be used with a PHY that does. */ |
| 859 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != |
| 860 | strap_val); |
| 861 | } |
| 862 | } |
| 863 | |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 864 | static void falcon_switch_mac(struct efx_nic *efx) |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 865 | { |
| 866 | struct efx_mac_operations *old_mac_op = efx->mac_op; |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 867 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 868 | unsigned int stats_done_offset; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 869 | |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 870 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 871 | WARN_ON(nic_data->stats_disable_count == 0); |
| 872 | |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 873 | efx->mac_op = (EFX_IS10G(efx) ? |
| 874 | &falcon_xmac_operations : &falcon_gmac_operations); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 875 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 876 | if (EFX_IS10G(efx)) |
| 877 | stats_done_offset = XgDmaDone_offset; |
| 878 | else |
| 879 | stats_done_offset = GDmaDone_offset; |
| 880 | nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset; |
| 881 | |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 882 | if (old_mac_op == efx->mac_op) |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 883 | return; |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 884 | |
Steve Hodgson | 26deba5 | 2009-11-25 16:11:03 +0000 | [diff] [blame] | 885 | falcon_clock_mac(efx); |
| 886 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 887 | netif_dbg(efx, hw, efx->net_dev, "selected %cMAC\n", |
| 888 | EFX_IS10G(efx) ? 'X' : 'G'); |
Steve Hodgson | 0cc128387 | 2009-01-29 17:49:59 +0000 | [diff] [blame] | 889 | /* Not all macs support a mac-level link state */ |
Ben Hutchings | 9007b9f | 2009-11-25 16:12:01 +0000 | [diff] [blame] | 890 | efx->xmac_poll_required = false; |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 891 | falcon_reset_macs(efx); |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 892 | } |
| 893 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 894 | /* This call is responsible for hooking in the MAC and PHY operations */ |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 895 | static int falcon_probe_port(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 896 | { |
| 897 | int rc; |
| 898 | |
Ben Hutchings | 96c45726 | 2009-10-23 08:32:42 +0000 | [diff] [blame] | 899 | switch (efx->phy_type) { |
| 900 | case PHY_TYPE_SFX7101: |
| 901 | efx->phy_op = &falcon_sfx7101_phy_ops; |
| 902 | break; |
| 903 | case PHY_TYPE_SFT9001A: |
| 904 | case PHY_TYPE_SFT9001B: |
| 905 | efx->phy_op = &falcon_sft9001_phy_ops; |
| 906 | break; |
| 907 | case PHY_TYPE_QT2022C2: |
| 908 | case PHY_TYPE_QT2025C: |
Ben Hutchings | b37b62f | 2009-10-23 08:33:42 +0000 | [diff] [blame] | 909 | efx->phy_op = &falcon_qt202x_phy_ops; |
Ben Hutchings | 96c45726 | 2009-10-23 08:32:42 +0000 | [diff] [blame] | 910 | break; |
| 911 | default: |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 912 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", |
| 913 | efx->phy_type); |
Ben Hutchings | 96c45726 | 2009-10-23 08:32:42 +0000 | [diff] [blame] | 914 | return -ENODEV; |
| 915 | } |
| 916 | |
Ben Hutchings | c1c4f45 | 2009-11-29 15:08:55 +0000 | [diff] [blame] | 917 | /* Fill out MDIO structure and loopback modes */ |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 918 | efx->mdio.mdio_read = falcon_mdio_read; |
| 919 | efx->mdio.mdio_write = falcon_mdio_write; |
Ben Hutchings | c1c4f45 | 2009-11-29 15:08:55 +0000 | [diff] [blame] | 920 | rc = efx->phy_op->probe(efx); |
| 921 | if (rc != 0) |
| 922 | return rc; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 923 | |
Steve Hodgson | b895d73 | 2009-11-28 05:35:00 +0000 | [diff] [blame] | 924 | /* Initial assumption */ |
| 925 | efx->link_state.speed = 10000; |
| 926 | efx->link_state.fd = true; |
| 927 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 928 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 929 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
Ben Hutchings | 04cc8ca | 2008-12-12 21:50:46 -0800 | [diff] [blame] | 930 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 931 | else |
Ben Hutchings | 04cc8ca | 2008-12-12 21:50:46 -0800 | [diff] [blame] | 932 | efx->wanted_fc = EFX_FC_RX; |
Steve Hodgson | 7a6b8f6 | 2010-02-03 09:30:38 +0000 | [diff] [blame] | 933 | if (efx->mdio.mmds & MDIO_DEVS_AN) |
| 934 | efx->wanted_fc |= EFX_FC_AUTO; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 935 | |
| 936 | /* Allocate buffer for stats */ |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 937 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
| 938 | FALCON_MAC_STATS_SIZE); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 939 | if (rc) |
| 940 | return rc; |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 941 | netif_dbg(efx, probe, efx->net_dev, |
| 942 | "stats buffer at %llx (virt %p phys %llx)\n", |
| 943 | (u64)efx->stats_buffer.dma_addr, |
| 944 | efx->stats_buffer.addr, |
| 945 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 946 | |
| 947 | return 0; |
| 948 | } |
| 949 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 950 | static void falcon_remove_port(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 951 | { |
Steve Hodgson | ff3b00a | 2009-12-23 13:46:36 +0000 | [diff] [blame] | 952 | efx->phy_op->remove(efx); |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 953 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | /************************************************************************** |
| 957 | * |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 958 | * Falcon test code |
| 959 | * |
| 960 | **************************************************************************/ |
| 961 | |
Ben Hutchings | 0aa3fba | 2009-11-29 03:43:33 +0000 | [diff] [blame] | 962 | static int |
| 963 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 964 | { |
| 965 | struct falcon_nvconfig *nvconfig; |
| 966 | struct efx_spi_device *spi; |
| 967 | void *region; |
| 968 | int rc, magic_num, struct_ver; |
| 969 | __le16 *word, *limit; |
| 970 | u32 csum; |
| 971 | |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 972 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
| 973 | if (!spi) |
| 974 | return -EINVAL; |
| 975 | |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame] | 976 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 977 | if (!region) |
| 978 | return -ENOMEM; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 979 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 980 | |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 981 | mutex_lock(&efx->spi_lock); |
Ben Hutchings | 7688483 | 2009-11-29 15:10:44 +0000 | [diff] [blame] | 982 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 983 | mutex_unlock(&efx->spi_lock); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 984 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 985 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", |
| 986 | efx->spi_flash ? "flash" : "EEPROM"); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 987 | rc = -EIO; |
| 988 | goto out; |
| 989 | } |
| 990 | |
| 991 | magic_num = le16_to_cpu(nvconfig->board_magic_num); |
| 992 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); |
| 993 | |
| 994 | rc = -EINVAL; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 995 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 996 | netif_err(efx, hw, efx->net_dev, |
| 997 | "NVRAM bad magic 0x%x\n", magic_num); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 998 | goto out; |
| 999 | } |
| 1000 | if (struct_ver < 2) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1001 | netif_err(efx, hw, efx->net_dev, |
| 1002 | "NVRAM has ancient version 0x%x\n", struct_ver); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1003 | goto out; |
| 1004 | } else if (struct_ver < 4) { |
| 1005 | word = &nvconfig->board_magic_num; |
| 1006 | limit = (__le16 *) (nvconfig + 1); |
| 1007 | } else { |
| 1008 | word = region; |
Ben Hutchings | 0a95f56 | 2008-11-04 20:33:11 +0000 | [diff] [blame] | 1009 | limit = region + FALCON_NVCONFIG_END; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1010 | } |
| 1011 | for (csum = 0; word < limit; ++word) |
| 1012 | csum += le16_to_cpu(*word); |
| 1013 | |
| 1014 | if (~csum & 0xffff) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1015 | netif_err(efx, hw, efx->net_dev, |
| 1016 | "NVRAM has incorrect checksum\n"); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1017 | goto out; |
| 1018 | } |
| 1019 | |
| 1020 | rc = 0; |
| 1021 | if (nvconfig_out) |
| 1022 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); |
| 1023 | |
| 1024 | out: |
| 1025 | kfree(region); |
| 1026 | return rc; |
| 1027 | } |
| 1028 | |
Ben Hutchings | 0aa3fba | 2009-11-29 03:43:33 +0000 | [diff] [blame] | 1029 | static int falcon_test_nvram(struct efx_nic *efx) |
| 1030 | { |
| 1031 | return falcon_read_nvram(efx, NULL); |
| 1032 | } |
| 1033 | |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1034 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1035 | { FR_AZ_ADR_REGION, |
Steve Hodgson | 4cddca5 | 2010-02-03 09:31:40 +0000 | [diff] [blame] | 1036 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1037 | { FR_AZ_RX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1038 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1039 | { FR_AZ_TX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1040 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1041 | { FR_AZ_TX_RESERVED, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1042 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1043 | { FR_AB_MAC_CTRL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1044 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1045 | { FR_AZ_SRM_TX_DC_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1046 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1047 | { FR_AZ_RX_DC_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1048 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1049 | { FR_AZ_RX_DC_PF_WM, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1050 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1051 | { FR_BZ_DP_CTRL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1052 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1053 | { FR_AB_GM_CFG2, |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1054 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1055 | { FR_AB_GMF_CFG0, |
Ben Hutchings | 177dfcd | 2008-12-12 21:50:08 -0800 | [diff] [blame] | 1056 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1057 | { FR_AB_XM_GLB_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1058 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1059 | { FR_AB_XM_TX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1060 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1061 | { FR_AB_XM_RX_CFG, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1062 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1063 | { FR_AB_XM_RX_PARAM, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1064 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1065 | { FR_AB_XM_FC, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1066 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1067 | { FR_AB_XM_ADR_LO, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1068 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1069 | { FR_AB_XX_SD_CTL, |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1070 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
| 1071 | }; |
| 1072 | |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1073 | static int falcon_b0_test_registers(struct efx_nic *efx) |
| 1074 | { |
| 1075 | return efx_nic_test_registers(efx, falcon_b0_register_tests, |
| 1076 | ARRAY_SIZE(falcon_b0_register_tests)); |
| 1077 | } |
| 1078 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1079 | /************************************************************************** |
| 1080 | * |
| 1081 | * Device reset |
| 1082 | * |
| 1083 | ************************************************************************** |
| 1084 | */ |
| 1085 | |
| 1086 | /* Resets NIC to known state. This routine must be called in process |
| 1087 | * context and is allowed to sleep. */ |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1088 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1089 | { |
| 1090 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 1091 | efx_oword_t glb_ctl_reg_ker; |
| 1092 | int rc; |
| 1093 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1094 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", |
| 1095 | RESET_TYPE(method)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1096 | |
| 1097 | /* Initiate device reset */ |
| 1098 | if (method == RESET_TYPE_WORLD) { |
| 1099 | rc = pci_save_state(efx->pci_dev); |
| 1100 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1101 | netif_err(efx, drv, efx->net_dev, |
| 1102 | "failed to backup PCI state of primary " |
| 1103 | "function prior to hardware reset\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1104 | goto fail1; |
| 1105 | } |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1106 | if (efx_nic_is_dual_func(efx)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1107 | rc = pci_save_state(nic_data->pci_dev2); |
| 1108 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1109 | netif_err(efx, drv, efx->net_dev, |
| 1110 | "failed to backup PCI state of " |
| 1111 | "secondary function prior to " |
| 1112 | "hardware reset\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1113 | goto fail2; |
| 1114 | } |
| 1115 | } |
| 1116 | |
| 1117 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1118 | FRF_AB_EXT_PHY_RST_DUR, |
| 1119 | FFE_AB_EXT_PHY_RST_DUR_10240US, |
| 1120 | FRF_AB_SWRST, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1121 | } else { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1122 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1123 | /* exclude PHY from "invisible" reset */ |
| 1124 | FRF_AB_EXT_PHY_RST_CTL, |
| 1125 | method == RESET_TYPE_INVISIBLE, |
| 1126 | /* exclude EEPROM/flash and PCIe */ |
| 1127 | FRF_AB_PCIE_CORE_RST_CTL, 1, |
| 1128 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, |
| 1129 | FRF_AB_PCIE_SD_RST_CTL, 1, |
| 1130 | FRF_AB_EE_RST_CTL, 1, |
| 1131 | FRF_AB_EXT_PHY_RST_DUR, |
| 1132 | FFE_AB_EXT_PHY_RST_DUR_10240US, |
| 1133 | FRF_AB_SWRST, 1); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1134 | } |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1135 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1136 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1137 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1138 | schedule_timeout_uninterruptible(HZ / 20); |
| 1139 | |
| 1140 | /* Restore PCI configuration if needed */ |
| 1141 | if (method == RESET_TYPE_WORLD) { |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1142 | if (efx_nic_is_dual_func(efx)) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1143 | rc = pci_restore_state(nic_data->pci_dev2); |
| 1144 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1145 | netif_err(efx, drv, efx->net_dev, |
| 1146 | "failed to restore PCI config for " |
| 1147 | "the secondary function\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1148 | goto fail3; |
| 1149 | } |
| 1150 | } |
| 1151 | rc = pci_restore_state(efx->pci_dev); |
| 1152 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1153 | netif_err(efx, drv, efx->net_dev, |
| 1154 | "failed to restore PCI config for the " |
| 1155 | "primary function\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1156 | goto fail4; |
| 1157 | } |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1158 | netif_dbg(efx, drv, efx->net_dev, |
| 1159 | "successfully restored PCI config\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | /* Assert that reset complete */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1163 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1164 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1165 | rc = -ETIMEDOUT; |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1166 | netif_err(efx, hw, efx->net_dev, |
| 1167 | "timed out waiting for hardware reset\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1168 | goto fail5; |
| 1169 | } |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1170 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1171 | |
| 1172 | return 0; |
| 1173 | |
| 1174 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ |
| 1175 | fail2: |
| 1176 | fail3: |
| 1177 | pci_restore_state(efx->pci_dev); |
| 1178 | fail1: |
| 1179 | fail4: |
| 1180 | fail5: |
| 1181 | return rc; |
| 1182 | } |
| 1183 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1184 | static void falcon_monitor(struct efx_nic *efx) |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1185 | { |
Steve Hodgson | fdaa9ae | 2009-11-28 05:34:05 +0000 | [diff] [blame] | 1186 | bool link_changed; |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1187 | int rc; |
| 1188 | |
Steve Hodgson | fdaa9ae | 2009-11-28 05:34:05 +0000 | [diff] [blame] | 1189 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
| 1190 | |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1191 | rc = falcon_board(efx)->type->monitor(efx); |
| 1192 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1193 | netif_err(efx, hw, efx->net_dev, |
| 1194 | "Board sensor %s; shutting down PHY\n", |
| 1195 | (rc == -ERANGE) ? "reported fault" : "failed"); |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1196 | efx->phy_mode |= PHY_MODE_LOW_POWER; |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 1197 | rc = __efx_reconfigure_port(efx); |
| 1198 | WARN_ON(rc); |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1199 | } |
Steve Hodgson | fdaa9ae | 2009-11-28 05:34:05 +0000 | [diff] [blame] | 1200 | |
| 1201 | if (LOOPBACK_INTERNAL(efx)) |
| 1202 | link_changed = falcon_loopback_link_poll(efx); |
| 1203 | else |
| 1204 | link_changed = efx->phy_op->poll(efx); |
| 1205 | |
| 1206 | if (link_changed) { |
| 1207 | falcon_stop_nic_stats(efx); |
| 1208 | falcon_deconfigure_mac_wrapper(efx); |
| 1209 | |
| 1210 | falcon_switch_mac(efx); |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 1211 | rc = efx->mac_op->reconfigure(efx); |
| 1212 | BUG_ON(rc); |
Steve Hodgson | fdaa9ae | 2009-11-28 05:34:05 +0000 | [diff] [blame] | 1213 | |
| 1214 | falcon_start_nic_stats(efx); |
| 1215 | |
| 1216 | efx_link_status_changed(efx); |
| 1217 | } |
| 1218 | |
Ben Hutchings | 9007b9f | 2009-11-25 16:12:01 +0000 | [diff] [blame] | 1219 | if (EFX_IS10G(efx)) |
| 1220 | falcon_poll_xmac(efx); |
Ben Hutchings | fe75820 | 2009-11-25 16:11:45 +0000 | [diff] [blame] | 1221 | } |
| 1222 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1223 | /* Zeroes out the SRAM contents. This routine must be called in |
| 1224 | * process context and is allowed to sleep. |
| 1225 | */ |
| 1226 | static int falcon_reset_sram(struct efx_nic *efx) |
| 1227 | { |
| 1228 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; |
| 1229 | int count; |
| 1230 | |
| 1231 | /* Set the SRAM wake/sleep GPIO appropriately. */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1232 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1233 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
| 1234 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1235 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1236 | |
| 1237 | /* Initiate SRAM reset */ |
| 1238 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1239 | FRF_AZ_SRM_INIT_EN, 1, |
| 1240 | FRF_AZ_SRM_NB_SZ, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1241 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1242 | |
| 1243 | /* Wait for SRAM reset to complete */ |
| 1244 | count = 0; |
| 1245 | do { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1246 | netif_dbg(efx, hw, efx->net_dev, |
| 1247 | "waiting for SRAM reset (attempt %d)...\n", count); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1248 | |
| 1249 | /* SRAM reset is slow; expect around 16ms */ |
| 1250 | schedule_timeout_uninterruptible(HZ / 50); |
| 1251 | |
| 1252 | /* Check for reset complete */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1253 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1254 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1255 | netif_dbg(efx, hw, efx->net_dev, |
| 1256 | "SRAM reset complete\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1257 | |
| 1258 | return 0; |
| 1259 | } |
| 1260 | } while (++count < 20); /* wait upto 0.4 sec */ |
| 1261 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1262 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1263 | return -ETIMEDOUT; |
| 1264 | } |
| 1265 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1266 | static int falcon_spi_device_init(struct efx_nic *efx, |
| 1267 | struct efx_spi_device **spi_device_ret, |
| 1268 | unsigned int device_id, u32 device_type) |
| 1269 | { |
| 1270 | struct efx_spi_device *spi_device; |
| 1271 | |
| 1272 | if (device_type != 0) { |
Ben Hutchings | 0c53d8c | 2008-12-12 22:08:50 -0800 | [diff] [blame] | 1273 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1274 | if (!spi_device) |
| 1275 | return -ENOMEM; |
| 1276 | spi_device->device_id = device_id; |
| 1277 | spi_device->size = |
| 1278 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); |
| 1279 | spi_device->addr_len = |
| 1280 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); |
| 1281 | spi_device->munge_address = (spi_device->size == 1 << 9 && |
| 1282 | spi_device->addr_len == 1); |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 1283 | spi_device->erase_command = |
| 1284 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); |
| 1285 | spi_device->erase_size = |
| 1286 | 1 << SPI_DEV_TYPE_FIELD(device_type, |
| 1287 | SPI_DEV_TYPE_ERASE_SIZE); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1288 | spi_device->block_size = |
| 1289 | 1 << SPI_DEV_TYPE_FIELD(device_type, |
| 1290 | SPI_DEV_TYPE_BLOCK_SIZE); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1291 | } else { |
| 1292 | spi_device = NULL; |
| 1293 | } |
| 1294 | |
| 1295 | kfree(*spi_device_ret); |
| 1296 | *spi_device_ret = spi_device; |
| 1297 | return 0; |
| 1298 | } |
| 1299 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1300 | static void falcon_remove_spi_devices(struct efx_nic *efx) |
| 1301 | { |
| 1302 | kfree(efx->spi_eeprom); |
| 1303 | efx->spi_eeprom = NULL; |
| 1304 | kfree(efx->spi_flash); |
| 1305 | efx->spi_flash = NULL; |
| 1306 | } |
| 1307 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1308 | /* Extract non-volatile configuration */ |
| 1309 | static int falcon_probe_nvconfig(struct efx_nic *efx) |
| 1310 | { |
| 1311 | struct falcon_nvconfig *nvconfig; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1312 | int board_rev; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1313 | int rc; |
| 1314 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1315 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1316 | if (!nvconfig) |
| 1317 | return -ENOMEM; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1318 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1319 | rc = falcon_read_nvram(efx, nvconfig); |
| 1320 | if (rc == -EINVAL) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1321 | netif_err(efx, probe, efx->net_dev, |
| 1322 | "NVRAM is invalid therefore using defaults\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1323 | efx->phy_type = PHY_TYPE_NONE; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 1324 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1325 | board_rev = 0; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1326 | rc = 0; |
| 1327 | } else if (rc) { |
| 1328 | goto fail1; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1329 | } else { |
| 1330 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1331 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1332 | |
| 1333 | efx->phy_type = v2->port0_phy_type; |
Ben Hutchings | 68e7f45 | 2009-04-29 08:05:08 +0000 | [diff] [blame] | 1334 | efx->mdio.prtad = v2->port0_phy_addr; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1335 | board_rev = le16_to_cpu(v2->board_revision); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1336 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1337 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1338 | rc = falcon_spi_device_init( |
| 1339 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, |
| 1340 | le32_to_cpu(v3->spi_device_type |
| 1341 | [FFE_AB_SPI_DEVICE_FLASH])); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1342 | if (rc) |
| 1343 | goto fail2; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1344 | rc = falcon_spi_device_init( |
| 1345 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, |
| 1346 | le32_to_cpu(v3->spi_device_type |
| 1347 | [FFE_AB_SPI_DEVICE_EEPROM])); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1348 | if (rc) |
| 1349 | goto fail2; |
| 1350 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1351 | } |
| 1352 | |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 1353 | /* Read the MAC addresses */ |
| 1354 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); |
| 1355 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1356 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", |
| 1357 | efx->phy_type, efx->mdio.prtad); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1358 | |
Ben Hutchings | e41c11e | 2010-04-28 09:01:50 +0000 | [diff] [blame] | 1359 | rc = falcon_probe_board(efx, board_rev); |
| 1360 | if (rc) |
| 1361 | goto fail2; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1362 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1363 | kfree(nvconfig); |
| 1364 | return 0; |
| 1365 | |
| 1366 | fail2: |
| 1367 | falcon_remove_spi_devices(efx); |
| 1368 | fail1: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1369 | kfree(nvconfig); |
| 1370 | return rc; |
| 1371 | } |
| 1372 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1373 | /* Probe all SPI devices on the NIC */ |
| 1374 | static void falcon_probe_spi_devices(struct efx_nic *efx) |
| 1375 | { |
| 1376 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1377 | int boot_dev; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1378 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1379 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
| 1380 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
| 1381 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1382 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1383 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
| 1384 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? |
| 1385 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1386 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", |
| 1387 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? |
| 1388 | "flash" : "EEPROM"); |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1389 | } else { |
| 1390 | /* Disable VPD and set clock dividers to safe |
| 1391 | * values for initial programming. */ |
| 1392 | boot_dev = -1; |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1393 | netif_dbg(efx, probe, efx->net_dev, |
| 1394 | "Booted from internal ASIC settings;" |
| 1395 | " setting SPI config\n"); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1396 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1397 | /* 125 MHz / 7 ~= 20 MHz */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1398 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1399 | /* 125 MHz / 63 ~= 2 MHz */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1400 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1401 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1402 | } |
| 1403 | |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1404 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
| 1405 | falcon_spi_device_init(efx, &efx->spi_flash, |
| 1406 | FFE_AB_SPI_DEVICE_FLASH, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1407 | default_flash_type); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1408 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
| 1409 | falcon_spi_device_init(efx, &efx->spi_eeprom, |
| 1410 | FFE_AB_SPI_DEVICE_EEPROM, |
Ben Hutchings | 2f7f573 | 2008-12-12 21:34:25 -0800 | [diff] [blame] | 1411 | large_eeprom_type); |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1412 | } |
| 1413 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1414 | static int falcon_probe_nic(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1415 | { |
| 1416 | struct falcon_nic_data *nic_data; |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1417 | struct falcon_board *board; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1418 | int rc; |
| 1419 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1420 | /* Allocate storage for hardware specific data */ |
| 1421 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); |
Ben Hutchings | 88c5942 | 2008-09-03 15:07:50 +0100 | [diff] [blame] | 1422 | if (!nic_data) |
| 1423 | return -ENOMEM; |
Ben Hutchings | 5daab96 | 2008-05-16 21:19:43 +0100 | [diff] [blame] | 1424 | efx->nic_data = nic_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1425 | |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1426 | rc = -ENODEV; |
| 1427 | |
| 1428 | if (efx_nic_fpga_ver(efx) != 0) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1429 | netif_err(efx, probe, efx->net_dev, |
| 1430 | "Falcon FPGA not supported\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1431 | goto fail1; |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1432 | } |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1433 | |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1434 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
| 1435 | efx_oword_t nic_stat; |
| 1436 | struct pci_dev *dev; |
| 1437 | u8 pci_rev = efx->pci_dev->revision; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1438 | |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1439 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1440 | netif_err(efx, probe, efx->net_dev, |
| 1441 | "Falcon rev A0 not supported\n"); |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1442 | goto fail1; |
| 1443 | } |
| 1444 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
| 1445 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1446 | netif_err(efx, probe, efx->net_dev, |
| 1447 | "Falcon rev A1 1G not supported\n"); |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1448 | goto fail1; |
| 1449 | } |
| 1450 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1451 | netif_err(efx, probe, efx->net_dev, |
| 1452 | "Falcon rev A1 PCI-X not supported\n"); |
Ben Hutchings | 5784946 | 2009-11-29 15:08:21 +0000 | [diff] [blame] | 1453 | goto fail1; |
| 1454 | } |
| 1455 | |
| 1456 | dev = pci_dev_get(efx->pci_dev); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1457 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, |
| 1458 | dev))) { |
| 1459 | if (dev->bus == efx->pci_dev->bus && |
| 1460 | dev->devfn == efx->pci_dev->devfn + 1) { |
| 1461 | nic_data->pci_dev2 = dev; |
| 1462 | break; |
| 1463 | } |
| 1464 | } |
| 1465 | if (!nic_data->pci_dev2) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1466 | netif_err(efx, probe, efx->net_dev, |
| 1467 | "failed to find secondary function\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1468 | rc = -ENODEV; |
| 1469 | goto fail2; |
| 1470 | } |
| 1471 | } |
| 1472 | |
| 1473 | /* Now we can reset the NIC */ |
| 1474 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); |
| 1475 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1476 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1477 | goto fail3; |
| 1478 | } |
| 1479 | |
| 1480 | /* Allocate memory for INT_KER */ |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1481 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1482 | if (rc) |
| 1483 | goto fail4; |
| 1484 | BUG_ON(efx->irq_status.dma_addr & 0x0f); |
| 1485 | |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1486 | netif_dbg(efx, probe, efx->net_dev, |
| 1487 | "INT_KER at %llx (virt %p phys %llx)\n", |
| 1488 | (u64)efx->irq_status.dma_addr, |
| 1489 | efx->irq_status.addr, |
| 1490 | (u64)virt_to_phys(efx->irq_status.addr)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1491 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1492 | falcon_probe_spi_devices(efx); |
| 1493 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1494 | /* Read in the non-volatile configuration */ |
| 1495 | rc = falcon_probe_nvconfig(efx); |
| 1496 | if (rc) |
| 1497 | goto fail5; |
| 1498 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 1499 | /* Initialise I2C adapter */ |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1500 | board = falcon_board(efx); |
| 1501 | board->i2c_adap.owner = THIS_MODULE; |
| 1502 | board->i2c_data = falcon_i2c_bit_operations; |
| 1503 | board->i2c_data.data = efx; |
| 1504 | board->i2c_adap.algo_data = &board->i2c_data; |
| 1505 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; |
| 1506 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", |
| 1507 | sizeof(board->i2c_adap.name)); |
| 1508 | rc = i2c_bit_add_bus(&board->i2c_adap); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 1509 | if (rc) |
| 1510 | goto fail5; |
| 1511 | |
Ben Hutchings | 44838a4 | 2009-11-25 16:09:41 +0000 | [diff] [blame] | 1512 | rc = falcon_board(efx)->type->init(efx); |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame] | 1513 | if (rc) { |
Ben Hutchings | 62776d0 | 2010-06-23 11:30:07 +0000 | [diff] [blame] | 1514 | netif_err(efx, probe, efx->net_dev, |
| 1515 | "failed to initialise board\n"); |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame] | 1516 | goto fail6; |
| 1517 | } |
| 1518 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 1519 | nic_data->stats_disable_count = 1; |
| 1520 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, |
| 1521 | (unsigned long)efx); |
| 1522 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1523 | return 0; |
| 1524 | |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame] | 1525 | fail6: |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1526 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
| 1527 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1528 | fail5: |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1529 | falcon_remove_spi_devices(efx); |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1530 | efx_nic_free_buffer(efx, &efx->irq_status); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1531 | fail4: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1532 | fail3: |
| 1533 | if (nic_data->pci_dev2) { |
| 1534 | pci_dev_put(nic_data->pci_dev2); |
| 1535 | nic_data->pci_dev2 = NULL; |
| 1536 | } |
| 1537 | fail2: |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1538 | fail1: |
| 1539 | kfree(efx->nic_data); |
| 1540 | return rc; |
| 1541 | } |
| 1542 | |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1543 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
| 1544 | { |
| 1545 | /* Prior to Siena the RX DMA engine will split each frame at |
| 1546 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to |
| 1547 | * be so large that that never happens. */ |
| 1548 | const unsigned huge_buf_size = (3 * 4096) >> 5; |
| 1549 | /* RX control FIFO thresholds (32 entries) */ |
| 1550 | const unsigned ctrl_xon_thr = 20; |
| 1551 | const unsigned ctrl_xoff_thr = 25; |
| 1552 | /* RX data FIFO thresholds (256-byte units; size varies) */ |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1553 | int data_xon_thr = efx_nic_rx_xon_thresh >> 8; |
| 1554 | int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8; |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1555 | efx_oword_t reg; |
| 1556 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1557 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1558 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
Ben Hutchings | 625b451 | 2009-10-23 08:30:17 +0000 | [diff] [blame] | 1559 | /* Data FIFO size is 5.5K */ |
| 1560 | if (data_xon_thr < 0) |
| 1561 | data_xon_thr = 512 >> 8; |
| 1562 | if (data_xoff_thr < 0) |
| 1563 | data_xoff_thr = 2048 >> 8; |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1564 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
| 1565 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, |
| 1566 | huge_buf_size); |
| 1567 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); |
| 1568 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); |
| 1569 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); |
| 1570 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1571 | } else { |
Ben Hutchings | 625b451 | 2009-10-23 08:30:17 +0000 | [diff] [blame] | 1572 | /* Data FIFO size is 80K; register fields moved */ |
| 1573 | if (data_xon_thr < 0) |
| 1574 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ |
| 1575 | if (data_xoff_thr < 0) |
| 1576 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1577 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
| 1578 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, |
| 1579 | huge_buf_size); |
| 1580 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); |
| 1581 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); |
| 1582 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); |
| 1583 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); |
| 1584 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
Ben Hutchings | 477e54e | 2010-06-25 07:05:56 +0000 | [diff] [blame] | 1585 | |
| 1586 | /* Enable hash insertion. This is broken for the |
| 1587 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and |
| 1588 | * IPv4 hashes. */ |
| 1589 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); |
| 1590 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); |
| 1591 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1592 | } |
Ben Hutchings | 4b0d29d | 2009-11-29 03:42:18 +0000 | [diff] [blame] | 1593 | /* Always enable XOFF signal from RX FIFO. We enable |
| 1594 | * or disable transmission of pause frames at the MAC. */ |
| 1595 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1596 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1597 | } |
| 1598 | |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1599 | /* This call performs hardware-specific global initialisation, such as |
| 1600 | * defining the descriptor cache sizes and number of RSS channels. |
| 1601 | * It does not set up any buffers, descriptor rings or event queues. |
| 1602 | */ |
| 1603 | static int falcon_init_nic(struct efx_nic *efx) |
| 1604 | { |
| 1605 | efx_oword_t temp; |
| 1606 | int rc; |
| 1607 | |
| 1608 | /* Use on-chip SRAM */ |
| 1609 | efx_reado(efx, &temp, FR_AB_NIC_STAT); |
| 1610 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
| 1611 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
| 1612 | |
| 1613 | /* Set the source of the GMAC clock */ |
| 1614 | if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) { |
| 1615 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); |
| 1616 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); |
| 1617 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); |
| 1618 | } |
| 1619 | |
| 1620 | /* Select the correct MAC */ |
| 1621 | falcon_clock_mac(efx); |
| 1622 | |
| 1623 | rc = falcon_reset_sram(efx); |
| 1624 | if (rc) |
| 1625 | return rc; |
| 1626 | |
| 1627 | /* Clear the parity enables on the TX data fifos as |
| 1628 | * they produce false parity errors because of timing issues |
| 1629 | */ |
| 1630 | if (EFX_WORKAROUND_5129(efx)) { |
| 1631 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); |
| 1632 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); |
| 1633 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); |
| 1634 | } |
| 1635 | |
| 1636 | if (EFX_WORKAROUND_7244(efx)) { |
| 1637 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
| 1638 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
| 1639 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); |
| 1640 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); |
| 1641 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); |
| 1642 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
| 1643 | } |
| 1644 | |
| 1645 | /* XXX This is documented only for Falcon A0/A1 */ |
| 1646 | /* Setup RX. Wait for descriptor is broken and must |
| 1647 | * be disabled. RXDP recovery shouldn't be needed, but is. |
| 1648 | */ |
| 1649 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
| 1650 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
| 1651 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); |
| 1652 | if (EFX_WORKAROUND_5583(efx)) |
| 1653 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
| 1654 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1655 | |
| 1656 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
| 1657 | * descriptors (which is bad). |
| 1658 | */ |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1659 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1660 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1661 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1662 | |
Ben Hutchings | 56241ce | 2009-10-23 08:30:06 +0000 | [diff] [blame] | 1663 | falcon_init_rx_cfg(efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1664 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1665 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
Ben Hutchings | 477e54e | 2010-06-25 07:05:56 +0000 | [diff] [blame] | 1666 | /* Set hash key for IPv4 */ |
| 1667 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); |
| 1668 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); |
| 1669 | |
| 1670 | /* Set destination of both TX and RX Flush events */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1671 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1672 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1673 | } |
| 1674 | |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1675 | efx_nic_init_common(efx); |
| 1676 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1677 | return 0; |
| 1678 | } |
| 1679 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1680 | static void falcon_remove_nic(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1681 | { |
| 1682 | struct falcon_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1683 | struct falcon_board *board = falcon_board(efx); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 1684 | int rc; |
| 1685 | |
Ben Hutchings | 44838a4 | 2009-11-25 16:09:41 +0000 | [diff] [blame] | 1686 | board->type->fini(efx); |
Ben Hutchings | 278c062 | 2009-11-23 16:05:12 +0000 | [diff] [blame] | 1687 | |
Ben Hutchings | 8c87037 | 2009-03-04 09:53:02 +0000 | [diff] [blame] | 1688 | /* Remove I2C adapter and clear it in preparation for a retry */ |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1689 | rc = i2c_del_adapter(&board->i2c_adap); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 1690 | BUG_ON(rc); |
Ben Hutchings | e775fb9 | 2009-11-23 16:06:02 +0000 | [diff] [blame] | 1691 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1692 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 1693 | falcon_remove_spi_devices(efx); |
Ben Hutchings | 152b6a6 | 2009-11-29 03:43:56 +0000 | [diff] [blame] | 1694 | efx_nic_free_buffer(efx, &efx->irq_status); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1695 | |
Ben Hutchings | 91ad757 | 2008-05-16 21:14:27 +0100 | [diff] [blame] | 1696 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1697 | |
| 1698 | /* Release the second function after the reset */ |
| 1699 | if (nic_data->pci_dev2) { |
| 1700 | pci_dev_put(nic_data->pci_dev2); |
| 1701 | nic_data->pci_dev2 = NULL; |
| 1702 | } |
| 1703 | |
| 1704 | /* Tear down the private nic state */ |
| 1705 | kfree(efx->nic_data); |
| 1706 | efx->nic_data = NULL; |
| 1707 | } |
| 1708 | |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1709 | static void falcon_update_nic_stats(struct efx_nic *efx) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1710 | { |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 1711 | struct falcon_nic_data *nic_data = efx->nic_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1712 | efx_oword_t cnt; |
| 1713 | |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 1714 | if (nic_data->stats_disable_count) |
| 1715 | return; |
| 1716 | |
Ben Hutchings | 12d00ca | 2009-10-23 08:30:46 +0000 | [diff] [blame] | 1717 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1718 | efx->n_rx_nodesc_drop_cnt += |
| 1719 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); |
Ben Hutchings | 55edc6e | 2009-11-25 16:11:35 +0000 | [diff] [blame] | 1720 | |
| 1721 | if (nic_data->stats_pending && |
| 1722 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { |
| 1723 | nic_data->stats_pending = false; |
| 1724 | rmb(); /* read the done flag before the stats */ |
| 1725 | efx->mac_op->update_stats(efx); |
| 1726 | } |
| 1727 | } |
| 1728 | |
| 1729 | void falcon_start_nic_stats(struct efx_nic *efx) |
| 1730 | { |
| 1731 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 1732 | |
| 1733 | spin_lock_bh(&efx->stats_lock); |
| 1734 | if (--nic_data->stats_disable_count == 0) |
| 1735 | falcon_stats_request(efx); |
| 1736 | spin_unlock_bh(&efx->stats_lock); |
| 1737 | } |
| 1738 | |
| 1739 | void falcon_stop_nic_stats(struct efx_nic *efx) |
| 1740 | { |
| 1741 | struct falcon_nic_data *nic_data = efx->nic_data; |
| 1742 | int i; |
| 1743 | |
| 1744 | might_sleep(); |
| 1745 | |
| 1746 | spin_lock_bh(&efx->stats_lock); |
| 1747 | ++nic_data->stats_disable_count; |
| 1748 | spin_unlock_bh(&efx->stats_lock); |
| 1749 | |
| 1750 | del_timer_sync(&nic_data->stats_timer); |
| 1751 | |
| 1752 | /* Wait enough time for the most recent transfer to |
| 1753 | * complete. */ |
| 1754 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { |
| 1755 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) |
| 1756 | break; |
| 1757 | msleep(1); |
| 1758 | } |
| 1759 | |
| 1760 | spin_lock_bh(&efx->stats_lock); |
| 1761 | falcon_stats_complete(efx); |
| 1762 | spin_unlock_bh(&efx->stats_lock); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1763 | } |
| 1764 | |
Ben Hutchings | 06629f0 | 2009-11-29 03:43:43 +0000 | [diff] [blame] | 1765 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
| 1766 | { |
| 1767 | falcon_board(efx)->type->set_id_led(efx, mode); |
| 1768 | } |
| 1769 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1770 | /************************************************************************** |
| 1771 | * |
Ben Hutchings | 89c758f | 2009-11-29 03:43:07 +0000 | [diff] [blame] | 1772 | * Wake on LAN |
| 1773 | * |
| 1774 | ************************************************************************** |
| 1775 | */ |
| 1776 | |
| 1777 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) |
| 1778 | { |
| 1779 | wol->supported = 0; |
| 1780 | wol->wolopts = 0; |
| 1781 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| 1782 | } |
| 1783 | |
| 1784 | static int falcon_set_wol(struct efx_nic *efx, u32 type) |
| 1785 | { |
| 1786 | if (type != 0) |
| 1787 | return -EINVAL; |
| 1788 | return 0; |
| 1789 | } |
| 1790 | |
| 1791 | /************************************************************************** |
| 1792 | * |
Ben Hutchings | 754c653 | 2010-02-03 09:31:57 +0000 | [diff] [blame] | 1793 | * Revision-dependent attributes used by efx.c and nic.c |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1794 | * |
| 1795 | ************************************************************************** |
| 1796 | */ |
| 1797 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1798 | struct efx_nic_type falcon_a1_nic_type = { |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1799 | .probe = falcon_probe_nic, |
| 1800 | .remove = falcon_remove_nic, |
| 1801 | .init = falcon_init_nic, |
| 1802 | .fini = efx_port_dummy_op_void, |
| 1803 | .monitor = falcon_monitor, |
| 1804 | .reset = falcon_reset_hw, |
| 1805 | .probe_port = falcon_probe_port, |
| 1806 | .remove_port = falcon_remove_port, |
| 1807 | .prepare_flush = falcon_prepare_flush, |
| 1808 | .update_stats = falcon_update_nic_stats, |
| 1809 | .start_stats = falcon_start_nic_stats, |
| 1810 | .stop_stats = falcon_stop_nic_stats, |
Ben Hutchings | 06629f0 | 2009-11-29 03:43:43 +0000 | [diff] [blame] | 1811 | .set_id_led = falcon_set_id_led, |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1812 | .push_irq_moderation = falcon_push_irq_moderation, |
| 1813 | .push_multicast_hash = falcon_push_multicast_hash, |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 1814 | .reconfigure_port = falcon_reconfigure_port, |
Ben Hutchings | 89c758f | 2009-11-29 03:43:07 +0000 | [diff] [blame] | 1815 | .get_wol = falcon_get_wol, |
| 1816 | .set_wol = falcon_set_wol, |
| 1817 | .resume_wol = efx_port_dummy_op_void, |
Ben Hutchings | 0aa3fba | 2009-11-29 03:43:33 +0000 | [diff] [blame] | 1818 | .test_nvram = falcon_test_nvram, |
Steve Hodgson | b895d73 | 2009-11-28 05:35:00 +0000 | [diff] [blame] | 1819 | .default_mac_ops = &falcon_xmac_operations, |
| 1820 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1821 | .revision = EFX_REV_FALCON_A1, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1822 | .mem_map_size = 0x20000, |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1823 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
| 1824 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, |
| 1825 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, |
| 1826 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, |
| 1827 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, |
Ben Hutchings | 6d51d30 | 2009-10-23 08:31:07 +0000 | [diff] [blame] | 1828 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1829 | .rx_buffer_padding = 0x24, |
| 1830 | .max_interrupt_mode = EFX_INT_MODE_MSI, |
| 1831 | .phys_addr_channels = 4, |
Ben Hutchings | 0228f5cdb0 | 2009-11-28 05:36:12 +0000 | [diff] [blame] | 1832 | .tx_dc_base = 0x130000, |
| 1833 | .rx_dc_base = 0x100000, |
Ben Hutchings | c383b53 | 2009-11-29 15:11:02 +0000 | [diff] [blame] | 1834 | .offload_features = NETIF_F_IP_CSUM, |
Ben Hutchings | eb9f674 | 2009-11-29 03:43:15 +0000 | [diff] [blame] | 1835 | .reset_world_flags = ETH_RESET_IRQ, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1836 | }; |
| 1837 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1838 | struct efx_nic_type falcon_b0_nic_type = { |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1839 | .probe = falcon_probe_nic, |
| 1840 | .remove = falcon_remove_nic, |
| 1841 | .init = falcon_init_nic, |
| 1842 | .fini = efx_port_dummy_op_void, |
| 1843 | .monitor = falcon_monitor, |
| 1844 | .reset = falcon_reset_hw, |
| 1845 | .probe_port = falcon_probe_port, |
| 1846 | .remove_port = falcon_remove_port, |
| 1847 | .prepare_flush = falcon_prepare_flush, |
| 1848 | .update_stats = falcon_update_nic_stats, |
| 1849 | .start_stats = falcon_start_nic_stats, |
| 1850 | .stop_stats = falcon_stop_nic_stats, |
Ben Hutchings | 06629f0 | 2009-11-29 03:43:43 +0000 | [diff] [blame] | 1851 | .set_id_led = falcon_set_id_led, |
Ben Hutchings | ef2b90e | 2009-11-29 03:42:31 +0000 | [diff] [blame] | 1852 | .push_irq_moderation = falcon_push_irq_moderation, |
| 1853 | .push_multicast_hash = falcon_push_multicast_hash, |
Ben Hutchings | d3245b2 | 2009-11-29 03:42:41 +0000 | [diff] [blame] | 1854 | .reconfigure_port = falcon_reconfigure_port, |
Ben Hutchings | 89c758f | 2009-11-29 03:43:07 +0000 | [diff] [blame] | 1855 | .get_wol = falcon_get_wol, |
| 1856 | .set_wol = falcon_set_wol, |
| 1857 | .resume_wol = efx_port_dummy_op_void, |
Ben Hutchings | 9bfc4bb | 2009-11-29 03:43:23 +0000 | [diff] [blame] | 1858 | .test_registers = falcon_b0_test_registers, |
Ben Hutchings | 0aa3fba | 2009-11-29 03:43:33 +0000 | [diff] [blame] | 1859 | .test_nvram = falcon_test_nvram, |
Steve Hodgson | b895d73 | 2009-11-28 05:35:00 +0000 | [diff] [blame] | 1860 | .default_mac_ops = &falcon_xmac_operations, |
| 1861 | |
Ben Hutchings | daeda63 | 2009-11-28 05:36:04 +0000 | [diff] [blame] | 1862 | .revision = EFX_REV_FALCON_B0, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1863 | /* Map everything up to and including the RSS indirection |
| 1864 | * table. Don't map MSI-X table, MSI-X PBA since Linux |
| 1865 | * requires that they not be mapped. */ |
Ben Hutchings | 3e6c453 | 2009-10-23 08:30:36 +0000 | [diff] [blame] | 1866 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
| 1867 | FR_BZ_RX_INDIRECTION_TBL_STEP * |
| 1868 | FR_BZ_RX_INDIRECTION_TBL_ROWS), |
| 1869 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, |
| 1870 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, |
| 1871 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, |
| 1872 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, |
| 1873 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, |
Ben Hutchings | 6d51d30 | 2009-10-23 08:31:07 +0000 | [diff] [blame] | 1874 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
Ben Hutchings | 39c9cf0 | 2010-06-23 11:31:28 +0000 | [diff] [blame] | 1875 | .rx_buffer_hash_size = 0x10, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1876 | .rx_buffer_padding = 0, |
| 1877 | .max_interrupt_mode = EFX_INT_MODE_MSIX, |
| 1878 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy |
| 1879 | * interrupt handler only supports 32 |
| 1880 | * channels */ |
Ben Hutchings | 0228f5cdb0 | 2009-11-28 05:36:12 +0000 | [diff] [blame] | 1881 | .tx_dc_base = 0x130000, |
| 1882 | .rx_dc_base = 0x100000, |
Ben Hutchings | 39c9cf0 | 2010-06-23 11:31:28 +0000 | [diff] [blame] | 1883 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH, |
Ben Hutchings | eb9f674 | 2009-11-29 03:43:15 +0000 | [diff] [blame] | 1884 | .reset_world_flags = ETH_RESET_IRQ, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1885 | }; |
| 1886 | |