blob: d13858818100e6f35cb328bab4394dc00885d712 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for x86 and x86_64 platform bugs.
3 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07004#include <linux/pci.h>
5#include <linux/irq.h>
6
Venki Pallipadid54bd572007-10-12 23:04:23 +02007#include <asm/hpet.h>
8
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
10
Andrew Mortona86f34b2007-05-02 19:27:04 +020011static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070012{
13 u8 config, rev;
Matthew Wilcox9585ca02008-02-10 23:18:15 -050014 u16 word;
Linus Torvalds1da177e2005-04-16 15:20:36 -070015
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
18 * based platforms.
19 * Disable SW irqbalance/affinity on those platforms.
20 */
Andrew Mortona86f34b2007-05-02 19:27:04 +020021 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
Linus Torvalds1da177e2005-04-16 15:20:36 -070022 if (rev > 0x9)
23 return;
24
Andrew Mortona86f34b2007-05-02 19:27:04 +020025 /* enable access to config space*/
26 pci_read_config_byte(dev, 0xf4, &config);
27 pci_write_config_byte(dev, 0xf4, config|0x2);
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Matthew Wilcox9585ca02008-02-10 23:18:15 -050029 /*
30 * read xTPR register. We may not have a pci_dev for device 8
31 * because it might be hidden until the above write.
32 */
33 pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
Linus Torvalds1da177e2005-04-16 15:20:36 -070034
35 if (!(word & (1 << 13))) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -070036 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
37 "disabling irq balancing and affinity\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070038#ifdef CONFIG_IRQBALANCE
39 irqbalance_disable("");
40#endif
41 noirqdebug_setup("");
42#ifdef CONFIG_PROC_FS
43 no_irq_affinity = 1;
44#endif
45 }
46
Andrew Mortona86f34b2007-05-02 19:27:04 +020047 /* put back the original value for config space*/
Alan Coxda9bb1d2006-01-18 17:44:13 -080048 if (!(config & 0x2))
Andrew Mortona86f34b2007-05-02 19:27:04 +020049 pci_write_config_byte(dev, 0xf4, config);
Linus Torvalds1da177e2005-04-16 15:20:36 -070050}
Thomas Gleixner76492232007-10-19 20:35:02 +020051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
52 quirk_intel_irqbalance);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
54 quirk_intel_irqbalance);
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
56 quirk_intel_irqbalance);
Linus Torvalds1da177e2005-04-16 15:20:36 -070057#endif
Venki Pallipadid54bd572007-10-12 23:04:23 +020058
59#if defined(CONFIG_HPET_TIMER)
60unsigned long force_hpet_address;
61
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +020062static enum {
63 NONE_FORCE_HPET_RESUME,
64 OLD_ICH_FORCE_HPET_RESUME,
Udo A. Steinbergb1968842007-10-19 20:35:02 +020065 ICH_FORCE_HPET_RESUME,
Carlos Corbachod79a5f82007-10-19 18:51:27 +010066 VT8237_FORCE_HPET_RESUME,
67 NVIDIA_FORCE_HPET_RESUME,
Andreas Herrmanne8aa4662008-05-09 11:49:11 +020068 ATI_FORCE_HPET_RESUME,
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +020069} force_hpet_resume_type;
70
Venki Pallipadid54bd572007-10-12 23:04:23 +020071static void __iomem *rcba_base;
72
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +020073static void ich_force_hpet_resume(void)
Venki Pallipadid54bd572007-10-12 23:04:23 +020074{
75 u32 val;
76
77 if (!force_hpet_address)
78 return;
79
80 if (rcba_base == NULL)
81 BUG();
82
83 /* read the Function Disable register, dword mode only */
84 val = readl(rcba_base + 0x3404);
85 if (!(val & 0x80)) {
86 /* HPET disabled in HPTC. Trying to enable */
87 writel(val | 0x80, rcba_base + 0x3404);
88 }
89
90 val = readl(rcba_base + 0x3404);
91 if (!(val & 0x80))
92 BUG();
93 else
94 printk(KERN_DEBUG "Force enabled HPET at resume\n");
95
96 return;
97}
98
99static void ich_force_enable_hpet(struct pci_dev *dev)
100{
101 u32 val;
102 u32 uninitialized_var(rcba);
103 int err = 0;
104
105 if (hpet_address || force_hpet_address)
106 return;
107
108 pci_read_config_dword(dev, 0xF0, &rcba);
109 rcba &= 0xFFFFC000;
110 if (rcba == 0) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700111 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
112 "cannot force enable HPET\n");
Venki Pallipadid54bd572007-10-12 23:04:23 +0200113 return;
114 }
115
116 /* use bits 31:14, 16 kB aligned */
117 rcba_base = ioremap_nocache(rcba, 0x4000);
118 if (rcba_base == NULL) {
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700119 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
120 "cannot force enable HPET\n");
Venki Pallipadid54bd572007-10-12 23:04:23 +0200121 return;
122 }
123
124 /* read the Function Disable register, dword mode only */
125 val = readl(rcba_base + 0x3404);
126
127 if (val & 0x80) {
128 /* HPET is enabled in HPTC. Just not reported by BIOS */
129 val = val & 0x3;
130 force_hpet_address = 0xFED00000 | (val << 12);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700131 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
132 "0x%lx\n", force_hpet_address);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200133 iounmap(rcba_base);
134 return;
135 }
136
137 /* HPET disabled in HPTC. Trying to enable */
138 writel(val | 0x80, rcba_base + 0x3404);
139
140 val = readl(rcba_base + 0x3404);
141 if (!(val & 0x80)) {
142 err = 1;
143 } else {
144 val = val & 0x3;
145 force_hpet_address = 0xFED00000 | (val << 12);
146 }
147
148 if (err) {
149 force_hpet_address = 0;
150 iounmap(rcba_base);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700151 dev_printk(KERN_DEBUG, &dev->dev,
152 "Failed to force enable HPET\n");
Venki Pallipadid54bd572007-10-12 23:04:23 +0200153 } else {
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200154 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700155 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
156 "0x%lx\n", force_hpet_address);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200157 }
158}
159
160DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
Thomas Gleixner76492232007-10-19 20:35:02 +0200161 ich_force_enable_hpet);
Krzysztof Oledzki74e411c2008-06-04 03:40:17 +0200162DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
163 ich_force_enable_hpet);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200164DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
Thomas Gleixner76492232007-10-19 20:35:02 +0200165 ich_force_enable_hpet);
Venki Pallipadied6fb172007-10-12 23:04:24 +0200166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
Thomas Gleixner76492232007-10-19 20:35:02 +0200167 ich_force_enable_hpet);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200168DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
Thomas Gleixner76492232007-10-19 20:35:02 +0200169 ich_force_enable_hpet);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
Thomas Gleixner76492232007-10-19 20:35:02 +0200171 ich_force_enable_hpet);
Venki Pallipadid54bd572007-10-12 23:04:23 +0200172DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
Thomas Gleixner76492232007-10-19 20:35:02 +0200173 ich_force_enable_hpet);
Alistair John Strachandff244a2008-01-30 13:33:39 +0100174DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
175 ich_force_enable_hpet);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200176
177
178static struct pci_dev *cached_dev;
179
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200180static void hpet_print_force_info(void)
181{
182 printk(KERN_INFO "HPET not enabled in BIOS. "
183 "You might try hpet=force boot option\n");
184}
185
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200186static void old_ich_force_hpet_resume(void)
187{
188 u32 val;
189 u32 uninitialized_var(gen_cntl);
190
191 if (!force_hpet_address || !cached_dev)
192 return;
193
194 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
195 gen_cntl &= (~(0x7 << 15));
196 gen_cntl |= (0x4 << 15);
197
198 pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
199 pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
200 val = gen_cntl >> 15;
201 val &= 0x7;
202 if (val == 0x4)
203 printk(KERN_DEBUG "Force enabled HPET at resume\n");
204 else
205 BUG();
206}
207
208static void old_ich_force_enable_hpet(struct pci_dev *dev)
209{
210 u32 val;
211 u32 uninitialized_var(gen_cntl);
212
213 if (hpet_address || force_hpet_address)
214 return;
215
216 pci_read_config_dword(dev, 0xD0, &gen_cntl);
217 /*
218 * Bit 17 is HPET enable bit.
219 * Bit 16:15 control the HPET base address.
220 */
221 val = gen_cntl >> 15;
222 val &= 0x7;
223 if (val & 0x4) {
224 val &= 0x3;
225 force_hpet_address = 0xFED00000 | (val << 12);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700226 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
227 force_hpet_address);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200228 return;
229 }
230
231 /*
232 * HPET is disabled. Trying enabling at FED00000 and check
233 * whether it sticks
234 */
235 gen_cntl &= (~(0x7 << 15));
236 gen_cntl |= (0x4 << 15);
237 pci_write_config_dword(dev, 0xD0, gen_cntl);
238
239 pci_read_config_dword(dev, 0xD0, &gen_cntl);
240
241 val = gen_cntl >> 15;
242 val &= 0x7;
243 if (val & 0x4) {
244 /* HPET is enabled in HPTC. Just not reported by BIOS */
245 val &= 0x3;
246 force_hpet_address = 0xFED00000 | (val << 12);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700247 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
248 "0x%lx\n", force_hpet_address);
Venki Pallipadi32a2da62007-10-12 23:04:24 +0200249 cached_dev = dev;
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200250 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
251 return;
252 }
253
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700254 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200255}
256
Udo A. Steinberg158ad322007-10-19 20:35:02 +0200257/*
258 * Undocumented chipset features. Make sure that the user enforced
259 * this.
260 */
261static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
262{
263 if (hpet_force_user)
264 old_ich_force_enable_hpet(dev);
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200265 else
266 hpet_print_force_info();
Udo A. Steinberg158ad322007-10-19 20:35:02 +0200267}
268
Joe Buehler4c2a9972008-06-09 08:55:20 -0400269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
270 old_ich_force_enable_hpet_user);
Udo A. Steinberg158ad322007-10-19 20:35:02 +0200271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
272 old_ich_force_enable_hpet_user);
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
274 old_ich_force_enable_hpet_user);
275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
276 old_ich_force_enable_hpet_user);
277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
278 old_ich_force_enable_hpet_user);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
Thomas Gleixner76492232007-10-19 20:35:02 +0200280 old_ich_force_enable_hpet);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
Thomas Gleixner76492232007-10-19 20:35:02 +0200282 old_ich_force_enable_hpet);
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200283
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200284
285static void vt8237_force_hpet_resume(void)
286{
287 u32 val;
288
289 if (!force_hpet_address || !cached_dev)
290 return;
291
292 val = 0xfed00000 | 0x80;
293 pci_write_config_dword(cached_dev, 0x68, val);
294
295 pci_read_config_dword(cached_dev, 0x68, &val);
296 if (val & 0x80)
297 printk(KERN_DEBUG "Force enabled HPET at resume\n");
298 else
299 BUG();
300}
301
302static void vt8237_force_enable_hpet(struct pci_dev *dev)
303{
304 u32 uninitialized_var(val);
305
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200306 if (hpet_address || force_hpet_address)
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200307 return;
308
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200309 if (!hpet_force_user) {
310 hpet_print_force_info();
311 return;
312 }
313
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200314 pci_read_config_dword(dev, 0x68, &val);
315 /*
316 * Bit 7 is HPET enable bit.
317 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
318 */
319 if (val & 0x80) {
320 force_hpet_address = (val & ~0x3ff);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700321 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
322 force_hpet_address);
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200323 return;
324 }
325
326 /*
327 * HPET is disabled. Trying enabling at FED00000 and check
328 * whether it sticks
329 */
330 val = 0xfed00000 | 0x80;
331 pci_write_config_dword(dev, 0x68, val);
332
333 pci_read_config_dword(dev, 0x68, &val);
334 if (val & 0x80) {
335 force_hpet_address = (val & ~0x3ff);
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700336 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
337 "0x%lx\n", force_hpet_address);
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200338 cached_dev = dev;
339 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
340 return;
341 }
342
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700343 dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200344}
345
346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
347 vt8237_force_enable_hpet);
348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
349 vt8237_force_enable_hpet);
350
Andreas Herrmanne8aa4662008-05-09 11:49:11 +0200351static void ati_force_hpet_resume(void)
352{
353 pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
354 printk(KERN_DEBUG "Force enabled HPET at resume\n");
355}
356
357static void ati_force_enable_hpet(struct pci_dev *dev)
358{
359 u32 uninitialized_var(val);
360
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200361 if (hpet_address || force_hpet_address)
Andreas Herrmanne8aa4662008-05-09 11:49:11 +0200362 return;
363
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200364 if (!hpet_force_user) {
365 hpet_print_force_info();
366 return;
367 }
368
Andreas Herrmanne8aa4662008-05-09 11:49:11 +0200369 pci_write_config_dword(dev, 0x14, 0xfed00000);
370 pci_read_config_dword(dev, 0x14, &val);
371 force_hpet_address = val;
372 force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
373 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
374 force_hpet_address);
375 cached_dev = dev;
376 return;
377}
378DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
379 ati_force_enable_hpet);
380
Carlos Corbachod79a5f82007-10-19 18:51:27 +0100381/*
382 * Undocumented chipset feature taken from LinuxBIOS.
383 */
384static void nvidia_force_hpet_resume(void)
385{
386 pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
387 printk(KERN_DEBUG "Force enabled HPET at resume\n");
388}
389
390static void nvidia_force_enable_hpet(struct pci_dev *dev)
391{
392 u32 uninitialized_var(val);
393
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200394 if (hpet_address || force_hpet_address)
Carlos Corbachod79a5f82007-10-19 18:51:27 +0100395 return;
396
Thomas Gleixner7c4728f2008-05-10 21:42:14 +0200397 if (!hpet_force_user) {
398 hpet_print_force_info();
399 return;
400 }
401
Carlos Corbachod79a5f82007-10-19 18:51:27 +0100402 pci_write_config_dword(dev, 0x44, 0xfed00001);
403 pci_read_config_dword(dev, 0x44, &val);
404 force_hpet_address = val & 0xfffffffe;
405 force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
bjorn.helgaas@hp.com9ed88552007-12-17 14:09:40 -0700406 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
Carlos Corbachod79a5f82007-10-19 18:51:27 +0100407 force_hpet_address);
408 cached_dev = dev;
409 return;
410}
411
412/* ISA Bridges */
413DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
414 nvidia_force_enable_hpet);
415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
416 nvidia_force_enable_hpet);
Udo A. Steinbergb1968842007-10-19 20:35:02 +0200417
Carlos Corbacho1b82ba62007-10-19 19:34:15 +0100418/* LPC bridges */
Zbigniew Luszpinski96bcf452008-03-19 15:51:50 +0100419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
420 nvidia_force_enable_hpet);
Carlos Corbacho1b82ba62007-10-19 19:34:15 +0100421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
422 nvidia_force_enable_hpet);
423DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
424 nvidia_force_enable_hpet);
425DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
426 nvidia_force_enable_hpet);
427DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
428 nvidia_force_enable_hpet);
429DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
430 nvidia_force_enable_hpet);
431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
432 nvidia_force_enable_hpet);
433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
434 nvidia_force_enable_hpet);
435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
436 nvidia_force_enable_hpet);
437
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200438void force_hpet_resume(void)
439{
440 switch (force_hpet_resume_type) {
Harvey Harrison4a5a77d2008-02-06 22:39:44 +0100441 case ICH_FORCE_HPET_RESUME:
442 ich_force_hpet_resume();
443 return;
444 case OLD_ICH_FORCE_HPET_RESUME:
445 old_ich_force_hpet_resume();
446 return;
447 case VT8237_FORCE_HPET_RESUME:
448 vt8237_force_hpet_resume();
449 return;
450 case NVIDIA_FORCE_HPET_RESUME:
451 nvidia_force_hpet_resume();
452 return;
Andreas Herrmanne8aa4662008-05-09 11:49:11 +0200453 case ATI_FORCE_HPET_RESUME:
454 ati_force_hpet_resume();
455 return;
Harvey Harrison4a5a77d2008-02-06 22:39:44 +0100456 default:
Venki Pallipadibfe0c1c2007-10-12 23:04:24 +0200457 break;
458 }
459}
460
Venki Pallipadid54bd572007-10-12 23:04:23 +0200461#endif