Marc St-Jean | 35832e2 | 2007-06-14 15:54:47 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Defines for the address space, registers and register configuration |
| 3 | * (bit masks, access macros etc) for the PMC-Sierra line of MSP products. |
| 4 | * This file contains addess maps for all the devices in the line of |
| 5 | * products but only has register definitions and configuration masks for |
| 6 | * registers which aren't definitely associated with any device. Things |
| 7 | * like clock settings, reset access, the ELB etc. Individual device |
| 8 | * drivers will reference the appropriate XXX_BASE value defined here |
| 9 | * and have individual registers offset from that. |
| 10 | * |
| 11 | * Copyright (C) 2005-2007 PMC-Sierra, Inc. All rights reserved. |
| 12 | * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com |
| 13 | * |
| 14 | * ######################################################################## |
| 15 | * |
| 16 | * This program is free software; you can distribute it and/or modify it |
| 17 | * under the terms of the GNU General Public License (Version 2) as |
| 18 | * published by the Free Software Foundation. |
| 19 | * |
| 20 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 21 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 22 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 23 | * for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License along |
| 26 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 27 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
| 28 | * |
| 29 | * ######################################################################## |
| 30 | */ |
| 31 | |
| 32 | #include <asm/addrspace.h> |
| 33 | #include <linux/types.h> |
| 34 | |
| 35 | #ifndef _ASM_MSP_REGS_H |
| 36 | #define _ASM_MSP_REGS_H |
| 37 | |
| 38 | /* |
| 39 | ######################################################################## |
| 40 | # Address space and device base definitions # |
| 41 | ######################################################################## |
| 42 | */ |
| 43 | |
| 44 | /* |
| 45 | *************************************************************************** |
| 46 | * System Logic and Peripherals (ELB, UART0, etc) device address space * |
| 47 | *************************************************************************** |
| 48 | */ |
| 49 | #define MSP_SLP_BASE 0x1c000000 |
| 50 | /* System Logic and Peripherals */ |
| 51 | #define MSP_RST_BASE (MSP_SLP_BASE + 0x10) |
| 52 | /* System reset register base */ |
| 53 | #define MSP_RST_SIZE 0x0C /* System reset register space */ |
| 54 | |
| 55 | #define MSP_WTIMER_BASE (MSP_SLP_BASE + 0x04C) |
| 56 | /* watchdog timer base */ |
| 57 | #define MSP_ITIMER_BASE (MSP_SLP_BASE + 0x054) |
| 58 | /* internal timer base */ |
| 59 | #define MSP_UART0_BASE (MSP_SLP_BASE + 0x100) |
| 60 | /* UART0 controller base */ |
| 61 | #define MSP_BCPY_CTRL_BASE (MSP_SLP_BASE + 0x120) |
| 62 | /* Block Copy controller base */ |
| 63 | #define MSP_BCPY_DESC_BASE (MSP_SLP_BASE + 0x160) |
| 64 | /* Block Copy descriptor base */ |
| 65 | |
| 66 | /* |
| 67 | *************************************************************************** |
| 68 | * PCI address space * |
| 69 | *************************************************************************** |
| 70 | */ |
| 71 | #define MSP_PCI_BASE 0x19000000 |
| 72 | |
| 73 | /* |
| 74 | *************************************************************************** |
| 75 | * MSbus device address space * |
| 76 | *************************************************************************** |
| 77 | */ |
| 78 | #define MSP_MSB_BASE 0x18000000 |
| 79 | /* MSbus address start */ |
| 80 | #define MSP_PER_BASE (MSP_MSB_BASE + 0x400000) |
| 81 | /* Peripheral device registers */ |
| 82 | #define MSP_MAC0_BASE (MSP_MSB_BASE + 0x600000) |
| 83 | /* MAC A device registers */ |
| 84 | #define MSP_MAC1_BASE (MSP_MSB_BASE + 0x700000) |
| 85 | /* MAC B device registers */ |
| 86 | #define MSP_MAC_SIZE 0xE0 /* MAC register space */ |
| 87 | |
| 88 | #define MSP_SEC_BASE (MSP_MSB_BASE + 0x800000) |
| 89 | /* Security Engine registers */ |
| 90 | #define MSP_MAC2_BASE (MSP_MSB_BASE + 0x900000) |
| 91 | /* MAC C device registers */ |
| 92 | #define MSP_ADSL2_BASE (MSP_MSB_BASE + 0xA80000) |
| 93 | /* ADSL2 device registers */ |
| 94 | #define MSP_USB_BASE (MSP_MSB_BASE + 0xB40000) |
| 95 | /* USB device registers */ |
| 96 | #define MSP_USB_BASE_START (MSP_MSB_BASE + 0xB40100) |
| 97 | /* USB device registers */ |
| 98 | #define MSP_USB_BASE_END (MSP_MSB_BASE + 0xB401FF) |
| 99 | /* USB device registers */ |
| 100 | #define MSP_CPUIF_BASE (MSP_MSB_BASE + 0xC00000) |
| 101 | /* CPU interface registers */ |
| 102 | |
| 103 | /* Devices within the MSbus peripheral block */ |
| 104 | #define MSP_UART1_BASE (MSP_PER_BASE + 0x030) |
| 105 | /* UART1 controller base */ |
| 106 | #define MSP_SPI_BASE (MSP_PER_BASE + 0x058) |
| 107 | /* SPI/MPI control registers */ |
| 108 | #define MSP_TWI_BASE (MSP_PER_BASE + 0x090) |
| 109 | /* Two-wire control registers */ |
| 110 | #define MSP_PTIMER_BASE (MSP_PER_BASE + 0x0F0) |
| 111 | /* Programmable timer control */ |
| 112 | |
| 113 | /* |
| 114 | *************************************************************************** |
| 115 | * Physical Memory configuration address space * |
| 116 | *************************************************************************** |
| 117 | */ |
| 118 | #define MSP_MEM_CFG_BASE 0x17f00000 |
| 119 | |
| 120 | #define MSP_MEM_INDIRECT_CTL_10 0x10 |
| 121 | |
| 122 | /* |
| 123 | * Notes: |
| 124 | * 1) The SPI registers are split into two blocks, one offset from the |
| 125 | * MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by |
| 126 | * 0x68. The SPI driver definitions for the register must be aware |
| 127 | * of this. |
| 128 | * 2) The block copy engine register are divided into two regions, one |
| 129 | * for the control/configuration of the engine proper and one for the |
| 130 | * values of the descriptors used in the copy process. These have |
| 131 | * different base defines (CTRL_BASE vs DESC_BASE) |
| 132 | * 3) These constants are for physical addresses which means that they |
| 133 | * work correctly with "ioremap" and friends. This means that device |
| 134 | * drivers will need to remap these addresses using ioremap and perhaps |
| 135 | * the readw/writew macros. Or they could use the regptr() macro |
| 136 | * defined below, but the readw/writew calls are the correct thing. |
| 137 | * 4) The UARTs have an additional status register offset from the base |
| 138 | * address. This register isn't used in the standard 8250 driver but |
| 139 | * may be used in other software. Consult the hardware datasheet for |
| 140 | * offset details. |
| 141 | * 5) For some unknown reason the security engine (MSP_SEC_BASE) registers |
| 142 | * start at an offset of 0x84 from the base address but the block of |
| 143 | * registers before this is reserved for the security engine. The |
| 144 | * driver will have to be aware of this but it makes the register |
| 145 | * definitions line up better with the documentation. |
| 146 | */ |
| 147 | |
| 148 | /* |
| 149 | ######################################################################## |
| 150 | # System register definitions. Not associated with a specific device # |
| 151 | ######################################################################## |
| 152 | */ |
| 153 | |
| 154 | /* |
| 155 | * This macro maps the physical register number into uncached space |
| 156 | * and (for C code) casts it into a u32 pointer so it can be dereferenced |
| 157 | * Normally these would be accessed with ioremap and readX/writeX, but |
| 158 | * these are convenient for a lot of internal kernel code. |
| 159 | */ |
| 160 | #ifdef __ASSEMBLER__ |
| 161 | #define regptr(addr) (KSEG1ADDR(addr)) |
| 162 | #else |
| 163 | #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr))) |
| 164 | #endif |
| 165 | |
| 166 | /* |
| 167 | *************************************************************************** |
| 168 | * System Logic and Peripherals (RESET, ELB, etc) registers * |
| 169 | *************************************************************************** |
| 170 | */ |
| 171 | |
| 172 | /* System Control register definitions */ |
| 173 | #define DEV_ID_REG regptr(MSP_SLP_BASE + 0x00) |
| 174 | /* Device-ID RO */ |
| 175 | #define FWR_ID_REG regptr(MSP_SLP_BASE + 0x04) |
| 176 | /* Firmware-ID Register RW */ |
| 177 | #define SYS_ID_REG0 regptr(MSP_SLP_BASE + 0x08) |
| 178 | /* System-ID Register-0 RW */ |
| 179 | #define SYS_ID_REG1 regptr(MSP_SLP_BASE + 0x0C) |
| 180 | /* System-ID Register-1 RW */ |
| 181 | |
| 182 | /* System Reset register definitions */ |
| 183 | #define RST_STS_REG regptr(MSP_SLP_BASE + 0x10) |
| 184 | /* System Reset Status RO */ |
| 185 | #define RST_SET_REG regptr(MSP_SLP_BASE + 0x14) |
| 186 | /* System Set Reset WO */ |
| 187 | #define RST_CLR_REG regptr(MSP_SLP_BASE + 0x18) |
| 188 | /* System Clear Reset WO */ |
| 189 | |
| 190 | /* System Clock Registers */ |
| 191 | #define PCI_SLP_REG regptr(MSP_SLP_BASE + 0x1C) |
| 192 | /* PCI clock generator RW */ |
| 193 | #define URT_SLP_REG regptr(MSP_SLP_BASE + 0x20) |
| 194 | /* UART clock generator RW */ |
| 195 | /* reserved (MSP_SLP_BASE + 0x24) */ |
| 196 | /* reserved (MSP_SLP_BASE + 0x28) */ |
| 197 | #define PLL1_SLP_REG regptr(MSP_SLP_BASE + 0x2C) |
| 198 | /* PLL1 clock generator RW */ |
| 199 | #define PLL0_SLP_REG regptr(MSP_SLP_BASE + 0x30) |
| 200 | /* PLL0 clock generator RW */ |
| 201 | #define MIPS_SLP_REG regptr(MSP_SLP_BASE + 0x34) |
| 202 | /* MIPS clock generator RW */ |
| 203 | #define VE_SLP_REG regptr(MSP_SLP_BASE + 0x38) |
| 204 | /* Voice Eng clock generator RW */ |
| 205 | /* reserved (MSP_SLP_BASE + 0x3C) */ |
| 206 | #define MSB_SLP_REG regptr(MSP_SLP_BASE + 0x40) |
| 207 | /* MS-Bus clock generator RW */ |
| 208 | #define SMAC_SLP_REG regptr(MSP_SLP_BASE + 0x44) |
| 209 | /* Sec & MAC clock generator RW */ |
| 210 | #define PERF_SLP_REG regptr(MSP_SLP_BASE + 0x48) |
| 211 | /* Per & TDM clock generator RW */ |
| 212 | |
| 213 | /* Interrupt Controller Registers */ |
| 214 | #define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70) |
| 215 | /* Interrupt status register RW */ |
| 216 | #define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74) |
| 217 | /* Interrupt enable/mask RW */ |
| 218 | #define SE_MBOX_REG regptr(MSP_SLP_BASE + 0x78) |
| 219 | /* Security Engine mailbox RW */ |
| 220 | #define VE_MBOX_REG regptr(MSP_SLP_BASE + 0x7C) |
| 221 | /* Voice Engine mailbox RW */ |
| 222 | |
| 223 | /* ELB Controller Registers */ |
| 224 | #define CS0_CNFG_REG regptr(MSP_SLP_BASE + 0x80) |
| 225 | /* ELB CS0 Configuration Reg */ |
| 226 | #define CS0_ADDR_REG regptr(MSP_SLP_BASE + 0x84) |
| 227 | /* ELB CS0 Base Address Reg */ |
| 228 | #define CS0_MASK_REG regptr(MSP_SLP_BASE + 0x88) |
| 229 | /* ELB CS0 Mask Register */ |
| 230 | #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C) |
| 231 | /* ELB CS0 access register */ |
| 232 | |
| 233 | #define CS1_CNFG_REG regptr(MSP_SLP_BASE + 0x90) |
| 234 | /* ELB CS1 Configuration Reg */ |
| 235 | #define CS1_ADDR_REG regptr(MSP_SLP_BASE + 0x94) |
| 236 | /* ELB CS1 Base Address Reg */ |
| 237 | #define CS1_MASK_REG regptr(MSP_SLP_BASE + 0x98) |
| 238 | /* ELB CS1 Mask Register */ |
| 239 | #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C) |
| 240 | /* ELB CS1 access register */ |
| 241 | |
| 242 | #define CS2_CNFG_REG regptr(MSP_SLP_BASE + 0xA0) |
| 243 | /* ELB CS2 Configuration Reg */ |
| 244 | #define CS2_ADDR_REG regptr(MSP_SLP_BASE + 0xA4) |
| 245 | /* ELB CS2 Base Address Reg */ |
| 246 | #define CS2_MASK_REG regptr(MSP_SLP_BASE + 0xA8) |
| 247 | /* ELB CS2 Mask Register */ |
| 248 | #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC) |
| 249 | /* ELB CS2 access register */ |
| 250 | |
| 251 | #define CS3_CNFG_REG regptr(MSP_SLP_BASE + 0xB0) |
| 252 | /* ELB CS3 Configuration Reg */ |
| 253 | #define CS3_ADDR_REG regptr(MSP_SLP_BASE + 0xB4) |
| 254 | /* ELB CS3 Base Address Reg */ |
| 255 | #define CS3_MASK_REG regptr(MSP_SLP_BASE + 0xB8) |
| 256 | /* ELB CS3 Mask Register */ |
| 257 | #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC) |
| 258 | /* ELB CS3 access register */ |
| 259 | |
| 260 | #define CS4_CNFG_REG regptr(MSP_SLP_BASE + 0xC0) |
| 261 | /* ELB CS4 Configuration Reg */ |
| 262 | #define CS4_ADDR_REG regptr(MSP_SLP_BASE + 0xC4) |
| 263 | /* ELB CS4 Base Address Reg */ |
| 264 | #define CS4_MASK_REG regptr(MSP_SLP_BASE + 0xC8) |
| 265 | /* ELB CS4 Mask Register */ |
| 266 | #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC) |
| 267 | /* ELB CS4 access register */ |
| 268 | |
| 269 | #define CS5_CNFG_REG regptr(MSP_SLP_BASE + 0xD0) |
| 270 | /* ELB CS5 Configuration Reg */ |
| 271 | #define CS5_ADDR_REG regptr(MSP_SLP_BASE + 0xD4) |
| 272 | /* ELB CS5 Base Address Reg */ |
| 273 | #define CS5_MASK_REG regptr(MSP_SLP_BASE + 0xD8) |
| 274 | /* ELB CS5 Mask Register */ |
| 275 | #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC) |
| 276 | /* ELB CS5 access register */ |
| 277 | |
| 278 | /* reserved 0xE0 - 0xE8 */ |
| 279 | #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC) |
| 280 | /* ELB single PC card detect */ |
| 281 | |
| 282 | /* reserved 0xF0 - 0xF8 */ |
| 283 | #define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC) |
| 284 | /* SDRAM read/ELB timing Reg */ |
| 285 | |
| 286 | /* Extended UART status registers */ |
| 287 | #define UART0_STATUS_REG regptr(MSP_UART0_BASE + 0x0c0) |
| 288 | /* UART Status Register 0 */ |
| 289 | #define UART1_STATUS_REG regptr(MSP_UART1_BASE + 0x170) |
| 290 | /* UART Status Register 1 */ |
| 291 | |
| 292 | /* Performance monitoring registers */ |
| 293 | #define PERF_MON_CTRL_REG regptr(MSP_SLP_BASE + 0x140) |
| 294 | /* Performance monitor control */ |
| 295 | #define PERF_MON_CLR_REG regptr(MSP_SLP_BASE + 0x144) |
| 296 | /* Performance monitor clear */ |
| 297 | #define PERF_MON_CNTH_REG regptr(MSP_SLP_BASE + 0x148) |
| 298 | /* Perf monitor counter high */ |
| 299 | #define PERF_MON_CNTL_REG regptr(MSP_SLP_BASE + 0x14C) |
| 300 | /* Perf monitor counter low */ |
| 301 | |
| 302 | /* System control registers */ |
| 303 | #define SYS_CTRL_REG regptr(MSP_SLP_BASE + 0x150) |
| 304 | /* System control register */ |
| 305 | #define SYS_ERR1_REG regptr(MSP_SLP_BASE + 0x154) |
| 306 | /* System Error status 1 */ |
| 307 | #define SYS_ERR2_REG regptr(MSP_SLP_BASE + 0x158) |
| 308 | /* System Error status 2 */ |
| 309 | #define SYS_INT_CFG_REG regptr(MSP_SLP_BASE + 0x15C) |
| 310 | /* System Interrupt config */ |
| 311 | |
| 312 | /* Voice Engine Memory configuration */ |
| 313 | #define VE_MEM_REG regptr(MSP_SLP_BASE + 0x17C) |
| 314 | /* Voice engine memory config */ |
| 315 | |
| 316 | /* CPU/SLP Error Status registers */ |
| 317 | #define CPU_ERR1_REG regptr(MSP_SLP_BASE + 0x180) |
| 318 | /* CPU/SLP Error status 1 */ |
| 319 | #define CPU_ERR2_REG regptr(MSP_SLP_BASE + 0x184) |
| 320 | /* CPU/SLP Error status 1 */ |
| 321 | |
| 322 | #define EXTENDED_GPIO_REG regptr(MSP_SLP_BASE + 0x188) |
| 323 | /* Extended GPIO register */ |
| 324 | |
| 325 | /* System Error registers */ |
| 326 | #define SLP_ERR_STS_REG regptr(MSP_SLP_BASE + 0x190) |
| 327 | /* Int status for SLP errors */ |
| 328 | #define SLP_ERR_MSK_REG regptr(MSP_SLP_BASE + 0x194) |
| 329 | /* Int mask for SLP errors */ |
| 330 | #define SLP_ELB_ERST_REG regptr(MSP_SLP_BASE + 0x198) |
| 331 | /* External ELB reset */ |
| 332 | #define SLP_BOOT_STS_REG regptr(MSP_SLP_BASE + 0x19C) |
| 333 | /* Boot Status */ |
| 334 | |
| 335 | /* Extended ELB addressing */ |
| 336 | #define CS0_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A0) |
| 337 | /* CS0 Extended address */ |
| 338 | #define CS1_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A4) |
| 339 | /* CS1 Extended address */ |
| 340 | #define CS2_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1A8) |
| 341 | /* CS2 Extended address */ |
| 342 | #define CS3_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1AC) |
| 343 | /* CS3 Extended address */ |
| 344 | /* reserved 0x1B0 */ |
| 345 | #define CS5_EXT_ADDR_REG regptr(MSP_SLP_BASE + 0x1B4) |
| 346 | /* CS5 Extended address */ |
| 347 | |
| 348 | /* PLL Adjustment registers */ |
| 349 | #define PLL_LOCK_REG regptr(MSP_SLP_BASE + 0x200) |
| 350 | /* PLL0 lock status */ |
| 351 | #define PLL_ARST_REG regptr(MSP_SLP_BASE + 0x204) |
| 352 | /* PLL Analog reset status */ |
| 353 | #define PLL0_ADJ_REG regptr(MSP_SLP_BASE + 0x208) |
| 354 | /* PLL0 Adjustment value */ |
| 355 | #define PLL1_ADJ_REG regptr(MSP_SLP_BASE + 0x20C) |
| 356 | /* PLL1 Adjustment value */ |
| 357 | |
| 358 | /* |
| 359 | *************************************************************************** |
| 360 | * Peripheral Register definitions * |
| 361 | *************************************************************************** |
| 362 | */ |
| 363 | |
| 364 | /* Peripheral status */ |
| 365 | #define PER_CTRL_REG regptr(MSP_PER_BASE + 0x50) |
| 366 | /* Peripheral control register */ |
| 367 | #define PER_STS_REG regptr(MSP_PER_BASE + 0x54) |
| 368 | /* Peripheral status register */ |
| 369 | |
| 370 | /* SPI/MPI Registers */ |
| 371 | #define SMPI_TX_SZ_REG regptr(MSP_PER_BASE + 0x58) |
| 372 | /* SPI/MPI Tx Size register */ |
| 373 | #define SMPI_RX_SZ_REG regptr(MSP_PER_BASE + 0x5C) |
| 374 | /* SPI/MPI Rx Size register */ |
| 375 | #define SMPI_CTL_REG regptr(MSP_PER_BASE + 0x60) |
| 376 | /* SPI/MPI Control register */ |
| 377 | #define SMPI_MS_REG regptr(MSP_PER_BASE + 0x64) |
| 378 | /* SPI/MPI Chip Select reg */ |
| 379 | #define SMPI_CORE_DATA_REG regptr(MSP_PER_BASE + 0xC0) |
| 380 | /* SPI/MPI Core Data reg */ |
| 381 | #define SMPI_CORE_CTRL_REG regptr(MSP_PER_BASE + 0xC4) |
| 382 | /* SPI/MPI Core Control reg */ |
| 383 | #define SMPI_CORE_STAT_REG regptr(MSP_PER_BASE + 0xC8) |
| 384 | /* SPI/MPI Core Status reg */ |
| 385 | #define SMPI_CORE_SSEL_REG regptr(MSP_PER_BASE + 0xCC) |
| 386 | /* SPI/MPI Core Ssel reg */ |
| 387 | #define SMPI_FIFO_REG regptr(MSP_PER_BASE + 0xD0) |
| 388 | /* SPI/MPI Data FIFO reg */ |
| 389 | |
| 390 | /* Peripheral Block Error Registers */ |
| 391 | #define PER_ERR_STS_REG regptr(MSP_PER_BASE + 0x70) |
| 392 | /* Error Bit Status Register */ |
| 393 | #define PER_ERR_MSK_REG regptr(MSP_PER_BASE + 0x74) |
| 394 | /* Error Bit Mask Register */ |
| 395 | #define PER_HDR1_REG regptr(MSP_PER_BASE + 0x78) |
| 396 | /* Error Header 1 Register */ |
| 397 | #define PER_HDR2_REG regptr(MSP_PER_BASE + 0x7C) |
| 398 | /* Error Header 2 Register */ |
| 399 | |
| 400 | /* Peripheral Block Interrupt Registers */ |
| 401 | #define PER_INT_STS_REG regptr(MSP_PER_BASE + 0x80) |
| 402 | /* Interrupt status register */ |
| 403 | #define PER_INT_MSK_REG regptr(MSP_PER_BASE + 0x84) |
| 404 | /* Interrupt Mask Register */ |
| 405 | #define GPIO_INT_STS_REG regptr(MSP_PER_BASE + 0x88) |
| 406 | /* GPIO interrupt status reg */ |
| 407 | #define GPIO_INT_MSK_REG regptr(MSP_PER_BASE + 0x8C) |
| 408 | /* GPIO interrupt MASK Reg */ |
| 409 | |
| 410 | /* POLO GPIO registers */ |
| 411 | #define POLO_GPIO_DAT1_REG regptr(MSP_PER_BASE + 0x0E0) |
| 412 | /* Polo GPIO[8:0] data reg */ |
| 413 | #define POLO_GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x0E4) |
| 414 | /* Polo GPIO[7:0] config reg */ |
| 415 | #define POLO_GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x0E8) |
| 416 | /* Polo GPIO[15:8] config reg */ |
| 417 | #define POLO_GPIO_OD1_REG regptr(MSP_PER_BASE + 0x0EC) |
| 418 | /* Polo GPIO[31:0] output drive */ |
| 419 | #define POLO_GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x170) |
| 420 | /* Polo GPIO[23:16] config reg */ |
| 421 | #define POLO_GPIO_DAT2_REG regptr(MSP_PER_BASE + 0x174) |
| 422 | /* Polo GPIO[15:9] data reg */ |
| 423 | #define POLO_GPIO_DAT3_REG regptr(MSP_PER_BASE + 0x178) |
| 424 | /* Polo GPIO[23:16] data reg */ |
| 425 | #define POLO_GPIO_DAT4_REG regptr(MSP_PER_BASE + 0x17C) |
| 426 | /* Polo GPIO[31:24] data reg */ |
| 427 | #define POLO_GPIO_DAT5_REG regptr(MSP_PER_BASE + 0x180) |
| 428 | /* Polo GPIO[39:32] data reg */ |
| 429 | #define POLO_GPIO_DAT6_REG regptr(MSP_PER_BASE + 0x184) |
| 430 | /* Polo GPIO[47:40] data reg */ |
| 431 | #define POLO_GPIO_DAT7_REG regptr(MSP_PER_BASE + 0x188) |
| 432 | /* Polo GPIO[54:48] data reg */ |
| 433 | #define POLO_GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) |
| 434 | /* Polo GPIO[31:24] config reg */ |
| 435 | #define POLO_GPIO_CFG5_REG regptr(MSP_PER_BASE + 0x190) |
| 436 | /* Polo GPIO[39:32] config reg */ |
| 437 | #define POLO_GPIO_CFG6_REG regptr(MSP_PER_BASE + 0x194) |
| 438 | /* Polo GPIO[47:40] config reg */ |
| 439 | #define POLO_GPIO_CFG7_REG regptr(MSP_PER_BASE + 0x198) |
| 440 | /* Polo GPIO[54:48] config reg */ |
| 441 | #define POLO_GPIO_OD2_REG regptr(MSP_PER_BASE + 0x19C) |
| 442 | /* Polo GPIO[54:32] output drive */ |
| 443 | |
| 444 | /* Generic GPIO registers */ |
| 445 | #define GPIO_DATA1_REG regptr(MSP_PER_BASE + 0x170) |
| 446 | /* GPIO[1:0] data register */ |
| 447 | #define GPIO_DATA2_REG regptr(MSP_PER_BASE + 0x174) |
| 448 | /* GPIO[5:2] data register */ |
| 449 | #define GPIO_DATA3_REG regptr(MSP_PER_BASE + 0x178) |
| 450 | /* GPIO[9:6] data register */ |
| 451 | #define GPIO_DATA4_REG regptr(MSP_PER_BASE + 0x17C) |
| 452 | /* GPIO[15:10] data register */ |
| 453 | #define GPIO_CFG1_REG regptr(MSP_PER_BASE + 0x180) |
| 454 | /* GPIO[1:0] config register */ |
| 455 | #define GPIO_CFG2_REG regptr(MSP_PER_BASE + 0x184) |
| 456 | /* GPIO[5:2] config register */ |
| 457 | #define GPIO_CFG3_REG regptr(MSP_PER_BASE + 0x188) |
| 458 | /* GPIO[9:6] config register */ |
| 459 | #define GPIO_CFG4_REG regptr(MSP_PER_BASE + 0x18C) |
| 460 | /* GPIO[15:10] config register */ |
| 461 | #define GPIO_OD_REG regptr(MSP_PER_BASE + 0x190) |
| 462 | /* GPIO[15:0] output drive */ |
| 463 | |
| 464 | /* |
| 465 | *************************************************************************** |
| 466 | * CPU Interface register definitions * |
| 467 | *************************************************************************** |
| 468 | */ |
| 469 | #define PCI_FLUSH_REG regptr(MSP_CPUIF_BASE + 0x00) |
| 470 | /* PCI-SDRAM queue flush trigger */ |
| 471 | #define OCP_ERR1_REG regptr(MSP_CPUIF_BASE + 0x04) |
| 472 | /* OCP Error Attribute 1 */ |
| 473 | #define OCP_ERR2_REG regptr(MSP_CPUIF_BASE + 0x08) |
| 474 | /* OCP Error Attribute 2 */ |
| 475 | #define OCP_STS_REG regptr(MSP_CPUIF_BASE + 0x0C) |
| 476 | /* OCP Error Status */ |
| 477 | #define CPUIF_PM_REG regptr(MSP_CPUIF_BASE + 0x10) |
| 478 | /* CPU policy configuration */ |
| 479 | #define CPUIF_CFG_REG regptr(MSP_CPUIF_BASE + 0x10) |
| 480 | /* Misc configuration options */ |
| 481 | |
| 482 | /* Central Interrupt Controller Registers */ |
| 483 | #define MSP_CIC_BASE (MSP_CPUIF_BASE + 0x8000) |
| 484 | /* Central Interrupt registers */ |
| 485 | #define CIC_EXT_CFG_REG regptr(MSP_CIC_BASE + 0x00) |
| 486 | /* External interrupt config */ |
| 487 | #define CIC_STS_REG regptr(MSP_CIC_BASE + 0x04) |
| 488 | /* CIC Interrupt Status */ |
| 489 | #define CIC_VPE0_MSK_REG regptr(MSP_CIC_BASE + 0x08) |
| 490 | /* VPE0 Interrupt Mask */ |
| 491 | #define CIC_VPE1_MSK_REG regptr(MSP_CIC_BASE + 0x0C) |
| 492 | /* VPE1 Interrupt Mask */ |
| 493 | #define CIC_TC0_MSK_REG regptr(MSP_CIC_BASE + 0x10) |
| 494 | /* Thread Context 0 Int Mask */ |
| 495 | #define CIC_TC1_MSK_REG regptr(MSP_CIC_BASE + 0x14) |
| 496 | /* Thread Context 1 Int Mask */ |
| 497 | #define CIC_TC2_MSK_REG regptr(MSP_CIC_BASE + 0x18) |
| 498 | /* Thread Context 2 Int Mask */ |
| 499 | #define CIC_TC3_MSK_REG regptr(MSP_CIC_BASE + 0x18) |
| 500 | /* Thread Context 3 Int Mask */ |
| 501 | #define CIC_TC4_MSK_REG regptr(MSP_CIC_BASE + 0x18) |
| 502 | /* Thread Context 4 Int Mask */ |
| 503 | #define CIC_PCIMSI_STS_REG regptr(MSP_CIC_BASE + 0x18) |
| 504 | #define CIC_PCIMSI_MSK_REG regptr(MSP_CIC_BASE + 0x18) |
| 505 | #define CIC_PCIFLSH_REG regptr(MSP_CIC_BASE + 0x18) |
| 506 | #define CIC_VPE0_SWINT_REG regptr(MSP_CIC_BASE + 0x08) |
| 507 | |
| 508 | |
| 509 | /* |
| 510 | *************************************************************************** |
| 511 | * Memory controller registers * |
| 512 | *************************************************************************** |
| 513 | */ |
| 514 | #define MEM_CFG1_REG regptr(MSP_MEM_CFG_BASE + 0x00) |
| 515 | #define MEM_SS_ADDR regptr(MSP_MEM_CFG_BASE + 0x00) |
| 516 | #define MEM_SS_DATA regptr(MSP_MEM_CFG_BASE + 0x04) |
| 517 | #define MEM_SS_WRITE regptr(MSP_MEM_CFG_BASE + 0x08) |
| 518 | |
| 519 | /* |
| 520 | *************************************************************************** |
| 521 | * PCI controller registers * |
| 522 | *************************************************************************** |
| 523 | */ |
| 524 | #define PCI_BASE_REG regptr(MSP_PCI_BASE + 0x00) |
| 525 | #define PCI_CONFIG_SPACE_REG regptr(MSP_PCI_BASE + 0x800) |
| 526 | #define PCI_JTAG_DEVID_REG regptr(MSP_SLP_BASE + 0x13c) |
| 527 | |
| 528 | /* |
| 529 | ######################################################################## |
| 530 | # Register content & macro definitions # |
| 531 | ######################################################################## |
| 532 | */ |
| 533 | |
| 534 | /* |
| 535 | *************************************************************************** |
| 536 | * DEV_ID defines * |
| 537 | *************************************************************************** |
| 538 | */ |
| 539 | #define DEV_ID_PCI_DIS (1 << 26) /* Set if PCI disabled */ |
| 540 | #define DEV_ID_PCI_HOST (1 << 20) /* Set if PCI host */ |
| 541 | #define DEV_ID_SINGLE_PC (1 << 19) /* Set if single PC Card */ |
| 542 | #define DEV_ID_FAMILY (0xff << 8) /* family ID code */ |
| 543 | #define POLO_ZEUS_SUB_FAMILY (0x7 << 16) /* sub family for Polo/Zeus */ |
| 544 | |
| 545 | #define MSPFPGA_ID (0x00 << 8) /* you are on your own here */ |
| 546 | #define MSP5000_ID (0x50 << 8) |
| 547 | #define MSP4F00_ID (0x4f << 8) /* FPGA version of MSP4200 */ |
| 548 | #define MSP4E00_ID (0x4f << 8) /* FPGA version of MSP7120 */ |
| 549 | #define MSP4200_ID (0x42 << 8) |
| 550 | #define MSP4000_ID (0x40 << 8) |
| 551 | #define MSP2XXX_ID (0x20 << 8) |
| 552 | #define MSPZEUS_ID (0x10 << 8) |
| 553 | |
| 554 | #define MSP2004_SUB_ID (0x0 << 16) |
| 555 | #define MSP2005_SUB_ID (0x1 << 16) |
| 556 | #define MSP2006_SUB_ID (0x1 << 16) |
| 557 | #define MSP2007_SUB_ID (0x2 << 16) |
| 558 | #define MSP2010_SUB_ID (0x3 << 16) |
| 559 | #define MSP2015_SUB_ID (0x4 << 16) |
| 560 | #define MSP2020_SUB_ID (0x5 << 16) |
| 561 | #define MSP2100_SUB_ID (0x6 << 16) |
| 562 | |
| 563 | /* |
| 564 | *************************************************************************** |
| 565 | * RESET defines * |
| 566 | *************************************************************************** |
| 567 | */ |
| 568 | #define MSP_GR_RST (0x01 << 0) /* Global reset bit */ |
| 569 | #define MSP_MR_RST (0x01 << 1) /* MIPS reset bit */ |
| 570 | #define MSP_PD_RST (0x01 << 2) /* PVC DMA reset bit */ |
| 571 | #define MSP_PP_RST (0x01 << 3) /* PVC reset bit */ |
| 572 | /* reserved */ |
| 573 | #define MSP_EA_RST (0x01 << 6) /* Mac A reset bit */ |
| 574 | #define MSP_EB_RST (0x01 << 7) /* Mac B reset bit */ |
| 575 | #define MSP_SE_RST (0x01 << 8) /* Security Eng reset bit */ |
| 576 | #define MSP_PB_RST (0x01 << 9) /* Per block reset bit */ |
| 577 | #define MSP_EC_RST (0x01 << 10) /* Mac C reset bit */ |
| 578 | #define MSP_TW_RST (0x01 << 11) /* TWI reset bit */ |
| 579 | #define MSP_SPI_RST (0x01 << 12) /* SPI/MPI reset bit */ |
| 580 | #define MSP_U1_RST (0x01 << 13) /* UART1 reset bit */ |
| 581 | #define MSP_U0_RST (0x01 << 14) /* UART0 reset bit */ |
| 582 | |
| 583 | /* |
| 584 | *************************************************************************** |
| 585 | * UART defines * |
| 586 | *************************************************************************** |
| 587 | */ |
| 588 | #ifndef CONFIG_MSP_FPGA |
| 589 | #define MSP_BASE_BAUD 25000000 |
| 590 | #else |
| 591 | #define MSP_BASE_BAUD 6000000 |
| 592 | #endif |
| 593 | #define MSP_UART_REG_LEN 0x20 |
| 594 | |
| 595 | /* |
| 596 | *************************************************************************** |
| 597 | * ELB defines * |
| 598 | *************************************************************************** |
| 599 | */ |
| 600 | #define PCCARD_32 0x02 /* Set if is PCCARD 32 (Cardbus) */ |
| 601 | #define SINGLE_PCCARD 0x01 /* Set to enable single PC card */ |
| 602 | |
| 603 | /* |
| 604 | *************************************************************************** |
| 605 | * CIC defines * |
| 606 | *************************************************************************** |
| 607 | */ |
| 608 | |
| 609 | /* CIC_EXT_CFG_REG */ |
| 610 | #define EXT_INT_POL(eirq) (1 << (eirq + 8)) |
| 611 | #define EXT_INT_EDGE(eirq) (1 << eirq) |
| 612 | |
| 613 | #define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq) (reg &= ~EXT_INT_EDGE(eirq)) |
| 614 | #define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq) (reg |= EXT_INT_EDGE(eirq)) |
| 615 | #define CIC_EXT_SET_ACTIVE_HI(reg, eirq) (reg |= EXT_INT_POL(eirq)) |
| 616 | #define CIC_EXT_SET_ACTIVE_LO(reg, eirq) (reg &= ~EXT_INT_POL(eirq)) |
| 617 | #define CIC_EXT_SET_ACTIVE_RISING CIC_EXT_SET_ACTIVE_HI |
| 618 | #define CIC_EXT_SET_ACTIVE_FALLING CIC_EXT_SET_ACTIVE_LO |
| 619 | |
| 620 | #define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \ |
| 621 | ((reg & EXT_INT_EDGE(eirq)) == 0) |
| 622 | #define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq) (reg & EXT_INT_EDGE(eirq)) |
| 623 | #define CIC_EXT_IS_ACTIVE_HI(reg, eirq) (reg & EXT_INT_POL(eirq)) |
| 624 | #define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \ |
| 625 | ((reg & EXT_INT_POL(eirq)) == 0) |
| 626 | #define CIC_EXT_IS_ACTIVE_RISING CIC_EXT_IS_ACTIVE_HI |
| 627 | #define CIC_EXT_IS_ACTIVE_FALLING CIC_EXT_IS_ACTIVE_LO |
| 628 | |
| 629 | /* |
| 630 | *************************************************************************** |
| 631 | * Memory Controller defines * |
| 632 | *************************************************************************** |
| 633 | */ |
| 634 | |
| 635 | /* Indirect memory controller registers */ |
| 636 | #define DDRC_CFG(n) (n) |
| 637 | #define DDRC_DEBUG(n) (0x04 + n) |
| 638 | #define DDRC_CTL(n) (0x40 + n) |
| 639 | |
| 640 | /* Macro to perform DDRC indirect write */ |
| 641 | #define DDRC_INDIRECT_WRITE(reg, mask, value) \ |
| 642 | ({ \ |
| 643 | *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \ |
| 644 | *MEM_SS_DATA = (value); \ |
| 645 | *MEM_SS_WRITE = 1; \ |
| 646 | }) |
| 647 | |
| 648 | /* |
| 649 | *************************************************************************** |
| 650 | * SPI/MPI Mode * |
| 651 | *************************************************************************** |
| 652 | */ |
| 653 | #define SPI_MPI_RX_BUSY 0x00008000 /* SPI/MPI Receive Busy */ |
| 654 | #define SPI_MPI_FIFO_EMPTY 0x00004000 /* SPI/MPI Fifo Empty */ |
| 655 | #define SPI_MPI_TX_BUSY 0x00002000 /* SPI/MPI Transmit Busy */ |
| 656 | #define SPI_MPI_FIFO_FULL 0x00001000 /* SPI/MPU FIFO full */ |
| 657 | |
| 658 | /* |
| 659 | *************************************************************************** |
| 660 | * SPI/MPI Control Register * |
| 661 | *************************************************************************** |
| 662 | */ |
| 663 | #define SPI_MPI_RX_START 0x00000004 /* Start receive command */ |
| 664 | #define SPI_MPI_FLUSH_Q 0x00000002 /* Flush SPI/MPI Queue */ |
| 665 | #define SPI_MPI_TX_START 0x00000001 /* Start Transmit Command */ |
| 666 | |
| 667 | #endif /* !_ASM_MSP_REGS_H */ |