blob: 2bbde607814334a811b91b21448c4d3ac75cfe00 [file] [log] [blame]
Jon Masone4650582006-06-26 13:58:14 +02001/*
2 * Derived from arch/powerpc/kernel/iommu.c
3 *
Muli Ben-Yehuda98822342007-07-21 17:10:48 +02004 * Copyright IBM Corporation, 2006-2007
Jon Masond8d2bed2006-10-05 18:47:21 +02005 * Copyright (C) 2006 Jon Mason <jdmason@kudzu.us>
Jon Masone4650582006-06-26 13:58:14 +02006 *
Jon Masond8d2bed2006-10-05 18:47:21 +02007 * Author: Jon Mason <jdmason@kudzu.us>
Muli Ben-Yehudaaa0a9f32006-07-10 17:06:15 +02008 * Author: Muli Ben-Yehuda <muli@il.ibm.com>
9
Jon Masone4650582006-06-26 13:58:14 +020010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
Jon Masone4650582006-06-26 13:58:14 +020025#include <linux/kernel.h>
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/slab.h>
29#include <linux/mm.h>
30#include <linux/spinlock.h>
31#include <linux/string.h>
Chandru95b68de2008-07-25 01:47:55 -070032#include <linux/crash_dump.h>
Jon Masone4650582006-06-26 13:58:14 +020033#include <linux/dma-mapping.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080034#include <linux/bitmap.h>
Jon Masone4650582006-06-26 13:58:14 +020035#include <linux/pci_ids.h>
36#include <linux/pci.h>
37#include <linux/delay.h>
Jens Axboe8b87d9f2007-07-24 12:38:15 +020038#include <linux/scatterlist.h>
FUJITA Tomonori1b39b072008-02-04 22:28:10 -080039#include <linux/iommu-helper.h>
Alexis Bruemmer1956a962008-07-25 19:44:51 -070040
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090041#include <asm/iommu.h>
Jon Masone4650582006-06-26 13:58:14 +020042#include <asm/calgary.h>
43#include <asm/tce.h>
44#include <asm/pci-direct.h>
45#include <asm/system.h>
46#include <asm/dma.h>
Laurent Vivierb34e90b2006-12-07 02:14:06 +010047#include <asm/rio.h>
Akinobu Mitaae5830a2008-04-19 23:55:19 +090048#include <asm/bios_ebda.h>
FUJITA Tomonorid7b9f7b2009-11-10 19:46:13 +090049#include <asm/x86_init.h>
Jon Masone4650582006-06-26 13:58:14 +020050
Muli Ben-Yehudabff65472006-12-07 02:14:07 +010051#ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
52int use_calgary __read_mostly = 1;
53#else
54int use_calgary __read_mostly = 0;
55#endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
56
Jon Masone4650582006-06-26 13:58:14 +020057#define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +020058#define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
Jon Masone4650582006-06-26 13:58:14 +020059
Jon Masone4650582006-06-26 13:58:14 +020060/* register offsets inside the host bridge space */
Muli Ben-Yehudacb01fc72006-10-22 00:41:15 +020061#define CALGARY_CONFIG_REG 0x0108
62#define PHB_CSR_OFFSET 0x0110 /* Channel Status */
Jon Masone4650582006-06-26 13:58:14 +020063#define PHB_PLSSR_OFFSET 0x0120
64#define PHB_CONFIG_RW_OFFSET 0x0160
65#define PHB_IOBASE_BAR_LOW 0x0170
66#define PHB_IOBASE_BAR_HIGH 0x0180
67#define PHB_MEM_1_LOW 0x0190
68#define PHB_MEM_1_HIGH 0x01A0
69#define PHB_IO_ADDR_SIZE 0x01B0
70#define PHB_MEM_1_SIZE 0x01C0
71#define PHB_MEM_ST_OFFSET 0x01D0
72#define PHB_AER_OFFSET 0x0200
73#define PHB_CONFIG_0_HIGH 0x0220
74#define PHB_CONFIG_0_LOW 0x0230
75#define PHB_CONFIG_0_END 0x0240
76#define PHB_MEM_2_LOW 0x02B0
77#define PHB_MEM_2_HIGH 0x02C0
78#define PHB_MEM_2_SIZE_HIGH 0x02D0
79#define PHB_MEM_2_SIZE_LOW 0x02E0
80#define PHB_DOSHOLE_OFFSET 0x08E0
81
Muli Ben-Yehudac3860102007-07-21 17:10:53 +020082/* CalIOC2 specific */
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +020083#define PHB_SAVIOR_L2 0x0DB0
84#define PHB_PAGE_MIG_CTRL 0x0DA8
85#define PHB_PAGE_MIG_DEBUG 0x0DA0
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +020086#define PHB_ROOT_COMPLEX_STATUS 0x0CB0
Muli Ben-Yehudac3860102007-07-21 17:10:53 +020087
Jon Masone4650582006-06-26 13:58:14 +020088/* PHB_CONFIG_RW */
89#define PHB_TCE_ENABLE 0x20000000
90#define PHB_SLOT_DISABLE 0x1C000000
91#define PHB_DAC_DISABLE 0x01000000
92#define PHB_MEM2_ENABLE 0x00400000
93#define PHB_MCSR_ENABLE 0x00100000
94/* TAR (Table Address Register) */
95#define TAR_SW_BITS 0x0000ffffffff800fUL
96#define TAR_VALID 0x0000000000000008UL
97/* CSR (Channel/DMA Status Register) */
98#define CSR_AGENT_MASK 0xffe0ffff
Muli Ben-Yehudacb01fc72006-10-22 00:41:15 +020099/* CCR (Calgary Configuration Register) */
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200100#define CCR_2SEC_TIMEOUT 0x000000000000000EUL
Muli Ben-Yehuda00be3fa2007-07-21 17:10:54 +0200101/* PMCR/PMDR (Page Migration Control/Debug Registers */
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200102#define PMR_SOFTSTOP 0x80000000
103#define PMR_SOFTSTOPFAULT 0x40000000
104#define PMR_HARDSTOP 0x20000000
Jon Masone4650582006-06-26 13:58:14 +0200105
106#define MAX_NUM_OF_PHBS 8 /* how many PHBs in total? */
Jon Masond2105b12006-07-29 21:42:43 +0200107#define MAX_NUM_CHASSIS 8 /* max number of chassis */
Muli Ben-Yehuda4ea8a5d2006-09-26 10:52:33 +0200108/* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
109#define MAX_PHB_BUS_NUM (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
Jon Masone4650582006-06-26 13:58:14 +0200110#define PHBS_PER_CALGARY 4
111
112/* register offsets in Calgary's internal register space */
113static const unsigned long tar_offsets[] = {
114 0x0580 /* TAR0 */,
115 0x0588 /* TAR1 */,
116 0x0590 /* TAR2 */,
117 0x0598 /* TAR3 */
118};
119
120static const unsigned long split_queue_offsets[] = {
121 0x4870 /* SPLIT QUEUE 0 */,
122 0x5870 /* SPLIT QUEUE 1 */,
123 0x6870 /* SPLIT QUEUE 2 */,
124 0x7870 /* SPLIT QUEUE 3 */
125};
126
127static const unsigned long phb_offsets[] = {
128 0x8000 /* PHB0 */,
129 0x9000 /* PHB1 */,
130 0xA000 /* PHB2 */,
131 0xB000 /* PHB3 */
132};
133
Laurent Vivierb34e90b2006-12-07 02:14:06 +0100134/* PHB debug registers */
135
136static const unsigned long phb_debug_offsets[] = {
137 0x4000 /* PHB 0 DEBUG */,
138 0x5000 /* PHB 1 DEBUG */,
139 0x6000 /* PHB 2 DEBUG */,
140 0x7000 /* PHB 3 DEBUG */
141};
142
143/*
144 * STUFF register for each debug PHB,
145 * byte 1 = start bus number, byte 2 = end bus number
146 */
147
148#define PHB_DEBUG_STUFF_OFFSET 0x0020
149
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100150#define EMERGENCY_PAGES 32 /* = 128KB */
151
Jon Masone4650582006-06-26 13:58:14 +0200152unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
153static int translate_empty_slots __read_mostly = 0;
154static int calgary_detected __read_mostly = 0;
155
Laurent Vivierb34e90b2006-12-07 02:14:06 +0100156static struct rio_table_hdr *rio_table_hdr __initdata;
157static struct scal_detail *scal_devs[MAX_NUMNODES] __initdata;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +0100158static struct rio_detail *rio_devs[MAX_NUMNODES * 4] __initdata;
Laurent Vivierb34e90b2006-12-07 02:14:06 +0100159
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200160struct calgary_bus_info {
161 void *tce_space;
Muli Ben-Yehuda0577f142006-09-26 10:52:31 +0200162 unsigned char translation_disabled;
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200163 signed char phbid;
Laurent Vivierb34e90b2006-12-07 02:14:06 +0100164 void __iomem *bbar;
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200165};
166
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200167static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
168static void calgary_tce_cache_blast(struct iommu_table *tbl);
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200169static void calgary_dump_error_regs(struct iommu_table *tbl);
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200170static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
Muli Ben-Yehuda00be3fa2007-07-21 17:10:54 +0200171static void calioc2_tce_cache_blast(struct iommu_table *tbl);
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200172static void calioc2_dump_error_regs(struct iommu_table *tbl);
Chandru95b68de2008-07-25 01:47:55 -0700173static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl);
174static void get_tce_space_from_tar(void);
Jon Masone4650582006-06-26 13:58:14 +0200175
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200176static struct cal_chipset_ops calgary_chip_ops = {
177 .handle_quirks = calgary_handle_quirks,
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200178 .tce_cache_blast = calgary_tce_cache_blast,
179 .dump_error_regs = calgary_dump_error_regs
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200180};
181
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200182static struct cal_chipset_ops calioc2_chip_ops = {
183 .handle_quirks = calioc2_handle_quirks,
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200184 .tce_cache_blast = calioc2_tce_cache_blast,
185 .dump_error_regs = calioc2_dump_error_regs
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200186};
187
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200188static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
Jon Masone4650582006-06-26 13:58:14 +0200189
Muli Ben-Yehudad588ba82007-10-17 18:04:35 +0200190static inline int translation_enabled(struct iommu_table *tbl)
191{
192 /* only PHBs with translation enabled have an IOMMU table */
193 return (tbl != NULL);
194}
195
Jon Masone4650582006-06-26 13:58:14 +0200196static void iommu_range_reserve(struct iommu_table *tbl,
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200197 unsigned long start_addr, unsigned int npages)
Jon Masone4650582006-06-26 13:58:14 +0200198{
199 unsigned long index;
200 unsigned long end;
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200201 unsigned long flags;
Jon Masone4650582006-06-26 13:58:14 +0200202
203 index = start_addr >> PAGE_SHIFT;
204
205 /* bail out if we're asked to reserve a region we don't cover */
206 if (index >= tbl->it_size)
207 return;
208
209 end = index + npages;
210 if (end > tbl->it_size) /* don't go off the table */
211 end = tbl->it_size;
212
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200213 spin_lock_irqsave(&tbl->it_lock, flags);
214
Akinobu Mitaa66022c2009-12-15 16:48:28 -0800215 bitmap_set(tbl->it_map, index, npages);
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200216
217 spin_unlock_irqrestore(&tbl->it_lock, flags);
Jon Masone4650582006-06-26 13:58:14 +0200218}
219
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800220static unsigned long iommu_range_alloc(struct device *dev,
221 struct iommu_table *tbl,
222 unsigned int npages)
Jon Masone4650582006-06-26 13:58:14 +0200223{
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200224 unsigned long flags;
Jon Masone4650582006-06-26 13:58:14 +0200225 unsigned long offset;
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800226 unsigned long boundary_size;
227
228 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
229 PAGE_SIZE) >> PAGE_SHIFT;
Jon Masone4650582006-06-26 13:58:14 +0200230
231 BUG_ON(npages == 0);
232
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200233 spin_lock_irqsave(&tbl->it_lock, flags);
234
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800235 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
236 npages, 0, boundary_size, 0);
Jon Masone4650582006-06-26 13:58:14 +0200237 if (offset == ~0UL) {
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200238 tbl->chip_ops->tce_cache_blast(tbl);
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800239
240 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
241 npages, 0, boundary_size, 0);
Jon Masone4650582006-06-26 13:58:14 +0200242 if (offset == ~0UL) {
243 printk(KERN_WARNING "Calgary: IOMMU full.\n");
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200244 spin_unlock_irqrestore(&tbl->it_lock, flags);
Jon Masone4650582006-06-26 13:58:14 +0200245 if (panic_on_overflow)
246 panic("Calgary: fix the allocator.\n");
247 else
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900248 return DMA_ERROR_CODE;
Jon Masone4650582006-06-26 13:58:14 +0200249 }
250 }
251
Jon Masone4650582006-06-26 13:58:14 +0200252 tbl->it_hint = offset + npages;
253 BUG_ON(tbl->it_hint > tbl->it_size);
254
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200255 spin_unlock_irqrestore(&tbl->it_lock, flags);
256
Jon Masone4650582006-06-26 13:58:14 +0200257 return offset;
258}
259
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800260static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
261 void *vaddr, unsigned int npages, int direction)
Jon Masone4650582006-06-26 13:58:14 +0200262{
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200263 unsigned long entry;
FUJITA Tomonori1f7564c2009-11-15 21:19:54 +0900264 dma_addr_t ret;
Jon Masone4650582006-06-26 13:58:14 +0200265
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800266 entry = iommu_range_alloc(dev, tbl, npages);
Jon Masone4650582006-06-26 13:58:14 +0200267
FUJITA Tomonori1f7564c2009-11-15 21:19:54 +0900268 if (unlikely(entry == DMA_ERROR_CODE)) {
269 printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
270 "iommu %p\n", npages, tbl);
271 return DMA_ERROR_CODE;
272 }
Jon Masone4650582006-06-26 13:58:14 +0200273
274 /* set the return dma address */
275 ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
276
277 /* put the TCEs in the HW table */
278 tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
279 direction);
Jon Masone4650582006-06-26 13:58:14 +0200280 return ret;
Jon Masone4650582006-06-26 13:58:14 +0200281}
282
Muli Ben-Yehuda3cc39bd2007-07-21 17:11:06 +0200283static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
Jon Masone4650582006-06-26 13:58:14 +0200284 unsigned int npages)
285{
286 unsigned long entry;
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100287 unsigned long badend;
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200288 unsigned long flags;
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100289
290 /* were we called with bad_dma_address? */
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900291 badend = DMA_ERROR_CODE + (EMERGENCY_PAGES * PAGE_SIZE);
292 if (unlikely((dma_addr >= DMA_ERROR_CODE) && (dma_addr < badend))) {
Arjan van de Venbde78a72008-07-08 09:51:56 -0700293 WARN(1, KERN_ERR "Calgary: driver tried unmapping bad DMA "
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100294 "address 0x%Lx\n", dma_addr);
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100295 return;
296 }
Jon Masone4650582006-06-26 13:58:14 +0200297
298 entry = dma_addr >> PAGE_SHIFT;
299
300 BUG_ON(entry + npages > tbl->it_size);
301
302 tce_free(tbl, entry, npages);
303
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200304 spin_lock_irqsave(&tbl->it_lock, flags);
305
Akinobu Mitaa66022c2009-12-15 16:48:28 -0800306 bitmap_clear(tbl->it_map, entry, npages);
Muli Ben-Yehuda820a1492007-07-21 17:11:04 +0200307
308 spin_unlock_irqrestore(&tbl->it_lock, flags);
Jon Masone4650582006-06-26 13:58:14 +0200309}
310
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200311static inline struct iommu_table *find_iommu_table(struct device *dev)
312{
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200313 struct pci_dev *pdev;
314 struct pci_bus *pbus;
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200315 struct iommu_table *tbl;
316
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200317 pdev = to_pci_dev(dev);
318
Darrick J. Wong45287522009-12-02 15:05:56 -0800319 /* search up the device tree for an iommu */
Murillo Fernandes Bernardesf055a062007-08-10 22:31:00 +0200320 pbus = pdev->bus;
Darrick J. Wong45287522009-12-02 15:05:56 -0800321 do {
322 tbl = pci_iommu(pbus);
323 if (tbl && tbl->it_busno == pbus->number)
324 break;
325 tbl = NULL;
Murillo Fernandes Bernardesf055a062007-08-10 22:31:00 +0200326 pbus = pbus->parent;
Darrick J. Wong45287522009-12-02 15:05:56 -0800327 } while (pbus);
Muli Ben-Yehuda7354b072007-07-21 17:11:03 +0200328
Murillo Fernandes Bernardesf055a062007-08-10 22:31:00 +0200329 BUG_ON(tbl && (tbl->it_busno != pbus->number));
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200330
331 return tbl;
332}
333
FUJITA Tomonori160c1d82009-01-05 23:59:02 +0900334static void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
335 int nelems,enum dma_data_direction dir,
336 struct dma_attrs *attrs)
Jon Masone4650582006-06-26 13:58:14 +0200337{
Muli Ben-Yehuda3cc39bd2007-07-21 17:11:06 +0200338 struct iommu_table *tbl = find_iommu_table(dev);
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200339 struct scatterlist *s;
340 int i;
Muli Ben-Yehuda3cc39bd2007-07-21 17:11:06 +0200341
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +0200342 if (!translation_enabled(tbl))
Muli Ben-Yehuda3cc39bd2007-07-21 17:11:06 +0200343 return;
344
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200345 for_each_sg(sglist, s, nelems, i) {
Jon Masone4650582006-06-26 13:58:14 +0200346 unsigned int npages;
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200347 dma_addr_t dma = s->dma_address;
348 unsigned int dmalen = s->dma_length;
Jon Masone4650582006-06-26 13:58:14 +0200349
350 if (dmalen == 0)
351 break;
352
Joerg Roedel036b4c52008-10-15 22:02:12 -0700353 npages = iommu_num_pages(dma, dmalen, PAGE_SIZE);
Muli Ben-Yehuda3cc39bd2007-07-21 17:11:06 +0200354 iommu_free(tbl, dma, npages);
Jon Masone4650582006-06-26 13:58:14 +0200355 }
356}
357
Yinghai Lu0b11e1c2007-07-21 17:11:05 +0200358static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +0900359 int nelems, enum dma_data_direction dir,
360 struct dma_attrs *attrs)
Jon Masone4650582006-06-26 13:58:14 +0200361{
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200362 struct iommu_table *tbl = find_iommu_table(dev);
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200363 struct scatterlist *s;
Jon Masone4650582006-06-26 13:58:14 +0200364 unsigned long vaddr;
365 unsigned int npages;
366 unsigned long entry;
367 int i;
368
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200369 for_each_sg(sg, s, nelems, i) {
Jens Axboe58b053e2007-10-22 20:02:46 +0200370 BUG_ON(!sg_page(s));
Jon Masone4650582006-06-26 13:58:14 +0200371
Jens Axboe58b053e2007-10-22 20:02:46 +0200372 vaddr = (unsigned long) sg_virt(s);
Joerg Roedel036b4c52008-10-15 22:02:12 -0700373 npages = iommu_num_pages(vaddr, s->length, PAGE_SIZE);
Jon Masone4650582006-06-26 13:58:14 +0200374
FUJITA Tomonori1b39b072008-02-04 22:28:10 -0800375 entry = iommu_range_alloc(dev, tbl, npages);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900376 if (entry == DMA_ERROR_CODE) {
Jon Masone4650582006-06-26 13:58:14 +0200377 /* makes sure unmap knows to stop */
378 s->dma_length = 0;
379 goto error;
380 }
381
382 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
383
384 /* insert into HW table */
FUJITA Tomonori160c1d82009-01-05 23:59:02 +0900385 tce_build(tbl, entry, npages, vaddr & PAGE_MASK, dir);
Jon Masone4650582006-06-26 13:58:14 +0200386
387 s->dma_length = s->length;
388 }
389
Jon Masone4650582006-06-26 13:58:14 +0200390 return nelems;
391error:
FUJITA Tomonori160c1d82009-01-05 23:59:02 +0900392 calgary_unmap_sg(dev, sg, nelems, dir, NULL);
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200393 for_each_sg(sg, s, nelems, i) {
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900394 sg->dma_address = DMA_ERROR_CODE;
Jens Axboe8b87d9f2007-07-24 12:38:15 +0200395 sg->dma_length = 0;
Jon Masone4650582006-06-26 13:58:14 +0200396 }
Jon Masone4650582006-06-26 13:58:14 +0200397 return 0;
398}
399
FUJITA Tomonori39916052009-01-05 23:47:24 +0900400static dma_addr_t calgary_map_page(struct device *dev, struct page *page,
401 unsigned long offset, size_t size,
402 enum dma_data_direction dir,
403 struct dma_attrs *attrs)
Jon Masone4650582006-06-26 13:58:14 +0200404{
FUJITA Tomonori39916052009-01-05 23:47:24 +0900405 void *vaddr = page_address(page) + offset;
Jon Masone4650582006-06-26 13:58:14 +0200406 unsigned long uaddr;
407 unsigned int npages;
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200408 struct iommu_table *tbl = find_iommu_table(dev);
Jon Masone4650582006-06-26 13:58:14 +0200409
410 uaddr = (unsigned long)vaddr;
Joerg Roedel036b4c52008-10-15 22:02:12 -0700411 npages = iommu_num_pages(uaddr, size, PAGE_SIZE);
Jon Masone4650582006-06-26 13:58:14 +0200412
FUJITA Tomonori39916052009-01-05 23:47:24 +0900413 return iommu_alloc(dev, tbl, vaddr, npages, dir);
Jon Masone4650582006-06-26 13:58:14 +0200414}
415
FUJITA Tomonori39916052009-01-05 23:47:24 +0900416static void calgary_unmap_page(struct device *dev, dma_addr_t dma_addr,
417 size_t size, enum dma_data_direction dir,
418 struct dma_attrs *attrs)
Jon Masone4650582006-06-26 13:58:14 +0200419{
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200420 struct iommu_table *tbl = find_iommu_table(dev);
Jon Masone4650582006-06-26 13:58:14 +0200421 unsigned int npages;
422
FUJITA Tomonori39916052009-01-05 23:47:24 +0900423 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
424 iommu_free(tbl, dma_addr, npages);
425}
426
Yinghai Lu0b11e1c2007-07-21 17:11:05 +0200427static void* calgary_alloc_coherent(struct device *dev, size_t size,
Jon Masone4650582006-06-26 13:58:14 +0200428 dma_addr_t *dma_handle, gfp_t flag)
429{
430 void *ret = NULL;
431 dma_addr_t mapping;
432 unsigned int npages, order;
Muli Ben-Yehuda35b6dfa2007-07-21 17:10:51 +0200433 struct iommu_table *tbl = find_iommu_table(dev);
Jon Masone4650582006-06-26 13:58:14 +0200434
435 size = PAGE_ALIGN(size); /* size rounded up to full pages */
436 npages = size >> PAGE_SHIFT;
437 order = get_order(size);
438
FUJITA Tomonorif10ac8a2008-09-11 23:08:47 +0900439 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
440
Jon Masone4650582006-06-26 13:58:14 +0200441 /* alloc enough pages (and possibly more) */
442 ret = (void *)__get_free_pages(flag, order);
443 if (!ret)
444 goto error;
445 memset(ret, 0, size);
446
Alexis Bruemmer1956a962008-07-25 19:44:51 -0700447 /* set up tces to cover the allocated range */
448 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900449 if (mapping == DMA_ERROR_CODE)
Alexis Bruemmer1956a962008-07-25 19:44:51 -0700450 goto free;
451 *dma_handle = mapping;
Jon Masone4650582006-06-26 13:58:14 +0200452 return ret;
Jon Masone4650582006-06-26 13:58:14 +0200453free:
454 free_pages((unsigned long)ret, get_order(size));
455 ret = NULL;
456error:
457 return ret;
458}
459
Joerg Roedele4ad68b2008-08-19 16:32:41 +0200460static void calgary_free_coherent(struct device *dev, size_t size,
461 void *vaddr, dma_addr_t dma_handle)
462{
463 unsigned int npages;
464 struct iommu_table *tbl = find_iommu_table(dev);
465
466 size = PAGE_ALIGN(size);
467 npages = size >> PAGE_SHIFT;
468
469 iommu_free(tbl, dma_handle, npages);
470 free_pages((unsigned long)vaddr, get_order(size));
471}
472
FUJITA Tomonori160c1d82009-01-05 23:59:02 +0900473static struct dma_map_ops calgary_dma_ops = {
Jon Masone4650582006-06-26 13:58:14 +0200474 .alloc_coherent = calgary_alloc_coherent,
Joerg Roedele4ad68b2008-08-19 16:32:41 +0200475 .free_coherent = calgary_free_coherent,
Jon Masone4650582006-06-26 13:58:14 +0200476 .map_sg = calgary_map_sg,
477 .unmap_sg = calgary_unmap_sg,
FUJITA Tomonori39916052009-01-05 23:47:24 +0900478 .map_page = calgary_map_page,
479 .unmap_page = calgary_unmap_page,
Jon Masone4650582006-06-26 13:58:14 +0200480};
481
Laurent Vivierb34e90b2006-12-07 02:14:06 +0100482static inline void __iomem * busno_to_bbar(unsigned char num)
483{
484 return bus_info[num].bbar;
485}
486
Jon Masone4650582006-06-26 13:58:14 +0200487static inline int busno_to_phbid(unsigned char num)
488{
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200489 return bus_info[num].phbid;
Jon Masone4650582006-06-26 13:58:14 +0200490}
491
492static inline unsigned long split_queue_offset(unsigned char num)
493{
494 size_t idx = busno_to_phbid(num);
495
496 return split_queue_offsets[idx];
497}
498
499static inline unsigned long tar_offset(unsigned char num)
500{
501 size_t idx = busno_to_phbid(num);
502
503 return tar_offsets[idx];
504}
505
506static inline unsigned long phb_offset(unsigned char num)
507{
508 size_t idx = busno_to_phbid(num);
509
510 return phb_offsets[idx];
511}
512
513static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
514{
515 unsigned long target = ((unsigned long)bar) | offset;
516 return (void __iomem*)target;
517}
518
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200519static inline int is_calioc2(unsigned short device)
520{
521 return (device == PCI_DEVICE_ID_IBM_CALIOC2);
522}
523
524static inline int is_calgary(unsigned short device)
525{
526 return (device == PCI_DEVICE_ID_IBM_CALGARY);
527}
528
529static inline int is_cal_pci_dev(unsigned short device)
530{
531 return (is_calgary(device) || is_calioc2(device));
532}
533
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200534static void calgary_tce_cache_blast(struct iommu_table *tbl)
Jon Masone4650582006-06-26 13:58:14 +0200535{
536 u64 val;
537 u32 aer;
538 int i = 0;
539 void __iomem *bbar = tbl->bbar;
540 void __iomem *target;
541
542 /* disable arbitration on the bus */
543 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
544 aer = readl(target);
545 writel(0, target);
546
547 /* read plssr to ensure it got there */
548 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
549 val = readl(target);
550
551 /* poll split queues until all DMA activity is done */
552 target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
553 do {
554 val = readq(target);
555 i++;
556 } while ((val & 0xff) != 0xff && i < 100);
557 if (i == 100)
558 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
559 "continuing anyway\n");
560
561 /* invalidate TCE cache */
562 target = calgary_reg(bbar, tar_offset(tbl->it_busno));
563 writeq(tbl->tar_val, target);
564
565 /* enable arbitration */
566 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
567 writel(aer, target);
568 (void)readl(target); /* flush */
569}
570
Muli Ben-Yehuda00be3fa2007-07-21 17:10:54 +0200571static void calioc2_tce_cache_blast(struct iommu_table *tbl)
572{
573 void __iomem *bbar = tbl->bbar;
574 void __iomem *target;
575 u64 val64;
576 u32 val;
577 int i = 0;
578 int count = 1;
579 unsigned char bus = tbl->it_busno;
580
581begin:
582 printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
583 "sequence - count %d\n", bus, count);
584
585 /* 1. using the Page Migration Control reg set SoftStop */
586 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
587 val = be32_to_cpu(readl(target));
588 printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
589 val |= PMR_SOFTSTOP;
590 printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
591 writel(cpu_to_be32(val), target);
592
593 /* 2. poll split queues until all DMA activity is done */
594 printk(KERN_DEBUG "2a. starting to poll split queues\n");
595 target = calgary_reg(bbar, split_queue_offset(bus));
596 do {
597 val64 = readq(target);
598 i++;
599 } while ((val64 & 0xff) != 0xff && i < 100);
600 if (i == 100)
601 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
602 "continuing anyway\n");
603
604 /* 3. poll Page Migration DEBUG for SoftStopFault */
605 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
606 val = be32_to_cpu(readl(target));
607 printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
608
609 /* 4. if SoftStopFault - goto (1) */
610 if (val & PMR_SOFTSTOPFAULT) {
611 if (++count < 100)
612 goto begin;
613 else {
614 printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
615 "aborting TCE cache flush sequence!\n");
616 return; /* pray for the best */
617 }
618 }
619
620 /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
621 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
622 printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
623 val = be32_to_cpu(readl(target));
624 printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
625 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
626 val = be32_to_cpu(readl(target));
627 printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
628
629 /* 6. invalidate TCE cache */
630 printk(KERN_DEBUG "6. invalidating TCE cache\n");
631 target = calgary_reg(bbar, tar_offset(bus));
632 writeq(tbl->tar_val, target);
633
634 /* 7. Re-read PMCR */
635 printk(KERN_DEBUG "7a. Re-reading PMCR\n");
636 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
637 val = be32_to_cpu(readl(target));
638 printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
639
640 /* 8. Remove HardStop */
641 printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
642 target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
643 val = 0;
644 printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
645 writel(cpu_to_be32(val), target);
646 val = be32_to_cpu(readl(target));
647 printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
648}
649
Jon Masone4650582006-06-26 13:58:14 +0200650static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
651 u64 limit)
652{
653 unsigned int numpages;
654
655 limit = limit | 0xfffff;
656 limit++;
657
658 numpages = ((limit - start) >> PAGE_SHIFT);
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300659 iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
Jon Masone4650582006-06-26 13:58:14 +0200660}
661
662static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
663{
664 void __iomem *target;
665 u64 low, high, sizelow;
666 u64 start, limit;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300667 struct iommu_table *tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200668 unsigned char busnum = dev->bus->number;
669 void __iomem *bbar = tbl->bbar;
670
671 /* peripheral MEM_1 region */
672 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
673 low = be32_to_cpu(readl(target));
674 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
675 high = be32_to_cpu(readl(target));
676 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
677 sizelow = be32_to_cpu(readl(target));
678
679 start = (high << 32) | low;
680 limit = sizelow;
681
682 calgary_reserve_mem_region(dev, start, limit);
683}
684
685static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
686{
687 void __iomem *target;
688 u32 val32;
689 u64 low, high, sizelow, sizehigh;
690 u64 start, limit;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300691 struct iommu_table *tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200692 unsigned char busnum = dev->bus->number;
693 void __iomem *bbar = tbl->bbar;
694
695 /* is it enabled? */
696 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
697 val32 = be32_to_cpu(readl(target));
698 if (!(val32 & PHB_MEM2_ENABLE))
699 return;
700
701 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
702 low = be32_to_cpu(readl(target));
703 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
704 high = be32_to_cpu(readl(target));
705 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
706 sizelow = be32_to_cpu(readl(target));
707 target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
708 sizehigh = be32_to_cpu(readl(target));
709
710 start = (high << 32) | low;
711 limit = (sizehigh << 32) | sizelow;
712
713 calgary_reserve_mem_region(dev, start, limit);
714}
715
716/*
717 * some regions of the IO address space do not get translated, so we
718 * must not give devices IO addresses in those regions. The regions
719 * are the 640KB-1MB region and the two PCI peripheral memory holes.
720 * Reserve all of them in the IOMMU bitmap to avoid giving them out
721 * later.
722 */
723static void __init calgary_reserve_regions(struct pci_dev *dev)
724{
725 unsigned int npages;
Jon Masone4650582006-06-26 13:58:14 +0200726 u64 start;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300727 struct iommu_table *tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200728
Muli Ben-Yehuda310adfd2007-02-13 13:26:24 +0100729 /* reserve EMERGENCY_PAGES from bad_dma_address and up */
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +0900730 iommu_range_reserve(tbl, DMA_ERROR_CODE, EMERGENCY_PAGES);
Jon Masone4650582006-06-26 13:58:14 +0200731
732 /* avoid the BIOS/VGA first 640KB-1MB region */
Muli Ben-Yehudae8f20412007-07-21 17:11:01 +0200733 /* for CalIOC2 - avoid the entire first MB */
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200734 if (is_calgary(dev->device)) {
735 start = (640 * 1024);
736 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
737 } else { /* calioc2 */
738 start = 0;
Muli Ben-Yehudae8f20412007-07-21 17:11:01 +0200739 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200740 }
Jon Masone4650582006-06-26 13:58:14 +0200741 iommu_range_reserve(tbl, start, npages);
742
743 /* reserve the two PCI peripheral memory regions in IO space */
744 calgary_reserve_peripheral_mem_1(dev);
745 calgary_reserve_peripheral_mem_2(dev);
746}
747
748static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
749{
750 u64 val64;
751 u64 table_phys;
752 void __iomem *target;
753 int ret;
754 struct iommu_table *tbl;
755
756 /* build TCE tables for each PHB */
757 ret = build_tce_table(dev, bbar);
758 if (ret)
759 return ret;
760
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300761 tbl = pci_iommu(dev->bus);
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200762 tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
Chandru95b68de2008-07-25 01:47:55 -0700763
764 if (is_kdump_kernel())
765 calgary_init_bitmap_from_tce_table(tbl);
766 else
767 tce_free(tbl, 0, tbl->it_size);
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +0200768
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200769 if (is_calgary(dev->device))
770 tbl->chip_ops = &calgary_chip_ops;
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200771 else if (is_calioc2(dev->device))
772 tbl->chip_ops = &calioc2_chip_ops;
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200773 else
774 BUG();
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +0200775
Jon Masone4650582006-06-26 13:58:14 +0200776 calgary_reserve_regions(dev);
777
778 /* set TARs for each PHB */
779 target = calgary_reg(bbar, tar_offset(dev->bus->number));
780 val64 = be64_to_cpu(readq(target));
781
782 /* zero out all TAR bits under sw control */
783 val64 &= ~TAR_SW_BITS;
Jon Masone4650582006-06-26 13:58:14 +0200784 table_phys = (u64)__pa(tbl->it_base);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200785
Jon Masone4650582006-06-26 13:58:14 +0200786 val64 |= table_phys;
787
788 BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
789 val64 |= (u64) specified_table_size;
790
791 tbl->tar_val = cpu_to_be64(val64);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200792
Jon Masone4650582006-06-26 13:58:14 +0200793 writeq(tbl->tar_val, target);
794 readq(target); /* flush */
795
796 return 0;
797}
798
Muli Ben-Yehudab8f4fe62006-09-26 10:52:31 +0200799static void __init calgary_free_bus(struct pci_dev *dev)
Jon Masone4650582006-06-26 13:58:14 +0200800{
801 u64 val64;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300802 struct iommu_table *tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200803 void __iomem *target;
Muli Ben-Yehudab8f4fe62006-09-26 10:52:31 +0200804 unsigned int bitmapsz;
Jon Masone4650582006-06-26 13:58:14 +0200805
806 target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
807 val64 = be64_to_cpu(readq(target));
808 val64 &= ~TAR_SW_BITS;
809 writeq(cpu_to_be64(val64), target);
810 readq(target); /* flush */
811
Muli Ben-Yehudab8f4fe62006-09-26 10:52:31 +0200812 bitmapsz = tbl->it_size / BITS_PER_BYTE;
813 free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
814 tbl->it_map = NULL;
815
Jon Masone4650582006-06-26 13:58:14 +0200816 kfree(tbl);
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300817
818 set_pci_iommu(dev->bus, NULL);
Muli Ben-Yehudab8f4fe62006-09-26 10:52:31 +0200819
820 /* Can't free bootmem allocated memory after system is up :-( */
821 bus_info[dev->bus->number].tce_space = NULL;
Jon Masone4650582006-06-26 13:58:14 +0200822}
823
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200824static void calgary_dump_error_regs(struct iommu_table *tbl)
825{
826 void __iomem *bbar = tbl->bbar;
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200827 void __iomem *target;
Muli Ben-Yehudaddbd41b2007-07-21 17:10:57 +0200828 u32 csr, plssr;
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200829
830 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
Muli Ben-Yehudaddbd41b2007-07-21 17:10:57 +0200831 csr = be32_to_cpu(readl(target));
832
833 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
834 plssr = be32_to_cpu(readl(target));
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200835
836 /* If no error, the agent ID in the CSR is not valid */
837 printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
Muli Ben-Yehudaddbd41b2007-07-21 17:10:57 +0200838 "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200839}
840
841static void calioc2_dump_error_regs(struct iommu_table *tbl)
842{
843 void __iomem *bbar = tbl->bbar;
844 u32 csr, csmr, plssr, mck, rcstat;
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200845 void __iomem *target;
846 unsigned long phboff = phb_offset(tbl->it_busno);
847 unsigned long erroff;
848 u32 errregs[7];
849 int i;
850
851 /* dump CSR */
852 target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
853 csr = be32_to_cpu(readl(target));
854 /* dump PLSSR */
855 target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
856 plssr = be32_to_cpu(readl(target));
857 /* dump CSMR */
858 target = calgary_reg(bbar, phboff | 0x290);
859 csmr = be32_to_cpu(readl(target));
860 /* dump mck */
861 target = calgary_reg(bbar, phboff | 0x800);
862 mck = be32_to_cpu(readl(target));
863
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200864 printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
865 tbl->it_busno);
866
867 printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
868 csr, plssr, csmr, mck);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200869
870 /* dump rest of error regs */
871 printk(KERN_EMERG "Calgary: ");
872 for (i = 0; i < ARRAY_SIZE(errregs); i++) {
Muli Ben-Yehuda7354b072007-07-21 17:11:03 +0200873 /* err regs are at 0x810 - 0x870 */
874 erroff = (0x810 + (i * 0x10));
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200875 target = calgary_reg(bbar, phboff | erroff);
876 errregs[i] = be32_to_cpu(readl(target));
877 printk("0x%08x@0x%lx ", errregs[i], erroff);
878 }
879 printk("\n");
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200880
881 /* root complex status */
882 target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
883 rcstat = be32_to_cpu(readl(target));
884 printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
885 PHB_ROOT_COMPLEX_STATUS);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200886}
887
Jon Masone4650582006-06-26 13:58:14 +0200888static void calgary_watchdog(unsigned long data)
889{
890 struct pci_dev *dev = (struct pci_dev *)data;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300891 struct iommu_table *tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200892 void __iomem *bbar = tbl->bbar;
893 u32 val32;
894 void __iomem *target;
895
896 target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
897 val32 = be32_to_cpu(readl(target));
898
899 /* If no error, the agent ID in the CSR is not valid */
900 if (val32 & CSR_AGENT_MASK) {
Muli Ben-Yehuda8cb32dc2007-07-21 17:10:55 +0200901 tbl->chip_ops->dump_error_regs(tbl);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200902
903 /* reset error */
Jon Masone4650582006-06-26 13:58:14 +0200904 writel(0, target);
905
906 /* Disable bus that caused the error */
907 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200908 PHB_CONFIG_RW_OFFSET);
Jon Masone4650582006-06-26 13:58:14 +0200909 val32 = be32_to_cpu(readl(target));
910 val32 |= PHB_SLOT_DISABLE;
911 writel(cpu_to_be32(val32), target);
912 readl(target); /* flush */
913 } else {
914 /* Reset the timer */
915 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
916 }
917}
918
Muli Ben-Yehudaa2b663f2007-07-21 17:10:47 +0200919static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
920 unsigned char busnum, unsigned long timeout)
Muli Ben-Yehudacb01fc72006-10-22 00:41:15 +0200921{
922 u64 val64;
923 void __iomem *target;
Muli Ben-Yehuda58db8542006-12-07 02:14:06 +0100924 unsigned int phb_shift = ~0; /* silence gcc */
Muli Ben-Yehudacb01fc72006-10-22 00:41:15 +0200925 u64 mask;
926
927 switch (busno_to_phbid(busnum)) {
928 case 0: phb_shift = (63 - 19);
929 break;
930 case 1: phb_shift = (63 - 23);
931 break;
932 case 2: phb_shift = (63 - 27);
933 break;
934 case 3: phb_shift = (63 - 35);
935 break;
936 default:
937 BUG_ON(busno_to_phbid(busnum));
938 }
939
940 target = calgary_reg(bbar, CALGARY_CONFIG_REG);
941 val64 = be64_to_cpu(readq(target));
942
943 /* zero out this PHB's timer bits */
944 mask = ~(0xFUL << phb_shift);
945 val64 &= mask;
Muli Ben-Yehudaa2b663f2007-07-21 17:10:47 +0200946 val64 |= (timeout << phb_shift);
Muli Ben-Yehudacb01fc72006-10-22 00:41:15 +0200947 writeq(cpu_to_be64(val64), target);
948 readq(target); /* flush */
949}
950
Sam Ravnborg31f3dff2008-02-01 17:49:42 +0100951static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200952{
953 unsigned char busnum = dev->bus->number;
954 void __iomem *bbar = tbl->bbar;
955 void __iomem *target;
956 u32 val;
957
Muli Ben-Yehuda8bcf7702007-07-21 17:11:00 +0200958 /*
959 * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
960 */
961 target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
962 val = cpu_to_be32(readl(target));
963 val |= 0x00800000;
964 writel(cpu_to_be32(val), target);
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200965}
966
Sam Ravnborg31f3dff2008-02-01 17:49:42 +0100967static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
Muli Ben-Yehudab8d2ea12007-07-21 17:10:49 +0200968{
969 unsigned char busnum = dev->bus->number;
Muli Ben-Yehudab8d2ea12007-07-21 17:10:49 +0200970
971 /*
972 * Give split completion a longer timeout on bus 1 for aic94xx
973 * http://bugzilla.kernel.org/show_bug.cgi?id=7180
974 */
Muli Ben-Yehudac3860102007-07-21 17:10:53 +0200975 if (is_calgary(dev->device) && (busnum == 1))
Muli Ben-Yehudab8d2ea12007-07-21 17:10:49 +0200976 calgary_set_split_completion_timeout(tbl->bbar, busnum,
977 CCR_2SEC_TIMEOUT);
978}
979
Jon Masone4650582006-06-26 13:58:14 +0200980static void __init calgary_enable_translation(struct pci_dev *dev)
981{
982 u32 val32;
983 unsigned char busnum;
984 void __iomem *target;
985 void __iomem *bbar;
986 struct iommu_table *tbl;
987
988 busnum = dev->bus->number;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +0300989 tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +0200990 bbar = tbl->bbar;
991
992 /* enable TCE in PHB Config Register */
993 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
994 val32 = be32_to_cpu(readl(target));
995 val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
996
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +0200997 printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
998 (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
999 "Calgary" : "CalIOC2", busnum);
Jon Masone4650582006-06-26 13:58:14 +02001000 printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1001 "bus.\n");
1002
1003 writel(cpu_to_be32(val32), target);
1004 readl(target); /* flush */
1005
1006 init_timer(&tbl->watchdog_timer);
1007 tbl->watchdog_timer.function = &calgary_watchdog;
1008 tbl->watchdog_timer.data = (unsigned long)dev;
1009 mod_timer(&tbl->watchdog_timer, jiffies);
1010}
1011
1012static void __init calgary_disable_translation(struct pci_dev *dev)
1013{
1014 u32 val32;
1015 unsigned char busnum;
1016 void __iomem *target;
1017 void __iomem *bbar;
1018 struct iommu_table *tbl;
1019
1020 busnum = dev->bus->number;
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +03001021 tbl = pci_iommu(dev->bus);
Jon Masone4650582006-06-26 13:58:14 +02001022 bbar = tbl->bbar;
1023
1024 /* disable TCE in PHB Config Register */
1025 target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1026 val32 = be32_to_cpu(readl(target));
1027 val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1028
Jon Mason70d666d2006-10-05 18:47:21 +02001029 printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
Jon Masone4650582006-06-26 13:58:14 +02001030 writel(cpu_to_be32(val32), target);
1031 readl(target); /* flush */
1032
1033 del_timer_sync(&tbl->watchdog_timer);
1034}
1035
Muli Ben-Yehudaa4fc5202006-09-26 10:52:31 +02001036static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
Jon Masone4650582006-06-26 13:58:14 +02001037{
Muli Ben-Yehuda871b1702006-09-26 10:52:31 +02001038 pci_dev_get(dev);
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +03001039 set_pci_iommu(dev->bus, NULL);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001040
1041 /* is the device behind a bridge? */
1042 if (dev->bus->parent)
1043 dev->bus->parent->self = dev;
1044 else
1045 dev->bus->self = dev;
Jon Masone4650582006-06-26 13:58:14 +02001046}
1047
1048static int __init calgary_init_one(struct pci_dev *dev)
1049{
Jon Masone4650582006-06-26 13:58:14 +02001050 void __iomem *bbar;
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +02001051 struct iommu_table *tbl;
Jon Masone4650582006-06-26 13:58:14 +02001052 int ret;
1053
Jon Masondedc9932006-10-05 18:47:21 +02001054 BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1055
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001056 bbar = busno_to_bbar(dev->bus->number);
Jon Masone4650582006-06-26 13:58:14 +02001057 ret = calgary_setup_tar(dev, bbar);
1058 if (ret)
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001059 goto done;
Jon Masone4650582006-06-26 13:58:14 +02001060
Muli Ben-Yehuda871b1702006-09-26 10:52:31 +02001061 pci_dev_get(dev);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001062
1063 if (dev->bus->parent) {
1064 if (dev->bus->parent->self)
1065 printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1066 "bus->parent->self!\n", dev);
1067 dev->bus->parent->self = dev;
1068 } else
1069 dev->bus->self = dev;
Muli Ben-Yehudab8d2ea12007-07-21 17:10:49 +02001070
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +03001071 tbl = pci_iommu(dev->bus);
Muli Ben-Yehudaff297b82007-07-21 17:10:50 +02001072 tbl->chip_ops->handle_quirks(tbl, dev);
Muli Ben-Yehudab8d2ea12007-07-21 17:10:49 +02001073
Jon Masone4650582006-06-26 13:58:14 +02001074 calgary_enable_translation(dev);
1075
1076 return 0;
1077
Jon Masone4650582006-06-26 13:58:14 +02001078done:
1079 return ret;
1080}
1081
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001082static int __init calgary_locate_bbars(void)
Jon Masone4650582006-06-26 13:58:14 +02001083{
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001084 int ret;
1085 int rioidx, phb, bus;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001086 void __iomem *bbar;
1087 void __iomem *target;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001088 unsigned long offset;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001089 u8 start_bus, end_bus;
1090 u32 val;
1091
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001092 ret = -ENODATA;
1093 for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1094 struct rio_detail *rio = rio_devs[rioidx];
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001095
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001096 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001097 continue;
1098
1099 /* map entire 1MB of Calgary config space */
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001100 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1101 if (!bbar)
1102 goto error;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001103
1104 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001105 offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1106 target = calgary_reg(bbar, offset);
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001107
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001108 val = be32_to_cpu(readl(target));
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001109
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001110 start_bus = (u8)((val & 0x00FF0000) >> 16);
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001111 end_bus = (u8)((val & 0x0000FF00) >> 8);
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001112
1113 if (end_bus) {
1114 for (bus = start_bus; bus <= end_bus; bus++) {
1115 bus_info[bus].bbar = bbar;
1116 bus_info[bus].phbid = phb;
1117 }
1118 } else {
1119 bus_info[start_bus].bbar = bbar;
1120 bus_info[start_bus].phbid = phb;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001121 }
1122 }
1123 }
1124
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001125 return 0;
1126
1127error:
1128 /* scan bus_info and iounmap any bbars we previously ioremap'd */
1129 for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1130 if (bus_info[bus].bbar)
1131 iounmap(bus_info[bus].bbar);
1132
1133 return ret;
1134}
1135
1136static int __init calgary_init(void)
1137{
1138 int ret;
1139 struct pci_dev *dev = NULL;
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001140 struct calgary_bus_info *info;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001141
1142 ret = calgary_locate_bbars();
1143 if (ret)
1144 return ret;
Jon Masone4650582006-06-26 13:58:14 +02001145
Chandru95b68de2008-07-25 01:47:55 -07001146 /* Purely for kdump kernel case */
1147 if (is_kdump_kernel())
1148 get_tce_space_from_tar();
1149
Jon Masondedc9932006-10-05 18:47:21 +02001150 do {
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001151 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
Jon Masone4650582006-06-26 13:58:14 +02001152 if (!dev)
1153 break;
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001154 if (!is_cal_pci_dev(dev->device))
1155 continue;
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001156
1157 info = &bus_info[dev->bus->number];
1158 if (info->translation_disabled) {
Jon Masone4650582006-06-26 13:58:14 +02001159 calgary_init_one_nontraslated(dev);
1160 continue;
1161 }
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001162
1163 if (!info->tce_space && !translate_empty_slots)
Jon Masone4650582006-06-26 13:58:14 +02001164 continue;
Muli Ben-Yehuda12de2572007-07-21 17:11:02 +02001165
Jon Masone4650582006-06-26 13:58:14 +02001166 ret = calgary_init_one(dev);
1167 if (ret)
1168 goto error;
Jon Masondedc9932006-10-05 18:47:21 +02001169 } while (1);
Jon Masone4650582006-06-26 13:58:14 +02001170
Alexis Bruemmer1956a962008-07-25 19:44:51 -07001171 dev = NULL;
1172 for_each_pci_dev(dev) {
1173 struct iommu_table *tbl;
1174
1175 tbl = find_iommu_table(&dev->dev);
1176
1177 if (translation_enabled(tbl))
1178 dev->dev.archdata.dma_ops = &calgary_dma_ops;
1179 }
1180
Jon Masone4650582006-06-26 13:58:14 +02001181 return ret;
1182
1183error:
Jon Masondedc9932006-10-05 18:47:21 +02001184 do {
Greg Kroah-Hartmana2b5d872008-02-13 09:32:03 -08001185 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
Muli Ben-Yehuda9f2dc462006-09-26 10:52:31 +02001186 if (!dev)
1187 break;
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001188 if (!is_cal_pci_dev(dev->device))
1189 continue;
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001190
1191 info = &bus_info[dev->bus->number];
1192 if (info->translation_disabled) {
Jon Masone4650582006-06-26 13:58:14 +02001193 pci_dev_put(dev);
1194 continue;
1195 }
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001196 if (!info->tce_space && !translate_empty_slots)
Jon Masone4650582006-06-26 13:58:14 +02001197 continue;
Muli Ben-Yehuda871b1702006-09-26 10:52:31 +02001198
Jon Masone4650582006-06-26 13:58:14 +02001199 calgary_disable_translation(dev);
Muli Ben-Yehudab8f4fe62006-09-26 10:52:31 +02001200 calgary_free_bus(dev);
Muli Ben-Yehuda871b1702006-09-26 10:52:31 +02001201 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
Alexis Bruemmer1956a962008-07-25 19:44:51 -07001202 dev->dev.archdata.dma_ops = NULL;
Jon Masondedc9932006-10-05 18:47:21 +02001203 } while (1);
Jon Masone4650582006-06-26 13:58:14 +02001204
1205 return ret;
1206}
1207
1208static inline int __init determine_tce_table_size(u64 ram)
1209{
1210 int ret;
1211
1212 if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1213 return specified_table_size;
1214
1215 /*
1216 * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1217 * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1218 * larger table size has twice as many entries, so shift the
1219 * max ram address by 13 to divide by 8K and then look at the
1220 * order of the result to choose between 0-7.
1221 */
1222 ret = get_order(ram >> 13);
1223 if (ret > TCE_TABLE_SIZE_8M)
1224 ret = TCE_TABLE_SIZE_8M;
1225
1226 return ret;
1227}
1228
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001229static int __init build_detail_arrays(void)
1230{
1231 unsigned long ptr;
David Howells85d57792008-08-18 11:58:17 +02001232 unsigned numnodes, i;
1233 int scal_detail_size, rio_detail_size;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001234
David Howells85d57792008-08-18 11:58:17 +02001235 numnodes = rio_table_hdr->num_scal_dev;
1236 if (numnodes > MAX_NUMNODES){
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001237 printk(KERN_WARNING
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001238 "Calgary: MAX_NUMNODES too low! Defined as %d, "
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001239 "but system has %d nodes.\n",
David Howells85d57792008-08-18 11:58:17 +02001240 MAX_NUMNODES, numnodes);
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001241 return -ENODEV;
1242 }
1243
1244 switch (rio_table_hdr->version){
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001245 case 2:
1246 scal_detail_size = 11;
1247 rio_detail_size = 13;
1248 break;
1249 case 3:
1250 scal_detail_size = 12;
1251 rio_detail_size = 15;
1252 break;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001253 default:
1254 printk(KERN_WARNING
1255 "Calgary: Invalid Rio Grande Table Version: %d\n",
1256 rio_table_hdr->version);
1257 return -EPROTO;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001258 }
1259
1260 ptr = ((unsigned long)rio_table_hdr) + 3;
David Howells85d57792008-08-18 11:58:17 +02001261 for (i = 0; i < numnodes; i++, ptr += scal_detail_size)
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001262 scal_devs[i] = (struct scal_detail *)ptr;
1263
1264 for (i = 0; i < rio_table_hdr->num_rio_dev;
1265 i++, ptr += rio_detail_size)
1266 rio_devs[i] = (struct rio_detail *)ptr;
1267
1268 return 0;
1269}
1270
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001271static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1272{
1273 int dev;
1274 u32 val;
1275
1276 if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1277 /*
1278 * FIXME: properly scan for devices accross the
1279 * PCI-to-PCI bridge on every CalIOC2 port.
1280 */
1281 return 1;
1282 }
1283
1284 for (dev = 1; dev < 8; dev++) {
1285 val = read_pci_config(bus, dev, 0, 0);
1286 if (val != 0xffffffff)
1287 break;
1288 }
1289 return (val != 0xffffffff);
1290}
1291
Chandru95b68de2008-07-25 01:47:55 -07001292/*
1293 * calgary_init_bitmap_from_tce_table():
1294 * Funtion for kdump case. In the second/kdump kernel initialize
1295 * the bitmap based on the tce table entries obtained from first kernel
1296 */
1297static void calgary_init_bitmap_from_tce_table(struct iommu_table *tbl)
1298{
1299 u64 *tp;
1300 unsigned int index;
1301 tp = ((u64 *)tbl->it_base);
1302 for (index = 0 ; index < tbl->it_size; index++) {
1303 if (*tp != 0x0)
1304 set_bit(index, tbl->it_map);
1305 tp++;
1306 }
1307}
1308
1309/*
1310 * get_tce_space_from_tar():
1311 * Function for kdump case. Get the tce tables from first kernel
1312 * by reading the contents of the base adress register of calgary iommu
1313 */
Marcin Slusarzf7106662008-08-17 17:50:52 +02001314static void __init get_tce_space_from_tar(void)
Chandru95b68de2008-07-25 01:47:55 -07001315{
1316 int bus;
1317 void __iomem *target;
1318 unsigned long tce_space;
1319
1320 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1321 struct calgary_bus_info *info = &bus_info[bus];
1322 unsigned short pci_device;
1323 u32 val;
1324
1325 val = read_pci_config(bus, 0, 0, 0);
1326 pci_device = (val & 0xFFFF0000) >> 16;
1327
1328 if (!is_cal_pci_dev(pci_device))
1329 continue;
1330 if (info->translation_disabled)
1331 continue;
1332
1333 if (calgary_bus_has_devices(bus, pci_device) ||
1334 translate_empty_slots) {
1335 target = calgary_reg(bus_info[bus].bbar,
1336 tar_offset(bus));
1337 tce_space = be64_to_cpu(readq(target));
1338 tce_space = tce_space & TAR_SW_BITS;
1339
1340 tce_space = tce_space & (~specified_table_size);
1341 info->tce_space = (u64 *)__va(tce_space);
1342 }
1343 }
1344 return;
1345}
1346
FUJITA Tomonorif4131c62009-11-14 21:26:50 +09001347static int __init calgary_iommu_init(void)
1348{
1349 int ret;
1350
1351 /* ok, we're trying to use Calgary - let's roll */
1352 printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1353
1354 ret = calgary_init();
1355 if (ret) {
1356 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1357 "falling back to no_iommu\n", ret);
1358 return ret;
1359 }
1360
FUJITA Tomonorif4131c62009-11-14 21:26:50 +09001361 return 0;
1362}
FUJITA Tomonorid7b9f7b2009-11-10 19:46:13 +09001363
Jon Masone4650582006-06-26 13:58:14 +02001364void __init detect_calgary(void)
1365{
Jon Masond2105b12006-07-29 21:42:43 +02001366 int bus;
Jon Masone4650582006-06-26 13:58:14 +02001367 void *tbl;
Jon Masond2105b12006-07-29 21:42:43 +02001368 int calgary_found = 0;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001369 unsigned long ptr;
Ingo Molnar136f1e72006-12-20 11:53:32 +01001370 unsigned int offset, prev_offset;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001371 int ret;
Jon Masone4650582006-06-26 13:58:14 +02001372
1373 /*
1374 * if the user specified iommu=off or iommu=soft or we found
1375 * another HW IOMMU already, bail out.
1376 */
FUJITA Tomonori75f1cdf2009-11-10 19:46:20 +09001377 if (no_iommu || iommu_detected)
Jon Masone4650582006-06-26 13:58:14 +02001378 return;
1379
Muli Ben-Yehudabff65472006-12-07 02:14:07 +01001380 if (!use_calgary)
1381 return;
1382
Andi Kleen0637a702006-09-26 10:52:41 +02001383 if (!early_pci_allowed())
1384 return;
1385
Muli Ben-Yehudab92cc552007-01-11 01:52:44 +01001386 printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1387
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001388 ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1389
1390 rio_table_hdr = NULL;
Ingo Molnar136f1e72006-12-20 11:53:32 +01001391 prev_offset = 0;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001392 offset = 0x180;
Ingo Molnar136f1e72006-12-20 11:53:32 +01001393 /*
1394 * The next offset is stored in the 1st word.
1395 * Only parse up until the offset increases:
1396 */
1397 while (offset > prev_offset) {
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001398 /* The block id is stored in the 2nd word */
1399 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1400 /* set the pointer past the offset & block id */
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001401 rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001402 break;
1403 }
Ingo Molnar136f1e72006-12-20 11:53:32 +01001404 prev_offset = offset;
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001405 offset = *((unsigned short *)(ptr + offset));
1406 }
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001407 if (!rio_table_hdr) {
Muli Ben-Yehudab92cc552007-01-11 01:52:44 +01001408 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1409 "in EBDA - bailing!\n");
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001410 return;
1411 }
1412
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001413 ret = build_detail_arrays();
1414 if (ret) {
Muli Ben-Yehudab92cc552007-01-11 01:52:44 +01001415 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001416 return;
Muli Ben-Yehudaeae93752006-12-07 02:14:06 +01001417 }
Laurent Vivierb34e90b2006-12-07 02:14:06 +01001418
Chandru95b68de2008-07-25 01:47:55 -07001419 specified_table_size = determine_tce_table_size((is_kdump_kernel() ?
1420 saved_max_pfn : max_pfn) * PAGE_SIZE);
Jon Masone4650582006-06-26 13:58:14 +02001421
Jon Masond2105b12006-07-29 21:42:43 +02001422 for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +02001423 struct calgary_bus_info *info = &bus_info[bus];
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001424 unsigned short pci_device;
1425 u32 val;
Jon Masond2105b12006-07-29 21:42:43 +02001426
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001427 val = read_pci_config(bus, 0, 0, 0);
1428 pci_device = (val & 0xFFFF0000) >> 16;
1429
1430 if (!is_cal_pci_dev(pci_device))
Jon Masone4650582006-06-26 13:58:14 +02001431 continue;
Jon Masond2105b12006-07-29 21:42:43 +02001432
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +02001433 if (info->translation_disabled)
Jon Masone4650582006-06-26 13:58:14 +02001434 continue;
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +02001435
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001436 if (calgary_bus_has_devices(bus, pci_device) ||
1437 translate_empty_slots) {
Chandru95b68de2008-07-25 01:47:55 -07001438 /*
1439 * If it is kdump kernel, find and use tce tables
1440 * from first kernel, else allocate tce tables here
1441 */
1442 if (!is_kdump_kernel()) {
1443 tbl = alloc_tce_table();
1444 if (!tbl)
1445 goto cleanup;
1446 info->tce_space = tbl;
1447 }
Muli Ben-Yehuda8a244592007-07-21 17:10:52 +02001448 calgary_found = 1;
Jon Masond2105b12006-07-29 21:42:43 +02001449 }
Jon Masone4650582006-06-26 13:58:14 +02001450 }
1451
Muli Ben-Yehudab92cc552007-01-11 01:52:44 +01001452 printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1453 calgary_found ? "found" : "not found");
1454
Jon Masond2105b12006-07-29 21:42:43 +02001455 if (calgary_found) {
Jon Masone4650582006-06-26 13:58:14 +02001456 iommu_detected = 1;
1457 calgary_detected = 1;
Muli Ben-Yehudade684652006-09-26 10:52:33 +02001458 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
FUJITA Tomonori7e055752009-04-14 12:12:29 +09001459 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d\n",
1460 specified_table_size);
Alexis Bruemmer1956a962008-07-25 19:44:51 -07001461
FUJITA Tomonorid7b9f7b2009-11-10 19:46:13 +09001462 x86_init.iommu.iommu_init = calgary_iommu_init;
Jon Masone4650582006-06-26 13:58:14 +02001463 }
1464 return;
1465
1466cleanup:
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +02001467 for (--bus; bus >= 0; --bus) {
1468 struct calgary_bus_info *info = &bus_info[bus];
1469
1470 if (info->tce_space)
1471 free_tce_table(info->tce_space);
1472 }
Jon Masone4650582006-06-26 13:58:14 +02001473}
1474
Jon Masone4650582006-06-26 13:58:14 +02001475static int __init calgary_parse_options(char *p)
1476{
1477 unsigned int bridge;
1478 size_t len;
1479 char* endp;
1480
1481 while (*p) {
1482 if (!strncmp(p, "64k", 3))
1483 specified_table_size = TCE_TABLE_SIZE_64K;
1484 else if (!strncmp(p, "128k", 4))
1485 specified_table_size = TCE_TABLE_SIZE_128K;
1486 else if (!strncmp(p, "256k", 4))
1487 specified_table_size = TCE_TABLE_SIZE_256K;
1488 else if (!strncmp(p, "512k", 4))
1489 specified_table_size = TCE_TABLE_SIZE_512K;
1490 else if (!strncmp(p, "1M", 2))
1491 specified_table_size = TCE_TABLE_SIZE_1M;
1492 else if (!strncmp(p, "2M", 2))
1493 specified_table_size = TCE_TABLE_SIZE_2M;
1494 else if (!strncmp(p, "4M", 2))
1495 specified_table_size = TCE_TABLE_SIZE_4M;
1496 else if (!strncmp(p, "8M", 2))
1497 specified_table_size = TCE_TABLE_SIZE_8M;
1498
1499 len = strlen("translate_empty_slots");
1500 if (!strncmp(p, "translate_empty_slots", len))
1501 translate_empty_slots = 1;
1502
1503 len = strlen("disable");
1504 if (!strncmp(p, "disable", len)) {
1505 p += len;
1506 if (*p == '=')
1507 ++p;
1508 if (*p == '\0')
1509 break;
Julia Lawalleff79ae2008-11-25 14:13:03 +01001510 bridge = simple_strtoul(p, &endp, 0);
Jon Masone4650582006-06-26 13:58:14 +02001511 if (p == endp)
1512 break;
1513
Jon Masond2105b12006-07-29 21:42:43 +02001514 if (bridge < MAX_PHB_BUS_NUM) {
Jon Masone4650582006-06-26 13:58:14 +02001515 printk(KERN_INFO "Calgary: disabling "
Jon Mason70d666d2006-10-05 18:47:21 +02001516 "translation for PHB %#x\n", bridge);
Muli Ben-Yehudaf38db652006-09-26 10:52:31 +02001517 bus_info[bridge].translation_disabled = 1;
Jon Masone4650582006-06-26 13:58:14 +02001518 }
1519 }
1520
1521 p = strpbrk(p, ",");
1522 if (!p)
1523 break;
1524
1525 p++; /* skip ',' */
1526 }
1527 return 1;
1528}
1529__setup("calgary=", calgary_parse_options);
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001530
1531static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1532{
1533 struct iommu_table *tbl;
1534 unsigned int npages;
1535 int i;
1536
Muli Ben-Yehuda08f1c192007-07-22 00:23:39 +03001537 tbl = pci_iommu(dev->bus);
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001538
1539 for (i = 0; i < 4; i++) {
1540 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1541
1542 /* Don't give out TCEs that map MEM resources */
1543 if (!(r->flags & IORESOURCE_MEM))
1544 continue;
1545
1546 /* 0-based? we reserve the whole 1st MB anyway */
1547 if (!r->start)
1548 continue;
1549
1550 /* cover the whole region */
1551 npages = (r->end - r->start) >> PAGE_SHIFT;
1552 npages++;
1553
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001554 iommu_range_reserve(tbl, r->start, npages);
1555 }
1556}
1557
1558static int __init calgary_fixup_tce_spaces(void)
1559{
1560 struct pci_dev *dev = NULL;
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001561 struct calgary_bus_info *info;
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001562
1563 if (no_iommu || swiotlb || !calgary_detected)
1564 return -ENODEV;
1565
Muli Ben-Yehuda12de2572007-07-21 17:11:02 +02001566 printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001567
1568 do {
1569 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1570 if (!dev)
1571 break;
1572 if (!is_cal_pci_dev(dev->device))
1573 continue;
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001574
1575 info = &bus_info[dev->bus->number];
1576 if (info->translation_disabled)
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001577 continue;
1578
Muli Ben-Yehudabc3c6052007-10-17 18:04:39 +02001579 if (!info->tce_space)
Muli Ben-Yehuda07877cf2007-07-21 17:10:58 +02001580 continue;
1581
1582 calgary_fixup_one_tce_space(dev);
1583
1584 } while (1);
1585
1586 return 0;
1587}
1588
1589/*
1590 * We need to be call after pcibios_assign_resources (fs_initcall level)
1591 * and before device_initcall.
1592 */
1593rootfs_initcall(calgary_fixup_tce_spaces);