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Prashant Gaikwadc7736ed2013-01-11 13:16:19 +05301/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
Thierry Reding306a7f92014-07-17 13:17:24 +020017#ifndef __SOC_TEGRA_FUSE_H__
18#define __SOC_TEGRA_FUSE_H__
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +053019
Thierry Reding304664e2014-07-11 09:52:41 +020020#define TEGRA20 0x20
21#define TEGRA30 0x30
22#define TEGRA114 0x35
23#define TEGRA124 0x40
Thierry Reding24ef5742015-01-08 08:24:45 +010024#define TEGRA132 0x13
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020025#define TEGRA210 0x21
Thierry Reding304664e2014-07-11 09:52:41 +020026
Peter De Schrijver783c8f42014-06-12 18:36:37 +030027#define TEGRA_FUSE_SKU_CALIB_0 0xf0
28#define TEGRA30_FUSE_SATA_CALIB 0x124
Thierry Reding87d66f22015-11-11 18:25:02 +010029#define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
Peter De Schrijver783c8f42014-06-12 18:36:37 +030030
Thierry Reding304664e2014-07-11 09:52:41 +020031#ifndef __ASSEMBLY__
32
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +053033u32 tegra_read_chipid(void);
Thierry Reding304664e2014-07-11 09:52:41 +020034u8 tegra_get_chip_id(void);
35
Peter De Schrijver35874f32014-06-12 18:36:36 +030036enum tegra_revision {
37 TEGRA_REVISION_UNKNOWN = 0,
38 TEGRA_REVISION_A01,
39 TEGRA_REVISION_A02,
40 TEGRA_REVISION_A03,
41 TEGRA_REVISION_A03p,
42 TEGRA_REVISION_A04,
43 TEGRA_REVISION_MAX,
44};
45
Peter De Schrijver783c8f42014-06-12 18:36:37 +030046struct tegra_sku_info {
47 int sku_id;
48 int cpu_process_id;
49 int cpu_speedo_id;
50 int cpu_speedo_value;
51 int cpu_iddq_value;
Thierry Reding03b3f4c2015-03-23 14:44:08 +010052 int soc_process_id;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030053 int soc_speedo_id;
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020054 int soc_speedo_value;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030055 int gpu_process_id;
Thierry Reding0dc5a0d2015-04-29 16:55:57 +020056 int gpu_speedo_id;
Peter De Schrijver783c8f42014-06-12 18:36:37 +030057 int gpu_speedo_value;
58 enum tegra_revision revision;
59};
60
Peter De Schrijver35874f32014-06-12 18:36:36 +030061u32 tegra_read_straps(void);
Mikko Perttunen6ea26092015-03-12 15:47:55 +010062u32 tegra_read_ram_code(void);
Peter De Schrijver35874f32014-06-12 18:36:36 +030063u32 tegra_read_chipid(void);
Peter De Schrijver783c8f42014-06-12 18:36:37 +030064int tegra_fuse_readl(unsigned long offset, u32 *value);
Peter De Schrijver35874f32014-06-12 18:36:36 +030065
Peter De Schrijver783c8f42014-06-12 18:36:37 +030066extern struct tegra_sku_info tegra_sku_info;
Peter De Schrijver35874f32014-06-12 18:36:36 +030067
Thierry Reding304664e2014-07-11 09:52:41 +020068#endif /* __ASSEMBLY__ */
Prashant Gaikwadc7736ed2013-01-11 13:16:19 +053069
Thierry Reding306a7f92014-07-17 13:17:24 +020070#endif /* __SOC_TEGRA_FUSE_H__ */