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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Mike Frysingerded963a2008-10-16 23:01:24 +08002 * Blackfin cache control code
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Mike Frysingerded963a2008-10-16 23:01:24 +08004 * Copyright 2004-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -07005 *
Mike Frysingerded963a2008-10-16 23:01:24 +08006 * Licensed under the GPL-2 or later.
Bryan Wu1394f032007-05-06 14:50:22 -07007 */
8
9#include <linux/linkage.h>
Bryan Wu1394f032007-05-06 14:50:22 -070010#include <asm/blackfin.h>
11#include <asm/cache.h>
Mike Frysingerded963a2008-10-16 23:01:24 +080012#include <asm/page.h>
Bryan Wu1394f032007-05-06 14:50:22 -070013
14.text
Bryan Wu1394f032007-05-06 14:50:22 -070015
Mike Frysinger78f28a02009-04-10 21:20:19 +000016/* 05000443 - IFLUSH cannot be last instruction in hardware loop */
17#if ANOMALY_05000443
18# define BROK_FLUSH_INST "IFLUSH"
19#else
20# define BROK_FLUSH_INST "no anomaly! yeah!"
21#endif
22
Mike Frysingerded963a2008-10-16 23:01:24 +080023/* Since all L1 caches work the same way, we use the same method for flushing
24 * them. Only the actual flush instruction differs. We write this in asm as
25 * GCC can be hard to coax into writing nice hardware loops.
Bryan Wu1394f032007-05-06 14:50:22 -070026 *
Mike Frysingerded963a2008-10-16 23:01:24 +080027 * Also, we assume the following register setup:
28 * R0 = start address
29 * R1 = end address
Bryan Wu1394f032007-05-06 14:50:22 -070030 */
Mike Frysinger78f28a02009-04-10 21:20:19 +000031.macro do_flush flushins:req label
Mike Frysingerded963a2008-10-16 23:01:24 +080032
Mike Frysinger39e96c82008-11-18 17:48:22 +080033 R2 = -L1_CACHE_BYTES;
34
35 /* start = (start & -L1_CACHE_BYTES) */
36 R0 = R0 & R2;
37
Mike Frysingerded963a2008-10-16 23:01:24 +080038 /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
39 R1 += -1;
Mike Frysingerded963a2008-10-16 23:01:24 +080040 R1 = R1 & R2;
41 R1 += L1_CACHE_BYTES;
42
43 /* count = (end - start) >> L1_CACHE_SHIFT */
44 R2 = R1 - R0;
45 R2 >>= L1_CACHE_SHIFT;
46 P1 = R2;
47
48.ifnb \label
49\label :
50.endif
51 P0 = R0;
Mike Frysinger78f28a02009-04-10 21:20:19 +000052
Mike Frysingerded963a2008-10-16 23:01:24 +080053 LSETUP (1f, 2f) LC1 = P1;
Bryan Wu1394f032007-05-06 14:50:22 -0700541:
Mike Frysinger78f28a02009-04-10 21:20:19 +000055.ifeqs "\flushins", BROK_FLUSH_INST
Mike Frysingerded963a2008-10-16 23:01:24 +080056 \flushins [P0++];
Mike Frysinger78f28a02009-04-10 21:20:19 +0000572: nop;
58.else
Mike Frysinger2cf851132008-10-28 16:34:42 +0800592: \flushins [P0++];
Mike Frysinger78f28a02009-04-10 21:20:19 +000060.endif
Mike Frysingerded963a2008-10-16 23:01:24 +080061
Bryan Wu1394f032007-05-06 14:50:22 -070062 RTS;
Mike Frysingerded963a2008-10-16 23:01:24 +080063.endm
64
65/* Invalidate all instruction cache lines assocoiated with this memory area */
66ENTRY(_blackfin_icache_flush_range)
Sonic Zhangd7ff1a92009-03-05 18:26:59 +080067/*
68 * Walkaround to avoid loading wrong instruction after invalidating icache
69 * and following sequence is met.
70 *
71 * 1) One instruction address is cached in the instruction cache.
72 * 2) This instruction in SDRAM is changed.
73 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
74 * 4) This instruction is executed again, but the old one is loaded.
75 */
76 P0 = R0;
77 IFLUSH[P0];
Mike Frysinger78f28a02009-04-10 21:20:19 +000078 do_flush IFLUSH
Mike Frysinger51be24c2007-06-11 15:31:30 +080079ENDPROC(_blackfin_icache_flush_range)
Bryan Wu1394f032007-05-06 14:50:22 -070080
Bryan Wu1394f032007-05-06 14:50:22 -070081/* Throw away all D-cached data in specified region without any obligation to
Mike Frysingerded963a2008-10-16 23:01:24 +080082 * write them back. Since the Blackfin ISA does not have an "invalidate"
83 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
84 * could bang on the DTEST MMRs ...
Bryan Wu1394f032007-05-06 14:50:22 -070085 */
Bryan Wu1394f032007-05-06 14:50:22 -070086ENTRY(_blackfin_dcache_invalidate_range)
Mike Frysingerded963a2008-10-16 23:01:24 +080087 do_flush FLUSHINV
Mike Frysinger51be24c2007-06-11 15:31:30 +080088ENDPROC(_blackfin_dcache_invalidate_range)
Bryan Wu1394f032007-05-06 14:50:22 -070089
Mike Frysingerded963a2008-10-16 23:01:24 +080090/* Flush all data cache lines assocoiated with this memory area */
Bryan Wu1394f032007-05-06 14:50:22 -070091ENTRY(_blackfin_dcache_flush_range)
Mike Frysinger78f28a02009-04-10 21:20:19 +000092 do_flush FLUSH, .Ldfr
Mike Frysinger51be24c2007-06-11 15:31:30 +080093ENDPROC(_blackfin_dcache_flush_range)
Bryan Wu1394f032007-05-06 14:50:22 -070094
Mike Frysingerded963a2008-10-16 23:01:24 +080095/* Our headers convert the page structure to an address, so just need to flush
96 * its contents like normal. We know the start address is page aligned (which
97 * greater than our cache alignment), as is the end address. So just jump into
98 * the middle of the dcache flush function.
99 */
Bryan Wu1394f032007-05-06 14:50:22 -0700100ENTRY(_blackfin_dflush_page)
101 P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT);
Mike Frysingerded963a2008-10-16 23:01:24 +0800102 jump .Ldfr;
Mike Frysinger51be24c2007-06-11 15:31:30 +0800103ENDPROC(_blackfin_dflush_page)