Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 2 | * Blackfin cache control code |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 4 | * Copyright 2004-2008 Analog Devices Inc. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 5 | * |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 6 | * Licensed under the GPL-2 or later. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #include <linux/linkage.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | #include <asm/blackfin.h> |
| 11 | #include <asm/cache.h> |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 12 | #include <asm/page.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 13 | |
| 14 | .text |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 15 | |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 16 | /* 05000443 - IFLUSH cannot be last instruction in hardware loop */ |
| 17 | #if ANOMALY_05000443 |
| 18 | # define BROK_FLUSH_INST "IFLUSH" |
| 19 | #else |
| 20 | # define BROK_FLUSH_INST "no anomaly! yeah!" |
| 21 | #endif |
| 22 | |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 23 | /* Since all L1 caches work the same way, we use the same method for flushing |
| 24 | * them. Only the actual flush instruction differs. We write this in asm as |
| 25 | * GCC can be hard to coax into writing nice hardware loops. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 26 | * |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 27 | * Also, we assume the following register setup: |
| 28 | * R0 = start address |
| 29 | * R1 = end address |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 30 | */ |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 31 | .macro do_flush flushins:req label |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 32 | |
Mike Frysinger | 39e96c8 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 33 | R2 = -L1_CACHE_BYTES; |
| 34 | |
| 35 | /* start = (start & -L1_CACHE_BYTES) */ |
| 36 | R0 = R0 & R2; |
| 37 | |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 38 | /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ |
| 39 | R1 += -1; |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 40 | R1 = R1 & R2; |
| 41 | R1 += L1_CACHE_BYTES; |
| 42 | |
| 43 | /* count = (end - start) >> L1_CACHE_SHIFT */ |
| 44 | R2 = R1 - R0; |
| 45 | R2 >>= L1_CACHE_SHIFT; |
| 46 | P1 = R2; |
| 47 | |
| 48 | .ifnb \label |
| 49 | \label : |
| 50 | .endif |
| 51 | P0 = R0; |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 52 | |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 53 | LSETUP (1f, 2f) LC1 = P1; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 54 | 1: |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 55 | .ifeqs "\flushins", BROK_FLUSH_INST |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 56 | \flushins [P0++]; |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 57 | 2: nop; |
| 58 | .else |
Mike Frysinger | 2cf85113 | 2008-10-28 16:34:42 +0800 | [diff] [blame] | 59 | 2: \flushins [P0++]; |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 60 | .endif |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 61 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 62 | RTS; |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 63 | .endm |
| 64 | |
| 65 | /* Invalidate all instruction cache lines assocoiated with this memory area */ |
| 66 | ENTRY(_blackfin_icache_flush_range) |
Sonic Zhang | d7ff1a9 | 2009-03-05 18:26:59 +0800 | [diff] [blame] | 67 | /* |
| 68 | * Walkaround to avoid loading wrong instruction after invalidating icache |
| 69 | * and following sequence is met. |
| 70 | * |
| 71 | * 1) One instruction address is cached in the instruction cache. |
| 72 | * 2) This instruction in SDRAM is changed. |
| 73 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). |
| 74 | * 4) This instruction is executed again, but the old one is loaded. |
| 75 | */ |
| 76 | P0 = R0; |
| 77 | IFLUSH[P0]; |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 78 | do_flush IFLUSH |
Mike Frysinger | 51be24c | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 79 | ENDPROC(_blackfin_icache_flush_range) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 80 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 81 | /* Throw away all D-cached data in specified region without any obligation to |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 82 | * write them back. Since the Blackfin ISA does not have an "invalidate" |
| 83 | * instruction, we use flush/invalidate. Perhaps as a speed optimization we |
| 84 | * could bang on the DTEST MMRs ... |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 85 | */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 86 | ENTRY(_blackfin_dcache_invalidate_range) |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 87 | do_flush FLUSHINV |
Mike Frysinger | 51be24c | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 88 | ENDPROC(_blackfin_dcache_invalidate_range) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 89 | |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 90 | /* Flush all data cache lines assocoiated with this memory area */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 91 | ENTRY(_blackfin_dcache_flush_range) |
Mike Frysinger | 78f28a0 | 2009-04-10 21:20:19 +0000 | [diff] [blame] | 92 | do_flush FLUSH, .Ldfr |
Mike Frysinger | 51be24c | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 93 | ENDPROC(_blackfin_dcache_flush_range) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 94 | |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 95 | /* Our headers convert the page structure to an address, so just need to flush |
| 96 | * its contents like normal. We know the start address is page aligned (which |
| 97 | * greater than our cache alignment), as is the end address. So just jump into |
| 98 | * the middle of the dcache flush function. |
| 99 | */ |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 100 | ENTRY(_blackfin_dflush_page) |
| 101 | P1 = 1 << (PAGE_SHIFT - L1_CACHE_SHIFT); |
Mike Frysinger | ded963a | 2008-10-16 23:01:24 +0800 | [diff] [blame] | 102 | jump .Ldfr; |
Mike Frysinger | 51be24c | 2007-06-11 15:31:30 +0800 | [diff] [blame] | 103 | ENDPROC(_blackfin_dflush_page) |