Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/common/it8152.c |
| 3 | * |
| 4 | * Copyright Compulab Ltd, 2002-2007 |
| 5 | * Mike Rapoport <mike@compulab.co.il> |
| 6 | * |
| 7 | * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c |
| 8 | * (see this file for respective copyrights) |
| 9 | * |
| 10 | * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation |
| 11 | * and demux code. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License version 2 as |
| 15 | * published by the Free Software Foundation. |
| 16 | */ |
| 17 | |
| 18 | #include <linux/sched.h> |
| 19 | #include <linux/kernel.h> |
| 20 | #include <linux/pci.h> |
| 21 | #include <linux/ptrace.h> |
| 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/mm.h> |
| 24 | #include <linux/slab.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/ioport.h> |
| 27 | #include <linux/irq.h> |
| 28 | #include <linux/io.h> |
| 29 | |
| 30 | #include <asm/mach/pci.h> |
| 31 | #include <asm/hardware/it8152.h> |
| 32 | |
| 33 | #define MAX_SLOTS 21 |
| 34 | |
| 35 | static void it8152_mask_irq(unsigned int irq) |
| 36 | { |
| 37 | if (irq >= IT8152_LD_IRQ(0)) { |
| 38 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | |
| 39 | (1 << (irq - IT8152_LD_IRQ(0)))), |
| 40 | IT8152_INTC_LDCNIMR); |
| 41 | } else if (irq >= IT8152_LP_IRQ(0)) { |
| 42 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | |
| 43 | (1 << (irq - IT8152_LP_IRQ(0)))), |
| 44 | IT8152_INTC_LPCNIMR); |
| 45 | } else if (irq >= IT8152_PD_IRQ(0)) { |
| 46 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | |
| 47 | (1 << (irq - IT8152_PD_IRQ(0)))), |
| 48 | IT8152_INTC_PDCNIMR); |
| 49 | } |
| 50 | } |
| 51 | |
| 52 | static void it8152_unmask_irq(unsigned int irq) |
| 53 | { |
| 54 | if (irq >= IT8152_LD_IRQ(0)) { |
| 55 | __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & |
| 56 | ~(1 << (irq - IT8152_LD_IRQ(0)))), |
| 57 | IT8152_INTC_LDCNIMR); |
| 58 | } else if (irq >= IT8152_LP_IRQ(0)) { |
| 59 | __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & |
| 60 | ~(1 << (irq - IT8152_LP_IRQ(0)))), |
| 61 | IT8152_INTC_LPCNIMR); |
| 62 | } else if (irq >= IT8152_PD_IRQ(0)) { |
| 63 | __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & |
| 64 | ~(1 << (irq - IT8152_PD_IRQ(0)))), |
| 65 | IT8152_INTC_PDCNIMR); |
| 66 | } |
| 67 | } |
| 68 | |
| 69 | static inline void it8152_irq(int irq) |
| 70 | { |
| 71 | struct irq_desc *desc; |
| 72 | |
Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 73 | desc = irq_desc + irq; |
| 74 | desc_handle_irq(irq, desc); |
| 75 | } |
| 76 | |
| 77 | static struct irq_chip it8152_irq_chip = { |
| 78 | .name = "it8152", |
| 79 | .ack = it8152_mask_irq, |
| 80 | .mask = it8152_mask_irq, |
| 81 | .unmask = it8152_unmask_irq, |
| 82 | }; |
| 83 | |
| 84 | void it8152_init_irq(void) |
| 85 | { |
| 86 | int irq; |
| 87 | |
| 88 | __raw_writel((0xffff), IT8152_INTC_PDCNIMR); |
| 89 | __raw_writel((0), IT8152_INTC_PDCNIRR); |
| 90 | __raw_writel((0xffff), IT8152_INTC_LPCNIMR); |
| 91 | __raw_writel((0), IT8152_INTC_LPCNIRR); |
| 92 | __raw_writel((0xffff), IT8152_INTC_LDCNIMR); |
| 93 | __raw_writel((0), IT8152_INTC_LDCNIRR); |
| 94 | |
| 95 | for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { |
| 96 | set_irq_chip(irq, &it8152_irq_chip); |
| 97 | set_irq_handler(irq, handle_level_irq); |
| 98 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | void it8152_irq_demux(unsigned int irq, struct irq_desc *desc) |
| 103 | { |
| 104 | int bits_pd, bits_lp, bits_ld; |
| 105 | int i; |
| 106 | |
Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 107 | while (1) { |
| 108 | /* Read all */ |
| 109 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); |
| 110 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); |
| 111 | bits_ld = __raw_readl(IT8152_INTC_LDCNIRR); |
| 112 | |
| 113 | /* Ack */ |
| 114 | __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR); |
| 115 | __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR); |
| 116 | __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR); |
| 117 | |
| 118 | if (!(bits_ld | bits_lp | bits_pd)) { |
| 119 | /* Re-read to guarantee, that there was a moment of |
| 120 | time, when they all three were 0. */ |
| 121 | bits_pd = __raw_readl(IT8152_INTC_PDCNIRR); |
| 122 | bits_lp = __raw_readl(IT8152_INTC_LPCNIRR); |
| 123 | if (!(bits_ld | bits_lp | bits_pd)) |
| 124 | return; |
| 125 | } |
| 126 | |
| 127 | bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1); |
| 128 | while (bits_pd) { |
| 129 | i = __ffs(bits_pd); |
| 130 | it8152_irq(IT8152_PD_IRQ(i)); |
| 131 | bits_pd &= ~(1 << i); |
| 132 | } |
| 133 | |
| 134 | bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1); |
| 135 | while (bits_lp) { |
| 136 | i = __ffs(bits_pd); |
| 137 | it8152_irq(IT8152_LP_IRQ(i)); |
| 138 | bits_lp &= ~(1 << i); |
| 139 | } |
| 140 | |
| 141 | bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1); |
| 142 | while (bits_ld) { |
| 143 | i = __ffs(bits_pd); |
| 144 | it8152_irq(IT8152_LD_IRQ(i)); |
| 145 | bits_ld &= ~(1 << i); |
| 146 | } |
| 147 | } |
| 148 | } |
| 149 | |
| 150 | /* mapping for on-chip devices */ |
| 151 | int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 152 | { |
| 153 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && |
| 154 | (dev->device == PCI_DEVICE_ID_ITE_8152)) { |
| 155 | if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO) |
| 156 | return IT8152_AUDIO_INT; |
| 157 | if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB) |
| 158 | return IT8152_USB_INT; |
| 159 | if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA) |
| 160 | return IT8152_CDMA_INT; |
| 161 | } |
| 162 | |
| 163 | return 0; |
| 164 | } |
| 165 | |
| 166 | static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus, |
| 167 | unsigned int devfn) |
| 168 | { |
| 169 | unsigned long addr = 0; |
| 170 | |
| 171 | if (bus->number == 0) { |
| 172 | if (devfn < PCI_DEVFN(MAX_SLOTS, 0)) |
| 173 | addr = (devfn << 8); |
| 174 | } else |
| 175 | addr = (bus->number << 16) | (devfn << 8); |
| 176 | |
| 177 | return addr; |
| 178 | } |
| 179 | |
| 180 | static int it8152_pci_read_config(struct pci_bus *bus, |
| 181 | unsigned int devfn, int where, |
| 182 | int size, u32 *value) |
| 183 | { |
| 184 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); |
| 185 | u32 v; |
| 186 | int shift; |
| 187 | |
| 188 | shift = (where & 3); |
| 189 | |
| 190 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); |
| 191 | v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift))); |
| 192 | |
| 193 | *value = v; |
| 194 | |
| 195 | return PCIBIOS_SUCCESSFUL; |
| 196 | } |
| 197 | |
| 198 | static int it8152_pci_write_config(struct pci_bus *bus, |
| 199 | unsigned int devfn, int where, |
| 200 | int size, u32 value) |
| 201 | { |
| 202 | unsigned long addr = it8152_pci_dev_base_address(bus, devfn); |
| 203 | u32 v, vtemp, mask = 0; |
| 204 | int shift; |
| 205 | |
| 206 | if (size == 1) |
| 207 | mask = 0xff; |
| 208 | if (size == 2) |
| 209 | mask = 0xffff; |
| 210 | |
| 211 | shift = (where & 3); |
| 212 | |
| 213 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); |
| 214 | vtemp = __raw_readl(IT8152_PCI_CFG_DATA); |
| 215 | |
| 216 | if (mask) |
| 217 | vtemp &= ~(mask << (8 * shift)); |
| 218 | else |
| 219 | vtemp = 0; |
| 220 | |
| 221 | v = (value << (8 * shift)); |
| 222 | __raw_writel((addr + where), IT8152_PCI_CFG_ADDR); |
| 223 | __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA); |
| 224 | |
| 225 | return PCIBIOS_SUCCESSFUL; |
| 226 | } |
| 227 | |
| 228 | static struct pci_ops it8152_ops = { |
| 229 | .read = it8152_pci_read_config, |
| 230 | .write = it8152_pci_write_config, |
| 231 | }; |
| 232 | |
| 233 | static struct resource it8152_io = { |
| 234 | .name = "IT8152 PCI I/O region", |
| 235 | .flags = IORESOURCE_IO, |
| 236 | }; |
| 237 | |
| 238 | static struct resource it8152_mem = { |
| 239 | .name = "IT8152 PCI memory region", |
| 240 | .start = 0x10000000, |
| 241 | .end = 0x13e00000, |
| 242 | .flags = IORESOURCE_MEM, |
| 243 | }; |
| 244 | |
| 245 | /* |
| 246 | * The following functions are needed for DMA bouncing. |
| 247 | * ITE8152 chip can addrees up to 64MByte, so all the devices |
| 248 | * connected to ITE8152 (PCI and USB) should have limited DMA window |
| 249 | */ |
| 250 | |
| 251 | /* |
| 252 | * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all |
| 253 | * other devices. |
| 254 | */ |
| 255 | static int it8152_pci_platform_notify(struct device *dev) |
| 256 | { |
| 257 | if (dev->bus == &pci_bus_type) { |
| 258 | if (dev->dma_mask) |
| 259 | *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET; |
| 260 | dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET; |
| 261 | dmabounce_register_dev(dev, 2048, 4096); |
| 262 | } |
| 263 | return 0; |
| 264 | } |
| 265 | |
| 266 | static int it8152_pci_platform_notify_remove(struct device *dev) |
| 267 | { |
| 268 | if (dev->bus == &pci_bus_type) |
| 269 | dmabounce_unregister_dev(dev); |
| 270 | |
| 271 | return 0; |
| 272 | } |
| 273 | |
| 274 | int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size) |
| 275 | { |
| 276 | dev_dbg(dev, "%s: dma_addr %08x, size %08x\n", |
| 277 | __FUNCTION__, dma_addr, size); |
| 278 | return (dev->bus == &pci_bus_type) && |
| 279 | ((dma_addr + size - PHYS_OFFSET) >= SZ_64M); |
| 280 | } |
| 281 | |
| 282 | /* |
| 283 | * We override these so we properly do dmabounce otherwise drivers |
| 284 | * are able to set the dma_mask to 0xffffffff and we can no longer |
| 285 | * trap bounces. :( |
| 286 | * |
| 287 | * We just return true on everyhing except for < 64MB in which case |
| 288 | * we will fail miseralby and die since we can't handle that case. |
| 289 | */ |
| 290 | int pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
| 291 | { |
Mike Rapoport | a0113a9 | 2007-11-25 08:55:34 +0100 | [diff] [blame] | 292 | dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask); |
Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 293 | if (mask >= PHYS_OFFSET + SZ_64M - 1) |
| 294 | return 0; |
| 295 | |
| 296 | return -EIO; |
| 297 | } |
| 298 | |
| 299 | int |
| 300 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
| 301 | { |
Mike Rapoport | a0113a9 | 2007-11-25 08:55:34 +0100 | [diff] [blame] | 302 | dev_dbg(&dev->dev, "%s: %llx\n", __FUNCTION__, mask); |
Mike Rapoport | a8fc078 | 2007-09-23 15:59:52 +0100 | [diff] [blame] | 303 | if (mask >= PHYS_OFFSET + SZ_64M - 1) |
| 304 | return 0; |
| 305 | |
| 306 | return -EIO; |
| 307 | } |
| 308 | |
| 309 | int __init it8152_pci_setup(int nr, struct pci_sys_data *sys) |
| 310 | { |
| 311 | it8152_io.start = IT8152_IO_BASE + 0x12000; |
| 312 | it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000; |
| 313 | |
| 314 | sys->mem_offset = 0x10000000; |
| 315 | sys->io_offset = IT8152_IO_BASE; |
| 316 | |
| 317 | if (request_resource(&ioport_resource, &it8152_io)) { |
| 318 | printk(KERN_ERR "PCI: unable to allocate IO region\n"); |
| 319 | goto err0; |
| 320 | } |
| 321 | if (request_resource(&iomem_resource, &it8152_mem)) { |
| 322 | printk(KERN_ERR "PCI: unable to allocate memory region\n"); |
| 323 | goto err1; |
| 324 | } |
| 325 | |
| 326 | sys->resource[0] = &it8152_io; |
| 327 | sys->resource[1] = &it8152_mem; |
| 328 | |
| 329 | if (platform_notify || platform_notify_remove) { |
| 330 | printk(KERN_ERR "PCI: Can't use platform_notify\n"); |
| 331 | goto err2; |
| 332 | } |
| 333 | |
| 334 | platform_notify = it8152_pci_platform_notify; |
| 335 | platform_notify_remove = it8152_pci_platform_notify_remove; |
| 336 | |
| 337 | return 1; |
| 338 | |
| 339 | err2: |
| 340 | release_resource(&it8152_io); |
| 341 | err1: |
| 342 | release_resource(&it8152_mem); |
| 343 | err0: |
| 344 | return -EBUSY; |
| 345 | } |
| 346 | |
| 347 | /* |
| 348 | * If we set up a device for bus mastering, we need to check the latency |
| 349 | * timer as we don't have even crappy BIOSes to set it properly. |
| 350 | * The implementation is from arch/i386/pci/i386.c |
| 351 | */ |
| 352 | unsigned int pcibios_max_latency = 255; |
| 353 | |
| 354 | void pcibios_set_master(struct pci_dev *dev) |
| 355 | { |
| 356 | u8 lat; |
| 357 | |
| 358 | /* no need to update on-chip OHCI controller */ |
| 359 | if ((dev->vendor == PCI_VENDOR_ID_ITE) && |
| 360 | (dev->device == PCI_DEVICE_ID_ITE_8152) && |
| 361 | ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)) |
| 362 | return; |
| 363 | |
| 364 | pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); |
| 365 | if (lat < 16) |
| 366 | lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; |
| 367 | else if (lat > pcibios_max_latency) |
| 368 | lat = pcibios_max_latency; |
| 369 | else |
| 370 | return; |
| 371 | printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", |
| 372 | pci_name(dev), lat); |
| 373 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); |
| 374 | } |
| 375 | |
| 376 | |
| 377 | struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys) |
| 378 | { |
| 379 | return pci_scan_bus(nr, &it8152_ops, sys); |
| 380 | } |
| 381 | |