Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Interrupt handler for DaVinci boards. |
| 3 | * |
| 4 | * Copyright (C) 2006 Texas Instruments. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 19 | * |
| 20 | */ |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/init.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/irq.h> |
Russell King | fced80c | 2008-09-06 12:10:45 +0100 | [diff] [blame] | 25 | #include <linux/io.h> |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 26 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 27 | #include <mach/hardware.h> |
Sudhakar Rajashekhara | 9e16469 | 2009-04-14 07:53:02 -0500 | [diff] [blame] | 28 | #include <mach/cputype.h> |
Mark A. Greer | 673dd36 | 2009-04-15 12:40:00 -0700 | [diff] [blame] | 29 | #include <mach/common.h> |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 30 | #include <asm/mach/irq.h> |
| 31 | |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 32 | #define FIQ_REG0_OFFSET 0x0000 |
| 33 | #define FIQ_REG1_OFFSET 0x0004 |
| 34 | #define IRQ_REG0_OFFSET 0x0008 |
| 35 | #define IRQ_REG1_OFFSET 0x000C |
| 36 | #define IRQ_ENT_REG0_OFFSET 0x0018 |
| 37 | #define IRQ_ENT_REG1_OFFSET 0x001C |
| 38 | #define IRQ_INCTL_REG_OFFSET 0x0020 |
| 39 | #define IRQ_EABASE_REG_OFFSET 0x0024 |
| 40 | #define IRQ_INTPRI0_REG_OFFSET 0x0030 |
| 41 | #define IRQ_INTPRI7_REG_OFFSET 0x004C |
| 42 | |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 43 | static inline void davinci_irq_writel(unsigned long value, int offset) |
| 44 | { |
Mark A. Greer | 673dd36 | 2009-04-15 12:40:00 -0700 | [diff] [blame] | 45 | __raw_writel(value, davinci_intc_base + offset); |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 46 | } |
| 47 | |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 48 | static __init void |
| 49 | davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 50 | { |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 51 | struct irq_chip_generic *gc; |
| 52 | struct irq_chip_type *ct; |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 53 | |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 54 | gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq); |
| 55 | ct = gc->chip_types; |
| 56 | ct->chip.irq_ack = irq_gc_ack; |
| 57 | ct->chip.irq_mask = irq_gc_mask_clr_bit; |
| 58 | ct->chip.irq_unmask = irq_gc_mask_set_bit; |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 59 | |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 60 | ct->regs.ack = IRQ_REG0_OFFSET; |
| 61 | ct->regs.mask = IRQ_ENT_REG0_OFFSET; |
| 62 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
| 63 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 64 | } |
| 65 | |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 66 | /* ARM Interrupt Controller Initialization */ |
| 67 | void __init davinci_irq_init(void) |
| 68 | { |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 69 | unsigned i, j; |
Mark A. Greer | 673dd36 | 2009-04-15 12:40:00 -0700 | [diff] [blame] | 70 | const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios; |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 71 | |
Cyril Chemparathy | bd80894 | 2010-05-07 17:06:37 -0400 | [diff] [blame] | 72 | davinci_intc_type = DAVINCI_INTC_TYPE_AINTC; |
| 73 | davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K); |
| 74 | if (WARN_ON(!davinci_intc_base)) |
| 75 | return; |
| 76 | |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 77 | /* Clear all interrupt requests */ |
| 78 | davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); |
| 79 | davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); |
| 80 | davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); |
| 81 | davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); |
| 82 | |
| 83 | /* Disable all interrupts */ |
| 84 | davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET); |
| 85 | davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET); |
| 86 | |
| 87 | /* Interrupts disabled immediately, IRQ entry reflects all */ |
| 88 | davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET); |
| 89 | |
| 90 | /* we don't use the hardware vector table, just its entry addresses */ |
| 91 | davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET); |
| 92 | |
| 93 | /* Clear all interrupt requests */ |
| 94 | davinci_irq_writel(~0x0, FIQ_REG0_OFFSET); |
| 95 | davinci_irq_writel(~0x0, FIQ_REG1_OFFSET); |
| 96 | davinci_irq_writel(~0x0, IRQ_REG0_OFFSET); |
| 97 | davinci_irq_writel(~0x0, IRQ_REG1_OFFSET); |
| 98 | |
| 99 | for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) { |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 100 | u32 pri; |
| 101 | |
Sudhakar Rajashekhara | 9e16469 | 2009-04-14 07:53:02 -0500 | [diff] [blame] | 102 | for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++) |
| 103 | pri |= (*davinci_def_priorities & 0x07) << j; |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 104 | davinci_irq_writel(pri, i); |
| 105 | } |
| 106 | |
Thomas Gleixner | aac4dd1 | 2011-04-15 11:19:57 +0200 | [diff] [blame] | 107 | for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04) |
| 108 | davinci_alloc_gc(davinci_intc_base + j, i, 32); |
| 109 | |
| 110 | irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq); |
Kevin Hilman | 7c6337e | 2007-04-30 19:37:19 +0100 | [diff] [blame] | 111 | } |