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LeafOS / LeafOS-Devices / android_kernel_realme_mt6785 / 22905f775dd6a8b73be99826dcad07ceec00244b / . / arch / m32r / lib / ashxdi3.S
blob: 78effca9d97adc010d8194169a4529d34b07ba12 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * linux/arch/m32r/lib/ashxdi3.S
3 *
4 * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
5 *
6 */
7/* $Id$ */
8
9#include <linux/config.h>
10
11;
12; input (r0,r1) src
13; input r2 shift val
14; r3 scratch
15; output (r0,r1)
16;
17
18#ifdef CONFIG_ISA_DUAL_ISSUE
19
20#ifndef __LITTLE_ENDIAN__
21
22 .text
23 .align 4
24 .globl __ashrdi3
25__ashrdi3:
26 cmpz r2 || ldi r3, #32
27 jc r14 || cmpu r2, r3
28 bc 1f
29 ; case 32 =< shift
30 mv r1, r0 || srai r0, #31
31 addi r2, #-32
32 sra r1, r2
33 jmp r14
34 .fillinsn
351: ; case shift <32
36 mv r3, r0 || srl r1, r2
37 sra r0, r2 || neg r2, r2
38 sll r3, r2
39 or r1, r3 || jmp r14
40
41 .align 4
42 .globl __ashldi3
43 .globl __lshldi3
44__ashldi3:
45__lshldi3:
46 cmpz r2 || ldi r3, #32
47 jc r14 || cmpu r2, r3
48 bc 1f
49 ; case 32 =< shift
50 mv r0, r1 || addi r2, #-32
51 sll r0, r2 || ldi r1, #0
52 jmp r14
53 .fillinsn
541: ; case shift <32
55 mv r3, r1 || sll r0, r2
56 sll r1, r2 || neg r2, r2
57 srl r3, r2
58 or r0, r3 || jmp r14
59
60 .align 4
61 .globl __lshrdi3
62__lshrdi3:
63 cmpz r2 || ldi r3, #32
64 jc r14 || cmpu r2, r3
65 bc 1f
66 ; case 32 =< shift
67 mv r1, r0 || addi r2, #-32
68 ldi r0, #0 || srl r1, r2
69 jmp r14
70 .fillinsn
711: ; case shift <32
72 mv r3, r0 || srl r1, r2
73 srl r0, r2 || neg r2, r2
74 sll r3, r2
75 or r1, r3 || jmp r14
76
77#else /* LITTLE_ENDIAN */
78
79 .text
80 .align 4
81 .globl __ashrdi3
82__ashrdi3:
83 cmpz r2 || ldi r3, #32
84 jc r14 || cmpu r2, r3
85 bc 1f
86 ; case 32 =< shift
87 mv r0, r1 || srai r1, #31
88 addi r2, #-32
89 sra r0, r2
90 jmp r14
91 .fillinsn
921: ; case shift <32
93 mv r3, r1 || srl r0, r2
94 sra r1, r2 || neg r2, r2
95 sll r3, r2
96 or r0, r3 || jmp r14
97
98 .align 4
99 .globl __ashldi3
100 .globl __lshldi3
101__ashldi3:
102__lshldi3:
103 cmpz r2 || ldi r3, #32
104 jc r14 || cmpu r2, r3
105 bc 1f
106 ; case 32 =< shift
107 mv r1, r0 || addi r2, #-32
108 sll r1, r2 || ldi r0, #0
109 jmp r14
110 .fillinsn
1111: ; case shift <32
112 mv r3, r0 || sll r1, r2
113 sll r0, r2 || neg r2, r2
114 srl r3, r2
115 or r1, r3 || jmp r14
116
117 .align 4
118 .globl __lshrdi3
119__lshrdi3:
120 cmpz r2 || ldi r3, #32
121 jc r14 || cmpu r2, r3
122 bc 1f
123 ; case 32 =< shift
124 mv r0, r1 || addi r2, #-32
125 ldi r1, #0 || srl r0, r2
126 jmp r14
127 .fillinsn
1281: ; case shift <32
129 mv r3, r1 || srl r0, r2
130 srl r1, r2 || neg r2, r2
131 sll r3, r2
132 or r0, r3 || jmp r14
133
134#endif
135
136#else /* not CONFIG_ISA_DUAL_ISSUE */
137
138#ifndef __LITTLE_ENDIAN__
139
140 .text
141 .align 4
142 .globl __ashrdi3
143__ashrdi3:
144 beqz r2, 2f
145 cmpui r2, #32
146 bc 1f
147 ; case 32 =< shift
148 mv r1, r0
149 srai r0, #31
150 addi r2, #-32
151 sra r1, r2
152 jmp r14
153 .fillinsn
1541: ; case shift <32
155 mv r3, r0
156 srl r1, r2
157 sra r0, r2
158 neg r2, r2
159 sll r3, r2
160 or r1, r3
161 .fillinsn
1622:
163 jmp r14
164
165 .align 4
166 .globl __ashldi3
167 .globl __lshldi3
168__ashldi3:
169__lshldi3:
170 beqz r2, 2f
171 cmpui r2, #32
172 bc 1f
173 ; case 32 =< shift
174 mv r0, r1
175 addi r2, #-32
176 sll r0, r2
177 ldi r1, #0
178 jmp r14
179 .fillinsn
1801: ; case shift <32
181 mv r3, r1
182 sll r0, r2
183 sll r1, r2
184 neg r2, r2
185 srl r3, r2
186 or r0, r3
187 .fillinsn
1882:
189 jmp r14
190
191 .align 4
192 .globl __lshrdi3
193__lshrdi3:
194 beqz r2, 2f
195 cmpui r2, #32
196 bc 1f
197 ; case 32 =< shift
198 mv r1, r0
199 ldi r0, #0
200 addi r2, #-32
201 srl r1, r2
202 jmp r14
203 .fillinsn
2041: ; case shift <32
205 mv r3, r0
206 srl r1, r2
207 srl r0, r2
208 neg r2, r2
209 sll r3, r2
210 or r1, r3
211 .fillinsn
2122:
213 jmp r14
214
215#else
216
217 .text
218 .align 4
219 .globl __ashrdi3
220__ashrdi3:
221 beqz r2, 2f
222 cmpui r2, #32
223 bc 1f
224 ; case 32 =< shift
225 mv r0, r1
226 srai r1, #31
227 addi r2, #-32
228 sra r0, r2
229 jmp r14
230 .fillinsn
2311: ; case shift <32
232 mv r3, r1
233 srl r0, r2
234 sra r1, r2
235 neg r2, r2
236 sll r3, r2
237 or r0, r3
238 .fillinsn
2392:
240 jmp r14
241
242 .align 4
243 .globl __ashldi3
244 .globl __lshldi3
245__ashldi3:
246__lshldi3:
247 beqz r2, 2f
248 cmpui r2, #32
249 bc 1f
250 ; case 32 =< shift
251 mv r1, r0
252 addi r2, #-32
253 sll r1, r2
254 ldi r0, #0
255 jmp r14
256 .fillinsn
2571: ; case shift <32
258 mv r3, r0
259 sll r1, r2
260 sll r0, r2
261 neg r2, r2
262 srl r3, r2
263 or r1, r3
264 .fillinsn
2652:
266 jmp r14
267
268 .align 4
269 .globl __lshrdi3
270__lshrdi3:
271 beqz r2, 2f
272 cmpui r2, #32
273 bc 1f
274 ; case 32 =< shift
275 mv r0, r1
276 ldi r1, #0
277 addi r2, #-32
278 srl r0, r2
279 jmp r14
280 .fillinsn
2811: ; case shift <32
282 mv r3, r1
283 srl r0, r2
284 srl r1, r2
285 neg r2, r2
286 sll r3, r2
287 or r0, r3
288 .fillinsn
2892:
290 jmp r14
291
292#endif
293
294#endif /* not CONFIG_ISA_DUAL_ISSUE */
295
296 .end
297