| Mike Frysinger | b03f203 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1 | /* mach/dma.h - arch-specific DMA defines |
| 2 | * |
| 3 | * Copyright 2004-2008 Analog Devices Inc. |
| 4 | * |
| 5 | * Licensed under the GPL-2 or later. |
| 6 | */ |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | |
| 8 | #ifndef _MACH_DMA_H_ |
| 9 | #define _MACH_DMA_H_ |
| 10 | |
| Mike Frysinger | 211daf9 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 11 | #define MAX_DMA_CHANNELS 36 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 12 | |
| Mike Frysinger | c9e0020 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 13 | /* [#4267] IMDMA channels have no PERIPHERAL_MAP MMR */ |
| 14 | #define MAX_DMA_SUSPEND_CHANNELS 32 |
| 15 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 16 | #define CH_PPI0 0 |
| 17 | #define CH_PPI (CH_PPI0) |
| 18 | #define CH_PPI1 1 |
| 19 | #define CH_SPORT0_RX 12 |
| 20 | #define CH_SPORT0_TX 13 |
| 21 | #define CH_SPORT1_RX 14 |
| 22 | #define CH_SPORT1_TX 15 |
| 23 | #define CH_SPI 16 |
| 24 | #define CH_UART_RX 17 |
| 25 | #define CH_UART_TX 18 |
| 26 | #define CH_MEM_STREAM0_DEST 24 /* TX */ |
| 27 | #define CH_MEM_STREAM0_SRC 25 /* RX */ |
| 28 | #define CH_MEM_STREAM1_DEST 26 /* TX */ |
| 29 | #define CH_MEM_STREAM1_SRC 27 /* RX */ |
| 30 | #define CH_MEM_STREAM2_DEST 28 |
| 31 | #define CH_MEM_STREAM2_SRC 29 |
| Michael Hennerich | 92322da | 2008-05-17 15:59:11 +0800 | [diff] [blame] | 32 | #define CH_MEM_STREAM3_DEST 30 |
| 33 | #define CH_MEM_STREAM3_SRC 31 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 34 | #define CH_IMEM_STREAM0_DEST 32 |
| 35 | #define CH_IMEM_STREAM0_SRC 33 |
| Michael Hennerich | 92322da | 2008-05-17 15:59:11 +0800 | [diff] [blame] | 36 | #define CH_IMEM_STREAM1_DEST 34 |
| 37 | #define CH_IMEM_STREAM1_SRC 35 |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 38 | |
| Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 39 | #endif |