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Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +01001#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07002#include <linux/kernel.h>
3#include <linux/init.h>
Ingo Molnaredc05e62008-02-18 03:30:47 +01004
Linus Torvalds1da177e2005-04-16 15:20:36 -07005#include <asm/processor.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07006#include <asm/e820.h>
Jesper Juhl52f4a912006-03-23 02:59:50 -08007#include <asm/mtrr.h>
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +01008#include <asm/msr.h>
Ingo Molnaredc05e62008-02-18 03:30:47 +01009
Linus Torvalds1da177e2005-04-16 15:20:36 -070010#include "cpu.h"
11
12#ifdef CONFIG_X86_OOSTORE
13
Magnus Dammb4af3f72006-09-26 10:52:36 +020014static u32 __cpuinit power2(u32 x)
Linus Torvalds1da177e2005-04-16 15:20:36 -070015{
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010016 u32 s = 1;
Ingo Molnaredc05e62008-02-18 03:30:47 +010017
18 while (s <= x)
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010019 s <<= 1;
Ingo Molnaredc05e62008-02-18 03:30:47 +010020
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010021 return s >>= 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070022}
23
24
25/*
Ingo Molnaredc05e62008-02-18 03:30:47 +010026 * Set up an actual MCR
Linus Torvalds1da177e2005-04-16 15:20:36 -070027 */
Magnus Dammb4af3f72006-09-26 10:52:36 +020028static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
Linus Torvalds1da177e2005-04-16 15:20:36 -070029{
30 u32 lo, hi;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010031
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 hi = base & ~0xFFF;
33 lo = ~(size-1); /* Size is a power of 2 so this makes a mask */
34 lo &= ~0xFFF; /* Remove the ctrl value bits */
35 lo |= key; /* Attribute we wish to set */
36 wrmsr(reg+MSR_IDT_MCR0, lo, hi);
37 mtrr_centaur_report_mcr(reg, lo, hi); /* Tell the mtrr driver */
38}
39
40/*
Ingo Molnaredc05e62008-02-18 03:30:47 +010041 * Figure what we can cover with MCR's
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 *
Ingo Molnaredc05e62008-02-18 03:30:47 +010043 * Shortcut: We know you can't put 4Gig of RAM on a winchip
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 */
Ingo Molnaredc05e62008-02-18 03:30:47 +010045static u32 __cpuinit ramtop(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070046{
Linus Torvalds1da177e2005-04-16 15:20:36 -070047 u32 clip = 0xFFFFFFFFUL;
Ingo Molnaredc05e62008-02-18 03:30:47 +010048 u32 top = 0;
49 int i;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010050
Linus Torvalds1da177e2005-04-16 15:20:36 -070051 for (i = 0; i < e820.nr_map; i++) {
52 unsigned long start, end;
53
54 if (e820.map[i].addr > 0xFFFFFFFFUL)
55 continue;
56 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +010057 * Don't MCR over reserved space. Ignore the ISA hole
58 * we frob around that catastrophe already
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 */
Ingo Molnaredc05e62008-02-18 03:30:47 +010060 if (e820.map[i].type == E820_RESERVED) {
61 if (e820.map[i].addr >= 0x100000UL &&
62 e820.map[i].addr < clip)
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 clip = e820.map[i].addr;
64 continue;
65 }
66 start = e820.map[i].addr;
67 end = e820.map[i].addr + e820.map[i].size;
68 if (start >= end)
69 continue;
70 if (end > top)
71 top = end;
72 }
Ingo Molnaredc05e62008-02-18 03:30:47 +010073 /*
74 * Everything below 'top' should be RAM except for the ISA hole.
75 * Because of the limited MCR's we want to map NV/ACPI into our
76 * MCR range for gunk in RAM
77 *
78 * Clip might cause us to MCR insufficient RAM but that is an
79 * acceptable failure mode and should only bite obscure boxes with
80 * a VESA hole at 15Mb
81 *
82 * The second case Clip sometimes kicks in is when the EBDA is marked
83 * as reserved. Again we fail safe with reasonable results
84 */
85 if (top > clip)
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +010086 top = clip;
87
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 return top;
89}
90
91/*
Ingo Molnaredc05e62008-02-18 03:30:47 +010092 * Compute a set of MCR's to give maximum coverage
Linus Torvalds1da177e2005-04-16 15:20:36 -070093 */
Magnus Dammb4af3f72006-09-26 10:52:36 +020094static int __cpuinit centaur_mcr_compute(int nr, int key)
Linus Torvalds1da177e2005-04-16 15:20:36 -070095{
96 u32 mem = ramtop();
97 u32 root = power2(mem);
98 u32 base = root;
99 u32 top = root;
100 u32 floor = 0;
101 int ct = 0;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100102
Ingo Molnaredc05e62008-02-18 03:30:47 +0100103 while (ct < nr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 u32 fspace = 0;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100105 u32 high;
106 u32 low;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700107
108 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100109 * Find the largest block we will fill going upwards
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110 */
Ingo Molnaredc05e62008-02-18 03:30:47 +0100111 high = power2(mem-top);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700112
113 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100114 * Find the largest block we will fill going downwards
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 */
Ingo Molnaredc05e62008-02-18 03:30:47 +0100116 low = base/2;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
118 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100119 * Don't fill below 1Mb going downwards as there
120 * is an ISA hole in the way.
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100121 */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100122 if (base <= 1024*1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 low = 0;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100124
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100126 * See how much space we could cover by filling below
127 * the ISA hole
Linus Torvalds1da177e2005-04-16 15:20:36 -0700128 */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100129
130 if (floor == 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 fspace = 512*1024;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100132 else if (floor == 512*1024)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 fspace = 128*1024;
134
135 /* And forget ROM space */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100136
Linus Torvalds1da177e2005-04-16 15:20:36 -0700137 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100138 * Now install the largest coverage we get
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139 */
Ingo Molnaredc05e62008-02-18 03:30:47 +0100140 if (fspace > high && fspace > low) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141 centaur_mcr_insert(ct, floor, fspace, key);
142 floor += fspace;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100143 } else if (high > low) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700144 centaur_mcr_insert(ct, top, high, key);
145 top += high;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100146 } else if (low > 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147 base -= low;
148 centaur_mcr_insert(ct, base, low, key);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100149 } else
150 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151 ct++;
152 }
153 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100154 * We loaded ct values. We now need to set the mask. The caller
155 * must do this bit.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700156 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700157 return ct;
158}
159
Magnus Dammb4af3f72006-09-26 10:52:36 +0200160static void __cpuinit centaur_create_optimal_mcr(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161{
Ingo Molnaredc05e62008-02-18 03:30:47 +0100162 int used;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700164
165 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100166 * Allocate up to 6 mcrs to mark as much of ram as possible
167 * as write combining and weak write ordered.
168 *
169 * To experiment with: Linux never uses stack operations for
170 * mmio spaces so we could globally enable stack operation wc
171 *
172 * Load the registers with type 31 - full write combining, all
173 * writes weakly ordered.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700174 */
Ingo Molnaredc05e62008-02-18 03:30:47 +0100175 used = centaur_mcr_compute(6, 31);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100176
Ingo Molnaredc05e62008-02-18 03:30:47 +0100177 /*
178 * Wipe unused MCRs
179 */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100180 for (i = used; i < 8; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 wrmsr(MSR_IDT_MCR0+i, 0, 0);
182}
183
Magnus Dammb4af3f72006-09-26 10:52:36 +0200184static void __cpuinit winchip2_create_optimal_mcr(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185{
186 u32 lo, hi;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100187 int used;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 int i;
189
190 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100191 * Allocate up to 6 mcrs to mark as much of ram as possible
192 * as write combining, weak store ordered.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 *
Ingo Molnaredc05e62008-02-18 03:30:47 +0100194 * Load the registers with type 25
195 * 8 - weak write ordering
196 * 16 - weak read ordering
197 * 1 - write combining
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198 */
Ingo Molnaredc05e62008-02-18 03:30:47 +0100199 used = centaur_mcr_compute(6, 25);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100200
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100202 * Mark the registers we are using.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700204 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100205 for (i = 0; i < used; i++)
206 lo |= 1<<(9+i);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700207 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100208
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 /*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100210 * Wipe unused MCRs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700211 */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100212
213 for (i = used; i < 8; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214 wrmsr(MSR_IDT_MCR0+i, 0, 0);
215}
216
217/*
Ingo Molnaredc05e62008-02-18 03:30:47 +0100218 * Handle the MCR key on the Winchip 2.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700219 */
Magnus Dammb4af3f72006-09-26 10:52:36 +0200220static void __cpuinit winchip2_unprotect_mcr(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221{
222 u32 lo, hi;
223 u32 key;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100224
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100226 lo &= ~0x1C0; /* blank bits 8-6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700227 key = (lo>>17) & 7;
228 lo |= key<<6; /* replace with unlock key */
229 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
230}
231
Magnus Dammb4af3f72006-09-26 10:52:36 +0200232static void __cpuinit winchip2_protect_mcr(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700233{
234 u32 lo, hi;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100235
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100237 lo &= ~0x1C0; /* blank bits 8-6 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
239}
240#endif /* CONFIG_X86_OOSTORE */
241
242#define ACE_PRESENT (1 << 6)
243#define ACE_ENABLED (1 << 7)
244#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
245
246#define RNG_PRESENT (1 << 2)
247#define RNG_ENABLED (1 << 3)
248#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
249
Magnus Dammb4af3f72006-09-26 10:52:36 +0200250static void __cpuinit init_c3(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251{
252 u32 lo, hi;
253
254 /* Test for Centaur Extended Feature Flags presence */
255 if (cpuid_eax(0xC0000000) >= 0xC0000001) {
256 u32 tmp = cpuid_edx(0xC0000001);
257
258 /* enable ACE unit, if present and disabled */
259 if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100260 rdmsr(MSR_VIA_FCR, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261 lo |= ACE_FCR; /* enable ACE unit */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100262 wrmsr(MSR_VIA_FCR, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263 printk(KERN_INFO "CPU: Enabled ACE h/w crypto\n");
264 }
265
266 /* enable RNG unit, if present and disabled */
267 if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100268 rdmsr(MSR_VIA_RNG, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269 lo |= RNG_ENABLE; /* enable RNG unit */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100270 wrmsr(MSR_VIA_RNG, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271 printk(KERN_INFO "CPU: Enabled h/w RNG\n");
272 }
273
274 /* store Centaur Extended Feature Flags as
275 * word 5 of the CPU capability bit array
276 */
277 c->x86_capability[5] = cpuid_edx(0xC0000001);
278 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100279#ifdef CONFIG_X86_32
Simon Arlott27b46d72007-10-20 01:13:56 +0200280 /* Cyrix III family needs CX8 & PGE explicitly enabled. */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100281 if (c->x86_model >= 6 && c->x86_model <= 9) {
282 rdmsr(MSR_VIA_FCR, lo, hi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283 lo |= (1<<1 | 1<<7);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100284 wrmsr(MSR_VIA_FCR, lo, hi);
Ingo Molnare1a94a92008-02-26 08:51:22 +0100285 set_cpu_cap(c, X86_FEATURE_CX8);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 }
287
288 /* Before Nehemiah, the C3's had 3dNOW! */
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100289 if (c->x86_model >= 6 && c->x86_model < 9)
Ingo Molnare1a94a92008-02-26 08:51:22 +0100290 set_cpu_cap(c, X86_FEATURE_3DNOW);
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100291#endif
292 if (c->x86 == 0x6 && c->x86_model >= 0xf) {
293 c->x86_cache_alignment = c->x86_clflush_size * 2;
294 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
295 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296
Borislav Petkov27c13ec2009-11-21 14:01:45 +0100297 cpu_detect_cache_sizes(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298}
299
Ingo Molnaredc05e62008-02-18 03:30:47 +0100300enum {
301 ECX8 = 1<<1,
302 EIERRINT = 1<<2,
303 DPM = 1<<3,
304 DMCE = 1<<4,
305 DSTPCLK = 1<<5,
306 ELINEAR = 1<<6,
307 DSMC = 1<<7,
308 DTLOCK = 1<<8,
309 EDCTLB = 1<<8,
310 EMMX = 1<<9,
311 DPDC = 1<<11,
312 EBRPRED = 1<<12,
313 DIC = 1<<13,
314 DDC = 1<<14,
315 DNA = 1<<15,
316 ERETSTK = 1<<16,
317 E2MMX = 1<<19,
318 EAMD3D = 1<<20,
319};
320
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200321static void __cpuinit early_init_centaur(struct cpuinfo_x86 *c)
322{
323 switch (c->x86) {
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100324#ifdef CONFIG_X86_32
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200325 case 5:
326 /* Emulate MTRRs using Centaur's MCR. */
327 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
328 break;
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100329#endif
330 case 6:
331 if (c->x86_model >= 0xf)
332 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
333 break;
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200334 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100335#ifdef CONFIG_X86_64
336 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
337#endif
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200338}
339
Magnus Dammb4af3f72006-09-26 10:52:36 +0200340static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341{
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100342#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343 char *name;
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100344 u32 fcr_set = 0;
345 u32 fcr_clr = 0;
346 u32 lo, hi, newlo;
347 u32 aa, bb, cc, dd;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348
Ingo Molnaredc05e62008-02-18 03:30:47 +0100349 /*
350 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
351 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
352 */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100353 clear_cpu_cap(c, 0*32+31);
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100354#endif
355 early_init_centaur(c);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 switch (c->x86) {
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100357#ifdef CONFIG_X86_32
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100358 case 5:
Ingo Molnaredc05e62008-02-18 03:30:47 +0100359 switch (c->x86_model) {
360 case 4:
361 name = "C6";
362 fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
363 fcr_clr = DPDC;
364 printk(KERN_NOTICE "Disabling bugged TSC.\n");
Ingo Molnare1a94a92008-02-26 08:51:22 +0100365 clear_cpu_cap(c, X86_FEATURE_TSC);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366#ifdef CONFIG_X86_OOSTORE
Ingo Molnaredc05e62008-02-18 03:30:47 +0100367 centaur_create_optimal_mcr();
368 /*
369 * Enable:
370 * write combining on non-stack, non-string
371 * write combining on string, all types
372 * weak write ordering
373 *
374 * The C6 original lacks weak read order
375 *
376 * Note 0x120 is write only on Winchip 1
377 */
378 wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0);
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100379#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380 break;
Ingo Molnaredc05e62008-02-18 03:30:47 +0100381 case 8:
382 switch (c->x86_mask) {
383 default:
384 name = "2";
385 break;
386 case 7 ... 9:
387 name = "2A";
388 break;
389 case 10 ... 15:
390 name = "2B";
391 break;
392 }
393 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
394 E2MMX|EAMD3D;
395 fcr_clr = DPDC;
396#ifdef CONFIG_X86_OOSTORE
397 winchip2_unprotect_mcr();
398 winchip2_create_optimal_mcr();
399 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
400 /*
401 * Enable:
402 * write combining on non-stack, non-string
403 * write combining on string, all types
404 * weak write ordering
405 */
406 lo |= 31;
407 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
408 winchip2_protect_mcr();
409#endif
410 break;
411 case 9:
412 name = "3";
413 fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
414 E2MMX|EAMD3D;
415 fcr_clr = DPDC;
416#ifdef CONFIG_X86_OOSTORE
417 winchip2_unprotect_mcr();
418 winchip2_create_optimal_mcr();
419 rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
420 /*
421 * Enable:
422 * write combining on non-stack, non-string
423 * write combining on string, all types
424 * weak write ordering
425 */
426 lo |= 31;
427 wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
428 winchip2_protect_mcr();
429#endif
430 break;
431 default:
432 name = "??";
433 }
434
435 rdmsr(MSR_IDT_FCR1, lo, hi);
436 newlo = (lo|fcr_set) & (~fcr_clr);
437
438 if (newlo != lo) {
439 printk(KERN_INFO "Centaur FCR was 0x%X now 0x%X\n",
440 lo, newlo);
441 wrmsr(MSR_IDT_FCR1, newlo, hi);
442 } else {
443 printk(KERN_INFO "Centaur FCR is 0x%X\n", lo);
444 }
445 /* Emulate MTRRs using Centaur's MCR. */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100446 set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100447 /* Report CX8 */
Ingo Molnare1a94a92008-02-26 08:51:22 +0100448 set_cpu_cap(c, X86_FEATURE_CX8);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100449 /* Set 3DNow! on Winchip 2 and above. */
450 if (c->x86_model >= 8)
Ingo Molnare1a94a92008-02-26 08:51:22 +0100451 set_cpu_cap(c, X86_FEATURE_3DNOW);
Ingo Molnaredc05e62008-02-18 03:30:47 +0100452 /* See if we can find out some more. */
453 if (cpuid_eax(0x80000000) >= 0x80000005) {
454 /* Yes, we can. */
455 cpuid(0x80000005, &aa, &bb, &cc, &dd);
456 /* Add L1 data and code cache sizes. */
457 c->x86_cache_size = (cc>>24)+(dd>>24);
458 }
459 sprintf(c->x86_model_id, "WinChip %s", name);
460 break;
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100461#endif
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100462 case 6:
Ingo Molnaredc05e62008-02-18 03:30:47 +0100463 init_c3(c);
464 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465 }
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100466#ifdef CONFIG_X86_64
467 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
468#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700469}
470
Ingo Molnaredc05e62008-02-18 03:30:47 +0100471static unsigned int __cpuinit
472centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700473{
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100474#ifdef CONFIG_X86_32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 /* VIA C3 CPUs (670-68F) need further shifting. */
476 if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
477 size >>= 8;
478
Ingo Molnaredc05e62008-02-18 03:30:47 +0100479 /*
480 * There's also an erratum in Nehemiah stepping 1, which
481 * returns '65KB' instead of '64KB'
482 * - Note, it seems this may only be in engineering samples.
483 */
484 if ((c->x86 == 6) && (c->x86_model == 9) &&
485 (c->x86_mask == 1) && (size == 65))
Paolo Ciarrocchi29a99942008-02-17 23:30:23 +0100486 size -= 1;
Sebastian Andrzej Siewior48f4c482009-03-14 12:24:02 +0100487#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 return size;
489}
490
Jan Beulich02dde8b2009-03-12 12:08:49 +0000491static const struct cpu_dev __cpuinitconst centaur_cpu_dev = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492 .c_vendor = "Centaur",
493 .c_ident = { "CentaurHauls" },
Yinghai Lu5fef55f2008-09-04 21:09:43 +0200494 .c_early_init = early_init_centaur,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700495 .c_init = init_centaur,
496 .c_size_cache = centaur_size_cache,
Yinghai Lu10a434f2008-09-04 21:09:45 +0200497 .c_x86_vendor = X86_VENDOR_CENTAUR,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498};
499
Yinghai Lu10a434f2008-09-04 21:09:45 +0200500cpu_dev_register(centaur_cpu_dev);