Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License |
| 6 | * as published by the Free Software Foundation, version 2. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, but |
| 9 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
| 11 | * NON INFRINGEMENT. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * Linux interrupt vectors. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/linkage.h> |
| 18 | #include <linux/errno.h> |
| 19 | #include <linux/unistd.h> |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 20 | #include <linux/init.h> |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 21 | #include <asm/ptrace.h> |
| 22 | #include <asm/thread_info.h> |
| 23 | #include <asm/irqflags.h> |
| 24 | #include <asm/asm-offsets.h> |
| 25 | #include <asm/types.h> |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 26 | #include <asm/traps.h> |
Chris Metcalf | 2858f85 | 2012-03-29 16:11:09 -0400 | [diff] [blame] | 27 | #include <asm/signal.h> |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 28 | #include <hv/hypervisor.h> |
| 29 | #include <arch/abi.h> |
| 30 | #include <arch/interrupts.h> |
| 31 | #include <arch/spr_def.h> |
| 32 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 33 | #define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg) |
| 34 | |
| 35 | #define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR) |
| 36 | |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 37 | #if CONFIG_KERNEL_PL == 1 || CONFIG_KERNEL_PL == 2 |
| 38 | /* |
| 39 | * Set "result" non-zero if ex1 holds the PL of the kernel |
| 40 | * (with or without ICS being set). Note this works only |
| 41 | * because we never find the PL at level 3. |
| 42 | */ |
| 43 | # define IS_KERNEL_EX1(result, ex1) andi result, ex1, CONFIG_KERNEL_PL |
| 44 | #else |
| 45 | # error Recode IS_KERNEL_EX1 for CONFIG_KERNEL_PL |
| 46 | #endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 47 | |
| 48 | .macro push_reg reg, ptr=sp, delta=-8 |
| 49 | { |
| 50 | st \ptr, \reg |
| 51 | addli \ptr, \ptr, \delta |
| 52 | } |
| 53 | .endm |
| 54 | |
| 55 | .macro pop_reg reg, ptr=sp, delta=8 |
| 56 | { |
| 57 | ld \reg, \ptr |
| 58 | addli \ptr, \ptr, \delta |
| 59 | } |
| 60 | .endm |
| 61 | |
| 62 | .macro pop_reg_zero reg, zreg, ptr=sp, delta=8 |
| 63 | { |
| 64 | move \zreg, zero |
| 65 | ld \reg, \ptr |
| 66 | addi \ptr, \ptr, \delta |
| 67 | } |
| 68 | .endm |
| 69 | |
| 70 | .macro push_extra_callee_saves reg |
| 71 | PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51)) |
| 72 | push_reg r51, \reg |
| 73 | push_reg r50, \reg |
| 74 | push_reg r49, \reg |
| 75 | push_reg r48, \reg |
| 76 | push_reg r47, \reg |
| 77 | push_reg r46, \reg |
| 78 | push_reg r45, \reg |
| 79 | push_reg r44, \reg |
| 80 | push_reg r43, \reg |
| 81 | push_reg r42, \reg |
| 82 | push_reg r41, \reg |
| 83 | push_reg r40, \reg |
| 84 | push_reg r39, \reg |
| 85 | push_reg r38, \reg |
| 86 | push_reg r37, \reg |
| 87 | push_reg r36, \reg |
| 88 | push_reg r35, \reg |
| 89 | push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34) |
| 90 | .endm |
| 91 | |
| 92 | .macro panic str |
| 93 | .pushsection .rodata, "a" |
| 94 | 1: |
| 95 | .asciz "\str" |
| 96 | .popsection |
| 97 | { |
| 98 | moveli r0, hw2_last(1b) |
| 99 | } |
| 100 | { |
| 101 | shl16insli r0, r0, hw1(1b) |
| 102 | } |
| 103 | { |
| 104 | shl16insli r0, r0, hw0(1b) |
| 105 | jal panic |
| 106 | } |
| 107 | .endm |
| 108 | |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 109 | /* |
| 110 | * Unalign data exception fast handling: In order to handle |
| 111 | * unaligned data access, a fast JIT version is generated and stored |
| 112 | * in a specific area in user space. We first need to do a quick poke |
| 113 | * to see if the JIT is available. We use certain bits in the fault |
| 114 | * PC (3 to 9 is used for 16KB page size) as index to address the JIT |
| 115 | * code area. The first 64bit word is the fault PC, and the 2nd one is |
| 116 | * the fault bundle itself. If these 2 words both match, then we |
| 117 | * directly "iret" to JIT code. If not, a slow path is invoked to |
| 118 | * generate new JIT code. Note: the current JIT code WILL be |
| 119 | * overwritten if it existed. So, ideally we can handle 128 unalign |
| 120 | * fixups via JIT. For lookup efficiency and to effectively support |
| 121 | * tight loops with multiple unaligned reference, a simple |
| 122 | * direct-mapped cache is used. |
| 123 | * |
| 124 | * SPR_EX_CONTEXT_K_0 is modified to return to JIT code. |
| 125 | * SPR_EX_CONTEXT_K_1 has ICS set. |
| 126 | * SPR_EX_CONTEXT_0_0 is setup to user program's next PC. |
| 127 | * SPR_EX_CONTEXT_0_1 = 0. |
| 128 | */ |
| 129 | .macro int_hand_unalign_fast vecnum, vecname |
| 130 | .org (\vecnum << 8) |
| 131 | intvec_\vecname: |
| 132 | /* Put r3 in SPR_SYSTEM_SAVE_K_1. */ |
| 133 | mtspr SPR_SYSTEM_SAVE_K_1, r3 |
| 134 | |
| 135 | mfspr r3, SPR_EX_CONTEXT_K_1 |
| 136 | /* |
| 137 | * Examine if exception comes from user without ICS set. |
| 138 | * If not, just go directly to the slow path. |
| 139 | */ |
| 140 | bnez r3, hand_unalign_slow_nonuser |
| 141 | |
| 142 | mfspr r3, SPR_SYSTEM_SAVE_K_0 |
| 143 | |
| 144 | /* Get &thread_info->unalign_jit_tmp[0] in r3. */ |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 145 | bfexts r3, r3, 0, CPU_SHIFT-1 |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 146 | mm r3, zero, LOG2_THREAD_SIZE, 63 |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 147 | addli r3, r3, THREAD_INFO_UNALIGN_JIT_TMP_OFFSET |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 148 | |
| 149 | /* |
| 150 | * Save r0, r1, r2 into thread_info array r3 points to |
| 151 | * from low to high memory in order. |
| 152 | */ |
| 153 | st_add r3, r0, 8 |
| 154 | st_add r3, r1, 8 |
| 155 | { |
| 156 | st_add r3, r2, 8 |
| 157 | andi r2, sp, 7 |
| 158 | } |
| 159 | |
| 160 | /* Save stored r3 value so we can revert it on a page fault. */ |
| 161 | mfspr r1, SPR_SYSTEM_SAVE_K_1 |
| 162 | st r3, r1 |
| 163 | |
| 164 | { |
| 165 | /* Generate a SIGBUS if sp is not 8-byte aligned. */ |
| 166 | bnez r2, hand_unalign_slow_badsp |
| 167 | } |
| 168 | |
| 169 | /* |
| 170 | * Get the thread_info in r0; load r1 with pc. Set the low bit of sp |
| 171 | * as an indicator to the page fault code in case we fault. |
| 172 | */ |
| 173 | { |
| 174 | ori sp, sp, 1 |
| 175 | mfspr r1, SPR_EX_CONTEXT_K_0 |
| 176 | } |
| 177 | |
| 178 | /* Add the jit_info offset in thread_info; extract r1 [3:9] into r2. */ |
| 179 | { |
| 180 | addli r0, r3, THREAD_INFO_UNALIGN_JIT_BASE_OFFSET - \ |
| 181 | (THREAD_INFO_UNALIGN_JIT_TMP_OFFSET + (3 * 8)) |
| 182 | bfextu r2, r1, 3, (2 + PAGE_SHIFT - UNALIGN_JIT_SHIFT) |
| 183 | } |
| 184 | |
| 185 | /* Load the jit_info; multiply r2 by 128. */ |
| 186 | { |
| 187 | ld r0, r0 |
| 188 | shli r2, r2, UNALIGN_JIT_SHIFT |
| 189 | } |
| 190 | |
| 191 | /* |
| 192 | * If r0 is NULL, the JIT page is not mapped, so go to slow path; |
| 193 | * add offset r2 to r0 at the same time. |
| 194 | */ |
| 195 | { |
| 196 | beqz r0, hand_unalign_slow |
| 197 | add r2, r0, r2 |
| 198 | } |
| 199 | |
| 200 | /* |
| 201 | * We are loading from userspace (both the JIT info PC and |
| 202 | * instruction word, and the instruction word we executed) |
| 203 | * and since either could fault while holding the interrupt |
| 204 | * critical section, we must tag this region and check it in |
| 205 | * do_page_fault() to handle it properly. |
| 206 | */ |
| 207 | ENTRY(__start_unalign_asm_code) |
| 208 | |
| 209 | /* Load first word of JIT in r0 and increment r2 by 8. */ |
| 210 | ld_add r0, r2, 8 |
| 211 | |
| 212 | /* |
| 213 | * Compare the PC with the 1st word in JIT; load the fault bundle |
| 214 | * into r1. |
| 215 | */ |
| 216 | { |
| 217 | cmpeq r0, r0, r1 |
| 218 | ld r1, r1 |
| 219 | } |
| 220 | |
| 221 | /* Go to slow path if PC doesn't match. */ |
| 222 | beqz r0, hand_unalign_slow |
| 223 | |
| 224 | /* |
| 225 | * Load the 2nd word of JIT, which is supposed to be the fault |
| 226 | * bundle for a cache hit. Increment r2; after this bundle r2 will |
| 227 | * point to the potential start of the JIT code we want to run. |
| 228 | */ |
| 229 | ld_add r0, r2, 8 |
| 230 | |
| 231 | /* No further accesses to userspace are done after this point. */ |
| 232 | ENTRY(__end_unalign_asm_code) |
| 233 | |
| 234 | /* Compare the real bundle with what is saved in the JIT area. */ |
| 235 | { |
| 236 | cmpeq r0, r1, r0 |
| 237 | mtspr SPR_EX_CONTEXT_0_1, zero |
| 238 | } |
| 239 | |
| 240 | /* Go to slow path if the fault bundle does not match. */ |
| 241 | beqz r0, hand_unalign_slow |
| 242 | |
| 243 | /* |
| 244 | * A cache hit is found. |
| 245 | * r2 points to start of JIT code (3rd word). |
| 246 | * r0 is the fault pc. |
| 247 | * r1 is the fault bundle. |
| 248 | * Reset the low bit of sp. |
| 249 | */ |
| 250 | { |
| 251 | mfspr r0, SPR_EX_CONTEXT_K_0 |
| 252 | andi sp, sp, ~1 |
| 253 | } |
| 254 | |
| 255 | /* Write r2 into EX_CONTEXT_K_0 and increment PC. */ |
| 256 | { |
| 257 | mtspr SPR_EX_CONTEXT_K_0, r2 |
| 258 | addi r0, r0, 8 |
| 259 | } |
| 260 | |
| 261 | /* |
| 262 | * Set ICS on kernel EX_CONTEXT_K_1 in order to "iret" to |
| 263 | * user with ICS set. This way, if the JIT fixup causes another |
| 264 | * unalign exception (which shouldn't be possible) the user |
| 265 | * process will be terminated with SIGBUS. Also, our fixup will |
| 266 | * run without interleaving with external interrupts. |
| 267 | * Each fixup is at most 14 bundles, so it won't hold ICS for long. |
| 268 | */ |
| 269 | { |
| 270 | movei r1, PL_ICS_EX1(USER_PL, 1) |
| 271 | mtspr SPR_EX_CONTEXT_0_0, r0 |
| 272 | } |
| 273 | |
| 274 | { |
| 275 | mtspr SPR_EX_CONTEXT_K_1, r1 |
| 276 | addi r3, r3, -(3 * 8) |
| 277 | } |
| 278 | |
| 279 | /* Restore r0..r3. */ |
| 280 | ld_add r0, r3, 8 |
| 281 | ld_add r1, r3, 8 |
| 282 | ld_add r2, r3, 8 |
| 283 | ld r3, r3 |
| 284 | |
| 285 | iret |
| 286 | ENDPROC(intvec_\vecname) |
| 287 | .endm |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 288 | |
| 289 | #ifdef __COLLECT_LINKER_FEEDBACK__ |
| 290 | .pushsection .text.intvec_feedback,"ax" |
| 291 | intvec_feedback: |
| 292 | .popsection |
| 293 | #endif |
| 294 | |
| 295 | /* |
| 296 | * Default interrupt handler. |
| 297 | * |
| 298 | * vecnum is where we'll put this code. |
| 299 | * c_routine is the C routine we'll call. |
| 300 | * |
| 301 | * The C routine is passed two arguments: |
| 302 | * - A pointer to the pt_regs state. |
| 303 | * - The interrupt vector number. |
| 304 | * |
| 305 | * The "processing" argument specifies the code for processing |
| 306 | * the interrupt. Defaults to "handle_interrupt". |
| 307 | */ |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 308 | .macro __int_hand vecnum, vecname, c_routine,processing=handle_interrupt |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 309 | intvec_\vecname: |
| 310 | /* Temporarily save a register so we have somewhere to work. */ |
| 311 | |
| 312 | mtspr SPR_SYSTEM_SAVE_K_1, r0 |
| 313 | mfspr r0, SPR_EX_CONTEXT_K_1 |
| 314 | |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 315 | /* |
| 316 | * The unalign data fastpath code sets the low bit in sp to |
| 317 | * force us to reset it here on fault. |
| 318 | */ |
| 319 | { |
| 320 | blbs sp, 2f |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 321 | IS_KERNEL_EX1(r0, r0) |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 322 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 323 | |
| 324 | .ifc \vecnum, INT_DOUBLE_FAULT |
| 325 | /* |
| 326 | * For double-faults from user-space, fall through to the normal |
| 327 | * register save and stack setup path. Otherwise, it's the |
| 328 | * hypervisor giving us one last chance to dump diagnostics, and we |
| 329 | * branch to the kernel_double_fault routine to do so. |
| 330 | */ |
| 331 | beqz r0, 1f |
| 332 | j _kernel_double_fault |
| 333 | 1: |
| 334 | .else |
| 335 | /* |
| 336 | * If we're coming from user-space, then set sp to the top of |
| 337 | * the kernel stack. Otherwise, assume sp is already valid. |
| 338 | */ |
| 339 | { |
| 340 | bnez r0, 0f |
| 341 | move r0, sp |
| 342 | } |
| 343 | .endif |
| 344 | |
| 345 | .ifc \c_routine, do_page_fault |
| 346 | /* |
| 347 | * The page_fault handler may be downcalled directly by the |
| 348 | * hypervisor even when Linux is running and has ICS set. |
| 349 | * |
| 350 | * In this case the contents of EX_CONTEXT_K_1 reflect the |
| 351 | * previous fault and can't be relied on to choose whether or |
| 352 | * not to reinitialize the stack pointer. So we add a test |
| 353 | * to see whether SYSTEM_SAVE_K_2 has the high bit set, |
| 354 | * and if so we don't reinitialize sp, since we must be coming |
| 355 | * from Linux. (In fact the precise case is !(val & ~1), |
| 356 | * but any Linux PC has to have the high bit set.) |
| 357 | * |
| 358 | * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for |
| 359 | * any path that turns into a downcall to one of our TLB handlers. |
| 360 | * |
| 361 | * FIXME: if we end up never using this path, perhaps we should |
| 362 | * prevent the hypervisor from generating downcalls in this case. |
| 363 | * The advantage of getting a downcall is we can panic in Linux. |
| 364 | */ |
| 365 | mfspr r0, SPR_SYSTEM_SAVE_K_2 |
| 366 | { |
| 367 | bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */ |
| 368 | move r0, sp |
| 369 | } |
| 370 | .endif |
| 371 | |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 372 | 2: |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 373 | /* |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 374 | * SYSTEM_SAVE_K_0 holds the cpu number in the high bits, and |
| 375 | * the current stack top in the lower bits. So we recover |
| 376 | * our starting stack value by sign-extending the low bits, then |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 377 | * point sp at the top aligned address on the actual stack page. |
| 378 | */ |
| 379 | mfspr r0, SPR_SYSTEM_SAVE_K_0 |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 380 | bfexts r0, r0, 0, CPU_SHIFT-1 |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 381 | |
| 382 | 0: |
| 383 | /* |
| 384 | * Align the stack mod 64 so we can properly predict what |
| 385 | * cache lines we need to write-hint to reduce memory fetch |
| 386 | * latency as we enter the kernel. The layout of memory is |
| 387 | * as follows, with cache line 0 at the lowest VA, and cache |
| 388 | * line 8 just below the r0 value this "andi" computes. |
| 389 | * Note that we never write to cache line 8, and we skip |
| 390 | * cache lines 1-3 for syscalls. |
| 391 | * |
| 392 | * cache line 8: ptregs padding (two words) |
| 393 | * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch |
| 394 | * cache line 6: r46...r53 (tp) |
| 395 | * cache line 5: r38...r45 |
| 396 | * cache line 4: r30...r37 |
| 397 | * cache line 3: r22...r29 |
| 398 | * cache line 2: r14...r21 |
| 399 | * cache line 1: r6...r13 |
| 400 | * cache line 0: 2 x frame, r0..r5 |
| 401 | */ |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 402 | #if STACK_TOP_DELTA != 64 |
| 403 | #error STACK_TOP_DELTA must be 64 for assumptions here and in task_pt_regs() |
| 404 | #endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 405 | andi r0, r0, -64 |
| 406 | |
| 407 | /* |
| 408 | * Push the first four registers on the stack, so that we can set |
| 409 | * them to vector-unique values before we jump to the common code. |
| 410 | * |
| 411 | * Registers are pushed on the stack as a struct pt_regs, |
| 412 | * with the sp initially just above the struct, and when we're |
| 413 | * done, sp points to the base of the struct, minus |
| 414 | * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code. |
| 415 | * |
| 416 | * This routine saves just the first four registers, plus the |
| 417 | * stack context so we can do proper backtracing right away, |
| 418 | * and defers to handle_interrupt to save the rest. |
Chris Metcalf | 5100700 | 2012-03-27 15:40:20 -0400 | [diff] [blame] | 419 | * The backtracer needs pc, ex1, lr, sp, r52, and faultnum, |
| 420 | * and needs sp set to its final location at the bottom of |
| 421 | * the stack frame. |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 422 | */ |
| 423 | addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP) |
| 424 | wh64 r0 /* cache line 7 */ |
| 425 | { |
| 426 | st r0, lr |
| 427 | addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR |
| 428 | } |
| 429 | { |
| 430 | st r0, sp |
| 431 | addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP |
| 432 | } |
| 433 | wh64 sp /* cache line 6 */ |
| 434 | { |
| 435 | st sp, r52 |
| 436 | addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52) |
| 437 | } |
| 438 | wh64 sp /* cache line 0 */ |
| 439 | { |
| 440 | st sp, r1 |
| 441 | addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1) |
| 442 | } |
| 443 | { |
| 444 | st sp, r2 |
| 445 | addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2) |
| 446 | } |
| 447 | { |
| 448 | st sp, r3 |
| 449 | addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3) |
| 450 | } |
| 451 | mfspr r0, SPR_EX_CONTEXT_K_0 |
| 452 | .ifc \processing,handle_syscall |
| 453 | /* |
| 454 | * Bump the saved PC by one bundle so that when we return, we won't |
| 455 | * execute the same swint instruction again. We need to do this while |
| 456 | * we're in the critical section. |
| 457 | */ |
| 458 | addi r0, r0, 8 |
| 459 | .endif |
| 460 | { |
| 461 | st sp, r0 |
| 462 | addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC |
| 463 | } |
| 464 | mfspr r0, SPR_EX_CONTEXT_K_1 |
| 465 | { |
| 466 | st sp, r0 |
| 467 | addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1 |
| 468 | /* |
| 469 | * Use r0 for syscalls so it's a temporary; use r1 for interrupts |
| 470 | * so that it gets passed through unchanged to the handler routine. |
| 471 | * Note that the .if conditional confusingly spans bundles. |
| 472 | */ |
| 473 | .ifc \processing,handle_syscall |
| 474 | movei r0, \vecnum |
| 475 | } |
| 476 | { |
| 477 | st sp, r0 |
| 478 | .else |
| 479 | movei r1, \vecnum |
| 480 | } |
| 481 | { |
| 482 | st sp, r1 |
| 483 | .endif |
| 484 | addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM |
| 485 | } |
| 486 | mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */ |
| 487 | { |
| 488 | st sp, r0 |
| 489 | addi sp, sp, -PTREGS_OFFSET_REG(0) - 8 |
| 490 | } |
| 491 | { |
| 492 | st sp, zero /* write zero into "Next SP" frame pointer */ |
| 493 | addi sp, sp, -8 /* leave SP pointing at bottom of frame */ |
| 494 | } |
| 495 | .ifc \processing,handle_syscall |
| 496 | j handle_syscall |
| 497 | .else |
| 498 | /* Capture per-interrupt SPR context to registers. */ |
| 499 | .ifc \c_routine, do_page_fault |
| 500 | mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */ |
| 501 | mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */ |
| 502 | .else |
| 503 | .ifc \vecnum, INT_ILL_TRANS |
Chris Metcalf | 70d2b59 | 2013-08-07 12:11:56 -0400 | [diff] [blame] | 504 | mfspr r2, ILL_VA_PC |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 505 | .else |
| 506 | .ifc \vecnum, INT_DOUBLE_FAULT |
| 507 | mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */ |
| 508 | .else |
| 509 | .ifc \c_routine, do_trap |
| 510 | mfspr r2, GPV_REASON |
| 511 | .else |
Zhigang Lu | 8e3441e | 2014-01-27 15:11:07 +0800 | [diff] [blame] | 512 | .ifc \c_routine, handle_perf_interrupt |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 513 | mfspr r2, PERF_COUNT_STS |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 514 | .else |
Zhigang Lu | 8e3441e | 2014-01-27 15:11:07 +0800 | [diff] [blame] | 515 | .ifc \c_routine, handle_perf_interrupt |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 516 | mfspr r2, AUX_PERF_COUNT_STS |
| 517 | .endif |
Chris Metcalf | e5701b7 | 2015-05-04 17:26:35 -0400 | [diff] [blame] | 518 | .ifc \c_routine, do_nmi |
| 519 | mfspr r2, SPR_SYSTEM_SAVE_K_2 /* nmi type */ |
| 520 | .else |
| 521 | .endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 522 | .endif |
| 523 | .endif |
| 524 | .endif |
| 525 | .endif |
| 526 | .endif |
| 527 | /* Put function pointer in r0 */ |
| 528 | moveli r0, hw2_last(\c_routine) |
| 529 | shl16insli r0, r0, hw1(\c_routine) |
| 530 | { |
| 531 | shl16insli r0, r0, hw0(\c_routine) |
| 532 | j \processing |
| 533 | } |
| 534 | .endif |
| 535 | ENDPROC(intvec_\vecname) |
| 536 | |
| 537 | #ifdef __COLLECT_LINKER_FEEDBACK__ |
| 538 | .pushsection .text.intvec_feedback,"ax" |
| 539 | .org (\vecnum << 5) |
Chris Metcalf | acbde1d | 2013-09-03 14:41:36 -0400 | [diff] [blame] | 540 | FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt, 1 << 8) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 541 | jrp lr |
| 542 | .popsection |
| 543 | #endif |
| 544 | |
| 545 | .endm |
| 546 | |
| 547 | |
| 548 | /* |
| 549 | * Save the rest of the registers that we didn't save in the actual |
| 550 | * vector itself. We can't use r0-r10 inclusive here. |
| 551 | */ |
| 552 | .macro finish_interrupt_save, function |
| 553 | |
| 554 | /* If it's a syscall, save a proper orig_r0, otherwise just zero. */ |
| 555 | PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0) |
| 556 | { |
| 557 | .ifc \function,handle_syscall |
| 558 | st r52, r0 |
| 559 | .else |
| 560 | st r52, zero |
| 561 | .endif |
| 562 | PTREGS_PTR(r52, PTREGS_OFFSET_TP) |
| 563 | } |
| 564 | st r52, tp |
| 565 | { |
| 566 | mfspr tp, CMPEXCH_VALUE |
| 567 | PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH) |
| 568 | } |
| 569 | |
| 570 | /* |
| 571 | * For ordinary syscalls, we save neither caller- nor callee- |
| 572 | * save registers, since the syscall invoker doesn't expect the |
| 573 | * caller-saves to be saved, and the called kernel functions will |
| 574 | * take care of saving the callee-saves for us. |
| 575 | * |
| 576 | * For interrupts we save just the caller-save registers. Saving |
| 577 | * them is required (since the "caller" can't save them). Again, |
| 578 | * the called kernel functions will restore the callee-save |
| 579 | * registers for us appropriately. |
| 580 | * |
| 581 | * On return, we normally restore nothing special for syscalls, |
| 582 | * and just the caller-save registers for interrupts. |
| 583 | * |
| 584 | * However, there are some important caveats to all this: |
| 585 | * |
| 586 | * - We always save a few callee-save registers to give us |
| 587 | * some scratchpad registers to carry across function calls. |
| 588 | * |
| 589 | * - fork/vfork/etc require us to save all the callee-save |
| 590 | * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below. |
| 591 | * |
| 592 | * - We always save r0..r5 and r10 for syscalls, since we need |
| 593 | * to reload them a bit later for the actual kernel call, and |
| 594 | * since we might need them for -ERESTARTNOINTR, etc. |
| 595 | * |
| 596 | * - Before invoking a signal handler, we save the unsaved |
| 597 | * callee-save registers so they are visible to the |
| 598 | * signal handler or any ptracer. |
| 599 | * |
| 600 | * - If the unsaved callee-save registers are modified, we set |
| 601 | * a bit in pt_regs so we know to reload them from pt_regs |
| 602 | * and not just rely on the kernel function unwinding. |
| 603 | * (Done for ptrace register writes and SA_SIGINFO handler.) |
| 604 | */ |
| 605 | { |
| 606 | st r52, tp |
| 607 | PTREGS_PTR(r52, PTREGS_OFFSET_REG(33)) |
| 608 | } |
| 609 | wh64 r52 /* cache line 4 */ |
| 610 | push_reg r33, r52 |
| 611 | push_reg r32, r52 |
| 612 | push_reg r31, r52 |
| 613 | .ifc \function,handle_syscall |
| 614 | push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30) |
| 615 | push_reg TREG_SYSCALL_NR_NAME, r52, \ |
| 616 | PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL |
| 617 | .else |
| 618 | |
| 619 | push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30) |
| 620 | wh64 r52 /* cache line 3 */ |
| 621 | push_reg r29, r52 |
| 622 | push_reg r28, r52 |
| 623 | push_reg r27, r52 |
| 624 | push_reg r26, r52 |
| 625 | push_reg r25, r52 |
| 626 | push_reg r24, r52 |
| 627 | push_reg r23, r52 |
| 628 | push_reg r22, r52 |
| 629 | wh64 r52 /* cache line 2 */ |
| 630 | push_reg r21, r52 |
| 631 | push_reg r20, r52 |
| 632 | push_reg r19, r52 |
| 633 | push_reg r18, r52 |
| 634 | push_reg r17, r52 |
| 635 | push_reg r16, r52 |
| 636 | push_reg r15, r52 |
| 637 | push_reg r14, r52 |
| 638 | wh64 r52 /* cache line 1 */ |
| 639 | push_reg r13, r52 |
| 640 | push_reg r12, r52 |
| 641 | push_reg r11, r52 |
| 642 | push_reg r10, r52 |
| 643 | push_reg r9, r52 |
| 644 | push_reg r8, r52 |
| 645 | push_reg r7, r52 |
| 646 | push_reg r6, r52 |
| 647 | |
| 648 | .endif |
| 649 | |
| 650 | push_reg r5, r52 |
| 651 | st r52, r4 |
| 652 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 653 | /* |
| 654 | * If we will be returning to the kernel, we will need to |
| 655 | * reset the interrupt masks to the state they had before. |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 656 | * Set DISABLE_IRQ in flags iff we came from kernel pl with |
| 657 | * irqs disabled. |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 658 | */ |
| 659 | mfspr r32, SPR_EX_CONTEXT_K_1 |
| 660 | { |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 661 | IS_KERNEL_EX1(r22, r22) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 662 | PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS) |
| 663 | } |
| 664 | beqzt r32, 1f /* zero if from user space */ |
| 665 | IRQS_DISABLED(r32) /* zero if irqs enabled */ |
| 666 | #if PT_FLAGS_DISABLE_IRQ != 1 |
| 667 | # error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix |
| 668 | #endif |
| 669 | 1: |
| 670 | .ifnc \function,handle_syscall |
| 671 | /* Record the fact that we saved the caller-save registers above. */ |
| 672 | ori r32, r32, PT_FLAGS_CALLER_SAVES |
| 673 | .endif |
| 674 | st r21, r32 |
| 675 | |
Chris Metcalf | 5100700 | 2012-03-27 15:40:20 -0400 | [diff] [blame] | 676 | /* |
| 677 | * we've captured enough state to the stack (including in |
| 678 | * particular our EX_CONTEXT state) that we can now release |
| 679 | * the interrupt critical section and replace it with our |
| 680 | * standard "interrupts disabled" mask value. This allows |
| 681 | * synchronous interrupts (and profile interrupts) to punch |
| 682 | * through from this point onwards. |
| 683 | * |
| 684 | * It's important that no code before this point touch memory |
| 685 | * other than our own stack (to keep the invariant that this |
| 686 | * is all that gets touched under ICS), and that no code after |
| 687 | * this point reference any interrupt-specific SPR, in particular |
| 688 | * the EX_CONTEXT_K_ values. |
| 689 | */ |
| 690 | .ifc \function,handle_nmi |
| 691 | IRQ_DISABLE_ALL(r20) |
| 692 | .else |
| 693 | IRQ_DISABLE(r20, r21) |
| 694 | .endif |
| 695 | mtspr INTERRUPT_CRITICAL_SECTION, zero |
| 696 | |
| 697 | /* Load tp with our per-cpu offset. */ |
| 698 | #ifdef CONFIG_SMP |
| 699 | { |
| 700 | mfspr r20, SPR_SYSTEM_SAVE_K_0 |
| 701 | moveli r21, hw2_last(__per_cpu_offset) |
| 702 | } |
| 703 | { |
| 704 | shl16insli r21, r21, hw1(__per_cpu_offset) |
Chris Metcalf | 35f0597 | 2013-08-10 12:35:02 -0400 | [diff] [blame] | 705 | bfextu r20, r20, CPU_SHIFT, 63 |
Chris Metcalf | 5100700 | 2012-03-27 15:40:20 -0400 | [diff] [blame] | 706 | } |
| 707 | shl16insli r21, r21, hw0(__per_cpu_offset) |
| 708 | shl3add r20, r20, r21 |
| 709 | ld tp, r20 |
| 710 | #else |
| 711 | move tp, zero |
| 712 | #endif |
| 713 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 714 | #ifdef __COLLECT_LINKER_FEEDBACK__ |
| 715 | /* |
| 716 | * Notify the feedback routines that we were in the |
| 717 | * appropriate fixed interrupt vector area. Note that we |
| 718 | * still have ICS set at this point, so we can't invoke any |
| 719 | * atomic operations or we will panic. The feedback |
| 720 | * routines internally preserve r0..r10 and r30 up. |
| 721 | */ |
| 722 | .ifnc \function,handle_syscall |
| 723 | shli r20, r1, 5 |
| 724 | .else |
| 725 | moveli r20, INT_SWINT_1 << 5 |
| 726 | .endif |
| 727 | moveli r21, hw2_last(intvec_feedback) |
| 728 | shl16insli r21, r21, hw1(intvec_feedback) |
| 729 | shl16insli r21, r21, hw0(intvec_feedback) |
| 730 | add r20, r20, r21 |
| 731 | jalr r20 |
| 732 | |
| 733 | /* And now notify the feedback routines that we are here. */ |
| 734 | FEEDBACK_ENTER(\function) |
| 735 | #endif |
| 736 | |
| 737 | /* |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 738 | * Prepare the first 256 stack bytes to be rapidly accessible |
| 739 | * without having to fetch the background data. |
| 740 | */ |
| 741 | addi r52, sp, -64 |
| 742 | { |
| 743 | wh64 r52 |
| 744 | addi r52, r52, -64 |
| 745 | } |
| 746 | { |
| 747 | wh64 r52 |
| 748 | addi r52, r52, -64 |
| 749 | } |
| 750 | { |
| 751 | wh64 r52 |
| 752 | addi r52, r52, -64 |
| 753 | } |
| 754 | wh64 r52 |
| 755 | |
| 756 | #ifdef CONFIG_TRACE_IRQFLAGS |
| 757 | .ifnc \function,handle_nmi |
| 758 | /* |
| 759 | * We finally have enough state set up to notify the irq |
| 760 | * tracing code that irqs were disabled on entry to the handler. |
| 761 | * The TRACE_IRQS_OFF call clobbers registers r0-r29. |
| 762 | * For syscalls, we already have the register state saved away |
| 763 | * on the stack, so we don't bother to do any register saves here, |
| 764 | * and later we pop the registers back off the kernel stack. |
| 765 | * For interrupt handlers, save r0-r3 in callee-saved registers. |
| 766 | */ |
| 767 | .ifnc \function,handle_syscall |
| 768 | { move r30, r0; move r31, r1 } |
| 769 | { move r32, r2; move r33, r3 } |
| 770 | .endif |
| 771 | TRACE_IRQS_OFF |
| 772 | .ifnc \function,handle_syscall |
| 773 | { move r0, r30; move r1, r31 } |
| 774 | { move r2, r32; move r3, r33 } |
| 775 | .endif |
| 776 | .endif |
| 777 | #endif |
| 778 | |
| 779 | .endm |
| 780 | |
| 781 | /* |
| 782 | * Redispatch a downcall. |
| 783 | */ |
| 784 | .macro dc_dispatch vecnum, vecname |
| 785 | .org (\vecnum << 8) |
| 786 | intvec_\vecname: |
Chris Metcalf | 9ae0983 | 2013-08-07 16:03:08 -0400 | [diff] [blame] | 787 | j _hv_downcall_dispatch |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 788 | ENDPROC(intvec_\vecname) |
| 789 | .endm |
| 790 | |
| 791 | /* |
| 792 | * Common code for most interrupts. The C function we're eventually |
| 793 | * going to is in r0, and the faultnum is in r1; the original |
| 794 | * values for those registers are on the stack. |
| 795 | */ |
| 796 | .pushsection .text.handle_interrupt,"ax" |
| 797 | handle_interrupt: |
| 798 | finish_interrupt_save handle_interrupt |
| 799 | |
| 800 | /* Jump to the C routine; it should enable irqs as soon as possible. */ |
| 801 | { |
| 802 | jalr r0 |
| 803 | PTREGS_PTR(r0, PTREGS_OFFSET_BASE) |
| 804 | } |
| 805 | FEEDBACK_REENTER(handle_interrupt) |
| 806 | { |
| 807 | movei r30, 0 /* not an NMI */ |
| 808 | j interrupt_return |
| 809 | } |
| 810 | STD_ENDPROC(handle_interrupt) |
| 811 | |
| 812 | /* |
| 813 | * This routine takes a boolean in r30 indicating if this is an NMI. |
| 814 | * If so, we also expect a boolean in r31 indicating whether to |
| 815 | * re-enable the oprofile interrupts. |
Chris Metcalf | e1d5c019 | 2012-03-30 16:29:06 -0400 | [diff] [blame] | 816 | * |
| 817 | * Note that .Lresume_userspace is jumped to directly in several |
| 818 | * places, and we need to make sure r30 is set correctly in those |
| 819 | * callers as well. |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 820 | */ |
| 821 | STD_ENTRY(interrupt_return) |
| 822 | /* If we're resuming to kernel space, don't check thread flags. */ |
| 823 | { |
| 824 | bnez r30, .Lrestore_all /* NMIs don't special-case user-space */ |
| 825 | PTREGS_PTR(r29, PTREGS_OFFSET_EX1) |
| 826 | } |
| 827 | ld r29, r29 |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 828 | IS_KERNEL_EX1(r29, r29) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 829 | { |
| 830 | beqzt r29, .Lresume_userspace |
Chris Metcalf | bc1a298 | 2013-08-07 11:36:54 -0400 | [diff] [blame] | 831 | move r29, sp |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 832 | } |
| 833 | |
Chris Metcalf | bc1a298 | 2013-08-07 11:36:54 -0400 | [diff] [blame] | 834 | #ifdef CONFIG_PREEMPT |
| 835 | /* Returning to kernel space. Check if we need preemption. */ |
| 836 | EXTRACT_THREAD_INFO(r29) |
| 837 | addli r28, r29, THREAD_INFO_FLAGS_OFFSET |
| 838 | { |
| 839 | ld r28, r28 |
| 840 | addli r29, r29, THREAD_INFO_PREEMPT_COUNT_OFFSET |
| 841 | } |
| 842 | { |
| 843 | andi r28, r28, _TIF_NEED_RESCHED |
| 844 | ld4s r29, r29 |
| 845 | } |
| 846 | beqzt r28, 1f |
| 847 | bnez r29, 1f |
Chris Metcalf | 3f725c5 | 2013-09-26 13:22:40 -0400 | [diff] [blame] | 848 | /* Disable interrupts explicitly for preemption. */ |
| 849 | IRQ_DISABLE(r20,r21) |
| 850 | TRACE_IRQS_OFF |
Chris Metcalf | bc1a298 | 2013-08-07 11:36:54 -0400 | [diff] [blame] | 851 | jal preempt_schedule_irq |
| 852 | FEEDBACK_REENTER(interrupt_return) |
| 853 | 1: |
| 854 | #endif |
| 855 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 856 | /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */ |
Chris Metcalf | bc1a298 | 2013-08-07 11:36:54 -0400 | [diff] [blame] | 857 | { |
| 858 | moveli r27, hw2_last(_cpu_idle_nap) |
| 859 | PTREGS_PTR(r29, PTREGS_OFFSET_PC) |
| 860 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 861 | { |
| 862 | ld r28, r29 |
| 863 | shl16insli r27, r27, hw1(_cpu_idle_nap) |
| 864 | } |
| 865 | { |
| 866 | shl16insli r27, r27, hw0(_cpu_idle_nap) |
| 867 | } |
| 868 | { |
| 869 | cmpeq r27, r27, r28 |
| 870 | } |
| 871 | { |
| 872 | blbc r27, .Lrestore_all |
| 873 | addi r28, r28, 8 |
| 874 | } |
| 875 | st r29, r28 |
| 876 | j .Lrestore_all |
| 877 | |
| 878 | .Lresume_userspace: |
| 879 | FEEDBACK_REENTER(interrupt_return) |
| 880 | |
| 881 | /* |
Chris Metcalf | fc327e2 | 2012-04-28 18:51:43 -0400 | [diff] [blame] | 882 | * Use r33 to hold whether we have already loaded the callee-saves |
| 883 | * into ptregs. We don't want to do it twice in this loop, since |
| 884 | * then we'd clobber whatever changes are made by ptrace, etc. |
| 885 | */ |
| 886 | { |
| 887 | movei r33, 0 |
| 888 | move r32, sp |
| 889 | } |
| 890 | |
| 891 | /* Get base of stack in r32. */ |
| 892 | EXTRACT_THREAD_INFO(r32) |
| 893 | |
| 894 | .Lretry_work_pending: |
| 895 | /* |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 896 | * Disable interrupts so as to make sure we don't |
| 897 | * miss an interrupt that sets any of the thread flags (like |
| 898 | * need_resched or sigpending) between sampling and the iret. |
| 899 | * Routines like schedule() or do_signal() may re-enable |
| 900 | * interrupts before returning. |
| 901 | */ |
| 902 | IRQ_DISABLE(r20, r21) |
| 903 | TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */ |
| 904 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 905 | |
| 906 | /* Check to see if there is any work to do before returning to user. */ |
| 907 | { |
| 908 | addi r29, r32, THREAD_INFO_FLAGS_OFFSET |
| 909 | moveli r1, hw1_last(_TIF_ALLWORK_MASK) |
| 910 | } |
| 911 | { |
| 912 | ld r29, r29 |
| 913 | shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK) |
| 914 | } |
| 915 | and r1, r29, r1 |
| 916 | beqzt r1, .Lrestore_all |
| 917 | |
| 918 | /* |
| 919 | * Make sure we have all the registers saved for signal |
Chris Metcalf | fc327e2 | 2012-04-28 18:51:43 -0400 | [diff] [blame] | 920 | * handling or notify-resume. Call out to C code to figure out |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 921 | * exactly what we need to do for each flag bit, then if |
| 922 | * necessary, reload the flags and recheck. |
| 923 | */ |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 924 | { |
| 925 | PTREGS_PTR(r0, PTREGS_OFFSET_BASE) |
Chris Metcalf | fc327e2 | 2012-04-28 18:51:43 -0400 | [diff] [blame] | 926 | bnez r33, 1f |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 927 | } |
Chris Metcalf | fc327e2 | 2012-04-28 18:51:43 -0400 | [diff] [blame] | 928 | push_extra_callee_saves r0 |
| 929 | movei r33, 1 |
| 930 | 1: jal do_work_pending |
| 931 | bnez r0, .Lretry_work_pending |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 932 | |
| 933 | /* |
| 934 | * In the NMI case we |
| 935 | * omit the call to single_process_check_nohz, which normally checks |
| 936 | * to see if we should start or stop the scheduler tick, because |
| 937 | * we can't call arbitrary Linux code from an NMI context. |
| 938 | * We always call the homecache TLB deferral code to re-trigger |
| 939 | * the deferral mechanism. |
| 940 | * |
| 941 | * The other chunk of responsibility this code has is to reset the |
| 942 | * interrupt masks appropriately to reset irqs and NMIs. We have |
| 943 | * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the |
| 944 | * lockdep-type stuff, but we can't set ICS until afterwards, since |
| 945 | * ICS can only be used in very tight chunks of code to avoid |
| 946 | * tripping over various assertions that it is off. |
| 947 | */ |
| 948 | .Lrestore_all: |
| 949 | PTREGS_PTR(r0, PTREGS_OFFSET_EX1) |
| 950 | { |
| 951 | ld r0, r0 |
| 952 | PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS) |
| 953 | } |
| 954 | { |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 955 | IS_KERNEL_EX1(r0, r0) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 956 | ld r32, r32 |
| 957 | } |
| 958 | bnez r0, 1f |
| 959 | j 2f |
| 960 | #if PT_FLAGS_DISABLE_IRQ != 1 |
| 961 | # error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below |
| 962 | #endif |
| 963 | 1: blbct r32, 2f |
| 964 | IRQ_DISABLE(r20,r21) |
| 965 | TRACE_IRQS_OFF |
| 966 | movei r0, 1 |
| 967 | mtspr INTERRUPT_CRITICAL_SECTION, r0 |
| 968 | beqzt r30, .Lrestore_regs |
| 969 | j 3f |
| 970 | 2: TRACE_IRQS_ON |
Chris Metcalf | 5100700 | 2012-03-27 15:40:20 -0400 | [diff] [blame] | 971 | IRQ_ENABLE_LOAD(r20, r21) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 972 | movei r0, 1 |
| 973 | mtspr INTERRUPT_CRITICAL_SECTION, r0 |
Chris Metcalf | 5100700 | 2012-03-27 15:40:20 -0400 | [diff] [blame] | 974 | IRQ_ENABLE_APPLY(r20, r21) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 975 | beqzt r30, .Lrestore_regs |
| 976 | 3: |
| 977 | |
Zhigang Lu | ba67823 | 2014-01-27 16:25:28 +0800 | [diff] [blame] | 978 | #if INT_PERF_COUNT + 1 != INT_AUX_PERF_COUNT |
| 979 | # error Bad interrupt assumption |
| 980 | #endif |
| 981 | { |
| 982 | movei r0, 3 /* two adjacent bits for the PERF_COUNT mask */ |
| 983 | beqz r31, .Lrestore_regs |
| 984 | } |
| 985 | shli r0, r0, INT_PERF_COUNT |
| 986 | mtspr SPR_INTERRUPT_MASK_RESET_K, r0 |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 987 | |
| 988 | /* |
| 989 | * We now commit to returning from this interrupt, since we will be |
| 990 | * doing things like setting EX_CONTEXT SPRs and unwinding the stack |
| 991 | * frame. No calls should be made to any other code after this point. |
| 992 | * This code should only be entered with ICS set. |
| 993 | * r32 must still be set to ptregs.flags. |
| 994 | * We launch loads to each cache line separately first, so we can |
| 995 | * get some parallelism out of the memory subsystem. |
| 996 | * We start zeroing caller-saved registers throughout, since |
| 997 | * that will save some cycles if this turns out to be a syscall. |
| 998 | */ |
| 999 | .Lrestore_regs: |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1000 | |
| 1001 | /* |
| 1002 | * Rotate so we have one high bit and one low bit to test. |
| 1003 | * - low bit says whether to restore all the callee-saved registers, |
| 1004 | * or just r30-r33, and r52 up. |
| 1005 | * - high bit (i.e. sign bit) says whether to restore all the |
| 1006 | * caller-saved registers, or just r0. |
| 1007 | */ |
| 1008 | #if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4 |
| 1009 | # error Rotate trick does not work :-) |
| 1010 | #endif |
| 1011 | { |
| 1012 | rotli r20, r32, 62 |
| 1013 | PTREGS_PTR(sp, PTREGS_OFFSET_REG(0)) |
| 1014 | } |
| 1015 | |
| 1016 | /* |
| 1017 | * Load cache lines 0, 4, 6 and 7, in that order, then use |
| 1018 | * the last loaded value, which makes it likely that the other |
| 1019 | * cache lines have also loaded, at which point we should be |
| 1020 | * able to safely read all the remaining words on those cache |
| 1021 | * lines without waiting for the memory subsystem. |
| 1022 | */ |
| 1023 | pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0) |
| 1024 | pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30) |
| 1025 | pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52) |
| 1026 | pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH |
| 1027 | pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1 |
| 1028 | { |
| 1029 | mtspr CMPEXCH_VALUE, r21 |
| 1030 | move r4, zero |
| 1031 | } |
| 1032 | pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC |
| 1033 | { |
| 1034 | mtspr SPR_EX_CONTEXT_K_1, lr |
Chris Metcalf | 051168d | 2013-09-03 14:45:52 -0400 | [diff] [blame] | 1035 | IS_KERNEL_EX1(lr, lr) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1036 | } |
| 1037 | { |
| 1038 | mtspr SPR_EX_CONTEXT_K_0, r21 |
| 1039 | move r5, zero |
| 1040 | } |
| 1041 | |
| 1042 | /* Restore callee-saveds that we actually use. */ |
| 1043 | pop_reg_zero r31, r6 |
| 1044 | pop_reg_zero r32, r7 |
| 1045 | pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33) |
| 1046 | |
| 1047 | /* |
| 1048 | * If we modified other callee-saveds, restore them now. |
| 1049 | * This is rare, but could be via ptrace or signal handler. |
| 1050 | */ |
| 1051 | { |
| 1052 | move r9, zero |
| 1053 | blbs r20, .Lrestore_callees |
| 1054 | } |
| 1055 | .Lcontinue_restore_regs: |
| 1056 | |
| 1057 | /* Check if we're returning from a syscall. */ |
| 1058 | { |
| 1059 | move r10, zero |
| 1060 | bltzt r20, 1f /* no, so go restore callee-save registers */ |
| 1061 | } |
| 1062 | |
| 1063 | /* |
| 1064 | * Check if we're returning to userspace. |
| 1065 | * Note that if we're not, we don't worry about zeroing everything. |
| 1066 | */ |
| 1067 | { |
| 1068 | addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29) |
| 1069 | bnez lr, .Lkernel_return |
| 1070 | } |
| 1071 | |
| 1072 | /* |
| 1073 | * On return from syscall, we've restored r0 from pt_regs, but we |
| 1074 | * clear the remainder of the caller-saved registers. We could |
| 1075 | * restore the syscall arguments, but there's not much point, |
| 1076 | * and it ensures user programs aren't trying to use the |
| 1077 | * caller-saves if we clear them, as well as avoiding leaking |
| 1078 | * kernel pointers into userspace. |
| 1079 | */ |
| 1080 | pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR |
| 1081 | pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP |
| 1082 | { |
| 1083 | ld sp, sp |
| 1084 | move r13, zero |
| 1085 | move r14, zero |
| 1086 | } |
| 1087 | { move r15, zero; move r16, zero } |
| 1088 | { move r17, zero; move r18, zero } |
| 1089 | { move r19, zero; move r20, zero } |
| 1090 | { move r21, zero; move r22, zero } |
| 1091 | { move r23, zero; move r24, zero } |
| 1092 | { move r25, zero; move r26, zero } |
| 1093 | |
| 1094 | /* Set r1 to errno if we are returning an error, otherwise zero. */ |
| 1095 | { |
| 1096 | moveli r29, 4096 |
| 1097 | sub r1, zero, r0 |
| 1098 | } |
| 1099 | { |
| 1100 | move r28, zero |
| 1101 | cmpltu r29, r1, r29 |
| 1102 | } |
| 1103 | { |
| 1104 | mnz r1, r29, r1 |
| 1105 | move r29, zero |
| 1106 | } |
| 1107 | iret |
| 1108 | |
| 1109 | /* |
| 1110 | * Not a syscall, so restore caller-saved registers. |
| 1111 | * First kick off loads for cache lines 1-3, which we're touching |
| 1112 | * for the first time here. |
| 1113 | */ |
| 1114 | .align 64 |
| 1115 | 1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29) |
| 1116 | pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21) |
| 1117 | pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13) |
| 1118 | pop_reg r1 |
| 1119 | pop_reg r2 |
| 1120 | pop_reg r3 |
| 1121 | pop_reg r4 |
| 1122 | pop_reg r5 |
| 1123 | pop_reg r6 |
| 1124 | pop_reg r7 |
| 1125 | pop_reg r8 |
| 1126 | pop_reg r9 |
| 1127 | pop_reg r10 |
| 1128 | pop_reg r11 |
| 1129 | pop_reg r12, sp, 16 |
| 1130 | /* r13 already restored above */ |
| 1131 | pop_reg r14 |
| 1132 | pop_reg r15 |
| 1133 | pop_reg r16 |
| 1134 | pop_reg r17 |
| 1135 | pop_reg r18 |
| 1136 | pop_reg r19 |
| 1137 | pop_reg r20, sp, 16 |
| 1138 | /* r21 already restored above */ |
| 1139 | pop_reg r22 |
| 1140 | pop_reg r23 |
| 1141 | pop_reg r24 |
| 1142 | pop_reg r25 |
| 1143 | pop_reg r26 |
| 1144 | pop_reg r27 |
| 1145 | pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28) |
| 1146 | /* r29 already restored above */ |
| 1147 | bnez lr, .Lkernel_return |
| 1148 | pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR |
| 1149 | pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP |
| 1150 | ld sp, sp |
| 1151 | iret |
| 1152 | |
| 1153 | /* |
| 1154 | * We can't restore tp when in kernel mode, since a thread might |
| 1155 | * have migrated from another cpu and brought a stale tp value. |
| 1156 | */ |
| 1157 | .Lkernel_return: |
| 1158 | pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR |
| 1159 | ld sp, sp |
| 1160 | iret |
| 1161 | |
| 1162 | /* Restore callee-saved registers from r34 to r51. */ |
| 1163 | .Lrestore_callees: |
| 1164 | addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29) |
| 1165 | pop_reg r34 |
| 1166 | pop_reg r35 |
| 1167 | pop_reg r36 |
| 1168 | pop_reg r37 |
| 1169 | pop_reg r38 |
| 1170 | pop_reg r39 |
| 1171 | pop_reg r40 |
| 1172 | pop_reg r41 |
| 1173 | pop_reg r42 |
| 1174 | pop_reg r43 |
| 1175 | pop_reg r44 |
| 1176 | pop_reg r45 |
| 1177 | pop_reg r46 |
| 1178 | pop_reg r47 |
| 1179 | pop_reg r48 |
| 1180 | pop_reg r49 |
| 1181 | pop_reg r50 |
| 1182 | pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51) |
| 1183 | j .Lcontinue_restore_regs |
| 1184 | STD_ENDPROC(interrupt_return) |
| 1185 | |
| 1186 | /* |
| 1187 | * "NMI" interrupts mask ALL interrupts before calling the |
| 1188 | * handler, and don't check thread flags, etc., on the way |
| 1189 | * back out. In general, the only things we do here for NMIs |
| 1190 | * are register save/restore and dataplane kernel-TLB management. |
| 1191 | * We don't (for example) deal with start/stop of the sched tick. |
| 1192 | */ |
| 1193 | .pushsection .text.handle_nmi,"ax" |
| 1194 | handle_nmi: |
| 1195 | finish_interrupt_save handle_nmi |
| 1196 | { |
| 1197 | jalr r0 |
| 1198 | PTREGS_PTR(r0, PTREGS_OFFSET_BASE) |
| 1199 | } |
| 1200 | FEEDBACK_REENTER(handle_nmi) |
| 1201 | { |
| 1202 | movei r30, 1 |
Zhigang Lu | ba67823 | 2014-01-27 16:25:28 +0800 | [diff] [blame] | 1203 | cmpeq r31, r0, zero |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1204 | } |
| 1205 | j interrupt_return |
| 1206 | STD_ENDPROC(handle_nmi) |
| 1207 | |
| 1208 | /* |
| 1209 | * Parallel code for syscalls to handle_interrupt. |
| 1210 | */ |
| 1211 | .pushsection .text.handle_syscall,"ax" |
| 1212 | handle_syscall: |
| 1213 | finish_interrupt_save handle_syscall |
| 1214 | |
| 1215 | /* Enable irqs. */ |
| 1216 | TRACE_IRQS_ON |
| 1217 | IRQ_ENABLE(r20, r21) |
| 1218 | |
| 1219 | /* Bump the counter for syscalls made on this tile. */ |
| 1220 | moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) |
| 1221 | shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) |
| 1222 | shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET) |
| 1223 | add r20, r20, tp |
| 1224 | ld4s r21, r20 |
Chris Metcalf | fc327e2 | 2012-04-28 18:51:43 -0400 | [diff] [blame] | 1225 | { |
| 1226 | addi r21, r21, 1 |
| 1227 | move r31, sp |
| 1228 | } |
| 1229 | { |
| 1230 | st4 r20, r21 |
| 1231 | EXTRACT_THREAD_INFO(r31) |
| 1232 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1233 | |
| 1234 | /* Trace syscalls, if requested. */ |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1235 | addi r31, r31, THREAD_INFO_FLAGS_OFFSET |
Simon Marchi | ef567f2 | 2013-01-21 19:54:57 -0500 | [diff] [blame] | 1236 | { |
| 1237 | ld r30, r31 |
| 1238 | moveli r32, _TIF_SYSCALL_ENTRY_WORK |
| 1239 | } |
| 1240 | and r30, r30, r32 |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1241 | { |
| 1242 | addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET |
| 1243 | beqzt r30, .Lrestore_syscall_regs |
| 1244 | } |
Simon Marchi | ef18272 | 2012-12-22 00:21:10 -0500 | [diff] [blame] | 1245 | { |
| 1246 | PTREGS_PTR(r0, PTREGS_OFFSET_BASE) |
| 1247 | jal do_syscall_trace_enter |
| 1248 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1249 | FEEDBACK_REENTER(handle_syscall) |
| 1250 | |
| 1251 | /* |
| 1252 | * We always reload our registers from the stack at this |
| 1253 | * point. They might be valid, if we didn't build with |
| 1254 | * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not |
| 1255 | * doing syscall tracing, but there are enough cases now that it |
| 1256 | * seems simplest just to do the reload unconditionally. |
| 1257 | */ |
| 1258 | .Lrestore_syscall_regs: |
| 1259 | { |
| 1260 | ld r30, r30 |
| 1261 | PTREGS_PTR(r11, PTREGS_OFFSET_REG(0)) |
| 1262 | } |
| 1263 | pop_reg r0, r11 |
| 1264 | pop_reg r1, r11 |
| 1265 | pop_reg r2, r11 |
| 1266 | pop_reg r3, r11 |
| 1267 | pop_reg r4, r11 |
| 1268 | pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5) |
| 1269 | { |
| 1270 | ld TREG_SYSCALL_NR_NAME, r11 |
| 1271 | moveli r21, __NR_syscalls |
| 1272 | } |
| 1273 | |
| 1274 | /* Ensure that the syscall number is within the legal range. */ |
| 1275 | { |
| 1276 | moveli r20, hw2(sys_call_table) |
Chris Metcalf | 570fd50 | 2013-02-01 15:31:25 -0500 | [diff] [blame] | 1277 | #ifdef CONFIG_COMPAT |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1278 | blbs r30, .Lcompat_syscall |
Chris Metcalf | 570fd50 | 2013-02-01 15:31:25 -0500 | [diff] [blame] | 1279 | #endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1280 | } |
| 1281 | { |
| 1282 | cmpltu r21, TREG_SYSCALL_NR_NAME, r21 |
| 1283 | shl16insli r20, r20, hw1(sys_call_table) |
| 1284 | } |
| 1285 | { |
| 1286 | blbc r21, .Linvalid_syscall |
| 1287 | shl16insli r20, r20, hw0(sys_call_table) |
| 1288 | } |
| 1289 | .Lload_syscall_pointer: |
| 1290 | shl3add r20, TREG_SYSCALL_NR_NAME, r20 |
| 1291 | ld r20, r20 |
| 1292 | |
| 1293 | /* Jump to syscall handler. */ |
| 1294 | jalr r20 |
| 1295 | .Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */ |
| 1296 | |
| 1297 | /* |
| 1298 | * Write our r0 onto the stack so it gets restored instead |
| 1299 | * of whatever the user had there before. |
| 1300 | * In compat mode, sign-extend r0 before storing it. |
| 1301 | */ |
| 1302 | { |
| 1303 | PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) |
| 1304 | blbct r30, 1f |
| 1305 | } |
| 1306 | addxi r0, r0, 0 |
| 1307 | 1: st r29, r0 |
| 1308 | |
| 1309 | .Lsyscall_sigreturn_skip: |
| 1310 | FEEDBACK_REENTER(handle_syscall) |
| 1311 | |
| 1312 | /* Do syscall trace again, if requested. */ |
Simon Marchi | ef567f2 | 2013-01-21 19:54:57 -0500 | [diff] [blame] | 1313 | { |
| 1314 | ld r30, r31 |
| 1315 | moveli r32, _TIF_SYSCALL_EXIT_WORK |
| 1316 | } |
| 1317 | and r0, r30, r32 |
Chris Metcalf | 2858f85 | 2012-03-29 16:11:09 -0400 | [diff] [blame] | 1318 | { |
| 1319 | andi r0, r30, _TIF_SINGLESTEP |
| 1320 | beqzt r0, 1f |
| 1321 | } |
Simon Marchi | ef18272 | 2012-12-22 00:21:10 -0500 | [diff] [blame] | 1322 | { |
| 1323 | PTREGS_PTR(r0, PTREGS_OFFSET_BASE) |
| 1324 | jal do_syscall_trace_exit |
| 1325 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1326 | FEEDBACK_REENTER(handle_syscall) |
Chris Metcalf | 2858f85 | 2012-03-29 16:11:09 -0400 | [diff] [blame] | 1327 | andi r0, r30, _TIF_SINGLESTEP |
| 1328 | |
| 1329 | 1: beqzt r0, 2f |
| 1330 | |
| 1331 | /* Single stepping -- notify ptrace. */ |
| 1332 | { |
| 1333 | movei r0, SIGTRAP |
| 1334 | jal ptrace_notify |
| 1335 | } |
| 1336 | FEEDBACK_REENTER(handle_syscall) |
| 1337 | |
Chris Metcalf | e1d5c019 | 2012-03-30 16:29:06 -0400 | [diff] [blame] | 1338 | 2: { |
| 1339 | movei r30, 0 /* not an NMI */ |
| 1340 | j .Lresume_userspace /* jump into middle of interrupt_return */ |
| 1341 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1342 | |
Chris Metcalf | 570fd50 | 2013-02-01 15:31:25 -0500 | [diff] [blame] | 1343 | #ifdef CONFIG_COMPAT |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1344 | .Lcompat_syscall: |
| 1345 | /* |
| 1346 | * Load the base of the compat syscall table in r20, and |
| 1347 | * range-check the syscall number (duplicated from 64-bit path). |
| 1348 | * Sign-extend all the user's passed arguments to make them consistent. |
| 1349 | * Also save the original "r(n)" values away in "r(11+n)" in |
| 1350 | * case the syscall table entry wants to validate them. |
| 1351 | */ |
| 1352 | moveli r20, hw2(compat_sys_call_table) |
| 1353 | { |
| 1354 | cmpltu r21, TREG_SYSCALL_NR_NAME, r21 |
| 1355 | shl16insli r20, r20, hw1(compat_sys_call_table) |
| 1356 | } |
| 1357 | { |
| 1358 | blbc r21, .Linvalid_syscall |
| 1359 | shl16insli r20, r20, hw0(compat_sys_call_table) |
| 1360 | } |
| 1361 | { move r11, r0; addxi r0, r0, 0 } |
| 1362 | { move r12, r1; addxi r1, r1, 0 } |
| 1363 | { move r13, r2; addxi r2, r2, 0 } |
| 1364 | { move r14, r3; addxi r3, r3, 0 } |
| 1365 | { move r15, r4; addxi r4, r4, 0 } |
| 1366 | { move r16, r5; addxi r5, r5, 0 } |
| 1367 | j .Lload_syscall_pointer |
Chris Metcalf | 570fd50 | 2013-02-01 15:31:25 -0500 | [diff] [blame] | 1368 | #endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1369 | |
| 1370 | .Linvalid_syscall: |
| 1371 | /* Report an invalid syscall back to the user program */ |
| 1372 | { |
| 1373 | PTREGS_PTR(r29, PTREGS_OFFSET_REG(0)) |
| 1374 | movei r28, -ENOSYS |
| 1375 | } |
| 1376 | st r29, r28 |
Chris Metcalf | e1d5c019 | 2012-03-30 16:29:06 -0400 | [diff] [blame] | 1377 | { |
| 1378 | movei r30, 0 /* not an NMI */ |
| 1379 | j .Lresume_userspace /* jump into middle of interrupt_return */ |
| 1380 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1381 | STD_ENDPROC(handle_syscall) |
| 1382 | |
| 1383 | /* Return the address for oprofile to suppress in backtraces. */ |
| 1384 | STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall) |
| 1385 | lnk r0 |
| 1386 | { |
| 1387 | addli r0, r0, .Lhandle_syscall_link - . |
| 1388 | jrp lr |
| 1389 | } |
| 1390 | STD_ENDPROC(handle_syscall_link_address) |
| 1391 | |
| 1392 | STD_ENTRY(ret_from_fork) |
| 1393 | jal sim_notify_fork |
| 1394 | jal schedule_tail |
| 1395 | FEEDBACK_REENTER(ret_from_fork) |
Chris Metcalf | e1d5c019 | 2012-03-30 16:29:06 -0400 | [diff] [blame] | 1396 | { |
| 1397 | movei r30, 0 /* not an NMI */ |
| 1398 | j .Lresume_userspace /* jump into middle of interrupt_return */ |
| 1399 | } |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1400 | STD_ENDPROC(ret_from_fork) |
| 1401 | |
Chris Metcalf | 0f8b983 | 2012-10-19 16:25:12 -0400 | [diff] [blame] | 1402 | STD_ENTRY(ret_from_kernel_thread) |
| 1403 | jal sim_notify_fork |
| 1404 | jal schedule_tail |
| 1405 | FEEDBACK_REENTER(ret_from_fork) |
| 1406 | { |
| 1407 | move r0, r31 |
| 1408 | jalr r30 |
| 1409 | } |
| 1410 | FEEDBACK_REENTER(ret_from_kernel_thread) |
| 1411 | { |
| 1412 | movei r30, 0 /* not an NMI */ |
| 1413 | j .Lresume_userspace /* jump into middle of interrupt_return */ |
| 1414 | } |
| 1415 | STD_ENDPROC(ret_from_kernel_thread) |
| 1416 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1417 | /* Various stub interrupt handlers and syscall handlers */ |
| 1418 | |
| 1419 | STD_ENTRY_LOCAL(_kernel_double_fault) |
| 1420 | mfspr r1, SPR_EX_CONTEXT_K_0 |
| 1421 | move r2, lr |
| 1422 | move r3, sp |
| 1423 | move r4, r52 |
| 1424 | addi sp, sp, -C_ABI_SAVE_AREA_SIZE |
| 1425 | j kernel_double_fault |
| 1426 | STD_ENDPROC(_kernel_double_fault) |
| 1427 | |
| 1428 | STD_ENTRY_LOCAL(bad_intr) |
| 1429 | mfspr r2, SPR_EX_CONTEXT_K_0 |
| 1430 | panic "Unhandled interrupt %#x: PC %#lx" |
| 1431 | STD_ENDPROC(bad_intr) |
| 1432 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1433 | /* |
| 1434 | * Special-case sigreturn to not write r0 to the stack on return. |
| 1435 | * This is technically more efficient, but it also avoids difficulties |
| 1436 | * in the 64-bit OS when handling 32-bit compat code, since we must not |
| 1437 | * sign-extend r0 for the sigreturn return-value case. |
| 1438 | */ |
| 1439 | #define PTREGS_SYSCALL_SIGRETURN(x, reg) \ |
| 1440 | STD_ENTRY(_##x); \ |
| 1441 | addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \ |
| 1442 | { \ |
| 1443 | PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \ |
| 1444 | j x \ |
| 1445 | }; \ |
| 1446 | STD_ENDPROC(_##x) |
| 1447 | |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1448 | PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0) |
| 1449 | #ifdef CONFIG_COMPAT |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1450 | PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0) |
| 1451 | #endif |
| 1452 | |
Chris Metcalf | 6b14e41 | 2012-10-23 13:30:54 -0400 | [diff] [blame] | 1453 | /* Save additional callee-saves to pt_regs and jump to standard function. */ |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1454 | STD_ENTRY(_sys_clone) |
| 1455 | push_extra_callee_saves r4 |
| 1456 | j sys_clone |
| 1457 | STD_ENDPROC(_sys_clone) |
| 1458 | |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 1459 | /* |
| 1460 | * Recover r3, r2, r1 and r0 here saved by unalign fast vector. |
| 1461 | * The vector area limit is 32 bundles, so we handle the reload here. |
| 1462 | * r0, r1, r2 are in thread_info from low to high memory in order. |
| 1463 | * r3 points to location the original r3 was saved. |
| 1464 | * We put this code in the __HEAD section so it can be reached |
| 1465 | * via a conditional branch from the fast path. |
| 1466 | */ |
| 1467 | __HEAD |
| 1468 | hand_unalign_slow: |
| 1469 | andi sp, sp, ~1 |
| 1470 | hand_unalign_slow_badsp: |
| 1471 | addi r3, r3, -(3 * 8) |
| 1472 | ld_add r0, r3, 8 |
| 1473 | ld_add r1, r3, 8 |
| 1474 | ld r2, r3 |
| 1475 | hand_unalign_slow_nonuser: |
| 1476 | mfspr r3, SPR_SYSTEM_SAVE_K_1 |
| 1477 | __int_hand INT_UNALIGN_DATA, UNALIGN_DATA_SLOW, int_unalign |
| 1478 | |
| 1479 | /* The unaligned data support needs to read all the registers. */ |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1480 | int_unalign: |
| 1481 | push_extra_callee_saves r0 |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 1482 | j do_unaligned |
| 1483 | ENDPROC(hand_unalign_slow) |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1484 | |
Chris Metcalf | e172353 | 2012-03-29 14:52:00 -0400 | [diff] [blame] | 1485 | /* Fill the return address stack with nonzero entries. */ |
| 1486 | STD_ENTRY(fill_ra_stack) |
| 1487 | { |
| 1488 | move r0, lr |
| 1489 | jal 1f |
| 1490 | } |
| 1491 | 1: jal 2f |
| 1492 | 2: jal 3f |
| 1493 | 3: jal 4f |
| 1494 | 4: jrp r0 |
| 1495 | STD_ENDPROC(fill_ra_stack) |
| 1496 | |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 1497 | .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt |
| 1498 | .org (\vecnum << 8) |
| 1499 | __int_hand \vecnum, \vecname, \c_routine, \processing |
| 1500 | .endm |
| 1501 | |
Chris Metcalf | acbde1d | 2013-09-03 14:41:36 -0400 | [diff] [blame] | 1502 | /* Include .intrpt array of interrupt vectors */ |
| 1503 | .section ".intrpt", "ax" |
| 1504 | .global intrpt_start |
| 1505 | intrpt_start: |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1506 | |
Zhigang Lu | 8e3441e | 2014-01-27 15:11:07 +0800 | [diff] [blame] | 1507 | #ifndef CONFIG_USE_PMC |
| 1508 | #define handle_perf_interrupt bad_intr |
| 1509 | #endif |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1510 | |
| 1511 | #ifndef CONFIG_HARDWALL |
| 1512 | #define do_hardwall_trap bad_intr |
| 1513 | #endif |
| 1514 | |
Chris Metcalf | a714fff | 2012-03-29 15:23:54 -0400 | [diff] [blame] | 1515 | int_hand INT_MEM_ERROR, MEM_ERROR, do_trap |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1516 | int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr |
| 1517 | #if CONFIG_KERNEL_PL == 2 |
| 1518 | int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle |
| 1519 | int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr |
| 1520 | #else |
| 1521 | int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr |
| 1522 | int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle |
| 1523 | #endif |
| 1524 | int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr |
| 1525 | int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr |
| 1526 | int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr |
| 1527 | int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault |
| 1528 | int_hand INT_ILL, ILL, do_trap |
| 1529 | int_hand INT_GPV, GPV, do_trap |
| 1530 | int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap |
| 1531 | int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap |
| 1532 | int_hand INT_SWINT_3, SWINT_3, do_trap |
| 1533 | int_hand INT_SWINT_2, SWINT_2, do_trap |
| 1534 | int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall |
| 1535 | int_hand INT_SWINT_0, SWINT_0, do_trap |
| 1536 | int_hand INT_ILL_TRANS, ILL_TRANS, do_trap |
Chris Metcalf | 2f9ac29 | 2013-08-06 16:04:13 -0400 | [diff] [blame] | 1537 | int_hand_unalign_fast INT_UNALIGN_DATA, UNALIGN_DATA |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1538 | int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault |
| 1539 | int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault |
Chris Metcalf | b8ace08 | 2012-03-30 16:01:48 -0400 | [diff] [blame] | 1540 | int_hand INT_IDN_FIREWALL, IDN_FIREWALL, do_hardwall_trap |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1541 | int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap |
| 1542 | int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt |
| 1543 | int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr |
| 1544 | int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr |
| 1545 | int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr |
| 1546 | int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr |
| 1547 | int_hand INT_IPI_3, IPI_3, bad_intr |
| 1548 | #if CONFIG_KERNEL_PL == 2 |
| 1549 | int_hand INT_IPI_2, IPI_2, tile_dev_intr |
| 1550 | int_hand INT_IPI_1, IPI_1, bad_intr |
| 1551 | #else |
| 1552 | int_hand INT_IPI_2, IPI_2, bad_intr |
| 1553 | int_hand INT_IPI_1, IPI_1, tile_dev_intr |
| 1554 | #endif |
| 1555 | int_hand INT_IPI_0, IPI_0, bad_intr |
| 1556 | int_hand INT_PERF_COUNT, PERF_COUNT, \ |
Zhigang Lu | 8e3441e | 2014-01-27 15:11:07 +0800 | [diff] [blame] | 1557 | handle_perf_interrupt, handle_nmi |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1558 | int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \ |
Zhigang Lu | 8e3441e | 2014-01-27 15:11:07 +0800 | [diff] [blame] | 1559 | handle_perf_interrupt, handle_nmi |
Chris Metcalf | 18aecc2 | 2011-05-04 14:38:26 -0400 | [diff] [blame] | 1560 | int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr |
| 1561 | #if CONFIG_KERNEL_PL == 2 |
| 1562 | dc_dispatch INT_INTCTRL_2, INTCTRL_2 |
| 1563 | int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr |
| 1564 | #else |
| 1565 | int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr |
| 1566 | dc_dispatch INT_INTCTRL_1, INTCTRL_1 |
| 1567 | #endif |
| 1568 | int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr |
| 1569 | int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \ |
| 1570 | hv_message_intr |
| 1571 | int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr |
| 1572 | int_hand INT_I_ASID, I_ASID, bad_intr |
| 1573 | int_hand INT_D_ASID, D_ASID, bad_intr |
| 1574 | int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap |
| 1575 | |
| 1576 | /* Synthetic interrupt delivered only by the simulator */ |
| 1577 | int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint |
Chris Metcalf | e5701b7 | 2015-05-04 17:26:35 -0400 | [diff] [blame] | 1578 | /* Synthetic interrupt delivered by hv */ |
| 1579 | int_hand INT_NMI_DWNCL, NMI_DWNCL, do_nmi, handle_nmi |