blob: 8c4c040a47b8cf69e75b4f022dafc3542f2ae908 [file] [log] [blame]
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
Joe Perches516304b2012-03-18 17:30:52 -070043#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
Jiri Slabyfa1c1142007-08-12 17:33:16 +020045#include <linux/module.h>
46#include <linux/delay.h>
Alexey Dobriyanb7f080c2011-06-16 11:01:34 +000047#include <linux/dma-mapping.h>
Jiri Slaby274c7c32008-07-15 17:44:20 +020048#include <linux/hardirq.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020049#include <linux/if.h>
Jiri Slaby274c7c32008-07-15 17:44:20 +020050#include <linux/io.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020051#include <linux/netdevice.h>
52#include <linux/cache.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020053#include <linux/ethtool.h>
54#include <linux/uaccess.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090055#include <linux/slab.h>
Ben Greearb1ae1ed2010-09-30 12:22:58 -070056#include <linux/etherdevice.h>
Pavel Roskin931be262011-07-26 22:26:59 -040057#include <linux/nl80211.h>
Jiri Slabyfa1c1142007-08-12 17:33:16 +020058
59#include <net/ieee80211_radiotap.h>
60
61#include <asm/unaligned.h>
62
63#include "base.h"
64#include "reg.h"
65#include "debug.h"
Bruno Randolf2111ac02010-04-02 18:44:08 +090066#include "ani.h"
Pavel Roskin931be262011-07-26 22:26:59 -040067#include "ath5k.h"
68#include "../regd.h"
Jiri Slabyfa1c1142007-08-12 17:33:16 +020069
Bob Copeland0e472252011-01-24 23:32:55 -050070#define CREATE_TRACE_POINTS
71#include "trace.h"
72
Rusty Russelleb939922011-12-19 14:08:01 +000073bool ath5k_modparam_nohwcrypt;
John W. Linville18cb6e32011-01-05 09:39:59 -050074module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
Bob Copeland9ad9a262008-10-29 08:30:54 -040075MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020076
Rusty Russelleb939922011-12-19 14:08:01 +000077static bool modparam_fastchanswitch;
Nick Kossifidisa99168e2011-06-02 03:09:48 +030078module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
79MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
80
John W. Linville11deb532012-01-24 14:58:47 -050081static bool ath5k_modparam_no_hw_rfkill_switch;
Nick Kossifidis84e1e732011-11-25 20:40:27 +020082module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch,
83 bool, S_IRUGO);
84MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state");
85
Nick Kossifidisa99168e2011-06-02 03:09:48 +030086
Jiri Slabyfa1c1142007-08-12 17:33:16 +020087/* Module info */
88MODULE_AUTHOR("Jiri Slaby");
89MODULE_AUTHOR("Nick Kossifidis");
90MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
91MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
92MODULE_LICENSE("Dual BSD/GPL");
Jiri Slabyfa1c1142007-08-12 17:33:16 +020093
Felix Fietkau132b1c32010-12-02 10:26:56 +010094static int ath5k_init(struct ieee80211_hw *hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -040095static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
Nick Kossifidis8aec7af2010-11-23 21:39:28 +020096 bool skip_pcu);
Jiri Slabyfa1c1142007-08-12 17:33:16 +020097
Jiri Slabyfa1c1142007-08-12 17:33:16 +020098/* Known SREVs */
Jiri Slaby2c91108c2009-03-07 10:26:41 +010099static const struct ath5k_srev_name srev_names[] = {
Felix Fietkaua0b907e2010-12-02 10:27:16 +0100100#ifdef CONFIG_ATHEROS_AR231X
101 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
103 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
104 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
106 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
108#else
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300109 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
110 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
111 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
112 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
113 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
114 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
115 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
116 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
117 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
118 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
119 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
120 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
121 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
122 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
123 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
124 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
125 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
126 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
Felix Fietkaua0b907e2010-12-02 10:27:16 +0100127#endif
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300128 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200129 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
130 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300131 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200132 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
133 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
134 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300135 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200136 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
137 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300138 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
139 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
140 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
Nick Kossifidis1bef0162008-09-29 02:09:09 +0300141 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200142 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
Felix Fietkaua0b907e2010-12-02 10:27:16 +0100143#ifdef CONFIG_ATHEROS_AR231X
144 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
145 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
146#endif
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
Jiri Slaby2c91108c2009-03-07 10:26:41 +0100150static const struct ieee80211_rate ath5k_rates[] = {
Bruno Randolf63266a62008-07-30 17:12:58 +0200151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
Bruno Randolf63266a62008-07-30 17:12:58 +0200189};
190
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200191static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
192{
193 u64 tsf = ath5k_hw_get_tsf64(ah);
194
195 if ((tsf & 0x7fff) < rstamp)
196 tsf -= 0x8000;
197
198 return (tsf & ~0x7fff) | rstamp;
199}
200
Felix Fietkaue5b046d2010-12-02 10:27:01 +0100201const char *
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200202ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
203{
204 const char *name = "xxxxx";
205 unsigned int i;
206
207 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
208 if (srev_names[i].sr_type != type)
209 continue;
Nick Kossifidis75d0edb2008-09-29 01:24:44 +0300210
211 if ((val & 0xf0) == srev_names[i].sr_val)
212 name = srev_names[i].sr_name;
213
214 if ((val & 0xff) == srev_names[i].sr_val) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200215 name = srev_names[i].sr_name;
216 break;
217 }
218 }
219
220 return name;
221}
Luis R. Rodrigueze5aa8472009-09-10 16:55:11 -0700222static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
223{
224 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
225 return ath5k_hw_reg_read(ah, reg_offset);
226}
227
228static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
229{
230 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
231 ath5k_hw_reg_write(ah, val, reg_offset);
232}
233
234static const struct ath_ops ath5k_common_ops = {
235 .read = ath5k_ioread32,
236 .write = ath5k_iowrite32,
237};
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200238
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200239/***********************\
240* Driver Initialization *
241\***********************/
242
Bob Copelandf769c362009-03-30 22:30:31 -0400243static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
244{
245 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
Pavel Roskine0d687b2011-07-14 20:21:55 -0400246 struct ath5k_hw *ah = hw->priv;
247 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
Bob Copelandf769c362009-03-30 22:30:31 -0400248
Luis R. Rodriguez608b88c2009-08-17 18:07:23 -0700249 return ath_reg_notifier_apply(wiphy, request, regulatory);
Bob Copelandf769c362009-03-30 22:30:31 -0400250}
251
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200252/********************\
253* Channel/mode setup *
254\********************/
255
256/*
Luis R. Rodriguez2f8684c2012-07-06 15:21:51 -0700257 * Returns true for the channel numbers used.
Bob Copeland42639fc2009-03-30 08:05:29 -0400258 */
Luis R. Rodriguez2f8684c2012-07-06 15:21:51 -0700259#ifdef CONFIG_ATH5K_TEST_CHANNELS
260static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
261{
262 return true;
263}
264
265#else
Bruno Randolf410e6122011-01-19 18:20:57 +0900266static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
Bob Copeland42639fc2009-03-30 08:05:29 -0400267{
Bruno Randolf410e6122011-01-19 18:20:57 +0900268 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
269 return true;
270
271 return /* UNII 1,2 */
272 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
Bob Copeland42639fc2009-03-30 08:05:29 -0400273 /* midband */
274 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
275 /* UNII-3 */
Bruno Randolf410e6122011-01-19 18:20:57 +0900276 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
277 /* 802.11j 5.030-5.080 GHz (20MHz) */
278 (chan == 8 || chan == 12 || chan == 16) ||
279 /* 802.11j 4.9GHz (20MHz) */
280 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
Bob Copeland42639fc2009-03-30 08:05:29 -0400281}
Luis R. Rodriguez2f8684c2012-07-06 15:21:51 -0700282#endif
Bob Copeland42639fc2009-03-30 08:05:29 -0400283
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200284static unsigned int
Bruno Randolf97d9c3a2011-01-19 18:20:52 +0900285ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
286 unsigned int mode, unsigned int max)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200287{
Pavel Roskin32c25462011-07-23 09:29:09 -0400288 unsigned int count, size, freq, ch;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900289 enum ieee80211_band band;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200290
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200291 switch (mode) {
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500292 case AR5K_MODE_11A:
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200293 /* 1..220, but 2GHz frequencies are filtered by check_channel */
Bruno Randolf97d9c3a2011-01-19 18:20:52 +0900294 size = 220;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900295 band = IEEE80211_BAND_5GHZ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200296 break;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500297 case AR5K_MODE_11B:
298 case AR5K_MODE_11G:
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500299 size = 26;
Bruno Randolf90c02d72011-01-19 18:20:36 +0900300 band = IEEE80211_BAND_2GHZ;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200301 break;
302 default:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400303 ATH5K_WARN(ah, "bad mode, not copying channels\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200304 return 0;
305 }
306
Bruno Randolf2b1351a2011-01-21 12:19:52 +0900307 count = 0;
308 for (ch = 1; ch <= size && count < max; ch++) {
Bruno Randolf90c02d72011-01-19 18:20:36 +0900309 freq = ieee80211_channel_to_frequency(ch, band);
310
311 if (freq == 0) /* mapping failed - not a standard channel */
312 continue;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500313
Pavel Roskin32c25462011-07-23 09:29:09 -0400314 /* Write channel info, needed for ath5k_channel_ok() */
315 channels[count].center_freq = freq;
316 channels[count].band = band;
317 channels[count].hw_value = mode;
318
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200319 /* Check if channel is supported by the chipset */
Pavel Roskin32c25462011-07-23 09:29:09 -0400320 if (!ath5k_channel_ok(ah, &channels[count]))
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200321 continue;
322
Luis R. Rodriguez2f8684c2012-07-06 15:21:51 -0700323 if (!ath5k_is_standard_channel(ch, band))
Bob Copeland42639fc2009-03-30 08:05:29 -0400324 continue;
325
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200326 count++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200327 }
328
329 return count;
330}
331
Bruno Randolf63266a62008-07-30 17:12:58 +0200332static void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400333ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
Bruno Randolf63266a62008-07-30 17:12:58 +0200334{
335 u8 i;
336
337 for (i = 0; i < AR5K_MAX_RATES; i++)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400338 ah->rate_idx[b->band][i] = -1;
Bruno Randolf63266a62008-07-30 17:12:58 +0200339
340 for (i = 0; i < b->n_bitrates; i++) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400341 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
Bruno Randolf63266a62008-07-30 17:12:58 +0200342 if (b->bitrates[i].hw_value_short)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400343 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
Bruno Randolf63266a62008-07-30 17:12:58 +0200344 }
345}
346
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200347static int
Bruno Randolf63266a62008-07-30 17:12:58 +0200348ath5k_setup_bands(struct ieee80211_hw *hw)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200349{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400350 struct ath5k_hw *ah = hw->priv;
Bruno Randolf63266a62008-07-30 17:12:58 +0200351 struct ieee80211_supported_band *sband;
352 int max_c, count_c = 0;
353 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200354
Pavel Roskine0d687b2011-07-14 20:21:55 -0400355 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
356 max_c = ARRAY_SIZE(ah->channels);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200357
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500358 /* 2GHz band */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400359 sband = &ah->sbands[IEEE80211_BAND_2GHZ];
Bruno Randolf63266a62008-07-30 17:12:58 +0200360 sband->band = IEEE80211_BAND_2GHZ;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400361 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200362
Pavel Roskine0d687b2011-07-14 20:21:55 -0400363 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
Bruno Randolf63266a62008-07-30 17:12:58 +0200364 /* G mode */
365 memcpy(sband->bitrates, &ath5k_rates[0],
366 sizeof(struct ieee80211_rate) * 12);
367 sband->n_bitrates = 12;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200368
Pavel Roskine0d687b2011-07-14 20:21:55 -0400369 sband->channels = ah->channels;
Bruno Randolf08105692011-01-19 18:20:47 +0900370 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Bruno Randolf63266a62008-07-30 17:12:58 +0200371 AR5K_MODE_11G, max_c);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500372
373 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
Bruno Randolf63266a62008-07-30 17:12:58 +0200374 count_c = sband->n_channels;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500375 max_c -= count_c;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400376 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
Bruno Randolf63266a62008-07-30 17:12:58 +0200377 /* B mode */
378 memcpy(sband->bitrates, &ath5k_rates[0],
379 sizeof(struct ieee80211_rate) * 4);
380 sband->n_bitrates = 4;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500381
Bruno Randolf63266a62008-07-30 17:12:58 +0200382 /* 5211 only supports B rates and uses 4bit rate codes
383 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
384 * fix them up here:
385 */
386 if (ah->ah_version == AR5K_AR5211) {
387 for (i = 0; i < 4; i++) {
388 sband->bitrates[i].hw_value =
389 sband->bitrates[i].hw_value & 0xF;
390 sband->bitrates[i].hw_value_short =
391 sband->bitrates[i].hw_value_short & 0xF;
392 }
393 }
394
Pavel Roskine0d687b2011-07-14 20:21:55 -0400395 sband->channels = ah->channels;
Bruno Randolf08105692011-01-19 18:20:47 +0900396 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Bruno Randolf63266a62008-07-30 17:12:58 +0200397 AR5K_MODE_11B, max_c);
398
399 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
400 count_c = sband->n_channels;
401 max_c -= count_c;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500402 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400403 ath5k_setup_rate_idx(ah, sband);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500404
Bruno Randolf63266a62008-07-30 17:12:58 +0200405 /* 5GHz band, A mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400406 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
407 sband = &ah->sbands[IEEE80211_BAND_5GHZ];
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500408 sband->band = IEEE80211_BAND_5GHZ;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400409 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
Bruno Randolf63266a62008-07-30 17:12:58 +0200410
411 memcpy(sband->bitrates, &ath5k_rates[4],
412 sizeof(struct ieee80211_rate) * 8);
413 sband->n_bitrates = 8;
414
Pavel Roskine0d687b2011-07-14 20:21:55 -0400415 sband->channels = &ah->channels[count_c];
Bruno Randolf08105692011-01-19 18:20:47 +0900416 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500417 AR5K_MODE_11A, max_c);
418
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500419 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
420 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400421 ath5k_setup_rate_idx(ah, sband);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500422
Pavel Roskine0d687b2011-07-14 20:21:55 -0400423 ath5k_debug_dump_bands(ah);
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500424
425 return 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200426}
427
428/*
Joerg Alberte30eb4a2009-08-05 01:52:07 +0200429 * Set/change channels. We always reset the chip.
430 * To accomplish this we must first cleanup any pending DMA,
431 * then restart stuff after a la ath5k_init.
Bob Copelandbe009372009-01-22 08:44:16 -0500432 *
Pavel Roskine0d687b2011-07-14 20:21:55 -0400433 * Called with ah->lock.
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200434 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900435int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400436ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200437{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400438 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +0900439 "channel set, resetting (%u -> %u MHz)\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -0400440 ah->curchan->center_freq, chan->center_freq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200441
Joerg Alberte30eb4a2009-08-05 01:52:07 +0200442 /*
443 * To switch channels clear any pending DMA operations;
444 * wait long enough for the RX fifo to drain, reset the
445 * hardware at the new frequency, and then re-enable
446 * the relevant bits of the h/w.
447 */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400448 return ath5k_reset(ah, chan, true);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200449}
450
Ben Greeare4b0b322011-03-03 14:39:05 -0800451void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700452{
Ben Greeare4b0b322011-03-03 14:39:05 -0800453 struct ath5k_vif_iter_data *iter_data = data;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700454 int i;
Ben Greear62c58fb2010-10-08 12:01:15 -0700455 struct ath5k_vif *avf = (void *)vif->drv_priv;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700456
457 if (iter_data->hw_macaddr)
458 for (i = 0; i < ETH_ALEN; i++)
459 iter_data->mask[i] &=
460 ~(iter_data->hw_macaddr[i] ^ mac[i]);
461
462 if (!iter_data->found_active) {
463 iter_data->found_active = true;
464 memcpy(iter_data->active_mac, mac, ETH_ALEN);
465 }
466
467 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
Joe Perches2e42e472012-05-09 17:17:46 +0000468 if (ether_addr_equal(iter_data->hw_macaddr, mac))
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700469 iter_data->need_set_hw_addr = false;
470
471 if (!iter_data->any_assoc) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700472 if (avf->assoc)
473 iter_data->any_assoc = true;
474 }
Ben Greear62c58fb2010-10-08 12:01:15 -0700475
476 /* Calculate combined mode - when APs are active, operate in AP mode.
477 * Otherwise use the mode of the new interface. This can currently
478 * only deal with combinations of APs and STAs. Only one ad-hoc
Ben Greear7afbb2f2010-11-10 11:43:51 -0800479 * interfaces is allowed.
Ben Greear62c58fb2010-10-08 12:01:15 -0700480 */
481 if (avf->opmode == NL80211_IFTYPE_AP)
482 iter_data->opmode = NL80211_IFTYPE_AP;
Ben Greeare4b0b322011-03-03 14:39:05 -0800483 else {
484 if (avf->opmode == NL80211_IFTYPE_STATION)
485 iter_data->n_stas++;
Ben Greear62c58fb2010-10-08 12:01:15 -0700486 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
487 iter_data->opmode = avf->opmode;
Ben Greeare4b0b322011-03-03 14:39:05 -0800488 }
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700489}
490
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900491void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400492ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900493 struct ieee80211_vif *vif)
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700494{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400495 struct ath_common *common = ath5k_hw_common(ah);
Ben Greeare4b0b322011-03-03 14:39:05 -0800496 struct ath5k_vif_iter_data iter_data;
497 u32 rfilt;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700498
499 /*
500 * Use the hardware MAC address as reference, the hardware uses it
501 * together with the BSSID mask when matching addresses.
502 */
503 iter_data.hw_macaddr = common->macaddr;
504 memset(&iter_data.mask, 0xff, ETH_ALEN);
505 iter_data.found_active = false;
506 iter_data.need_set_hw_addr = true;
Ben Greear62c58fb2010-10-08 12:01:15 -0700507 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
Ben Greeare4b0b322011-03-03 14:39:05 -0800508 iter_data.n_stas = 0;
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700509
510 if (vif)
Ben Greeare4b0b322011-03-03 14:39:05 -0800511 ath5k_vif_iter(&iter_data, vif->addr, vif);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700512
513 /* Get list of all active MAC addresses */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400514 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700515 &iter_data);
Pavel Roskine0d687b2011-07-14 20:21:55 -0400516 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700517
Pavel Roskine0d687b2011-07-14 20:21:55 -0400518 ah->opmode = iter_data.opmode;
519 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
Ben Greear62c58fb2010-10-08 12:01:15 -0700520 /* Nothing active, default to station mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400521 ah->opmode = NL80211_IFTYPE_STATION;
Ben Greear62c58fb2010-10-08 12:01:15 -0700522
Pavel Roskine0d687b2011-07-14 20:21:55 -0400523 ath5k_hw_set_opmode(ah, ah->opmode);
524 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
525 ah->opmode, ath_opmode_to_string(ah->opmode));
Ben Greear62c58fb2010-10-08 12:01:15 -0700526
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700527 if (iter_data.need_set_hw_addr && iter_data.found_active)
Pavel Roskine0d687b2011-07-14 20:21:55 -0400528 ath5k_hw_set_lladdr(ah, iter_data.active_mac);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700529
Pavel Roskine0d687b2011-07-14 20:21:55 -0400530 if (ath5k_hw_hasbssidmask(ah))
531 ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700532
Ben Greeare4b0b322011-03-03 14:39:05 -0800533 /* Set up RX Filter */
534 if (iter_data.n_stas > 1) {
535 /* If you have multiple STA interfaces connected to
536 * different APs, ARPs are not received (most of the time?)
Pavel Roskin6a2a0e72011-07-09 00:17:51 -0400537 * Enabling PROMISC appears to fix that problem.
Ben Greeare4b0b322011-03-03 14:39:05 -0800538 */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400539 ah->filter_flags |= AR5K_RX_FILTER_PROM;
Ben Greeare4b0b322011-03-03 14:39:05 -0800540 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200541
Pavel Roskine0d687b2011-07-14 20:21:55 -0400542 rfilt = ah->filter_flags;
543 ath5k_hw_set_rx_filter(ah, rfilt);
544 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200545}
546
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500547static inline int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400548ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
Bruno Randolf63266a62008-07-30 17:12:58 +0200549{
Bob Copelandb7266042009-03-02 21:55:18 -0500550 int rix;
551
552 /* return base rate on errors */
553 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
554 "hw_rix out of bounds: %x\n", hw_rix))
555 return 0;
556
Pavel Roskine0d687b2011-07-14 20:21:55 -0400557 rix = ah->rate_idx[ah->curchan->band][hw_rix];
Bob Copelandb7266042009-03-02 21:55:18 -0500558 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
559 rix = 0;
560
561 return rix;
Luis R. Rodriguezd8ee3982008-02-03 21:51:04 -0500562}
563
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200564/***************\
565* Buffers setup *
566\***************/
567
Bob Copelandb6ea0352009-01-10 14:42:54 -0500568static
Pavel Roskine0d687b2011-07-14 20:21:55 -0400569struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
Bob Copelandb6ea0352009-01-10 14:42:54 -0500570{
Pavel Roskine0d687b2011-07-14 20:21:55 -0400571 struct ath_common *common = ath5k_hw_common(ah);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500572 struct sk_buff *skb;
Bob Copelandb6ea0352009-01-10 14:42:54 -0500573
574 /*
575 * Allocate buffer with headroom_needed space for the
576 * fake physical layer header at the start.
577 */
Luis R. Rodriguezdb719712009-09-10 11:20:57 -0700578 skb = ath_rxbuf_alloc(common,
Luis R. Rodriguezdd849782009-11-04 09:44:50 -0800579 common->rx_bufsize,
Luis R. Rodriguezaeb63cf2009-08-12 09:57:00 -0700580 GFP_ATOMIC);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500581
582 if (!skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400583 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
Luis R. Rodriguezdd849782009-11-04 09:44:50 -0800584 common->rx_bufsize);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500585 return NULL;
586 }
Bob Copelandb6ea0352009-01-10 14:42:54 -0500587
Pavel Roskine0d687b2011-07-14 20:21:55 -0400588 *skb_addr = dma_map_single(ah->dev,
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -0800589 skb->data, common->rx_bufsize,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100590 DMA_FROM_DEVICE);
591
Pavel Roskine0d687b2011-07-14 20:21:55 -0400592 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
593 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500594 dev_kfree_skb(skb);
595 return NULL;
596 }
597 return skb;
598}
599
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200600static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400601ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200602{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200603 struct sk_buff *skb = bf->skb;
604 struct ath5k_desc *ds;
Bruno Randolfb5eae9f2010-05-19 10:18:16 +0900605 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200606
Bob Copelandb6ea0352009-01-10 14:42:54 -0500607 if (!skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400608 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
Bob Copelandb6ea0352009-01-10 14:42:54 -0500609 if (!skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200610 return -ENOMEM;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200611 bf->skb = skb;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200612 }
613
614 /*
615 * Setup descriptors. For receive we always terminate
616 * the descriptor list with a self-linked entry so we'll
617 * not get overrun under high load (as can happen with a
618 * 5212 when ANI processing enables PHY error frames).
619 *
Bruno Randolfbeade632010-06-16 19:11:25 +0900620 * To ensure the last descriptor is self-linked we create
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200621 * each descriptor as self-linked and add it to the end. As
622 * each additional descriptor is added the previous self-linked
Bruno Randolfbeade632010-06-16 19:11:25 +0900623 * entry is "fixed" naturally. This should be safe even
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200624 * if DMA is happening. When processing RX interrupts we
625 * never remove/process the last, self-linked, entry on the
Bruno Randolfbeade632010-06-16 19:11:25 +0900626 * descriptor list. This ensures the hardware always has
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200627 * someplace to write a new frame.
628 */
629 ds = bf->desc;
630 ds->ds_link = bf->daddr; /* link to self */
631 ds->ds_data = bf->skbaddr;
Bruno Randolfa6668192010-06-16 19:12:01 +0900632 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
Bruno Randolf0452d4a2010-06-16 19:11:35 +0900633 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400634 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
Bruno Randolfb5eae9f2010-05-19 10:18:16 +0900635 return ret;
Bruno Randolf0452d4a2010-06-16 19:11:35 +0900636 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200637
Pavel Roskine0d687b2011-07-14 20:21:55 -0400638 if (ah->rxlink != NULL)
639 *ah->rxlink = bf->daddr;
640 ah->rxlink = &ds->ds_link;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200641 return 0;
642}
643
Bob Copeland2ac29272010-02-09 13:06:54 -0500644static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
645{
646 struct ieee80211_hdr *hdr;
647 enum ath5k_pkt_type htype;
648 __le16 fc;
649
650 hdr = (struct ieee80211_hdr *)skb->data;
651 fc = hdr->frame_control;
652
653 if (ieee80211_is_beacon(fc))
654 htype = AR5K_PKT_TYPE_BEACON;
655 else if (ieee80211_is_probe_resp(fc))
656 htype = AR5K_PKT_TYPE_PROBE_RESP;
657 else if (ieee80211_is_atim(fc))
658 htype = AR5K_PKT_TYPE_ATIM;
659 else if (ieee80211_is_pspoll(fc))
660 htype = AR5K_PKT_TYPE_PSPOLL;
661 else
662 htype = AR5K_PKT_TYPE_NORMAL;
663
664 return htype;
665}
666
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200667static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400668ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
Benoit Papillault8127fbd2010-02-27 23:05:26 +0100669 struct ath5k_txq *txq, int padsize)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200670{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200671 struct ath5k_desc *ds = bf->desc;
672 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +0200673 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200674 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200675 struct ieee80211_rate *rate;
676 unsigned int mrr_rate[3], mrr_tries[3];
677 int i, ret;
Bob Copeland8902ff42009-01-22 08:44:20 -0500678 u16 hw_rate;
Bob Copeland07c1e852009-01-22 08:44:21 -0500679 u16 cts_rate = 0;
680 u16 duration = 0;
Bob Copeland8902ff42009-01-22 08:44:20 -0500681 u8 rc_flags;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200682
683 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
Johannes Berge039fa42008-05-15 12:55:29 +0200684
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200685 /* XXX endianness */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400686 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100687 DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200688
Pavel Roskine0d687b2011-07-14 20:21:55 -0400689 rate = ieee80211_get_tx_rate(ah->hw, info);
John W. Linvilled8e1ba72010-08-24 15:27:34 -0400690 if (!rate) {
691 ret = -EINVAL;
692 goto err_unmap;
693 }
Bob Copeland8902ff42009-01-22 08:44:20 -0500694
Johannes Berge039fa42008-05-15 12:55:29 +0200695 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200696 flags |= AR5K_TXDESC_NOACK;
697
Bob Copeland8902ff42009-01-22 08:44:20 -0500698 rc_flags = info->control.rates[0].flags;
699 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
700 rate->hw_value_short : rate->hw_value;
701
Bruno Randolf281c56d2008-02-05 18:44:55 +0900702 pktlen = skb->len;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200703
Nick Kossifidis8f655dd2009-03-15 22:20:35 +0200704 /* FIXME: If we are in g mode and rate is a CCK rate
705 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
706 * from tx power (value is in dB units already) */
Bob Copeland362695e2009-02-15 12:06:12 -0500707 if (info->control.hw_key) {
708 keyidx = info->control.hw_key->hw_key_idx;
709 pktlen += info->control.hw_key->icv_len;
710 }
Bob Copeland07c1e852009-01-22 08:44:21 -0500711 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
712 flags |= AR5K_TXDESC_RTSENA;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400713 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
714 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700715 info->control.vif, pktlen, info));
Bob Copeland07c1e852009-01-22 08:44:21 -0500716 }
717 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
718 flags |= AR5K_TXDESC_CTSENA;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400719 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
720 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700721 info->control.vif, pktlen, info));
Bob Copeland07c1e852009-01-22 08:44:21 -0500722 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200723 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
Benoit Papillault8127fbd2010-02-27 23:05:26 +0100724 ieee80211_get_hdrlen_from_skb(skb), padsize,
Bob Copeland2ac29272010-02-09 13:06:54 -0500725 get_hw_packet_type(skb),
Pavel Roskine0d687b2011-07-14 20:21:55 -0400726 (ah->power_level * 2),
Bob Copeland8902ff42009-01-22 08:44:20 -0500727 hw_rate,
Nick Kossifidis2bed03e2009-04-30 15:55:49 -0400728 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
Bob Copeland07c1e852009-01-22 08:44:21 -0500729 cts_rate, duration);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200730 if (ret)
731 goto err_unmap;
732
Nick Kossifidis86f62d92011-11-25 20:40:28 +0200733 /* Set up MRR descriptor */
734 if (ah->ah_capabilities.cap_has_mrr_support) {
735 memset(mrr_rate, 0, sizeof(mrr_rate));
736 memset(mrr_tries, 0, sizeof(mrr_tries));
737 for (i = 0; i < 3; i++) {
738 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
739 if (!rate)
740 break;
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200741
Nick Kossifidis86f62d92011-11-25 20:40:28 +0200742 mrr_rate[i] = rate->hw_value;
743 mrr_tries[i] = info->control.rates[i + 1].count;
744 }
745
746 ath5k_hw_setup_mrr_tx_desc(ah, ds,
747 mrr_rate[0], mrr_tries[0],
748 mrr_rate[1], mrr_tries[1],
749 mrr_rate[2], mrr_tries[2]);
Felix Fietkau2f7fe872008-10-05 18:05:48 +0200750 }
751
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200752 ds->ds_link = 0;
753 ds->ds_data = bf->skbaddr;
754
755 spin_lock_bh(&txq->lock);
756 list_add_tail(&bf->list, &txq->q);
Bruno Randolf925e0b02010-09-17 11:36:35 +0900757 txq->txq_len++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200758 if (txq->link == NULL) /* is this first packet? */
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300759 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200760 else /* no, so only link it */
761 *txq->link = bf->daddr;
762
763 txq->link = &ds->ds_link;
Nick Kossifidisc6e387a2008-08-29 22:45:39 +0300764 ath5k_hw_start_tx_dma(ah, txq->qnum);
Jiri Slaby274c7c32008-07-15 17:44:20 +0200765 mmiowb();
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200766 spin_unlock_bh(&txq->lock);
767
768 return 0;
769err_unmap:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400770 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200771 return ret;
772}
773
774/*******************\
775* Descriptors setup *
776\*******************/
777
778static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400779ath5k_desc_alloc(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200780{
781 struct ath5k_desc *ds;
782 struct ath5k_buf *bf;
783 dma_addr_t da;
784 unsigned int i;
785 int ret;
786
787 /* allocate descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400788 ah->desc_len = sizeof(struct ath5k_desc) *
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200789 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
Felix Fietkauaeae4ac2010-12-02 10:26:51 +0100790
Pavel Roskine0d687b2011-07-14 20:21:55 -0400791 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
792 &ah->desc_daddr, GFP_KERNEL);
793 if (ah->desc == NULL) {
794 ATH5K_ERR(ah, "can't allocate descriptors\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200795 ret = -ENOMEM;
796 goto err;
797 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400798 ds = ah->desc;
799 da = ah->desc_daddr;
800 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
801 ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200802
803 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
804 sizeof(struct ath5k_buf), GFP_KERNEL);
805 if (bf == NULL) {
Pavel Roskine0d687b2011-07-14 20:21:55 -0400806 ATH5K_ERR(ah, "can't allocate bufptr\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200807 ret = -ENOMEM;
808 goto err_free;
809 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400810 ah->bufptr = bf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200811
Pavel Roskine0d687b2011-07-14 20:21:55 -0400812 INIT_LIST_HEAD(&ah->rxbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200813 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
814 bf->desc = ds;
815 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400816 list_add_tail(&bf->list, &ah->rxbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200817 }
818
Pavel Roskine0d687b2011-07-14 20:21:55 -0400819 INIT_LIST_HEAD(&ah->txbuf);
820 ah->txbuf_len = ATH_TXBUF;
Pavel Roskine4bbf2f2011-07-07 18:14:13 -0400821 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200822 bf->desc = ds;
823 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400824 list_add_tail(&bf->list, &ah->txbuf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200825 }
826
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700827 /* beacon buffers */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400828 INIT_LIST_HEAD(&ah->bcbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700829 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
830 bf->desc = ds;
831 bf->daddr = da;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400832 list_add_tail(&bf->list, &ah->bcbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -0700833 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200834
835 return 0;
836err_free:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400837 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200838err:
Pavel Roskine0d687b2011-07-14 20:21:55 -0400839 ah->desc = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200840 return ret;
841}
842
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900843void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400844ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900845{
846 BUG_ON(!bf);
847 if (!bf->skb)
848 return;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400849 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900850 DMA_TO_DEVICE);
851 dev_kfree_skb_any(bf->skb);
852 bf->skb = NULL;
853 bf->skbaddr = 0;
854 bf->desc->ds_data = 0;
855}
856
857void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400858ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900859{
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900860 struct ath_common *common = ath5k_hw_common(ah);
861
862 BUG_ON(!bf);
863 if (!bf->skb)
864 return;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400865 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
Bruno Randolfcd2c5482010-12-22 19:20:32 +0900866 DMA_FROM_DEVICE);
867 dev_kfree_skb_any(bf->skb);
868 bf->skb = NULL;
869 bf->skbaddr = 0;
870 bf->desc->ds_data = 0;
871}
872
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200873static void
Pavel Roskine0d687b2011-07-14 20:21:55 -0400874ath5k_desc_free(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200875{
876 struct ath5k_buf *bf;
877
Pavel Roskine0d687b2011-07-14 20:21:55 -0400878 list_for_each_entry(bf, &ah->txbuf, list)
879 ath5k_txbuf_free_skb(ah, bf);
880 list_for_each_entry(bf, &ah->rxbuf, list)
881 ath5k_rxbuf_free_skb(ah, bf);
882 list_for_each_entry(bf, &ah->bcbuf, list)
883 ath5k_txbuf_free_skb(ah, bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200884
885 /* Free memory associated with all descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -0400886 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
887 ah->desc = NULL;
888 ah->desc_daddr = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200889
Pavel Roskine0d687b2011-07-14 20:21:55 -0400890 kfree(ah->bufptr);
891 ah->bufptr = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200892}
893
894
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200895/**************\
896* Queues setup *
897\**************/
898
899static struct ath5k_txq *
Pavel Roskine0d687b2011-07-14 20:21:55 -0400900ath5k_txq_setup(struct ath5k_hw *ah,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200901 int qtype, int subtype)
902{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200903 struct ath5k_txq *txq;
904 struct ath5k_txq_info qi = {
905 .tqi_subtype = subtype,
Bruno Randolfde8af452010-09-17 11:37:12 +0900906 /* XXX: default values not correct for B and XR channels,
907 * but who cares? */
908 .tqi_aifs = AR5K_TUNE_AIFS,
909 .tqi_cw_min = AR5K_TUNE_CWMIN,
910 .tqi_cw_max = AR5K_TUNE_CWMAX
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200911 };
912 int qnum;
913
914 /*
915 * Enable interrupts only for EOL and DESC conditions.
916 * We mark tx descriptors to receive a DESC interrupt
Bob Copelanda180a132010-08-15 13:03:12 -0400917 * when a tx queue gets deep; otherwise we wait for the
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200918 * EOL to reap descriptors. Note that this is done to
919 * reduce interrupt load and this only defers reaping
920 * descriptors, never transmitting frames. Aside from
921 * reducing interrupts this also permits more concurrency.
922 * The only potential downside is if the tx queue backs
923 * up in which case the top half of the kernel may backup
924 * due to a lack of tx descriptors.
925 */
926 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
927 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
928 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
929 if (qnum < 0) {
930 /*
931 * NB: don't print a message, this happens
932 * normally on parts with too few tx queues
933 */
934 return ERR_PTR(qnum);
935 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400936 txq = &ah->txqs[qnum];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200937 if (!txq->setup) {
938 txq->qnum = qnum;
939 txq->link = NULL;
940 INIT_LIST_HEAD(&txq->q);
941 spin_lock_init(&txq->lock);
942 txq->setup = true;
Bruno Randolf925e0b02010-09-17 11:36:35 +0900943 txq->txq_len = 0;
John W. Linville81266ba2011-03-07 16:32:59 -0500944 txq->txq_max = ATH5K_TXQ_LEN_MAX;
Bruno Randolf4edd7612010-09-17 11:36:56 +0900945 txq->txq_poll_mark = false;
Bruno Randolf923e5b32010-09-17 11:37:02 +0900946 txq->txq_stuck = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200947 }
Pavel Roskine0d687b2011-07-14 20:21:55 -0400948 return &ah->txqs[qnum];
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200949}
950
951static int
952ath5k_beaconq_setup(struct ath5k_hw *ah)
953{
954 struct ath5k_txq_info qi = {
Bruno Randolfde8af452010-09-17 11:37:12 +0900955 /* XXX: default values not correct for B and XR channels,
956 * but who cares? */
957 .tqi_aifs = AR5K_TUNE_AIFS,
958 .tqi_cw_min = AR5K_TUNE_CWMIN,
959 .tqi_cw_max = AR5K_TUNE_CWMAX,
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200960 /* NB: for dynamic turbo, don't enable any other interrupts */
961 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
962 };
963
964 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
965}
966
967static int
Pavel Roskine0d687b2011-07-14 20:21:55 -0400968ath5k_beaconq_config(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200969{
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200970 struct ath5k_txq_info qi;
971 int ret;
972
Pavel Roskine0d687b2011-07-14 20:21:55 -0400973 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200974 if (ret)
Bob Copelanda951ae22010-01-20 23:51:04 -0500975 goto err;
976
Pavel Roskine0d687b2011-07-14 20:21:55 -0400977 if (ah->opmode == NL80211_IFTYPE_AP ||
978 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200979 /*
980 * Always burst out beacon and CAB traffic
981 * (aifs = cwmin = cwmax = 0)
982 */
983 qi.tqi_aifs = 0;
984 qi.tqi_cw_min = 0;
985 qi.tqi_cw_max = 0;
Pavel Roskine0d687b2011-07-14 20:21:55 -0400986 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Bruno Randolf6d91e1d2008-01-19 18:18:41 +0900987 /*
988 * Adhoc mode; backoff between 0 and (2 * cw_min).
989 */
990 qi.tqi_aifs = 0;
991 qi.tqi_cw_min = 0;
Bruno Randolfde8af452010-09-17 11:37:12 +0900992 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
Jiri Slabyfa1c1142007-08-12 17:33:16 +0200993 }
994
Pavel Roskine0d687b2011-07-14 20:21:55 -0400995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6d91e1d2008-01-19 18:18:41 +0900996 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
997 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
998
Pavel Roskine0d687b2011-07-14 20:21:55 -0400999 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001000 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001001 ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001002 "hardware queue!\n", __func__);
Bob Copelanda951ae22010-01-20 23:51:04 -05001003 goto err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001004 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001005 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
Bob Copelanda951ae22010-01-20 23:51:04 -05001006 if (ret)
1007 goto err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001008
Bob Copelanda951ae22010-01-20 23:51:04 -05001009 /* reconfigure cabq with ready time to 80% of beacon_interval */
1010 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1011 if (ret)
1012 goto err;
1013
Pavel Roskine0d687b2011-07-14 20:21:55 -04001014 qi.tqi_ready_time = (ah->bintval * 80) / 100;
Bob Copelanda951ae22010-01-20 23:51:04 -05001015 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1016 if (ret)
1017 goto err;
1018
1019 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1020err:
1021 return ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001022}
1023
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001024/**
1025 * ath5k_drain_tx_buffs - Empty tx buffers
1026 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04001027 * @ah The &struct ath5k_hw
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001028 *
1029 * Empty tx buffers from all queues in preparation
1030 * of a reset or during shutdown.
1031 *
1032 * NB: this assumes output has been stopped and
1033 * we do not need to block ath5k_tx_tasklet
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001034 */
1035static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001036ath5k_drain_tx_buffs(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001037{
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001038 struct ath5k_txq *txq;
1039 struct ath5k_buf *bf, *bf0;
1040 int i;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001041
Pavel Roskine0d687b2011-07-14 20:21:55 -04001042 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
1043 if (ah->txqs[i].setup) {
1044 txq = &ah->txqs[i];
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001045 spin_lock_bh(&txq->lock);
1046 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001047 ath5k_debug_printtxbuf(ah, bf);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001048
Pavel Roskine0d687b2011-07-14 20:21:55 -04001049 ath5k_txbuf_free_skb(ah, bf);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001050
Bob Copeland66179422012-06-15 16:03:29 -04001051 spin_lock(&ah->txbuflock);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001052 list_move_tail(&bf->list, &ah->txbuf);
1053 ah->txbuf_len++;
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001054 txq->txq_len--;
Bob Copeland66179422012-06-15 16:03:29 -04001055 spin_unlock(&ah->txbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001056 }
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001057 txq->link = NULL;
1058 txq->txq_poll_mark = false;
1059 spin_unlock_bh(&txq->lock);
1060 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001061 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001062}
1063
1064static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001065ath5k_txq_release(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001066{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001067 struct ath5k_txq *txq = ah->txqs;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001068 unsigned int i;
1069
Pavel Roskine0d687b2011-07-14 20:21:55 -04001070 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001071 if (txq->setup) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001072 ath5k_hw_release_tx_queue(ah, txq->qnum);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001073 txq->setup = false;
1074 }
1075}
1076
1077
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001078/*************\
1079* RX Handling *
1080\*************/
1081
1082/*
1083 * Enable the receive h/w following a reset.
1084 */
1085static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001086ath5k_rx_start(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001087{
Luis R. Rodriguezdb719712009-09-10 11:20:57 -07001088 struct ath_common *common = ath5k_hw_common(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001089 struct ath5k_buf *bf;
1090 int ret;
1091
Nick Kossifidisb6127982010-08-15 13:03:11 -04001092 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001093
Pavel Roskine0d687b2011-07-14 20:21:55 -04001094 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -08001095 common->cachelsz, common->rx_bufsize);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001096
Pavel Roskine0d687b2011-07-14 20:21:55 -04001097 spin_lock_bh(&ah->rxbuflock);
1098 ah->rxlink = NULL;
1099 list_for_each_entry(bf, &ah->rxbuf, list) {
1100 ret = ath5k_rxbuf_setup(ah, bf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001101 if (ret != 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001102 spin_unlock_bh(&ah->rxbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001103 goto err;
1104 }
1105 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001106 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
Bob Copeland26925042009-04-15 07:57:36 -04001107 ath5k_hw_set_rxdp(ah, bf->daddr);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001108 spin_unlock_bh(&ah->rxbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001109
Nick Kossifidisc6e387a2008-08-29 22:45:39 +03001110 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001111 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001112 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1113
1114 return 0;
1115err:
1116 return ret;
1117}
1118
1119/*
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001120 * Disable the receive logic on PCU (DRU)
1121 * In preparation for a shutdown.
1122 *
1123 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1124 * does.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001125 */
1126static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001127ath5k_rx_stop(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001128{
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001129
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001130 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02001131 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001132
Pavel Roskine0d687b2011-07-14 20:21:55 -04001133 ath5k_debug_printrxbuffs(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001134}
1135
1136static unsigned int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001137ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf8a89f062010-06-16 19:11:51 +09001138 struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001139{
Luis R. Rodriguezdc1e0012009-11-04 17:47:31 -08001140 struct ath_common *common = ath5k_hw_common(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001141 struct ieee80211_hdr *hdr = (void *)skb->data;
Harvey Harrison798ee982008-07-15 18:44:02 -07001142 unsigned int keyix, hlen;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001143
Bruno Randolfb47f4072008-03-05 18:35:45 +09001144 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1145 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001146 return RX_FLAG_DECRYPTED;
1147
1148 /* Apparently when a default key is used to decrypt the packet
1149 the hw does not set the index used to decrypt. In such cases
1150 get the index from the packet. */
Harvey Harrison798ee982008-07-15 18:44:02 -07001151 hlen = ieee80211_hdrlen(hdr->frame_control);
Harvey Harrison24b56e72008-06-14 23:33:38 -07001152 if (ieee80211_has_protected(hdr->frame_control) &&
1153 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1154 skb->len >= hlen + 4) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001155 keyix = skb->data[hlen + 3] >> 6;
1156
Luis R. Rodriguezdc1e0012009-11-04 17:47:31 -08001157 if (test_bit(keyix, common->keymap))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001158 return RX_FLAG_DECRYPTED;
1159 }
1160
1161 return 0;
1162}
1163
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001164
1165static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001166ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001167 struct ieee80211_rx_status *rxs)
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001168{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001169 struct ath_common *common = ath5k_hw_common(ah);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001170 u64 tsf, bc_tstamp;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001171 u32 hw_tu;
1172 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1173
Harvey Harrison24b56e72008-06-14 23:33:38 -07001174 if (ieee80211_is_beacon(mgmt->frame_control) &&
Pavel Roskin38c07b42008-02-26 17:59:14 -05001175 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
Joe Perches2e42e472012-05-09 17:17:46 +00001176 ether_addr_equal(mgmt->bssid, common->curbssid)) {
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001177 /*
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001178 * Received an IBSS beacon with the same BSSID. Hardware *must*
1179 * have updated the local TSF. We have to work around various
1180 * hardware bugs, though...
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001181 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001182 tsf = ath5k_hw_get_tsf64(ah);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001183 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1184 hw_tu = TSF_TO_TU(tsf);
1185
Pavel Roskine0d687b2011-07-14 20:21:55 -04001186 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001187 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001188 (unsigned long long)bc_tstamp,
1189 (unsigned long long)rxs->mactime,
1190 (unsigned long long)(rxs->mactime - bc_tstamp),
1191 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001192
1193 /*
1194 * Sometimes the HW will give us a wrong tstamp in the rx
1195 * status, causing the timestamp extension to go wrong.
1196 * (This seems to happen especially with beacon frames bigger
1197 * than 78 byte (incl. FCS))
1198 * But we know that the receive timestamp must be later than the
1199 * timestamp of the beacon since HW must have synced to that.
1200 *
1201 * NOTE: here we assume mactime to be after the frame was
1202 * received, not like mac80211 which defines it at the start.
1203 */
1204 if (bc_tstamp > rxs->mactime) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001205 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001206 "fixing mactime from %llx to %llx\n",
John W. Linville06501d22008-04-01 17:38:47 -04001207 (unsigned long long)rxs->mactime,
1208 (unsigned long long)tsf);
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001209 rxs->mactime = tsf;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001210 }
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001211
1212 /*
1213 * Local TSF might have moved higher than our beacon timers,
1214 * in that case we have to update them to continue sending
1215 * beacons. This also takes care of synchronizing beacon sending
1216 * times with other stations.
1217 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001218 if (hw_tu >= ah->nexttbtt)
1219 ath5k_beacon_update_timers(ah, bc_tstamp);
Bruno Randolf7f896122010-09-27 12:22:21 +09001220
1221 /* Check if the beacon timers are still correct, because a TSF
1222 * update might have created a window between them - for a
1223 * longer description see the comment of this function: */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001224 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
1225 ath5k_beacon_update_timers(ah, bc_tstamp);
1226 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf7f896122010-09-27 12:22:21 +09001227 "fixed beacon timers after beacon receive\n");
1228 }
Bruno Randolf036cd1e2008-01-19 18:18:21 +09001229 }
1230}
1231
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001232static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001233ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001234{
1235 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001236 struct ath_common *common = ath5k_hw_common(ah);
1237
1238 /* only beacons from our BSSID */
1239 if (!ieee80211_is_beacon(mgmt->frame_control) ||
Joe Perches2e42e472012-05-09 17:17:46 +00001240 !ether_addr_equal(mgmt->bssid, common->curbssid))
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001241 return;
1242
Bruno Randolfeef39be2010-11-16 10:58:43 +09001243 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
Bruno Randolfb4ea4492010-03-25 14:49:25 +09001244
1245 /* in IBSS mode we should keep RSSI statistics per neighbour */
1246 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1247}
1248
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001249/*
Bob Copelanda180a132010-08-15 13:03:12 -04001250 * Compute padding position. skb must contain an IEEE 802.11 frame
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001251 */
1252static int ath5k_common_padpos(struct sk_buff *skb)
1253{
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001254 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001255 __le16 frame_control = hdr->frame_control;
1256 int padpos = 24;
1257
Pavel Roskind2c7f772011-07-07 18:14:07 -04001258 if (ieee80211_has_a4(frame_control))
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001259 padpos += ETH_ALEN;
Pavel Roskind2c7f772011-07-07 18:14:07 -04001260
1261 if (ieee80211_is_data_qos(frame_control))
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001262 padpos += IEEE80211_QOS_CTL_LEN;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001263
1264 return padpos;
1265}
1266
1267/*
Bob Copelanda180a132010-08-15 13:03:12 -04001268 * This function expects an 802.11 frame and returns the number of
1269 * bytes added, or -1 if we don't have enough header room.
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001270 */
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001271static int ath5k_add_padding(struct sk_buff *skb)
1272{
1273 int padpos = ath5k_common_padpos(skb);
1274 int padsize = padpos & 3;
1275
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001276 if (padsize && skb->len > padpos) {
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001277
1278 if (skb_headroom(skb) < padsize)
1279 return -1;
1280
1281 skb_push(skb, padsize);
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001282 memmove(skb->data, skb->data + padsize, padpos);
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001283 return padsize;
1284 }
1285
1286 return 0;
1287}
1288
1289/*
Bob Copelanda180a132010-08-15 13:03:12 -04001290 * The MAC header is padded to have 32-bit boundary if the
1291 * packet payload is non-zero. The general calculation for
1292 * padsize would take into account odd header lengths:
1293 * padsize = 4 - (hdrlen & 3); however, since only
1294 * even-length headers are used, padding can only be 0 or 2
1295 * bytes and we can optimize this a bit. We must not try to
1296 * remove padding from short control frames that do not have a
1297 * payload.
1298 *
1299 * This function expects an 802.11 frame and returns the number of
1300 * bytes removed.
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001301 */
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001302static int ath5k_remove_padding(struct sk_buff *skb)
1303{
1304 int padpos = ath5k_common_padpos(skb);
1305 int padsize = padpos & 3;
1306
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001307 if (padsize && skb->len >= padpos + padsize) {
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001308 memmove(skb->data + padsize, skb->data, padpos);
1309 skb_pull(skb, padsize);
1310 return padsize;
1311 }
1312
1313 return 0;
1314}
1315
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001316static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001317ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
Bruno Randolf8a89f062010-06-16 19:11:51 +09001318 struct ath5k_rx_status *rs)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001319{
Bob Copeland1c5256b2009-08-24 23:00:32 -04001320 struct ieee80211_rx_status *rxs;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001321
Bruno Randolf8a89f062010-06-16 19:11:51 +09001322 ath5k_remove_padding(skb);
1323
1324 rxs = IEEE80211_SKB_RXCB(skb);
1325
1326 rxs->flag = 0;
1327 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1328 rxs->flag |= RX_FLAG_MMIC_ERROR;
1329
1330 /*
1331 * always extend the mac timestamp, since this information is
1332 * also needed for proper IBSS merging.
1333 *
1334 * XXX: it might be too late to do it here, since rs_tstamp is
1335 * 15bit only. that means TSF extension has to be done within
1336 * 32768usec (about 32ms). it might be necessary to move this to
1337 * the interrupt handler, like it is done in madwifi.
1338 *
1339 * Unfortunately we don't know when the hardware takes the rx
1340 * timestamp (beginning of phy frame, data frame, end of rx?).
1341 * The only thing we know is that it is hardware specific...
1342 * On AR5213 it seems the rx timestamp is at the end of the
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04001343 * frame, but I'm not sure.
Bruno Randolf8a89f062010-06-16 19:11:51 +09001344 *
1345 * NOTE: mac80211 defines mactime at the beginning of the first
1346 * data symbol. Since we don't have any time references it's
1347 * impossible to comply to that. This affects IBSS merge only
1348 * right now, so it's not too bad...
1349 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001350 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
Johannes Berg6ebacbb2011-02-23 15:06:08 +01001351 rxs->flag |= RX_FLAG_MACTIME_MPDU;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001352
Pavel Roskine0d687b2011-07-14 20:21:55 -04001353 rxs->freq = ah->curchan->center_freq;
1354 rxs->band = ah->curchan->band;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001355
Pavel Roskine0d687b2011-07-14 20:21:55 -04001356 rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001357
1358 rxs->antenna = rs->rs_antenna;
1359
1360 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001361 ah->stats.antenna_rx[rs->rs_antenna]++;
Bruno Randolf8a89f062010-06-16 19:11:51 +09001362 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04001363 ah->stats.antenna_rx[0]++; /* invalid */
Bruno Randolf8a89f062010-06-16 19:11:51 +09001364
Pavel Roskine0d687b2011-07-14 20:21:55 -04001365 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
1366 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001367
1368 if (rxs->rate_idx >= 0 && rs->rs_rate ==
Pavel Roskine0d687b2011-07-14 20:21:55 -04001369 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
Bruno Randolf8a89f062010-06-16 19:11:51 +09001370 rxs->flag |= RX_FLAG_SHORTPRE;
1371
Pavel Roskine0d687b2011-07-14 20:21:55 -04001372 trace_ath5k_rx(ah, skb);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001373
Pavel Roskine0d687b2011-07-14 20:21:55 -04001374 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001375
1376 /* check beacons in IBSS mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001377 if (ah->opmode == NL80211_IFTYPE_ADHOC)
1378 ath5k_check_ibss_tsf(ah, skb, rxs);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001379
Pavel Roskine0d687b2011-07-14 20:21:55 -04001380 ieee80211_rx(ah->hw, skb);
Bruno Randolf8a89f062010-06-16 19:11:51 +09001381}
1382
Bruno Randolf02a78b42010-06-16 19:11:56 +09001383/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1384 *
1385 * Check if we want to further process this frame or not. Also update
1386 * statistics. Return true if we want this frame, false if not.
1387 */
1388static bool
Pavel Roskine0d687b2011-07-14 20:21:55 -04001389ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
Bruno Randolf02a78b42010-06-16 19:11:56 +09001390{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001391 ah->stats.rx_all_count++;
1392 ah->stats.rx_bytes_count += rs->rs_datalen;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001393
1394 if (unlikely(rs->rs_status)) {
1395 if (rs->rs_status & AR5K_RXERR_CRC)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001396 ah->stats.rxerr_crc++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001397 if (rs->rs_status & AR5K_RXERR_FIFO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001398 ah->stats.rxerr_fifo++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001399 if (rs->rs_status & AR5K_RXERR_PHY) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001400 ah->stats.rxerr_phy++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001401 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001402 ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001403 return false;
1404 }
1405 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1406 /*
1407 * Decrypt error. If the error occurred
1408 * because there was no hardware key, then
1409 * let the frame through so the upper layers
1410 * can process it. This is necessary for 5210
1411 * parts which have no way to setup a ``clear''
1412 * key cache entry.
1413 *
1414 * XXX do key cache faulting
1415 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001416 ah->stats.rxerr_decrypt++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001417 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1418 !(rs->rs_status & AR5K_RXERR_CRC))
1419 return true;
1420 }
1421 if (rs->rs_status & AR5K_RXERR_MIC) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001422 ah->stats.rxerr_mic++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001423 return true;
1424 }
1425
Bob Copeland23538c22010-08-15 13:03:13 -04001426 /* reject any frames with non-crypto errors */
1427 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
Bruno Randolf02a78b42010-06-16 19:11:56 +09001428 return false;
1429 }
1430
1431 if (unlikely(rs->rs_more)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001432 ah->stats.rxerr_jumbo++;
Bruno Randolf02a78b42010-06-16 19:11:56 +09001433 return false;
1434 }
1435 return true;
1436}
1437
Bruno Randolf8a89f062010-06-16 19:11:51 +09001438static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001439ath5k_set_current_imask(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02001440{
Pavel Roskin4fc54012011-07-07 18:14:25 -04001441 enum ath5k_int imask;
Felix Fietkauc266c712011-04-10 18:32:19 +02001442 unsigned long flags;
1443
Pavel Roskine0d687b2011-07-14 20:21:55 -04001444 spin_lock_irqsave(&ah->irqlock, flags);
1445 imask = ah->imask;
1446 if (ah->rx_pending)
Felix Fietkauc266c712011-04-10 18:32:19 +02001447 imask &= ~AR5K_INT_RX_ALL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001448 if (ah->tx_pending)
Felix Fietkauc266c712011-04-10 18:32:19 +02001449 imask &= ~AR5K_INT_TX_ALL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001450 ath5k_hw_set_imr(ah, imask);
1451 spin_unlock_irqrestore(&ah->irqlock, flags);
Felix Fietkauc266c712011-04-10 18:32:19 +02001452}
1453
1454static void
Bruno Randolf8a89f062010-06-16 19:11:51 +09001455ath5k_tasklet_rx(unsigned long data)
1456{
Bruno Randolfb47f4072008-03-05 18:35:45 +09001457 struct ath5k_rx_status rs = {};
Bob Copelandb6ea0352009-01-10 14:42:54 -05001458 struct sk_buff *skb, *next_skb;
1459 dma_addr_t next_skb_addr;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001460 struct ath5k_hw *ah = (void *)data;
Luis R. Rodriguezcc861f72009-11-04 09:11:34 -08001461 struct ath_common *common = ath5k_hw_common(ah);
Bob Copelandc57ca812009-04-15 07:57:35 -04001462 struct ath5k_buf *bf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001463 struct ath5k_desc *ds;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001464 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001465
Pavel Roskine0d687b2011-07-14 20:21:55 -04001466 spin_lock(&ah->rxbuflock);
1467 if (list_empty(&ah->rxbuf)) {
1468 ATH5K_WARN(ah, "empty rx buf pool\n");
Jiri Slaby3a0f2c82008-07-15 17:44:18 +02001469 goto unlock;
1470 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001471 do {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001472 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001473 BUG_ON(bf->skb == NULL);
1474 skb = bf->skb;
1475 ds = bf->desc;
1476
Bob Copelandc57ca812009-04-15 07:57:35 -04001477 /* bail if HW is still using self-linked descriptor */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001478 if (ath5k_hw_get_rxdp(ah) == bf->daddr)
Bob Copelandc57ca812009-04-15 07:57:35 -04001479 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001480
Pavel Roskine0d687b2011-07-14 20:21:55 -04001481 ret = ah->ah_proc_rx_desc(ah, ds, &rs);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001482 if (unlikely(ret == -EINPROGRESS))
1483 break;
1484 else if (unlikely(ret)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001485 ATH5K_ERR(ah, "error in processing rx descriptor\n");
1486 ah->stats.rxerr_proc++;
Bruno Randolfb16062f2010-06-16 19:11:46 +09001487 break;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001488 }
1489
Pavel Roskine0d687b2011-07-14 20:21:55 -04001490 if (ath5k_receive_frame_ok(ah, &rs)) {
1491 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
Bruno Randolf76443952010-03-09 16:56:00 +09001492
Bruno Randolf02a78b42010-06-16 19:11:56 +09001493 /*
1494 * If we can't replace bf->skb with a new skb under
1495 * memory pressure, just skip this packet
1496 */
1497 if (!next_skb)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001498 goto next;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001499
Pavel Roskine0d687b2011-07-14 20:21:55 -04001500 dma_unmap_single(ah->dev, bf->skbaddr,
Bruno Randolf02a78b42010-06-16 19:11:56 +09001501 common->rx_bufsize,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001502 DMA_FROM_DEVICE);
Bruno Randolf02a78b42010-06-16 19:11:56 +09001503
1504 skb_put(skb, rs.rs_datalen);
1505
Pavel Roskine0d687b2011-07-14 20:21:55 -04001506 ath5k_receive_frame(ah, skb, &rs);
Bruno Randolf02a78b42010-06-16 19:11:56 +09001507
1508 bf->skb = next_skb;
1509 bf->skbaddr = next_skb_addr;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001510 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001511next:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001512 list_move_tail(&bf->list, &ah->rxbuf);
1513 } while (ath5k_rxbuf_setup(ah, bf) == 0);
Jiri Slaby3a0f2c82008-07-15 17:44:18 +02001514unlock:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001515 spin_unlock(&ah->rxbuflock);
1516 ah->rx_pending = false;
1517 ath5k_set_current_imask(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001518}
1519
1520
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001521/*************\
1522* TX Handling *
1523\*************/
1524
Johannes Berg7bb45682011-02-24 14:42:06 +01001525void
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001526ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1527 struct ath5k_txq *txq)
Bob Copeland8a63fac2010-09-17 12:45:07 +09001528{
Pavel Roskine0d687b2011-07-14 20:21:55 -04001529 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001530 struct ath5k_buf *bf;
1531 unsigned long flags;
1532 int padsize;
1533
Pavel Roskine0d687b2011-07-14 20:21:55 -04001534 trace_ath5k_tx(ah, skb, txq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001535
1536 /*
1537 * The hardware expects the header padded to 4 byte boundaries.
1538 * If this is not the case, we add the padding after the header.
1539 */
1540 padsize = ath5k_add_padding(skb);
1541 if (padsize < 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001542 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
Bob Copeland8a63fac2010-09-17 12:45:07 +09001543 " headroom to pad");
1544 goto drop_packet;
1545 }
1546
Felix Fietkau4e868792011-07-12 09:02:05 +08001547 if (txq->txq_len >= txq->txq_max &&
1548 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
Bruno Randolf925e0b02010-09-17 11:36:35 +09001549 ieee80211_stop_queue(hw, txq->qnum);
1550
Pavel Roskine0d687b2011-07-14 20:21:55 -04001551 spin_lock_irqsave(&ah->txbuflock, flags);
1552 if (list_empty(&ah->txbuf)) {
1553 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
1554 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bruno Randolf651d9372010-09-17 11:36:46 +09001555 ieee80211_stop_queues(hw);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001556 goto drop_packet;
1557 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001558 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001559 list_del(&bf->list);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001560 ah->txbuf_len--;
1561 if (list_empty(&ah->txbuf))
Bob Copeland8a63fac2010-09-17 12:45:07 +09001562 ieee80211_stop_queues(hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001563 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001564
1565 bf->skb = skb;
1566
Pavel Roskine0d687b2011-07-14 20:21:55 -04001567 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
Bob Copeland8a63fac2010-09-17 12:45:07 +09001568 bf->skb = NULL;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001569 spin_lock_irqsave(&ah->txbuflock, flags);
1570 list_add_tail(&bf->list, &ah->txbuf);
1571 ah->txbuf_len++;
1572 spin_unlock_irqrestore(&ah->txbuflock, flags);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001573 goto drop_packet;
1574 }
Johannes Berg7bb45682011-02-24 14:42:06 +01001575 return;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001576
1577drop_packet:
1578 dev_kfree_skb_any(skb);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001579}
1580
Bruno Randolf14404012010-09-17 11:36:51 +09001581static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001582ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
Bob Copeland0e472252011-01-24 23:32:55 -05001583 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
Bruno Randolf14404012010-09-17 11:36:51 +09001584{
1585 struct ieee80211_tx_info *info;
Felix Fietkaued895082011-04-10 18:32:17 +02001586 u8 tries[3];
Bruno Randolf14404012010-09-17 11:36:51 +09001587 int i;
1588
Pavel Roskine0d687b2011-07-14 20:21:55 -04001589 ah->stats.tx_all_count++;
1590 ah->stats.tx_bytes_count += skb->len;
Bruno Randolf14404012010-09-17 11:36:51 +09001591 info = IEEE80211_SKB_CB(skb);
1592
Felix Fietkaued895082011-04-10 18:32:17 +02001593 tries[0] = info->status.rates[0].count;
1594 tries[1] = info->status.rates[1].count;
1595 tries[2] = info->status.rates[2].count;
1596
Bruno Randolf14404012010-09-17 11:36:51 +09001597 ieee80211_tx_info_clear_status(info);
Felix Fietkaued895082011-04-10 18:32:17 +02001598
1599 for (i = 0; i < ts->ts_final_idx; i++) {
Bruno Randolf14404012010-09-17 11:36:51 +09001600 struct ieee80211_tx_rate *r =
1601 &info->status.rates[i];
1602
Felix Fietkaued895082011-04-10 18:32:17 +02001603 r->count = tries[i];
Bruno Randolf14404012010-09-17 11:36:51 +09001604 }
1605
Felix Fietkaued895082011-04-10 18:32:17 +02001606 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
Felix Fietkau6d7b97b2011-04-09 21:37:14 +02001607 info->status.rates[ts->ts_final_idx + 1].idx = -1;
Bruno Randolf14404012010-09-17 11:36:51 +09001608
1609 if (unlikely(ts->ts_status)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001610 ah->stats.ack_fail++;
Bruno Randolf14404012010-09-17 11:36:51 +09001611 if (ts->ts_status & AR5K_TXERR_FILT) {
1612 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001613 ah->stats.txerr_filt++;
Bruno Randolf14404012010-09-17 11:36:51 +09001614 }
1615 if (ts->ts_status & AR5K_TXERR_XRETRY)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001616 ah->stats.txerr_retry++;
Bruno Randolf14404012010-09-17 11:36:51 +09001617 if (ts->ts_status & AR5K_TXERR_FIFO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001618 ah->stats.txerr_fifo++;
Bruno Randolf14404012010-09-17 11:36:51 +09001619 } else {
1620 info->flags |= IEEE80211_TX_STAT_ACK;
1621 info->status.ack_signal = ts->ts_rssi;
Felix Fietkau6d7b97b2011-04-09 21:37:14 +02001622
1623 /* count the successful attempt as well */
1624 info->status.rates[ts->ts_final_idx].count++;
Bruno Randolf14404012010-09-17 11:36:51 +09001625 }
1626
1627 /*
1628 * Remove MAC header padding before giving the frame
1629 * back to mac80211.
1630 */
1631 ath5k_remove_padding(skb);
1632
1633 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001634 ah->stats.antenna_tx[ts->ts_antenna]++;
Bruno Randolf14404012010-09-17 11:36:51 +09001635 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04001636 ah->stats.antenna_tx[0]++; /* invalid */
Bruno Randolf14404012010-09-17 11:36:51 +09001637
Pavel Roskine0d687b2011-07-14 20:21:55 -04001638 trace_ath5k_tx_complete(ah, skb, txq, ts);
1639 ieee80211_tx_status(ah->hw, skb);
Bruno Randolf14404012010-09-17 11:36:51 +09001640}
Bob Copeland8a63fac2010-09-17 12:45:07 +09001641
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001642static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001643ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001644{
Bruno Randolfb47f4072008-03-05 18:35:45 +09001645 struct ath5k_tx_status ts = {};
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001646 struct ath5k_buf *bf, *bf0;
1647 struct ath5k_desc *ds;
1648 struct sk_buff *skb;
Bruno Randolf14404012010-09-17 11:36:51 +09001649 int ret;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001650
1651 spin_lock(&txq->lock);
1652 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
Bruno Randolf23413292010-09-17 11:37:07 +09001653
1654 txq->txq_poll_mark = false;
1655
1656 /* skb might already have been processed last time. */
1657 if (bf->skb != NULL) {
1658 ds = bf->desc;
1659
Pavel Roskine0d687b2011-07-14 20:21:55 -04001660 ret = ah->ah_proc_tx_desc(ah, ds, &ts);
Bruno Randolf23413292010-09-17 11:37:07 +09001661 if (unlikely(ret == -EINPROGRESS))
1662 break;
1663 else if (unlikely(ret)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001664 ATH5K_ERR(ah,
Bruno Randolf23413292010-09-17 11:37:07 +09001665 "error %d while processing "
1666 "queue %u\n", ret, txq->qnum);
1667 break;
1668 }
1669
1670 skb = bf->skb;
1671 bf->skb = NULL;
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001672
Pavel Roskine0d687b2011-07-14 20:21:55 -04001673 dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001674 DMA_TO_DEVICE);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001675 ath5k_tx_frame_completed(ah, skb, txq, &ts);
Bruno Randolf23413292010-09-17 11:37:07 +09001676 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001677
Bob Copelanda05988b2010-04-07 23:55:58 -04001678 /*
1679 * It's possible that the hardware can say the buffer is
1680 * completed when it hasn't yet loaded the ds_link from
Bruno Randolf23413292010-09-17 11:37:07 +09001681 * host memory and moved on.
1682 * Always keep the last descriptor to avoid HW races...
Bob Copelanda05988b2010-04-07 23:55:58 -04001683 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001684 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
1685 spin_lock(&ah->txbuflock);
1686 list_move_tail(&bf->list, &ah->txbuf);
1687 ah->txbuf_len++;
Bruno Randolf23413292010-09-17 11:37:07 +09001688 txq->txq_len--;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001689 spin_unlock(&ah->txbuflock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001690 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001691 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001692 spin_unlock(&txq->lock);
Bruno Randolf4198a8d2010-10-05 13:27:17 +09001693 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001694 ieee80211_wake_queue(ah->hw, txq->qnum);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001695}
1696
1697static void
1698ath5k_tasklet_tx(unsigned long data)
1699{
Bob Copeland8784d2e2009-07-29 17:32:28 -04001700 int i;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001701 struct ath5k_hw *ah = (void *)data;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001702
Pavel Roskine4bbf2f2011-07-07 18:14:13 -04001703 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
Nick Kossifidis7ff7c822011-11-25 20:40:20 +02001704 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i)))
Pavel Roskine0d687b2011-07-14 20:21:55 -04001705 ath5k_tx_processq(ah, &ah->txqs[i]);
Felix Fietkauc266c712011-04-10 18:32:19 +02001706
Pavel Roskine0d687b2011-07-14 20:21:55 -04001707 ah->tx_pending = false;
1708 ath5k_set_current_imask(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001709}
1710
1711
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001712/*****************\
1713* Beacon handling *
1714\*****************/
1715
1716/*
1717 * Setup the beacon frame for transmit.
1718 */
1719static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04001720ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001721{
1722 struct sk_buff *skb = bf->skb;
Johannes Berga888d522008-05-26 16:43:39 +02001723 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001724 struct ath5k_desc *ds;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001725 int ret = 0;
1726 u8 antenna;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001727 u32 flags;
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001728 const int padsize = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001729
Pavel Roskine0d687b2011-07-14 20:21:55 -04001730 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001731 DMA_TO_DEVICE);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001732 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001733 "skbaddr %llx\n", skb, skb->data, skb->len,
1734 (unsigned long long)bf->skbaddr);
Felix Fietkauaeae4ac2010-12-02 10:26:51 +01001735
Pavel Roskine0d687b2011-07-14 20:21:55 -04001736 if (dma_mapping_error(ah->dev, bf->skbaddr)) {
1737 ATH5K_ERR(ah, "beacon DMA mapping failed\n");
Bob Copelandbdc71bc2011-08-07 19:36:07 -04001738 dev_kfree_skb_any(skb);
1739 bf->skb = NULL;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001740 return -EIO;
1741 }
1742
1743 ds = bf->desc;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001744 antenna = ah->ah_tx_ant;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001745
1746 flags = AR5K_TXDESC_NOACK;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001747 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001748 ds->ds_link = bf->daddr; /* self-linked */
1749 flags |= AR5K_TXDESC_VEOL;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001750 } else
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001751 ds->ds_link = 0;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001752
1753 /*
1754 * If we use multiple antennas on AP and use
1755 * the Sectored AP scenario, switch antenna every
1756 * 4 beacons to make sure everybody hears our AP.
1757 * When a client tries to associate, hw will keep
1758 * track of the tx antenna to be used for this client
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04001759 * automatically, based on ACKed packets.
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001760 *
1761 * Note: AP still listens and transmits RTS on the
1762 * default antenna which is supposed to be an omni.
1763 *
1764 * Note2: On sectored scenarios it's possible to have
Bob Copelanda180a132010-08-15 13:03:12 -04001765 * multiple antennas (1 omni -- the default -- and 14
1766 * sectors), so if we choose to actually support this
1767 * mode, we need to allow the user to set how many antennas
1768 * we have and tweak the code below to send beacons
1769 * on all of them.
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001770 */
1771 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001772 antenna = ah->bsent & 4 ? 2 : 1;
Nick Kossifidis2bed03e2009-04-30 15:55:49 -04001773
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001774
Nick Kossifidis8f655dd2009-03-15 22:20:35 +02001775 /* FIXME: If we are in g mode and rate is a CCK rate
1776 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1777 * from tx power (value is in dB units already) */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001778 ds->ds_data = bf->skbaddr;
Bruno Randolf281c56d2008-02-05 18:44:55 +09001779 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
Benoit Papillault8127fbd2010-02-27 23:05:26 +01001780 ieee80211_get_hdrlen_from_skb(skb), padsize,
Pavel Roskine0d687b2011-07-14 20:21:55 -04001781 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
1782 ieee80211_get_tx_rate(ah->hw, info)->hw_value,
Johannes Berg2e92e6f2008-05-15 12:55:27 +02001783 1, AR5K_TXKEYIX_INVALID,
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05001784 antenna, flags, 0, 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001785 if (ret)
1786 goto err_unmap;
1787
1788 return 0;
1789err_unmap:
Pavel Roskine0d687b2011-07-14 20:21:55 -04001790 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001791 return ret;
1792}
1793
1794/*
Bob Copeland8a63fac2010-09-17 12:45:07 +09001795 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1796 * this is called only once at config_bss time, for AP we do it every
1797 * SWBA interrupt so that the TIM will reflect buffered frames.
1798 *
1799 * Called with the beacon lock.
1800 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001801int
Bob Copeland8a63fac2010-09-17 12:45:07 +09001802ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1803{
1804 int ret;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001805 struct ath5k_hw *ah = hw->priv;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001806 struct ath5k_vif *avf = (void *)vif->drv_priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09001807 struct sk_buff *skb;
1808
1809 if (WARN_ON(!vif)) {
1810 ret = -EINVAL;
1811 goto out;
1812 }
1813
1814 skb = ieee80211_beacon_get(hw, vif);
1815
1816 if (!skb) {
1817 ret = -ENOMEM;
1818 goto out;
1819 }
1820
Pavel Roskine0d687b2011-07-14 20:21:55 -04001821 ath5k_txbuf_free_skb(ah, avf->bbuf);
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001822 avf->bbuf->skb = skb;
Pavel Roskine0d687b2011-07-14 20:21:55 -04001823 ret = ath5k_beacon_setup(ah, avf->bbuf);
Bob Copeland8a63fac2010-09-17 12:45:07 +09001824out:
1825 return ret;
1826}
1827
1828/*
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001829 * Transmit a beacon frame at SWBA. Dynamic updates to the
1830 * frame contents are done as needed and the slot time is
1831 * also adjusted based on current state.
1832 *
Bob Copeland5faaff72010-07-13 11:32:40 -04001833 * This is called from software irq context (beacontq tasklets)
1834 * or user context from ath5k_beacon_config.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001835 */
1836static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001837ath5k_beacon_send(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001838{
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001839 struct ieee80211_vif *vif;
1840 struct ath5k_vif *avf;
1841 struct ath5k_buf *bf;
Bob Copelandcec8db22009-07-04 12:59:51 -04001842 struct sk_buff *skb;
Bob Copelandbdc71bc2011-08-07 19:36:07 -04001843 int err;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001844
Pavel Roskine0d687b2011-07-14 20:21:55 -04001845 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001846
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001847 /*
1848 * Check if the previous beacon has gone out. If
Bob Copelanda180a132010-08-15 13:03:12 -04001849 * not, don't don't try to post another: skip this
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001850 * period and wait for the next. Missed beacons
1851 * indicate a problem and should not occur. If we
1852 * miss too many consecutive beacons reset the device.
1853 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001854 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
1855 ah->bmisscount++;
1856 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
1857 "missed %u consecutive beacons\n", ah->bmisscount);
1858 if (ah->bmisscount > 10) { /* NB: 10 is a guess */
1859 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001860 "stuck beacon time (%u missed)\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001861 ah->bmisscount);
1862 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09001863 "stuck beacon, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04001864 ieee80211_queue_work(ah->hw, &ah->reset_work);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001865 }
1866 return;
1867 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04001868 if (unlikely(ah->bmisscount != 0)) {
1869 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001870 "resume beacon xmit after %u misses\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001871 ah->bmisscount);
1872 ah->bmisscount = 0;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001873 }
1874
Chun-Yeow Yeohda473b62012-03-03 09:48:56 +08001875 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs +
1876 ah->num_mesh_vifs > 1) ||
Pavel Roskine0d687b2011-07-14 20:21:55 -04001877 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001878 u64 tsf = ath5k_hw_get_tsf64(ah);
1879 u32 tsftu = TSF_TO_TU(tsf);
Pavel Roskine0d687b2011-07-14 20:21:55 -04001880 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
1881 vif = ah->bslot[(slot + 1) % ATH_BCBUF];
1882 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001883 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04001884 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001885 } else /* only one interface */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001886 vif = ah->bslot[0];
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001887
1888 if (!vif)
1889 return;
1890
1891 avf = (void *)vif->drv_priv;
1892 bf = avf->bbuf;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001893
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001894 /*
1895 * Stop any current dma and put the new frame on the queue.
1896 * This should never fail since we check above that no frames
1897 * are still pending on the queue.
1898 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001899 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
1900 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001901 /* NB: hw still stops DMA, so proceed */
1902 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001903
Javier Cardonad82b5772010-12-07 13:35:55 -08001904 /* refresh the beacon for AP or MESH mode */
Pavel Roskine0d687b2011-07-14 20:21:55 -04001905 if (ah->opmode == NL80211_IFTYPE_AP ||
Bob Copelandbdc71bc2011-08-07 19:36:07 -04001906 ah->opmode == NL80211_IFTYPE_MESH_POINT) {
1907 err = ath5k_beacon_update(ah->hw, vif);
1908 if (err)
1909 return;
1910 }
1911
1912 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
1913 ah->opmode == NL80211_IFTYPE_MONITOR)) {
1914 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
1915 return;
1916 }
Bob Copeland1071db82009-05-18 10:59:52 -04001917
Pavel Roskine0d687b2011-07-14 20:21:55 -04001918 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
Bob Copeland0e472252011-01-24 23:32:55 -05001919
Pavel Roskine0d687b2011-07-14 20:21:55 -04001920 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
1921 ath5k_hw_start_tx_dma(ah, ah->bhalq);
1922 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
1923 ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001924
Pavel Roskine0d687b2011-07-14 20:21:55 -04001925 skb = ieee80211_get_buffered_bc(ah->hw, vif);
Bob Copelandcec8db22009-07-04 12:59:51 -04001926 while (skb) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04001927 ath5k_tx_queue(ah->hw, skb, ah->cabq);
Felix Fietkau4e868792011-07-12 09:02:05 +08001928
Pavel Roskine0d687b2011-07-14 20:21:55 -04001929 if (ah->cabq->txq_len >= ah->cabq->txq_max)
Felix Fietkau4e868792011-07-12 09:02:05 +08001930 break;
1931
Pavel Roskine0d687b2011-07-14 20:21:55 -04001932 skb = ieee80211_get_buffered_bc(ah->hw, vif);
Bob Copelandcec8db22009-07-04 12:59:51 -04001933 }
1934
Pavel Roskine0d687b2011-07-14 20:21:55 -04001935 ah->bsent++;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001936}
1937
Bruno Randolf9804b982008-01-19 18:17:59 +09001938/**
1939 * ath5k_beacon_update_timers - update beacon timers
1940 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04001941 * @ah: struct ath5k_hw pointer we are operating on
Bruno Randolf9804b982008-01-19 18:17:59 +09001942 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1943 * beacon timer update based on the current HW TSF.
1944 *
1945 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1946 * of a received beacon or the current local hardware TSF and write it to the
1947 * beacon timer registers.
1948 *
1949 * This is called in a variety of situations, e.g. when a beacon is received,
Bruno Randolf6ba81c22008-03-05 18:36:26 +09001950 * when a TSF update has been detected, but also when an new IBSS is created or
Bruno Randolf9804b982008-01-19 18:17:59 +09001951 * when we otherwise know we have to update the timers, but we keep it in this
1952 * function to have it all together in one place.
1953 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09001954void
Pavel Roskine0d687b2011-07-14 20:21:55 -04001955ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001956{
Bruno Randolf9804b982008-01-19 18:17:59 +09001957 u32 nexttbtt, intval, hw_tu, bc_tu;
1958 u64 hw_tsf;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001959
Pavel Roskine0d687b2011-07-14 20:21:55 -04001960 intval = ah->bintval & AR5K_BEACON_PERIOD;
Chun-Yeow Yeohda473b62012-03-03 09:48:56 +08001961 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs
1962 + ah->num_mesh_vifs > 1) {
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001963 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1964 if (intval < 15)
Pavel Roskine0d687b2011-07-14 20:21:55 -04001965 ATH5K_WARN(ah, "intval %u is too low, min 15\n",
Ben Greearb1ae1ed2010-09-30 12:22:58 -07001966 intval);
1967 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001968 if (WARN_ON(!intval))
1969 return;
1970
Bruno Randolf9804b982008-01-19 18:17:59 +09001971 /* beacon TSF converted to TU */
1972 bc_tu = TSF_TO_TU(bc_tsf);
1973
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001974 /* current TSF converted to TU */
Bruno Randolf9804b982008-01-19 18:17:59 +09001975 hw_tsf = ath5k_hw_get_tsf64(ah);
1976 hw_tu = TSF_TO_TU(hw_tsf);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02001977
Pavel Roskin633d0062011-07-07 18:14:01 -04001978#define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
Bruno Randolf11f21df2010-09-27 12:22:26 +09001979 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001980 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
Bruno Randolf11f21df2010-09-27 12:22:26 +09001981 * configuration we need to make sure it is bigger than that. */
1982
Bruno Randolf9804b982008-01-19 18:17:59 +09001983 if (bc_tsf == -1) {
1984 /*
1985 * no beacons received, called internally.
1986 * just need to refresh timers based on HW TSF.
1987 */
1988 nexttbtt = roundup(hw_tu + FUDGE, intval);
1989 } else if (bc_tsf == 0) {
1990 /*
1991 * no beacon received, probably called by ath5k_reset_tsf().
1992 * reset TSF to start with 0.
1993 */
1994 nexttbtt = intval;
1995 intval |= AR5K_BEACON_RESET_TSF;
1996 } else if (bc_tsf > hw_tsf) {
1997 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001998 * beacon received, SW merge happened but HW TSF not yet updated.
Bruno Randolf9804b982008-01-19 18:17:59 +09001999 * not possible to reconfigure timers yet, but next time we
2000 * receive a beacon with the same BSSID, the hardware will
2001 * automatically update the TSF and then we need to reconfigure
2002 * the timers.
2003 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002004 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002005 "need to wait for HW TSF sync\n");
2006 return;
2007 } else {
2008 /*
2009 * most important case for beacon synchronization between STA.
2010 *
2011 * beacon received and HW TSF has been already updated by HW.
2012 * update next TBTT based on the TSF of the beacon, but make
2013 * sure it is ahead of our local TSF timer.
2014 */
2015 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2016 }
2017#undef FUDGE
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002018
Pavel Roskine0d687b2011-07-14 20:21:55 -04002019 ah->nexttbtt = nexttbtt;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002020
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002021 intval |= AR5K_BEACON_ENA;
Nick Kossifidisc47faa32011-11-25 20:40:25 +02002022 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval);
Bruno Randolf9804b982008-01-19 18:17:59 +09002023
2024 /*
2025 * debugging output last in order to preserve the time critical aspect
2026 * of this function
2027 */
2028 if (bc_tsf == -1)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002029 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002030 "reconfigured timers based on HW TSF\n");
2031 else if (bc_tsf == 0)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002032 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002033 "reset HW TSF and timers\n");
2034 else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002035 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
Bruno Randolf9804b982008-01-19 18:17:59 +09002036 "updated timers based on beacon TSF\n");
2037
Pavel Roskine0d687b2011-07-14 20:21:55 -04002038 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
David Miller04f93a82008-02-15 16:08:59 -08002039 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2040 (unsigned long long) bc_tsf,
2041 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002042 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
Bruno Randolf9804b982008-01-19 18:17:59 +09002043 intval & AR5K_BEACON_PERIOD,
2044 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2045 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002046}
2047
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002048/**
2049 * ath5k_beacon_config - Configure the beacon queues and interrupts
2050 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04002051 * @ah: struct ath5k_hw pointer we are operating on
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002052 *
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002053 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002054 * interrupts to detect TSF updates only.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002055 */
Bruno Randolfcd2c5482010-12-22 19:20:32 +09002056void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002057ath5k_beacon_config(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002058{
Bob Copelandb5f03952009-02-15 12:06:10 -05002059 unsigned long flags;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002060
Pavel Roskine0d687b2011-07-14 20:21:55 -04002061 spin_lock_irqsave(&ah->block, flags);
2062 ah->bmisscount = 0;
2063 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002064
Pavel Roskine0d687b2011-07-14 20:21:55 -04002065 if (ah->enable_beacon) {
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002066 /*
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002067 * In IBSS mode we use a self-linked tx descriptor and let the
2068 * hardware send the beacons automatically. We have to load it
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002069 * only once here.
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002070 * We use the SWBA interrupt only to keep track of the beacon
Bruno Randolf6ba81c22008-03-05 18:36:26 +09002071 * timers in order to detect automatic TSF updates.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002072 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002073 ath5k_beaconq_config(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002074
Pavel Roskine0d687b2011-07-14 20:21:55 -04002075 ah->imask |= AR5K_INT_SWBA;
Bruno Randolf036cd1e2008-01-19 18:18:21 +09002076
Pavel Roskine0d687b2011-07-14 20:21:55 -04002077 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Bob Copeland21800492009-07-04 12:59:52 -04002078 if (ath5k_hw_hasveol(ah))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002079 ath5k_beacon_send(ah);
Jiri Slabyda966bc2008-10-12 22:54:10 +02002080 } else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002081 ath5k_beacon_update_timers(ah, -1);
Bob Copeland21800492009-07-04 12:59:52 -04002082 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002083 ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002084 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002085
Pavel Roskine0d687b2011-07-14 20:21:55 -04002086 ath5k_hw_set_imr(ah, ah->imask);
Bob Copeland21800492009-07-04 12:59:52 -04002087 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002088 spin_unlock_irqrestore(&ah->block, flags);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002089}
2090
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002091static void ath5k_tasklet_beacon(unsigned long data)
2092{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002093 struct ath5k_hw *ah = (struct ath5k_hw *) data;
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002094
2095 /*
2096 * Software beacon alert--time to send a beacon.
2097 *
2098 * In IBSS mode we use this interrupt just to
2099 * keep track of the next TBTT (target beacon
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002100 * transmission time) in order to detect whether
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002101 * automatic TSF updates happened.
2102 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002103 if (ah->opmode == NL80211_IFTYPE_ADHOC) {
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002104 /* XXX: only if VEOL supported */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002105 u64 tsf = ath5k_hw_get_tsf64(ah);
2106 ah->nexttbtt += ah->bintval;
2107 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002108 "SWBA nexttbtt: %x hw_tu: %x "
2109 "TSF: %llx\n",
Pavel Roskine0d687b2011-07-14 20:21:55 -04002110 ah->nexttbtt,
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002111 TSF_TO_TU(tsf),
2112 (unsigned long long) tsf);
2113 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002114 spin_lock(&ah->block);
2115 ath5k_beacon_send(ah);
2116 spin_unlock(&ah->block);
Nick Kossifidis428cbd42009-04-30 15:55:47 -04002117 }
2118}
2119
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002120
2121/********************\
2122* Interrupt handling *
2123\********************/
2124
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002125static void
2126ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2127{
Bruno Randolf2111ac02010-04-02 18:44:08 +09002128 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002129 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2130 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2131
2132 /* Run ANI only when calibration is not active */
2133
Bruno Randolf2111ac02010-04-02 18:44:08 +09002134 ah->ah_cal_next_ani = jiffies +
2135 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002136 tasklet_schedule(&ah->ani_tasklet);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002137
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002138 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) &&
2139 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
2140 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) {
2141
2142 /* Run calibration only when another calibration
2143 * is not running.
2144 *
2145 * Note: This is for both full/short calibration,
2146 * if it's time for a full one, ath5k_calibrate_work will deal
2147 * with it. */
2148
2149 ah->ah_cal_next_short = jiffies +
2150 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2151 ieee80211_queue_work(ah->hw, &ah->calib_work);
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002152 }
2153 /* we could use SWI to generate enough interrupts to meet our
2154 * calibration interval requirements, if necessary:
2155 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2156}
2157
Felix Fietkauc266c712011-04-10 18:32:19 +02002158static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002159ath5k_schedule_rx(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02002160{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002161 ah->rx_pending = true;
2162 tasklet_schedule(&ah->rxtq);
Felix Fietkauc266c712011-04-10 18:32:19 +02002163}
2164
2165static void
Pavel Roskine0d687b2011-07-14 20:21:55 -04002166ath5k_schedule_tx(struct ath5k_hw *ah)
Felix Fietkauc266c712011-04-10 18:32:19 +02002167{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002168 ah->tx_pending = true;
2169 tasklet_schedule(&ah->txtq);
Felix Fietkauc266c712011-04-10 18:32:19 +02002170}
2171
Pavel Roskinf5cbc8b2011-06-15 18:03:22 -04002172static irqreturn_t
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002173ath5k_intr(int irq, void *dev_id)
2174{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002175 struct ath5k_hw *ah = dev_id;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002176 enum ath5k_int status;
2177 unsigned int counter = 1000;
2178
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002179
2180 /*
2181 * If hw is not ready (or detached) and we get an
2182 * interrupt, or if we have no interrupts pending
2183 * (that means it's not for us) skip it.
2184 *
2185 * NOTE: Group 0/1 PCI interface registers are not
2186 * supported on WiSOCs, so we can't check for pending
2187 * interrupts (ISR belongs to another register group
2188 * so we are ok).
2189 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002190 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002191 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2192 !ath5k_hw_is_intr_pending(ah))))
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002193 return IRQ_NONE;
2194
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002195 /** Main loop **/
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002196 do {
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002197 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2198
Pavel Roskine0d687b2011-07-14 20:21:55 -04002199 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2200 status, ah->imask);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002201
2202 /*
2203 * Fatal hw error -> Log and reset
2204 *
2205 * Fatal errors are unrecoverable so we have to
2206 * reset the card. These errors include bus and
2207 * dma errors.
2208 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002209 if (unlikely(status & AR5K_INT_FATAL)) {
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002210
Pavel Roskine0d687b2011-07-14 20:21:55 -04002211 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09002212 "fatal int, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002213 ieee80211_queue_work(ah->hw, &ah->reset_work);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002214
2215 /*
2216 * RX Overrun -> Count and reset if needed
2217 *
2218 * Receive buffers are full. Either the bus is busy or
2219 * the CPU is not fast enough to process all received
2220 * frames.
2221 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002222 } else if (unlikely(status & AR5K_INT_RXORN)) {
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002223
Bruno Randolf87d77c42010-04-12 16:38:52 +09002224 /*
Bruno Randolf87d77c42010-04-12 16:38:52 +09002225 * Older chipsets need a reset to come out of this
2226 * condition, but we treat it as RX for newer chips.
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002227 * We don't know exactly which versions need a reset
Bruno Randolf87d77c42010-04-12 16:38:52 +09002228 * this guess is copied from the HAL.
2229 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002230 ah->stats.rxorn_intr++;
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002231
Bruno Randolf8d67a032010-06-16 19:11:12 +09002232 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002233 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf8d67a032010-06-16 19:11:12 +09002234 "rx overrun, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002235 ieee80211_queue_work(ah->hw, &ah->reset_work);
Pavel Roskind2c7f772011-07-07 18:14:07 -04002236 } else
Pavel Roskine0d687b2011-07-14 20:21:55 -04002237 ath5k_schedule_rx(ah);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002238
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002239 } else {
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002240
2241 /* Software Beacon Alert -> Schedule beacon tasklet */
Pavel Roskind2c7f772011-07-07 18:14:07 -04002242 if (status & AR5K_INT_SWBA)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002243 tasklet_hi_schedule(&ah->beacontq);
Pavel Roskind2c7f772011-07-07 18:14:07 -04002244
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002245 /*
2246 * No more RX descriptors -> Just count
2247 *
2248 * NB: the hardware should re-read the link when
2249 * RXE bit is written, but it doesn't work at
2250 * least on older hardware revs.
2251 */
2252 if (status & AR5K_INT_RXEOL)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002253 ah->stats.rxeol_intr++;
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002254
2255
2256 /* TX Underrun -> Bump tx trigger level */
2257 if (status & AR5K_INT_TXURN)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002258 ath5k_hw_update_tx_triglevel(ah, true);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002259
2260 /* RX -> Schedule rx tasklet */
Nick Kossifidis4c674c62008-10-26 20:40:25 +02002261 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002262 ath5k_schedule_rx(ah);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002263
2264 /* TX -> Schedule tx tasklet */
2265 if (status & (AR5K_INT_TXOK
2266 | AR5K_INT_TXDESC
2267 | AR5K_INT_TXERR
2268 | AR5K_INT_TXEOL))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002269 ath5k_schedule_tx(ah);
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002270
2271 /* Missed beacon -> TODO
2272 if (status & AR5K_INT_BMISS)
2273 */
2274
2275 /* MIB event -> Update counters and notify ANI */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002276 if (status & AR5K_INT_MIB) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002277 ah->stats.mib_intr++;
Bruno Randolf495391d2010-03-25 14:49:36 +09002278 ath5k_hw_update_mib_counters(ah);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002279 ath5k_ani_mib_intr(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002280 }
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002281
2282 /* GPIO -> Notify RFKill layer */
Tobias Doerffele6a3b612009-06-09 17:33:27 +02002283 if (status & AR5K_INT_GPIO)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002284 tasklet_schedule(&ah->rf_kill.toggleq);
Bob Copelanda6ae0712009-06-09 23:43:11 -04002285
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002286 }
Felix Fietkau4cebb342010-12-02 10:27:21 +01002287
2288 if (ath5k_get_bus_type(ah) == ATH_AHB)
2289 break;
2290
Bob Copeland2516baa2009-04-27 22:18:10 -04002291 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002292
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002293 /*
2294 * Until we handle rx/tx interrupts mask them on IMR
2295 *
2296 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets
2297 * and unset after we 've handled the interrupts.
2298 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002299 if (ah->rx_pending || ah->tx_pending)
2300 ath5k_set_current_imask(ah);
Felix Fietkauc266c712011-04-10 18:32:19 +02002301
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002302 if (unlikely(!counter))
Pavel Roskine0d687b2011-07-14 20:21:55 -04002303 ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002304
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002305 /* Fire up calibration poll */
Bruno Randolf6a8a3f62010-03-25 14:49:19 +09002306 ath5k_intr_calibration_poll(ah);
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002307
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002308 return IRQ_HANDLED;
2309}
2310
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002311/*
2312 * Periodically recalibrate the PHY to account
2313 * for temperature/environment changes.
2314 */
2315static void
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002316ath5k_calibrate_work(struct work_struct *work)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002317{
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002318 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
2319 calib_work);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002320
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002321 /* Should we run a full calibration ? */
2322 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
2323
2324 ah->ah_cal_next_full = jiffies +
2325 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2326 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
2327
2328 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
2329 "running full calibration\n");
2330
2331 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2332 /*
2333 * Rfgain is out of bounds, reset the chip
2334 * to load new gain values.
2335 */
2336 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
2337 "got new rfgain, resetting\n");
2338 ieee80211_queue_work(ah->hw, &ah->reset_work);
2339 }
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002340 } else
2341 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT;
2342
Nick Kossifidis6e2206622009-08-10 03:31:31 +03002343
Pavel Roskine0d687b2011-07-14 20:21:55 -04002344 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2345 ieee80211_frequency_to_channel(ah->curchan->center_freq),
2346 ah->curchan->hw_value);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002347
Pavel Roskine0d687b2011-07-14 20:21:55 -04002348 if (ath5k_hw_phy_calibrate(ah, ah->curchan))
2349 ATH5K_ERR(ah, "calibration of channel %u failed\n",
Luis R. Rodriguez400ec452008-02-03 21:51:49 -05002350 ieee80211_frequency_to_channel(
Pavel Roskine0d687b2011-07-14 20:21:55 -04002351 ah->curchan->center_freq));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002352
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002353 /* Clear calibration flags */
Felix Fietkau62e2c102012-03-06 11:06:37 +01002354 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL)
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002355 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
Felix Fietkau62e2c102012-03-06 11:06:37 +01002356 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002357 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002358}
2359
2360
Bruno Randolf2111ac02010-04-02 18:44:08 +09002361static void
2362ath5k_tasklet_ani(unsigned long data)
2363{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002364 struct ath5k_hw *ah = (void *)data;
Bruno Randolf2111ac02010-04-02 18:44:08 +09002365
2366 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2367 ath5k_ani_calibration(ah);
2368 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002369}
2370
2371
Bruno Randolf4edd7612010-09-17 11:36:56 +09002372static void
2373ath5k_tx_complete_poll_work(struct work_struct *work)
2374{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002375 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002376 tx_complete_work.work);
2377 struct ath5k_txq *txq;
2378 int i;
2379 bool needreset = false;
2380
Pavel Roskine0d687b2011-07-14 20:21:55 -04002381 mutex_lock(&ah->lock);
Bob Copeland599b13a2011-01-18 08:06:43 -05002382
Pavel Roskine0d687b2011-07-14 20:21:55 -04002383 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
2384 if (ah->txqs[i].setup) {
2385 txq = &ah->txqs[i];
Bruno Randolf4edd7612010-09-17 11:36:56 +09002386 spin_lock_bh(&txq->lock);
Bruno Randolf23413292010-09-17 11:37:07 +09002387 if (txq->txq_len > 1) {
Bruno Randolf4edd7612010-09-17 11:36:56 +09002388 if (txq->txq_poll_mark) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002389 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002390 "TX queue stuck %d\n",
2391 txq->qnum);
2392 needreset = true;
Bruno Randolf923e5b32010-09-17 11:37:02 +09002393 txq->txq_stuck++;
Bruno Randolf4edd7612010-09-17 11:36:56 +09002394 spin_unlock_bh(&txq->lock);
2395 break;
2396 } else {
2397 txq->txq_poll_mark = true;
2398 }
2399 }
2400 spin_unlock_bh(&txq->lock);
2401 }
2402 }
2403
2404 if (needreset) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002405 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002406 "TX queues stuck, resetting\n");
Pavel Roskine0d687b2011-07-14 20:21:55 -04002407 ath5k_reset(ah, NULL, true);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002408 }
2409
Pavel Roskine0d687b2011-07-14 20:21:55 -04002410 mutex_unlock(&ah->lock);
Bob Copeland599b13a2011-01-18 08:06:43 -05002411
Pavel Roskine0d687b2011-07-14 20:21:55 -04002412 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002413 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2414}
2415
2416
Bob Copeland8a63fac2010-09-17 12:45:07 +09002417/*************************\
2418* Initialization routines *
2419\*************************/
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002420
Felix Fietkau9b4760e2012-04-17 00:39:27 -04002421static const struct ieee80211_iface_limit if_limits[] = {
2422 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) },
2423 { .max = 4, .types =
2424#ifdef CONFIG_MAC80211_MESH
2425 BIT(NL80211_IFTYPE_MESH_POINT) |
2426#endif
2427 BIT(NL80211_IFTYPE_AP) },
2428};
2429
2430static const struct ieee80211_iface_combination if_comb = {
2431 .limits = if_limits,
2432 .n_limits = ARRAY_SIZE(if_limits),
2433 .max_interfaces = 2048,
2434 .num_different_channels = 1,
2435};
2436
Pavel Roskin25380d82011-07-07 18:13:42 -04002437int __devinit
Pavel Roskinbb1f3ad2011-07-26 22:27:05 -04002438ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
Felix Fietkau132b1c32010-12-02 10:26:56 +01002439{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002440 struct ieee80211_hw *hw = ah->hw;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002441 struct ath_common *common;
2442 int ret;
2443 int csz;
2444
2445 /* Initialize driver private data */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002446 SET_IEEE80211_DEV(hw, ah->dev);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
Nick Kossifidisb9e61f12010-12-03 06:12:39 +02002448 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2449 IEEE80211_HW_SIGNAL_DBM |
2450 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002451
2452 hw->wiphy->interface_modes =
2453 BIT(NL80211_IFTYPE_AP) |
2454 BIT(NL80211_IFTYPE_STATION) |
2455 BIT(NL80211_IFTYPE_ADHOC) |
2456 BIT(NL80211_IFTYPE_MESH_POINT);
2457
Felix Fietkau9b4760e2012-04-17 00:39:27 -04002458 hw->wiphy->iface_combinations = &if_comb;
2459 hw->wiphy->n_iface_combinations = 1;
2460
Antonio Quartullif9972572012-01-14 11:42:43 +01002461 /* SW support for IBSS_RSN is provided by mac80211 */
2462 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
2463
Bruno Randolf3de135d2010-12-16 11:30:33 +09002464 /* both antennas can be configured as RX or TX */
2465 hw->wiphy->available_antennas_tx = 0x3;
2466 hw->wiphy->available_antennas_rx = 0x3;
2467
Felix Fietkau132b1c32010-12-02 10:26:56 +01002468 hw->extra_tx_headroom = 2;
2469 hw->channel_change_time = 5000;
2470
2471 /*
2472 * Mark the device as detached to avoid processing
2473 * interrupts until setup is complete.
2474 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002475 __set_bit(ATH_STAT_INVALID, ah->status);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002476
Pavel Roskine0d687b2011-07-14 20:21:55 -04002477 ah->opmode = NL80211_IFTYPE_STATION;
2478 ah->bintval = 1000;
2479 mutex_init(&ah->lock);
2480 spin_lock_init(&ah->rxbuflock);
2481 spin_lock_init(&ah->txbuflock);
2482 spin_lock_init(&ah->block);
2483 spin_lock_init(&ah->irqlock);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002484
2485 /* Setup interrupt handler */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002486 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002487 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002488 ATH5K_ERR(ah, "request_irq failed\n");
Felix Fietkau132b1c32010-12-02 10:26:56 +01002489 goto err;
2490 }
2491
Pavel Roskine0d687b2011-07-14 20:21:55 -04002492 common = ath5k_hw_common(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002493 common->ops = &ath5k_common_ops;
2494 common->bus_ops = bus_ops;
Pavel Roskine0d687b2011-07-14 20:21:55 -04002495 common->ah = ah;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002496 common->hw = hw;
Pavel Roskine0d687b2011-07-14 20:21:55 -04002497 common->priv = ah;
Felix Fietkau26d16d22011-07-12 09:02:01 +08002498 common->clockrate = 40;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002499
2500 /*
2501 * Cache line size is used to size and align various
2502 * structures used to communicate with the hardware.
2503 */
2504 ath5k_read_cachesize(common, &csz);
2505 common->cachelsz = csz << 2; /* convert to bytes */
2506
2507 spin_lock_init(&common->cc_lock);
2508
2509 /* Initialize device */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002510 ret = ath5k_hw_init(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002511 if (ret)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002512 goto err_irq;
Felix Fietkau132b1c32010-12-02 10:26:56 +01002513
Nick Kossifidis86f62d92011-11-25 20:40:28 +02002514 /* Set up multi-rate retry capabilities */
2515 if (ah->ah_capabilities.cap_has_mrr_support) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002516 hw->max_rates = 4;
Bruno Randolf76a9f6f2011-01-28 16:52:11 +09002517 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2518 AR5K_INIT_RETRY_LONG);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002519 }
2520
2521 hw->vif_data_size = sizeof(struct ath5k_vif);
2522
2523 /* Finish private driver data initialization */
2524 ret = ath5k_init(hw);
2525 if (ret)
2526 goto err_ah;
2527
Pavel Roskine0d687b2011-07-14 20:21:55 -04002528 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2529 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
2530 ah->ah_mac_srev,
2531 ah->ah_phy_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002532
Pavel Roskine0d687b2011-07-14 20:21:55 -04002533 if (!ah->ah_single_chip) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002534 /* Single chip radio (!RF5111) */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002535 if (ah->ah_radio_5ghz_revision &&
2536 !ah->ah_radio_2ghz_revision) {
Felix Fietkau132b1c32010-12-02 10:26:56 +01002537 /* No 5GHz support -> report 2GHz radio */
2538 if (!test_bit(AR5K_MODE_11A,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002539 ah->ah_capabilities.cap_mode)) {
2540 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002541 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002542 ah->ah_radio_5ghz_revision),
2543 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002544 /* No 2GHz support (5110 and some
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002545 * 5GHz only cards) -> report 5GHz radio */
Felix Fietkau132b1c32010-12-02 10:26:56 +01002546 } else if (!test_bit(AR5K_MODE_11B,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002547 ah->ah_capabilities.cap_mode)) {
2548 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002549 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002550 ah->ah_radio_5ghz_revision),
2551 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002552 /* Multiband radio */
2553 } else {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002554 ATH5K_INFO(ah, "RF%s multiband radio found"
Felix Fietkau132b1c32010-12-02 10:26:56 +01002555 " (0x%x)\n",
2556 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002557 ah->ah_radio_5ghz_revision),
2558 ah->ah_radio_5ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002559 }
2560 }
2561 /* Multi chip radio (RF5111 - RF2111) ->
2562 * report both 2GHz/5GHz radios */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002563 else if (ah->ah_radio_5ghz_revision &&
2564 ah->ah_radio_2ghz_revision) {
2565 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002566 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002567 ah->ah_radio_5ghz_revision),
2568 ah->ah_radio_5ghz_revision);
2569 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
Felix Fietkau132b1c32010-12-02 10:26:56 +01002570 ath5k_chip_name(AR5K_VERSION_RAD,
Pavel Roskine0d687b2011-07-14 20:21:55 -04002571 ah->ah_radio_2ghz_revision),
2572 ah->ah_radio_2ghz_revision);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002573 }
2574 }
2575
Pavel Roskine0d687b2011-07-14 20:21:55 -04002576 ath5k_debug_init_device(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002577
2578 /* ready to process interrupts */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002579 __clear_bit(ATH_STAT_INVALID, ah->status);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002580
2581 return 0;
2582err_ah:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002583 ath5k_hw_deinit(ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002584err_irq:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002585 free_irq(ah->irq, ah);
Felix Fietkau132b1c32010-12-02 10:26:56 +01002586err:
2587 return ret;
2588}
2589
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002590static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04002591ath5k_stop_locked(struct ath5k_hw *ah)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002592{
Bob Copelandcec8db22009-07-04 12:59:51 -04002593
Pavel Roskine0d687b2011-07-14 20:21:55 -04002594 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
2595 test_bit(ATH_STAT_INVALID, ah->status));
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002596
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002597 /*
Bob Copeland8a63fac2010-09-17 12:45:07 +09002598 * Shutdown the hardware and driver:
2599 * stop output from above
2600 * disable interrupts
2601 * turn off timers
2602 * turn off the radio
2603 * clear transmit machinery
2604 * clear receive machinery
2605 * drain and release tx queues
2606 * reclaim beacon resources
2607 * power down hardware
2608 *
2609 * Note that some of this work is not possible if the
2610 * hardware is gone (invalid).
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002611 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002612 ieee80211_stop_queues(ah->hw);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002613
Pavel Roskine0d687b2011-07-14 20:21:55 -04002614 if (!test_bit(ATH_STAT_INVALID, ah->status)) {
2615 ath5k_led_off(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002616 ath5k_hw_set_imr(ah, 0);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002617 synchronize_irq(ah->irq);
2618 ath5k_rx_stop(ah);
Nick Kossifidis80dac9e2010-11-23 20:45:38 +02002619 ath5k_hw_dma_stop(ah);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002620 ath5k_drain_tx_buffs(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002621 ath5k_hw_phy_disable(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002622 }
2623
Bob Copeland8a63fac2010-09-17 12:45:07 +09002624 return 0;
2625}
2626
Pavel Roskinfabba042011-07-21 13:36:28 -04002627int ath5k_start(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002628{
Pavel Roskinfabba042011-07-21 13:36:28 -04002629 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002630 struct ath_common *common = ath5k_hw_common(ah);
2631 int ret, i;
2632
Pavel Roskine0d687b2011-07-14 20:21:55 -04002633 mutex_lock(&ah->lock);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002634
Pavel Roskine0d687b2011-07-14 20:21:55 -04002635 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002636
2637 /*
2638 * Stop anything previously setup. This is safe
2639 * no matter this is the first time through or not.
2640 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002641 ath5k_stop_locked(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002642
2643 /*
2644 * The basic interface to setting the hardware in a good
2645 * state is ``reset''. On return the hardware is known to
2646 * be powered up and with interrupts disabled. This must
2647 * be followed by initialization of the appropriate bits
2648 * and then setup of the interrupt mask.
2649 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002650 ah->curchan = ah->hw->conf.channel;
Nick Kossifidis34ce6442011-11-25 20:40:22 +02002651 ah->imask = AR5K_INT_RXOK
2652 | AR5K_INT_RXERR
2653 | AR5K_INT_RXEOL
2654 | AR5K_INT_RXORN
2655 | AR5K_INT_TXDESC
2656 | AR5K_INT_TXEOL
2657 | AR5K_INT_FATAL
2658 | AR5K_INT_GLOBAL
2659 | AR5K_INT_MIB;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002660
Pavel Roskine0d687b2011-07-14 20:21:55 -04002661 ret = ath5k_reset(ah, NULL, false);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002662 if (ret)
2663 goto done;
2664
Nick Kossifidis84e1e732011-11-25 20:40:27 +02002665 if (!ath5k_modparam_no_hw_rfkill_switch)
2666 ath5k_rfkill_hw_start(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002667
2668 /*
2669 * Reset the key cache since some parts do not reset the
2670 * contents on initial power up or resume from suspend.
2671 */
2672 for (i = 0; i < common->keymax; i++)
2673 ath_hw_keyreset(common, (u16) i);
2674
Nick Kossifidis61cde032010-11-23 21:12:23 +02002675 /* Use higher rates for acks instead of base
2676 * rate */
2677 ah->ah_ack_bitrate_high = true;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002678
Pavel Roskine0d687b2011-07-14 20:21:55 -04002679 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
2680 ah->bslot[i] = NULL;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07002681
Bob Copeland8a63fac2010-09-17 12:45:07 +09002682 ret = 0;
2683done:
2684 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002685 mutex_unlock(&ah->lock);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002686
Pavel Roskine0d687b2011-07-14 20:21:55 -04002687 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
Bruno Randolf4edd7612010-09-17 11:36:56 +09002688 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2689
Bob Copeland8a63fac2010-09-17 12:45:07 +09002690 return ret;
2691}
2692
Pavel Roskine0d687b2011-07-14 20:21:55 -04002693static void ath5k_stop_tasklets(struct ath5k_hw *ah)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002694{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002695 ah->rx_pending = false;
2696 ah->tx_pending = false;
2697 tasklet_kill(&ah->rxtq);
2698 tasklet_kill(&ah->txtq);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002699 tasklet_kill(&ah->beacontq);
2700 tasklet_kill(&ah->ani_tasklet);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002701}
2702
2703/*
2704 * Stop the device, grabbing the top-level lock to protect
2705 * against concurrent entry through ath5k_init (which can happen
2706 * if another thread does a system call and the thread doing the
2707 * stop is preempted).
2708 */
Pavel Roskinfabba042011-07-21 13:36:28 -04002709void ath5k_stop(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002710{
Pavel Roskinfabba042011-07-21 13:36:28 -04002711 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002712 int ret;
2713
Pavel Roskine0d687b2011-07-14 20:21:55 -04002714 mutex_lock(&ah->lock);
2715 ret = ath5k_stop_locked(ah);
2716 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
Bob Copeland8a63fac2010-09-17 12:45:07 +09002717 /*
2718 * Don't set the card in full sleep mode!
2719 *
2720 * a) When the device is in this state it must be carefully
2721 * woken up or references to registers in the PCI clock
2722 * domain may freeze the bus (and system). This varies
2723 * by chip and is mostly an issue with newer parts
2724 * (madwifi sources mentioned srev >= 0x78) that go to
2725 * sleep more quickly.
2726 *
2727 * b) On older chips full sleep results a weird behaviour
2728 * during wakeup. I tested various cards with srev < 0x78
2729 * and they don't wake up after module reload, a second
2730 * module reload is needed to bring the card up again.
2731 *
2732 * Until we figure out what's going on don't enable
2733 * full chip reset on any chip (this is what Legacy HAL
2734 * and Sam's HAL do anyway). Instead Perform a full reset
2735 * on the device (same as initial state after attach) and
2736 * leave it idle (keep MAC/BB on warm reset) */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002737 ret = ath5k_hw_on_hold(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002738
Pavel Roskine0d687b2011-07-14 20:21:55 -04002739 ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
Bob Copeland8a63fac2010-09-17 12:45:07 +09002740 "putting device to sleep\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002741 }
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002742
Bob Copeland8a63fac2010-09-17 12:45:07 +09002743 mmiowb();
Pavel Roskine0d687b2011-07-14 20:21:55 -04002744 mutex_unlock(&ah->lock);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002745
Pavel Roskine0d687b2011-07-14 20:21:55 -04002746 ath5k_stop_tasklets(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002747
Pavel Roskine0d687b2011-07-14 20:21:55 -04002748 cancel_delayed_work_sync(&ah->tx_complete_work);
Bruno Randolf4edd7612010-09-17 11:36:56 +09002749
Nick Kossifidis84e1e732011-11-25 20:40:27 +02002750 if (!ath5k_modparam_no_hw_rfkill_switch)
2751 ath5k_rfkill_hw_stop(ah);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002752}
2753
Bob Copeland209d8892009-05-07 08:09:08 -04002754/*
2755 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2756 * and change to the given channel.
Bob Copeland5faaff72010-07-13 11:32:40 -04002757 *
Pavel Roskine0d687b2011-07-14 20:21:55 -04002758 * This should be called with ah->lock.
Bob Copeland209d8892009-05-07 08:09:08 -04002759 */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002760static int
Pavel Roskine0d687b2011-07-14 20:21:55 -04002761ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
Nick Kossifidis8aec7af2010-11-23 21:39:28 +02002762 bool skip_pcu)
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002763{
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002764 struct ath_common *common = ath5k_hw_common(ah);
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002765 int ret, ani_mode;
Nick Kossifidisa99168e2011-06-02 03:09:48 +03002766 bool fast;
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002767
Pavel Roskine0d687b2011-07-14 20:21:55 -04002768 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002769
Bob Copeland450464d2010-07-13 11:32:41 -04002770 ath5k_hw_set_imr(ah, 0);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002771 synchronize_irq(ah->irq);
2772 ath5k_stop_tasklets(ah);
Bob Copeland450464d2010-07-13 11:32:41 -04002773
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002774 /* Save ani mode and disable ANI during
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002775 * reset. If we don't we might get false
2776 * PHY error interrupts. */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002777 ani_mode = ah->ani_state.ani_mode;
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002778 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2779
Nick Kossifidis19252ec2010-12-03 06:05:19 +02002780 /* We are going to empty hw queues
2781 * so we should also free any remaining
2782 * tx buffers */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002783 ath5k_drain_tx_buffs(ah);
Bruno Randolf930a7622011-01-19 18:21:13 +09002784 if (chan)
Pavel Roskine0d687b2011-07-14 20:21:55 -04002785 ah->curchan = chan;
Nick Kossifidisa99168e2011-06-02 03:09:48 +03002786
2787 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
2788
Pavel Roskine0d687b2011-07-14 20:21:55 -04002789 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002790 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002791 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002792 goto err;
2793 }
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002794
Pavel Roskine0d687b2011-07-14 20:21:55 -04002795 ret = ath5k_rx_start(ah);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002796 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002797 ATH5K_ERR(ah, "can't start recv logic\n");
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002798 goto err;
2799 }
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002800
Nick Kossifidis344b54b2010-12-03 06:07:13 +02002801 ath5k_ani_init(ah, ani_mode);
Bruno Randolf2111ac02010-04-02 18:44:08 +09002802
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002803 /*
2804 * Set calibration intervals
2805 *
2806 * Note: We don't need to run calibration imediately
2807 * since some initial calibration is done on reset
2808 * even for fast channel switching. Also on scanning
2809 * this will get set again and again and it won't get
2810 * executed unless we connect somewhere and spend some
2811 * time on the channel (that's what calibration needs
2812 * anyway to be accurate).
2813 */
2814 ah->ah_cal_next_full = jiffies +
2815 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2816 ah->ah_cal_next_ani = jiffies +
2817 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2818 ah->ah_cal_next_short = jiffies +
2819 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT);
2820
Bruno Randolf5dcc03f2010-12-02 19:12:31 +09002821 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
Bruno Randolfafe86282010-05-19 10:31:10 +09002822
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002823 /* clear survey data and cycle counters */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002824 memset(&ah->survey, 0, sizeof(ah->survey));
Bob Copelandbb007552010-12-26 12:10:05 -05002825 spin_lock_bh(&common->cc_lock);
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002826 ath_hw_cycle_counters_update(common);
2827 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2828 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
Bob Copelandbb007552010-12-26 12:10:05 -05002829 spin_unlock_bh(&common->cc_lock);
Bruno Randolff15a4bb2010-12-16 16:22:20 +09002830
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002831 /*
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002832 * Change channels and update the h/w rate map if we're switching;
2833 * e.g. 11a to 11b/g.
2834 *
2835 * We may be doing a reset in response to an ioctl that changes the
2836 * channel so update any state that might change as a result.
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002837 *
2838 * XXX needed?
2839 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002840/* ath5k_chan_change(ah, c); */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002841
Pavel Roskine0d687b2011-07-14 20:21:55 -04002842 ath5k_beacon_config(ah);
Jiri Slabyd7dc1002008-07-23 13:17:35 +02002843 /* intrs are enabled by ath5k_beacon_config */
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002844
Pavel Roskine0d687b2011-07-14 20:21:55 -04002845 ieee80211_wake_queues(ah->hw);
Bruno Randolf397f3852010-05-19 10:30:49 +09002846
Jiri Slabyfa1c1142007-08-12 17:33:16 +02002847 return 0;
2848err:
2849 return ret;
2850}
2851
Bob Copeland5faaff72010-07-13 11:32:40 -04002852static void ath5k_reset_work(struct work_struct *work)
2853{
Pavel Roskine0d687b2011-07-14 20:21:55 -04002854 struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
Bob Copeland5faaff72010-07-13 11:32:40 -04002855 reset_work);
2856
Pavel Roskine0d687b2011-07-14 20:21:55 -04002857 mutex_lock(&ah->lock);
2858 ath5k_reset(ah, NULL, true);
2859 mutex_unlock(&ah->lock);
Bob Copeland5faaff72010-07-13 11:32:40 -04002860}
2861
Pavel Roskin25380d82011-07-07 18:13:42 -04002862static int __devinit
Felix Fietkau132b1c32010-12-02 10:26:56 +01002863ath5k_init(struct ieee80211_hw *hw)
Bob Copeland8a63fac2010-09-17 12:45:07 +09002864{
Felix Fietkau132b1c32010-12-02 10:26:56 +01002865
Pavel Roskine0d687b2011-07-14 20:21:55 -04002866 struct ath5k_hw *ah = hw->priv;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002867 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
Bruno Randolf925e0b02010-09-17 11:36:35 +09002868 struct ath5k_txq *txq;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002869 u8 mac[ETH_ALEN] = {};
2870 int ret;
2871
Bob Copeland8a63fac2010-09-17 12:45:07 +09002872
2873 /*
Bob Copeland8a63fac2010-09-17 12:45:07 +09002874 * Collect the channel list. The 802.11 layer
Pavel Roskin6a2a0e72011-07-09 00:17:51 -04002875 * is responsible for filtering this list based
Bob Copeland8a63fac2010-09-17 12:45:07 +09002876 * on settings like the phy mode and regulatory
2877 * domain restrictions.
2878 */
2879 ret = ath5k_setup_bands(hw);
2880 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002881 ATH5K_ERR(ah, "can't get channels\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002882 goto err;
2883 }
2884
Bob Copeland8a63fac2010-09-17 12:45:07 +09002885 /*
2886 * Allocate tx+rx descriptors and populate the lists.
2887 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002888 ret = ath5k_desc_alloc(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002889 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002890 ATH5K_ERR(ah, "can't allocate descriptors\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002891 goto err;
2892 }
2893
2894 /*
2895 * Allocate hardware transmit queues: one queue for
2896 * beacon frames and one data queue for each QoS
2897 * priority. Note that hw functions handle resetting
2898 * these queues at the needed time.
2899 */
2900 ret = ath5k_beaconq_setup(ah);
2901 if (ret < 0) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002902 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002903 goto err_desc;
2904 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002905 ah->bhalq = ret;
2906 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
2907 if (IS_ERR(ah->cabq)) {
2908 ATH5K_ERR(ah, "can't setup cab queue\n");
2909 ret = PTR_ERR(ah->cabq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002910 goto err_bhal;
2911 }
2912
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002913 /* 5211 and 5212 usually support 10 queues but we better rely on the
2914 * capability information */
2915 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2916 /* This order matches mac80211's queue priority, so we can
2917 * directly use the mac80211 queue number without any mapping */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002918 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002919 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002920 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002921 ret = PTR_ERR(txq);
2922 goto err_queues;
2923 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002924 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002925 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002926 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002927 ret = PTR_ERR(txq);
2928 goto err_queues;
2929 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002930 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002931 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002932 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002933 ret = PTR_ERR(txq);
2934 goto err_queues;
2935 }
Pavel Roskine0d687b2011-07-14 20:21:55 -04002936 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002937 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002938 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002939 ret = PTR_ERR(txq);
2940 goto err_queues;
2941 }
2942 hw->queues = 4;
2943 } else {
2944 /* older hardware (5210) can only support one data queue */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002945 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002946 if (IS_ERR(txq)) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002947 ATH5K_ERR(ah, "can't setup xmit queue\n");
Bruno Randolf22d8d9f2010-12-07 11:08:12 +09002948 ret = PTR_ERR(txq);
2949 goto err_queues;
2950 }
2951 hw->queues = 1;
Bob Copeland8a63fac2010-09-17 12:45:07 +09002952 }
2953
Pavel Roskine0d687b2011-07-14 20:21:55 -04002954 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
2955 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002956 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
2957 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002958
Pavel Roskine0d687b2011-07-14 20:21:55 -04002959 INIT_WORK(&ah->reset_work, ath5k_reset_work);
Nick Kossifidisce169ac2011-11-25 20:40:23 +02002960 INIT_WORK(&ah->calib_work, ath5k_calibrate_work);
Pavel Roskine0d687b2011-07-14 20:21:55 -04002961 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002962
Felix Fietkaufa9bfd62011-04-13 21:56:44 +02002963 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002964 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002965 ATH5K_ERR(ah, "unable to read address from EEPROM\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002966 goto err_queues;
2967 }
2968
2969 SET_IEEE80211_PERM_ADDR(hw, mac);
2970 /* All MAC address bits matter for ACKs */
Pavel Roskine0d687b2011-07-14 20:21:55 -04002971 ath5k_update_bssid_mask_and_opmode(ah, NULL);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002972
2973 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2974 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2975 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002976 ATH5K_ERR(ah, "can't initialize regulatory system\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002977 goto err_queues;
2978 }
2979
2980 ret = ieee80211_register_hw(hw);
2981 if (ret) {
Pavel Roskine0d687b2011-07-14 20:21:55 -04002982 ATH5K_ERR(ah, "can't register ieee80211 hw\n");
Bob Copeland8a63fac2010-09-17 12:45:07 +09002983 goto err_queues;
2984 }
2985
2986 if (!ath_is_world_regd(regulatory))
2987 regulatory_hint(hw->wiphy, regulatory->alpha2);
2988
Pavel Roskine0d687b2011-07-14 20:21:55 -04002989 ath5k_init_leds(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002990
Pavel Roskine0d687b2011-07-14 20:21:55 -04002991 ath5k_sysfs_register(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002992
2993 return 0;
2994err_queues:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002995 ath5k_txq_release(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002996err_bhal:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002997 ath5k_hw_release_tx_queue(ah, ah->bhalq);
Bob Copeland8a63fac2010-09-17 12:45:07 +09002998err_desc:
Pavel Roskine0d687b2011-07-14 20:21:55 -04002999 ath5k_desc_free(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09003000err:
3001 return ret;
3002}
3003
Felix Fietkau132b1c32010-12-02 10:26:56 +01003004void
Pavel Roskinbb1f3ad2011-07-26 22:27:05 -04003005ath5k_deinit_ah(struct ath5k_hw *ah)
Bob Copeland8a63fac2010-09-17 12:45:07 +09003006{
Pavel Roskine0d687b2011-07-14 20:21:55 -04003007 struct ieee80211_hw *hw = ah->hw;
Bob Copeland8a63fac2010-09-17 12:45:07 +09003008
3009 /*
3010 * NB: the order of these is important:
3011 * o call the 802.11 layer before detaching ath5k_hw to
3012 * ensure callbacks into the driver to delete global
3013 * key cache entries can be handled
3014 * o reclaim the tx queue data structures after calling
3015 * the 802.11 layer as we'll get called back to reclaim
3016 * node state and potentially want to use them
3017 * o to cleanup the tx queues the hal is called, so detach
3018 * it last
3019 * XXX: ??? detach ath5k_hw ???
3020 * Other than that, it's straightforward...
3021 */
3022 ieee80211_unregister_hw(hw);
Pavel Roskine0d687b2011-07-14 20:21:55 -04003023 ath5k_desc_free(ah);
3024 ath5k_txq_release(ah);
3025 ath5k_hw_release_tx_queue(ah, ah->bhalq);
3026 ath5k_unregister_leds(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09003027
Pavel Roskine0d687b2011-07-14 20:21:55 -04003028 ath5k_sysfs_unregister(ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09003029 /*
3030 * NB: can't reclaim these until after ieee80211_ifdetach
3031 * returns because we'll get called back to reclaim node
3032 * state and potentially want to use them.
3033 */
Pavel Roskine0d687b2011-07-14 20:21:55 -04003034 ath5k_hw_deinit(ah);
3035 free_irq(ah->irq, ah);
Bob Copeland8a63fac2010-09-17 12:45:07 +09003036}
3037
Bruno Randolfcd2c5482010-12-22 19:20:32 +09003038bool
Pavel Roskine0d687b2011-07-14 20:21:55 -04003039ath5k_any_vif_assoc(struct ath5k_hw *ah)
Ben Greearb1ae1ed2010-09-30 12:22:58 -07003040{
Ben Greeare4b0b322011-03-03 14:39:05 -08003041 struct ath5k_vif_iter_data iter_data;
Ben Greearb1ae1ed2010-09-30 12:22:58 -07003042 iter_data.hw_macaddr = NULL;
3043 iter_data.any_assoc = false;
3044 iter_data.need_set_hw_addr = false;
3045 iter_data.found_active = true;
3046
Pavel Roskine0d687b2011-07-14 20:21:55 -04003047 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
Ben Greearb1ae1ed2010-09-30 12:22:58 -07003048 &iter_data);
3049 return iter_data.any_assoc;
3050}
3051
Bruno Randolfcd2c5482010-12-22 19:20:32 +09003052void
Pavel Roskinf5cbc8b2011-06-15 18:03:22 -04003053ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
Martin Xu02969b32008-11-24 10:49:27 +08003054{
Pavel Roskine0d687b2011-07-14 20:21:55 -04003055 struct ath5k_hw *ah = hw->priv;
Martin Xu02969b32008-11-24 10:49:27 +08003056 u32 rfilt;
3057 rfilt = ath5k_hw_get_rx_filter(ah);
3058 if (enable)
3059 rfilt |= AR5K_RX_FILTER_BEACON;
3060 else
3061 rfilt &= ~AR5K_RX_FILTER_BEACON;
3062 ath5k_hw_set_rx_filter(ah, rfilt);
Pavel Roskine0d687b2011-07-14 20:21:55 -04003063 ah->filter_flags = rfilt;
Martin Xu02969b32008-11-24 10:49:27 +08003064}
Joe Perches227842d2012-03-18 17:30:53 -07003065
3066void _ath5k_printk(const struct ath5k_hw *ah, const char *level,
3067 const char *fmt, ...)
3068{
3069 struct va_format vaf;
3070 va_list args;
3071
3072 va_start(args, fmt);
3073
3074 vaf.fmt = fmt;
3075 vaf.va = &args;
3076
3077 if (ah && ah->hw)
3078 printk("%s" pr_fmt("%s: %pV"),
3079 level, wiphy_name(ah->hw->wiphy), &vaf);
3080 else
3081 printk("%s" pr_fmt("%pV"), level, &vaf);
3082
3083 va_end(args);
3084}