Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | # |
| 2 | # For a description of the syntax of this configuration file, |
| 3 | # see Documentation/kbuild/kconfig-language.txt. |
| 4 | # |
| 5 | |
Mike Frysinger | 53f8a25 | 2007-11-15 15:48:01 +0800 | [diff] [blame] | 6 | mainmenu "Blackfin Kernel Configuration" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 7 | |
| 8 | config MMU |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 9 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | |
| 11 | config FPU |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 12 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 13 | |
| 14 | config RWSEM_GENERIC_SPINLOCK |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 15 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 16 | |
| 17 | config RWSEM_XCHGADD_ALGORITHM |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 18 | def_bool n |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 19 | |
| 20 | config BLACKFIN |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 21 | def_bool y |
Mike Frysinger | 1ee76d7 | 2009-06-10 04:45:29 -0400 | [diff] [blame] | 22 | select HAVE_FUNCTION_GRAPH_TRACER |
Mike Frysinger | 1c873be | 2009-06-09 07:25:09 -0400 | [diff] [blame] | 23 | select HAVE_FUNCTION_TRACER |
Sam Ravnborg | ec7748b | 2008-02-09 10:46:40 +0100 | [diff] [blame] | 24 | select HAVE_IDE |
Mike Frysinger | 538067c | 2009-06-07 03:47:01 -0400 | [diff] [blame] | 25 | select HAVE_KERNEL_GZIP |
| 26 | select HAVE_KERNEL_BZIP2 |
| 27 | select HAVE_KERNEL_LZMA |
Mathieu Desnoyers | 42d4b83 | 2008-02-02 15:10:34 -0500 | [diff] [blame] | 28 | select HAVE_OPROFILE |
Michael Hennerich | a4f0b32c | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 29 | select ARCH_WANT_OPTIONAL_GPIOLIB |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 30 | |
Mike Frysinger | 70f1256 | 2009-06-07 17:18:25 -0400 | [diff] [blame] | 31 | config GENERIC_BUG |
| 32 | def_bool y |
| 33 | depends on BUG |
| 34 | |
Aubrey Li | e3defff | 2007-05-21 18:09:11 +0800 | [diff] [blame] | 35 | config ZONE_DMA |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 36 | def_bool y |
Aubrey Li | e3defff | 2007-05-21 18:09:11 +0800 | [diff] [blame] | 37 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 38 | config GENERIC_FIND_NEXT_BIT |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 39 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 40 | |
| 41 | config GENERIC_HWEIGHT |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 42 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 43 | |
| 44 | config GENERIC_HARDIRQS |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 45 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 46 | |
| 47 | config GENERIC_IRQ_PROBE |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 48 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 49 | |
Michael Hennerich | b2d1583 | 2007-07-24 15:46:36 +0800 | [diff] [blame] | 50 | config GENERIC_GPIO |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 51 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 52 | |
| 53 | config FORCE_MAX_ZONEORDER |
| 54 | int |
| 55 | default "14" |
| 56 | |
| 57 | config GENERIC_CALIBRATE_DELAY |
Mike Frysinger | bac7d89 | 2009-06-07 03:46:06 -0400 | [diff] [blame] | 58 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 59 | |
Mike Frysinger | 6fa68e7 | 2009-06-08 18:45:01 -0400 | [diff] [blame] | 60 | config LOCKDEP_SUPPORT |
| 61 | def_bool y |
| 62 | |
Mike Frysinger | c7b412f | 2009-06-08 18:44:45 -0400 | [diff] [blame] | 63 | config STACKTRACE_SUPPORT |
| 64 | def_bool y |
| 65 | |
Mike Frysinger | 8f86001 | 2009-06-08 12:49:48 -0400 | [diff] [blame] | 66 | config TRACE_IRQFLAGS_SUPPORT |
| 67 | def_bool y |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 68 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 69 | source "init/Kconfig" |
Matt Helsley | dc52ddc | 2008-10-18 20:27:21 -0700 | [diff] [blame] | 70 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 71 | source "kernel/Kconfig.preempt" |
| 72 | |
Matt Helsley | dc52ddc | 2008-10-18 20:27:21 -0700 | [diff] [blame] | 73 | source "kernel/Kconfig.freezer" |
| 74 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 75 | menu "Blackfin Processor Options" |
| 76 | |
| 77 | comment "Processor and Board Settings" |
| 78 | |
| 79 | choice |
| 80 | prompt "CPU" |
| 81 | default BF533 |
| 82 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 83 | config BF512 |
| 84 | bool "BF512" |
| 85 | help |
| 86 | BF512 Processor Support. |
| 87 | |
| 88 | config BF514 |
| 89 | bool "BF514" |
| 90 | help |
| 91 | BF514 Processor Support. |
| 92 | |
| 93 | config BF516 |
| 94 | bool "BF516" |
| 95 | help |
| 96 | BF516 Processor Support. |
| 97 | |
| 98 | config BF518 |
| 99 | bool "BF518" |
| 100 | help |
| 101 | BF518 Processor Support. |
| 102 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 103 | config BF522 |
| 104 | bool "BF522" |
| 105 | help |
| 106 | BF522 Processor Support. |
| 107 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 108 | config BF523 |
| 109 | bool "BF523" |
| 110 | help |
| 111 | BF523 Processor Support. |
| 112 | |
| 113 | config BF524 |
| 114 | bool "BF524" |
| 115 | help |
| 116 | BF524 Processor Support. |
| 117 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 118 | config BF525 |
| 119 | bool "BF525" |
| 120 | help |
| 121 | BF525 Processor Support. |
| 122 | |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 123 | config BF526 |
| 124 | bool "BF526" |
| 125 | help |
| 126 | BF526 Processor Support. |
| 127 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 128 | config BF527 |
| 129 | bool "BF527" |
| 130 | help |
| 131 | BF527 Processor Support. |
| 132 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 133 | config BF531 |
| 134 | bool "BF531" |
| 135 | help |
| 136 | BF531 Processor Support. |
| 137 | |
| 138 | config BF532 |
| 139 | bool "BF532" |
| 140 | help |
| 141 | BF532 Processor Support. |
| 142 | |
| 143 | config BF533 |
| 144 | bool "BF533" |
| 145 | help |
| 146 | BF533 Processor Support. |
| 147 | |
| 148 | config BF534 |
| 149 | bool "BF534" |
| 150 | help |
| 151 | BF534 Processor Support. |
| 152 | |
| 153 | config BF536 |
| 154 | bool "BF536" |
| 155 | help |
| 156 | BF536 Processor Support. |
| 157 | |
| 158 | config BF537 |
| 159 | bool "BF537" |
| 160 | help |
| 161 | BF537 Processor Support. |
| 162 | |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 163 | config BF538 |
| 164 | bool "BF538" |
| 165 | help |
| 166 | BF538 Processor Support. |
| 167 | |
| 168 | config BF539 |
| 169 | bool "BF539" |
| 170 | help |
| 171 | BF539 Processor Support. |
| 172 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 173 | config BF542 |
| 174 | bool "BF542" |
| 175 | help |
| 176 | BF542 Processor Support. |
| 177 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 178 | config BF542M |
| 179 | bool "BF542m" |
| 180 | help |
| 181 | BF542 Processor Support. |
| 182 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 183 | config BF544 |
| 184 | bool "BF544" |
| 185 | help |
| 186 | BF544 Processor Support. |
| 187 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 188 | config BF544M |
| 189 | bool "BF544m" |
| 190 | help |
| 191 | BF544 Processor Support. |
| 192 | |
Mike Frysinger | 7c7fd17 | 2007-11-15 21:10:21 +0800 | [diff] [blame] | 193 | config BF547 |
| 194 | bool "BF547" |
| 195 | help |
| 196 | BF547 Processor Support. |
| 197 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 198 | config BF547M |
| 199 | bool "BF547m" |
| 200 | help |
| 201 | BF547 Processor Support. |
| 202 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 203 | config BF548 |
| 204 | bool "BF548" |
| 205 | help |
| 206 | BF548 Processor Support. |
| 207 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 208 | config BF548M |
| 209 | bool "BF548m" |
| 210 | help |
| 211 | BF548 Processor Support. |
| 212 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 213 | config BF549 |
| 214 | bool "BF549" |
| 215 | help |
| 216 | BF549 Processor Support. |
| 217 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 218 | config BF549M |
| 219 | bool "BF549m" |
| 220 | help |
| 221 | BF549 Processor Support. |
| 222 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 223 | config BF561 |
| 224 | bool "BF561" |
| 225 | help |
Mike Frysinger | cd88b4d | 2008-10-09 12:03:22 +0800 | [diff] [blame] | 226 | BF561 Processor Support. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 227 | |
| 228 | endchoice |
| 229 | |
Graf Yang | 46fa5ee | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 230 | config SMP |
| 231 | depends on BF561 |
Graf Yang | 9b9bfde | 2009-05-27 09:58:35 +0000 | [diff] [blame] | 232 | select GENERIC_TIME |
Graf Yang | 46fa5ee | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 233 | bool "Symmetric multi-processing support" |
| 234 | ---help--- |
| 235 | This enables support for systems with more than one CPU, |
| 236 | like the dual core BF561. If you have a system with only one |
| 237 | CPU, say N. If you have a system with more than one CPU, say Y. |
| 238 | |
| 239 | If you don't know what to do here, say N. |
| 240 | |
| 241 | config NR_CPUS |
| 242 | int |
| 243 | depends on SMP |
| 244 | default 2 if BF561 |
| 245 | |
| 246 | config IRQ_PER_CPU |
| 247 | bool |
| 248 | depends on SMP |
| 249 | default y |
| 250 | |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 251 | config BF_REV_MIN |
| 252 | int |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 253 | default 0 if (BF51x || BF52x || (BF54x && !BF54xM)) |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 254 | default 2 if (BF537 || BF536 || BF534) |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 255 | default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM) |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 256 | default 4 if (BF538 || BF539) |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 257 | |
| 258 | config BF_REV_MAX |
| 259 | int |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 260 | default 2 if (BF51x || BF52x || (BF54x && !BF54xM)) |
| 261 | default 3 if (BF537 || BF536 || BF534 || BF54xM) |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 262 | default 5 if (BF561 || BF538 || BF539) |
Mike Frysinger | 0c0497c | 2008-10-09 17:32:28 +0800 | [diff] [blame] | 263 | default 6 if (BF533 || BF532 || BF531) |
| 264 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 265 | choice |
| 266 | prompt "Silicon Rev" |
Mike Frysinger | f8b5565 | 2009-04-13 21:58:34 +0000 | [diff] [blame] | 267 | default BF_REV_0_0 if (BF51x || BF52x) |
| 268 | default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM)) |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 269 | default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 270 | |
| 271 | config BF_REV_0_0 |
| 272 | bool "0.0" |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 273 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 274 | |
| 275 | config BF_REV_0_1 |
Mike Frysinger | d07f438 | 2007-11-15 15:49:17 +0800 | [diff] [blame] | 276 | bool "0.1" |
Mike Frysinger | 3d15f30 | 2009-06-15 16:21:44 +0000 | [diff] [blame] | 277 | depends on (BF51x || BF52x || (BF54x && !BF54xM)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 278 | |
| 279 | config BF_REV_0_2 |
| 280 | bool "0.2" |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 281 | depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 282 | |
| 283 | config BF_REV_0_3 |
| 284 | bool "0.3" |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 285 | depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 286 | |
| 287 | config BF_REV_0_4 |
| 288 | bool "0.4" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 289 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 290 | |
| 291 | config BF_REV_0_5 |
| 292 | bool "0.5" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 293 | depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 294 | |
Mike Frysinger | 49f7253 | 2008-10-09 12:06:27 +0800 | [diff] [blame] | 295 | config BF_REV_0_6 |
| 296 | bool "0.6" |
| 297 | depends on (BF533 || BF532 || BF531) |
| 298 | |
Jie Zhang | de3025f | 2007-06-25 18:04:12 +0800 | [diff] [blame] | 299 | config BF_REV_ANY |
| 300 | bool "any" |
| 301 | |
| 302 | config BF_REV_NONE |
| 303 | bool "none" |
| 304 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 305 | endchoice |
| 306 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 307 | config BF51x |
| 308 | bool |
| 309 | depends on (BF512 || BF514 || BF516 || BF518) |
| 310 | default y |
| 311 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 312 | config BF52x |
| 313 | bool |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 314 | depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 315 | default y |
| 316 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 317 | config BF53x |
| 318 | bool |
| 319 | depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537) |
| 320 | default y |
| 321 | |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 322 | config BF54xM |
| 323 | bool |
| 324 | depends on (BF542M || BF544M || BF547M || BF548M || BF549M) |
| 325 | default y |
| 326 | |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 327 | config BF54x |
| 328 | bool |
Mike Frysinger | 2f89c06 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 329 | depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM) |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 330 | default y |
| 331 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 332 | config MEM_GENERIC_BOARD |
| 333 | bool |
| 334 | depends on GENERIC_BOARD |
| 335 | default y |
| 336 | |
| 337 | config MEM_MT48LC64M4A2FB_7E |
| 338 | bool |
| 339 | depends on (BFIN533_STAMP) |
| 340 | default y |
| 341 | |
| 342 | config MEM_MT48LC16M16A2TG_75 |
| 343 | bool |
| 344 | depends on (BFIN533_EZKIT || BFIN561_EZKIT \ |
Javier Herrero | ab472a0 | 2007-10-29 16:14:44 +0800 | [diff] [blame] | 345 | || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \ |
Michael Hennerich | 9db144f | 2008-07-19 17:16:07 +0800 | [diff] [blame] | 346 | || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 347 | default y |
| 348 | |
| 349 | config MEM_MT48LC32M8A2_75 |
| 350 | bool |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 351 | depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 352 | default y |
| 353 | |
| 354 | config MEM_MT48LC8M32B2B5_7 |
| 355 | bool |
| 356 | depends on (BFIN561_BLUETECHNIX_CM) |
| 357 | default y |
| 358 | |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 359 | config MEM_MT48LC32M16A2TG_75 |
| 360 | bool |
Graf Yang | ee48efb | 2009-06-18 04:32:04 +0000 | [diff] [blame] | 361 | depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 362 | default y |
| 363 | |
Sonic Zhang | 4934540 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 364 | config MEM_MT48LC32M8A2_75 |
| 365 | bool |
| 366 | depends on (BFIN518F_EZBRD) |
| 367 | default y |
| 368 | |
Graf Yang | ee48efb | 2009-06-18 04:32:04 +0000 | [diff] [blame] | 369 | config MEM_MT48H32M16LFCJ_75 |
| 370 | bool |
| 371 | depends on (BFIN526_EZBRD) |
| 372 | default y |
| 373 | |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 374 | source "arch/blackfin/mach-bf518/Kconfig" |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 375 | source "arch/blackfin/mach-bf527/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 376 | source "arch/blackfin/mach-bf533/Kconfig" |
| 377 | source "arch/blackfin/mach-bf561/Kconfig" |
| 378 | source "arch/blackfin/mach-bf537/Kconfig" |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 379 | source "arch/blackfin/mach-bf538/Kconfig" |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 380 | source "arch/blackfin/mach-bf548/Kconfig" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 381 | |
| 382 | menu "Board customizations" |
| 383 | |
| 384 | config CMDLINE_BOOL |
| 385 | bool "Default bootloader kernel arguments" |
| 386 | |
| 387 | config CMDLINE |
| 388 | string "Initial kernel command string" |
| 389 | depends on CMDLINE_BOOL |
| 390 | default "console=ttyBF0,57600" |
| 391 | help |
| 392 | If you don't have a boot loader capable of passing a command line string |
| 393 | to the kernel, you may specify one here. As a minimum, you should specify |
| 394 | the memory size and the root device (e.g., mem=8M, root=/dev/nfs). |
| 395 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 396 | config BOOT_LOAD |
| 397 | hex "Kernel load address for booting" |
| 398 | default "0x1000" |
| 399 | range 0x1000 0x20000000 |
| 400 | help |
| 401 | This option allows you to set the load address of the kernel. |
| 402 | This can be useful if you are on a board which has a small amount |
| 403 | of memory or you wish to reserve some memory at the beginning of |
| 404 | the address space. |
| 405 | |
| 406 | Note that you need to keep this value above 4k (0x1000) as this |
| 407 | memory region is used to capture NULL pointer references as well |
| 408 | as some core kernel functions. |
| 409 | |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 410 | config ROM_BASE |
| 411 | hex "Kernel ROM Base" |
Mike Frysinger | 8624991 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 412 | depends on ROMKERNEL |
Michael Hennerich | 8cc7117 | 2008-10-13 14:45:06 +0800 | [diff] [blame] | 413 | default "0x20040000" |
| 414 | range 0x20000000 0x20400000 if !(BF54x || BF561) |
| 415 | range 0x20000000 0x30000000 if (BF54x || BF561) |
| 416 | help |
| 417 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 418 | comment "Clock/PLL Setup" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 419 | |
| 420 | config CLKIN_HZ |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 421 | int "Frequency of the crystal on the board in Hz" |
Mike Frysinger | 5d1617b | 2008-04-24 05:03:26 +0800 | [diff] [blame] | 422 | default "10000000" if BFIN532_IP0X |
Mike Frysinger | d0cb9b4 | 2009-06-11 21:52:35 +0000 | [diff] [blame] | 423 | default "11059200" if BFIN533_STAMP |
| 424 | default "24576000" if PNAV10 |
| 425 | default "25000000" # most people use this |
| 426 | default "27000000" if BFIN533_EZKIT |
| 427 | default "30000000" if BFIN561_EZKIT |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 428 | help |
| 429 | The frequency of CLKIN crystal oscillator on the board in Hz. |
Sonic Zhang | 2fb6cb4 | 2008-04-25 04:39:28 +0800 | [diff] [blame] | 430 | Warning: This value should match the crystal on the board. Otherwise, |
| 431 | peripherals won't work properly. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 432 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 433 | config BFIN_KERNEL_CLOCK |
| 434 | bool "Re-program Clocks while Kernel boots?" |
| 435 | default n |
| 436 | help |
| 437 | This option decides if kernel clocks are re-programed from the |
| 438 | bootloader settings. If the clocks are not set, the SDRAM settings |
| 439 | are also not changed, and the Bootloader does 100% of the hardware |
| 440 | configuration. |
| 441 | |
| 442 | config PLL_BYPASS |
Mike Frysinger | e4e9a7a | 2007-11-15 20:39:34 +0800 | [diff] [blame] | 443 | bool "Bypass PLL" |
| 444 | depends on BFIN_KERNEL_CLOCK |
| 445 | default n |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 446 | |
| 447 | config CLKIN_HALF |
| 448 | bool "Half Clock In" |
| 449 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 450 | default n |
| 451 | help |
| 452 | If this is set the clock will be divided by 2, before it goes to the PLL. |
| 453 | |
| 454 | config VCO_MULT |
| 455 | int "VCO Multiplier" |
| 456 | depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS) |
| 457 | range 1 64 |
| 458 | default "22" if BFIN533_EZKIT |
| 459 | default "45" if BFIN533_STAMP |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 460 | default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 461 | default "22" if BFIN533_BLUETECHNIX_CM |
Michael Hennerich | 9db144f | 2008-07-19 17:16:07 +0800 | [diff] [blame] | 462 | default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 463 | default "20" if BFIN561_EZKIT |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 464 | default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD) |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 465 | help |
| 466 | This controls the frequency of the on-chip PLL. This can be between 1 and 64. |
| 467 | PLL Frequency = (Crystal Frequency) * (this setting) |
| 468 | |
| 469 | choice |
| 470 | prompt "Core Clock Divider" |
| 471 | depends on BFIN_KERNEL_CLOCK |
| 472 | default CCLK_DIV_1 |
| 473 | help |
| 474 | This sets the frequency of the core. It can be 1, 2, 4 or 8 |
| 475 | Core Frequency = (PLL frequency) / (this setting) |
| 476 | |
| 477 | config CCLK_DIV_1 |
| 478 | bool "1" |
| 479 | |
| 480 | config CCLK_DIV_2 |
| 481 | bool "2" |
| 482 | |
| 483 | config CCLK_DIV_4 |
| 484 | bool "4" |
| 485 | |
| 486 | config CCLK_DIV_8 |
| 487 | bool "8" |
| 488 | endchoice |
| 489 | |
| 490 | config SCLK_DIV |
| 491 | int "System Clock Divider" |
| 492 | depends on BFIN_KERNEL_CLOCK |
| 493 | range 1 15 |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 494 | default 5 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 495 | help |
| 496 | This sets the frequency of the system clock (including SDRAM or DDR). |
| 497 | This can be between 1 and 15 |
| 498 | System Clock = (PLL frequency) / (this setting) |
| 499 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 500 | choice |
| 501 | prompt "DDR SDRAM Chip Type" |
| 502 | depends on BFIN_KERNEL_CLOCK |
| 503 | depends on BF54x |
| 504 | default MEM_MT46V32M16_5B |
| 505 | |
| 506 | config MEM_MT46V32M16_6T |
| 507 | bool "MT46V32M16_6T" |
| 508 | |
| 509 | config MEM_MT46V32M16_5B |
| 510 | bool "MT46V32M16_5B" |
| 511 | endchoice |
| 512 | |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 513 | choice |
| 514 | prompt "DDR/SDRAM Timing" |
| 515 | depends on BFIN_KERNEL_CLOCK |
| 516 | default BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 517 | help |
| 518 | This option allows you to specify Blackfin SDRAM/DDR Timing parameters |
| 519 | The calculated SDRAM timing parameters may not be 100% |
| 520 | accurate - This option is therefore marked experimental. |
| 521 | |
| 522 | config BFIN_KERNEL_CLOCK_MEMINIT_CALC |
| 523 | bool "Calculate Timings (EXPERIMENTAL)" |
| 524 | depends on EXPERIMENTAL |
| 525 | |
| 526 | config BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
| 527 | bool "Provide accurate Timings based on target SCLK" |
| 528 | help |
| 529 | Please consult the Blackfin Hardware Reference Manuals as well |
| 530 | as the memory device datasheet. |
| 531 | http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram |
| 532 | endchoice |
| 533 | |
| 534 | menu "Memory Init Control" |
| 535 | depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC |
| 536 | |
| 537 | config MEM_DDRCTL0 |
| 538 | depends on BF54x |
| 539 | hex "DDRCTL0" |
| 540 | default 0x0 |
| 541 | |
| 542 | config MEM_DDRCTL1 |
| 543 | depends on BF54x |
| 544 | hex "DDRCTL1" |
| 545 | default 0x0 |
| 546 | |
| 547 | config MEM_DDRCTL2 |
| 548 | depends on BF54x |
| 549 | hex "DDRCTL2" |
| 550 | default 0x0 |
| 551 | |
| 552 | config MEM_EBIU_DDRQUE |
| 553 | depends on BF54x |
| 554 | hex "DDRQUE" |
| 555 | default 0x0 |
| 556 | |
| 557 | config MEM_SDRRC |
| 558 | depends on !BF54x |
| 559 | hex "SDRRC" |
| 560 | default 0x0 |
| 561 | |
| 562 | config MEM_SDGCTL |
| 563 | depends on !BF54x |
| 564 | hex "SDGCTL" |
| 565 | default 0x0 |
| 566 | endmenu |
| 567 | |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 568 | # |
| 569 | # Max & Min Speeds for various Chips |
| 570 | # |
| 571 | config MAX_VCO_HZ |
| 572 | int |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 573 | default 400000000 if BF512 |
| 574 | default 400000000 if BF514 |
| 575 | default 400000000 if BF516 |
| 576 | default 400000000 if BF518 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 577 | default 600000000 if BF522 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 578 | default 400000000 if BF523 |
| 579 | default 400000000 if BF524 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 580 | default 600000000 if BF525 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 581 | default 400000000 if BF526 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 582 | default 600000000 if BF527 |
| 583 | default 400000000 if BF531 |
| 584 | default 400000000 if BF532 |
| 585 | default 750000000 if BF533 |
| 586 | default 500000000 if BF534 |
| 587 | default 400000000 if BF536 |
| 588 | default 600000000 if BF537 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 589 | default 533333333 if BF538 |
| 590 | default 533333333 if BF539 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 591 | default 600000000 if BF542 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 592 | default 533333333 if BF544 |
Mike Frysinger | 1545a11 | 2007-12-24 16:54:48 +0800 | [diff] [blame] | 593 | default 600000000 if BF547 |
| 594 | default 600000000 if BF548 |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 595 | default 533333333 if BF549 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 596 | default 600000000 if BF561 |
| 597 | |
| 598 | config MIN_VCO_HZ |
| 599 | int |
| 600 | default 50000000 |
| 601 | |
| 602 | config MAX_SCLK_HZ |
| 603 | int |
Robin Getz | f72eecb | 2007-11-21 16:29:20 +0800 | [diff] [blame] | 604 | default 133333333 |
Robin Getz | f16295e | 2007-08-03 18:07:17 +0800 | [diff] [blame] | 605 | |
| 606 | config MIN_SCLK_HZ |
| 607 | int |
| 608 | default 27000000 |
| 609 | |
| 610 | comment "Kernel Timer/Scheduler" |
| 611 | |
| 612 | source kernel/Kconfig.hz |
| 613 | |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 614 | config GENERIC_TIME |
| 615 | bool "Generic time" |
| 616 | default y |
| 617 | |
| 618 | config GENERIC_CLOCKEVENTS |
| 619 | bool "Generic clock events" |
| 620 | depends on GENERIC_TIME |
| 621 | default y |
| 622 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 623 | choice |
| 624 | prompt "Kernel Tick Source" |
| 625 | depends on GENERIC_CLOCKEVENTS |
| 626 | default TICKSOURCE_CORETMR |
| 627 | |
| 628 | config TICKSOURCE_GPTMR0 |
| 629 | bool "Gptimer0 (SCLK domain)" |
| 630 | select BFIN_GPTIMERS |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 631 | |
| 632 | config TICKSOURCE_CORETMR |
| 633 | bool "Core timer (CCLK domain)" |
| 634 | |
| 635 | endchoice |
| 636 | |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 637 | config CYCLES_CLOCKSOURCE |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 638 | bool "Use 'CYCLES' as a clocksource" |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 639 | depends on GENERIC_CLOCKEVENTS |
| 640 | depends on !BFIN_SCRATCH_REG_CYCLES |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 641 | depends on !SMP |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 642 | help |
| 643 | If you say Y here, you will enable support for using the 'cycles' |
| 644 | registers as a clock source. Doing so means you will be unable to |
| 645 | safely write to the 'cycles' register during runtime. You will |
| 646 | still be able to read it (such as for performance monitoring), but |
| 647 | writing the registers will most likely crash the kernel. |
| 648 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 649 | config GPTMR0_CLOCKSOURCE |
| 650 | bool "Use GPTimer0 as a clocksource (higher rating)" |
Mike Frysinger | 3aca47c | 2009-06-18 19:40:47 +0000 | [diff] [blame] | 651 | select BFIN_GPTIMERS |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 652 | depends on GENERIC_CLOCKEVENTS |
| 653 | depends on !TICKSOURCE_GPTMR0 |
| 654 | |
Vitja Makarov | 8b5f79f | 2008-02-29 12:24:23 +0800 | [diff] [blame] | 655 | source kernel/time/Kconfig |
| 656 | |
Mike Frysinger | 5f004c2 | 2008-04-25 02:11:24 +0800 | [diff] [blame] | 657 | comment "Misc" |
Sonic Zhang | 971d5bc | 2008-01-27 16:32:31 +0800 | [diff] [blame] | 658 | |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 659 | choice |
| 660 | prompt "Blackfin Exception Scratch Register" |
| 661 | default BFIN_SCRATCH_REG_RETN |
| 662 | help |
| 663 | Select the resource to reserve for the Exception handler: |
| 664 | - RETN: Non-Maskable Interrupt (NMI) |
| 665 | - RETE: Exception Return (JTAG/ICE) |
| 666 | - CYCLES: Performance counter |
| 667 | |
| 668 | If you are unsure, please select "RETN". |
| 669 | |
| 670 | config BFIN_SCRATCH_REG_RETN |
| 671 | bool "RETN" |
| 672 | help |
| 673 | Use the RETN register in the Blackfin exception handler |
| 674 | as a stack scratch register. This means you cannot |
| 675 | safely use NMI on the Blackfin while running Linux, but |
| 676 | you can debug the system with a JTAG ICE and use the |
| 677 | CYCLES performance registers. |
| 678 | |
| 679 | If you are unsure, please select "RETN". |
| 680 | |
| 681 | config BFIN_SCRATCH_REG_RETE |
| 682 | bool "RETE" |
| 683 | help |
| 684 | Use the RETE register in the Blackfin exception handler |
| 685 | as a stack scratch register. This means you cannot |
| 686 | safely use a JTAG ICE while debugging a Blackfin board, |
| 687 | but you can safely use the CYCLES performance registers |
| 688 | and the NMI. |
| 689 | |
| 690 | If you are unsure, please select "RETN". |
| 691 | |
| 692 | config BFIN_SCRATCH_REG_CYCLES |
| 693 | bool "CYCLES" |
| 694 | help |
| 695 | Use the CYCLES register in the Blackfin exception handler |
| 696 | as a stack scratch register. This means you cannot |
| 697 | safely use the CYCLES performance registers on a Blackfin |
| 698 | board at anytime, but you can debug the system with a JTAG |
| 699 | ICE and use the NMI. |
| 700 | |
| 701 | If you are unsure, please select "RETN". |
| 702 | |
| 703 | endchoice |
| 704 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 705 | endmenu |
| 706 | |
| 707 | |
| 708 | menu "Blackfin Kernel Optimizations" |
Graf Yang | 46fa5ee | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 709 | depends on !SMP |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 710 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 711 | comment "Memory Optimizations" |
| 712 | |
| 713 | config I_ENTRY_L1 |
| 714 | bool "Locate interrupt entry code in L1 Memory" |
| 715 | default y |
| 716 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 717 | If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked |
| 718 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 719 | |
| 720 | config EXCPT_IRQ_SYSC_L1 |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 721 | bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 722 | default y |
| 723 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 724 | If enabled, the entire ASM lowlevel exception and interrupt entry code |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 725 | (STORE/RESTORE CONTEXT) is linked into L1 instruction memory. |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 726 | (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 727 | |
| 728 | config DO_IRQ_L1 |
| 729 | bool "Locate frequently called do_irq dispatcher function in L1 Memory" |
| 730 | default y |
| 731 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 732 | If enabled, the frequently called do_irq dispatcher function is linked |
| 733 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 734 | |
| 735 | config CORE_TIMER_IRQ_L1 |
| 736 | bool "Locate frequently called timer_interrupt() function in L1 Memory" |
| 737 | default y |
| 738 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 739 | If enabled, the frequently called timer_interrupt() function is linked |
| 740 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 741 | |
| 742 | config IDLE_L1 |
| 743 | bool "Locate frequently idle function in L1 Memory" |
| 744 | default y |
| 745 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 746 | If enabled, the frequently called idle function is linked |
| 747 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 748 | |
| 749 | config SCHEDULE_L1 |
| 750 | bool "Locate kernel schedule function in L1 Memory" |
| 751 | default y |
| 752 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 753 | If enabled, the frequently called kernel schedule is linked |
| 754 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 755 | |
| 756 | config ARITHMETIC_OPS_L1 |
| 757 | bool "Locate kernel owned arithmetic functions in L1 Memory" |
| 758 | default y |
| 759 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 760 | If enabled, arithmetic functions are linked |
| 761 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 762 | |
| 763 | config ACCESS_OK_L1 |
| 764 | bool "Locate access_ok function in L1 Memory" |
| 765 | default y |
| 766 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 767 | If enabled, the access_ok function is linked |
| 768 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 769 | |
| 770 | config MEMSET_L1 |
| 771 | bool "Locate memset function in L1 Memory" |
| 772 | default y |
| 773 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 774 | If enabled, the memset function is linked |
| 775 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 776 | |
| 777 | config MEMCPY_L1 |
| 778 | bool "Locate memcpy function in L1 Memory" |
| 779 | default y |
| 780 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 781 | If enabled, the memcpy function is linked |
| 782 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 783 | |
| 784 | config SYS_BFIN_SPINLOCK_L1 |
| 785 | bool "Locate sys_bfin_spinlock function in L1 Memory" |
| 786 | default y |
| 787 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 788 | If enabled, sys_bfin_spinlock function is linked |
| 789 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 790 | |
| 791 | config IP_CHECKSUM_L1 |
| 792 | bool "Locate IP Checksum function in L1 Memory" |
| 793 | default n |
| 794 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 795 | If enabled, the IP Checksum function is linked |
| 796 | into L1 instruction memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 797 | |
| 798 | config CACHELINE_ALIGNED_L1 |
| 799 | bool "Locate cacheline_aligned data to L1 Data Memory" |
Michael Hennerich | 157cc5a | 2007-07-12 16:20:21 +0800 | [diff] [blame] | 800 | default y if !BF54x |
| 801 | default n if BF54x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 802 | depends on !BF531 |
| 803 | help |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 804 | If enabled, cacheline_aligned data is linked |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 805 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 806 | |
| 807 | config SYSCALL_TAB_L1 |
| 808 | bool "Locate Syscall Table L1 Data Memory" |
| 809 | default n |
| 810 | depends on !BF531 |
| 811 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 812 | If enabled, the Syscall LUT is linked |
| 813 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 814 | |
| 815 | config CPLB_SWITCH_TAB_L1 |
| 816 | bool "Locate CPLB Switch Tables L1 Data Memory" |
| 817 | default n |
| 818 | depends on !BF531 |
| 819 | help |
Matt LaPlante | 01dd2fb | 2007-10-20 01:34:40 +0200 | [diff] [blame] | 820 | If enabled, the CPLB Switch Tables are linked |
| 821 | into L1 data memory. (less latency) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 822 | |
Graf Yang | ca87b7a | 2008-10-08 17:30:01 +0800 | [diff] [blame] | 823 | config APP_STACK_L1 |
| 824 | bool "Support locating application stack in L1 Scratch Memory" |
| 825 | default y |
| 826 | help |
| 827 | If enabled the application stack can be located in L1 |
| 828 | scratch memory (less latency). |
| 829 | |
| 830 | Currently only works with FLAT binaries. |
| 831 | |
Mike Frysinger | 6ad2b84 | 2008-10-28 11:03:09 +0800 | [diff] [blame] | 832 | config EXCEPTION_L1_SCRATCH |
| 833 | bool "Locate exception stack in L1 Scratch Memory" |
| 834 | default n |
Graf Yang | f82e0a0 | 2009-04-08 08:30:22 +0000 | [diff] [blame] | 835 | depends on !APP_STACK_L1 |
Mike Frysinger | 6ad2b84 | 2008-10-28 11:03:09 +0800 | [diff] [blame] | 836 | help |
| 837 | Whenever an exception occurs, use the L1 Scratch memory for |
| 838 | stack storage. You cannot place the stacks of FLAT binaries |
| 839 | in L1 when using this option. |
| 840 | |
| 841 | If you don't use L1 Scratch, then you should say Y here. |
| 842 | |
Robin Getz | 251383c | 2008-08-14 15:12:55 +0800 | [diff] [blame] | 843 | comment "Speed Optimizations" |
| 844 | config BFIN_INS_LOWOVERHEAD |
| 845 | bool "ins[bwl] low overhead, higher interrupt latency" |
| 846 | default y |
| 847 | help |
| 848 | Reads on the Blackfin are speculative. In Blackfin terms, this means |
| 849 | they can be interrupted at any time (even after they have been issued |
| 850 | on to the external bus), and re-issued after the interrupt occurs. |
| 851 | For memory - this is not a big deal, since memory does not change if |
| 852 | it sees a read. |
| 853 | |
| 854 | If a FIFO is sitting on the end of the read, it will see two reads, |
| 855 | when the core only sees one since the FIFO receives both the read |
| 856 | which is cancelled (and not delivered to the core) and the one which |
| 857 | is re-issued (which is delivered to the core). |
| 858 | |
| 859 | To solve this, interrupts are turned off before reads occur to |
| 860 | I/O space. This option controls which the overhead/latency of |
| 861 | controlling interrupts during this time |
| 862 | "n" turns interrupts off every read |
| 863 | (higher overhead, but lower interrupt latency) |
| 864 | "y" turns interrupts off every loop |
| 865 | (low overhead, but longer interrupt latency) |
| 866 | |
| 867 | default behavior is to leave this set to on (type "Y"). If you are experiencing |
| 868 | interrupt latency issues, it is safe and OK to turn this off. |
| 869 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 870 | endmenu |
| 871 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 872 | choice |
| 873 | prompt "Kernel executes from" |
| 874 | help |
| 875 | Choose the memory type that the kernel will be running in. |
| 876 | |
| 877 | config RAMKERNEL |
| 878 | bool "RAM" |
| 879 | help |
| 880 | The kernel will be resident in RAM when running. |
| 881 | |
| 882 | config ROMKERNEL |
| 883 | bool "ROM" |
| 884 | help |
| 885 | The kernel will be resident in FLASH/ROM when running. |
| 886 | |
| 887 | endchoice |
| 888 | |
| 889 | source "mm/Kconfig" |
| 890 | |
Mike Frysinger | 780431e | 2007-10-21 23:37:54 +0800 | [diff] [blame] | 891 | config BFIN_GPTIMERS |
| 892 | tristate "Enable Blackfin General Purpose Timers API" |
| 893 | default n |
| 894 | help |
| 895 | Enable support for the General Purpose Timers API. If you |
| 896 | are unsure, say N. |
| 897 | |
| 898 | To compile this driver as a module, choose M here: the module |
Pavel Machek | 4737f09 | 2009-06-05 00:44:53 +0200 | [diff] [blame] | 899 | will be called gptimers. |
Mike Frysinger | 780431e | 2007-10-21 23:37:54 +0800 | [diff] [blame] | 900 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 901 | choice |
Mike Frysinger | d292b00 | 2008-10-28 11:15:36 +0800 | [diff] [blame] | 902 | prompt "Uncached DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 903 | default DMA_UNCACHED_1M |
Cliff Cai | 86ad793 | 2008-05-17 16:36:52 +0800 | [diff] [blame] | 904 | config DMA_UNCACHED_4M |
| 905 | bool "Enable 4M DMA region" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 906 | config DMA_UNCACHED_2M |
| 907 | bool "Enable 2M DMA region" |
| 908 | config DMA_UNCACHED_1M |
| 909 | bool "Enable 1M DMA region" |
| 910 | config DMA_UNCACHED_NONE |
| 911 | bool "Disable DMA region" |
| 912 | endchoice |
| 913 | |
| 914 | |
| 915 | comment "Cache Support" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 916 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 917 | config BFIN_ICACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 918 | bool "Enable ICACHE" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 919 | default y |
| 920 | config BFIN_ICACHE_LOCK |
| 921 | bool "Enable Instruction Cache Locking" |
| 922 | depends on BFIN_ICACHE |
| 923 | default n |
| 924 | config BFIN_EXTMEM_ICACHEABLE |
| 925 | bool "Enable ICACHE for external memory" |
| 926 | depends on BFIN_ICACHE |
| 927 | default y |
| 928 | config BFIN_L2_ICACHEABLE |
| 929 | bool "Enable ICACHE for L2 SRAM" |
| 930 | depends on BFIN_ICACHE |
| 931 | depends on BF54x || BF561 |
| 932 | default n |
| 933 | |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 934 | config BFIN_DCACHE |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 935 | bool "Enable DCACHE" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 936 | default y |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 937 | config BFIN_DCACHE_BANKA |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 938 | bool "Enable only 16k BankA DCACHE - BankB is SRAM" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 939 | depends on BFIN_DCACHE && !BF531 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 940 | default n |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 941 | config BFIN_EXTMEM_DCACHEABLE |
| 942 | bool "Enable DCACHE for external memory" |
Robin Getz | 3bebca2 | 2007-10-10 23:55:26 +0800 | [diff] [blame] | 943 | depends on BFIN_DCACHE |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 944 | default y |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 945 | choice |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 946 | prompt "External memory DCACHE policy" |
| 947 | depends on BFIN_EXTMEM_DCACHEABLE |
| 948 | default BFIN_EXTMEM_WRITEBACK if !SMP |
| 949 | default BFIN_EXTMEM_WRITETHROUGH if SMP |
| 950 | config BFIN_EXTMEM_WRITEBACK |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 951 | bool "Write back" |
| 952 | depends on !SMP |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 953 | help |
| 954 | Write Back Policy: |
| 955 | Cached data will be written back to SDRAM only when needed. |
| 956 | This can give a nice increase in performance, but beware of |
| 957 | broken drivers that do not properly invalidate/flush their |
| 958 | cache. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 959 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 960 | Write Through Policy: |
| 961 | Cached data will always be written back to SDRAM when the |
| 962 | cache is updated. This is a completely safe setting, but |
| 963 | performance is worse than Write Back. |
| 964 | |
| 965 | If you are unsure of the options and you want to be safe, |
| 966 | then go with Write Through. |
| 967 | |
| 968 | config BFIN_EXTMEM_WRITETHROUGH |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 969 | bool "Write through" |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 970 | help |
| 971 | Write Back Policy: |
| 972 | Cached data will be written back to SDRAM only when needed. |
| 973 | This can give a nice increase in performance, but beware of |
| 974 | broken drivers that do not properly invalidate/flush their |
| 975 | cache. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 976 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 977 | Write Through Policy: |
| 978 | Cached data will always be written back to SDRAM when the |
| 979 | cache is updated. This is a completely safe setting, but |
| 980 | performance is worse than Write Back. |
| 981 | |
| 982 | If you are unsure of the options and you want to be safe, |
| 983 | then go with Write Through. |
Graf Yang | 5ba7667 | 2009-05-07 04:09:15 +0000 | [diff] [blame] | 984 | |
| 985 | endchoice |
Sonic Zhang | f099f39 | 2008-10-09 14:11:57 +0800 | [diff] [blame] | 986 | |
Jie Zhang | 41ba653 | 2009-06-16 09:48:33 +0000 | [diff] [blame] | 987 | config BFIN_L2_DCACHEABLE |
| 988 | bool "Enable DCACHE for L2 SRAM" |
| 989 | depends on BFIN_DCACHE |
| 990 | depends on BF54x || BF561 |
| 991 | default n |
| 992 | choice |
| 993 | prompt "L2 SRAM DCACHE policy" |
| 994 | depends on BFIN_L2_DCACHEABLE |
| 995 | default BFIN_L2_WRITEBACK |
| 996 | config BFIN_L2_WRITEBACK |
| 997 | bool "Write back" |
| 998 | depends on !SMP |
| 999 | |
| 1000 | config BFIN_L2_WRITETHROUGH |
| 1001 | bool "Write through" |
| 1002 | depends on !SMP |
| 1003 | endchoice |
| 1004 | |
| 1005 | |
| 1006 | comment "Memory Protection Unit" |
Bernd Schmidt | b97b8a9 | 2008-01-27 18:39:16 +0800 | [diff] [blame] | 1007 | config MPU |
| 1008 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
| 1009 | default n |
| 1010 | help |
| 1011 | Use the processor's MPU to protect applications from accessing |
| 1012 | memory they do not own. This comes at a performance penalty |
| 1013 | and is recommended only for debugging. |
| 1014 | |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 1015 | comment "Asynchronous Memory Configuration" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1016 | |
Mike Frysinger | ddf416b | 2007-10-10 18:06:47 +0800 | [diff] [blame] | 1017 | menu "EBIU_AMGCTL Global Control" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1018 | config C_AMCKEN |
| 1019 | bool "Enable CLKOUT" |
| 1020 | default y |
| 1021 | |
| 1022 | config C_CDPRIO |
| 1023 | bool "DMA has priority over core for ext. accesses" |
| 1024 | default n |
| 1025 | |
| 1026 | config C_B0PEN |
| 1027 | depends on BF561 |
| 1028 | bool "Bank 0 16 bit packing enable" |
| 1029 | default y |
| 1030 | |
| 1031 | config C_B1PEN |
| 1032 | depends on BF561 |
| 1033 | bool "Bank 1 16 bit packing enable" |
| 1034 | default y |
| 1035 | |
| 1036 | config C_B2PEN |
| 1037 | depends on BF561 |
| 1038 | bool "Bank 2 16 bit packing enable" |
| 1039 | default y |
| 1040 | |
| 1041 | config C_B3PEN |
| 1042 | depends on BF561 |
| 1043 | bool "Bank 3 16 bit packing enable" |
| 1044 | default n |
| 1045 | |
| 1046 | choice |
Matt LaPlante | 692105b | 2009-01-26 11:12:25 +0100 | [diff] [blame] | 1047 | prompt "Enable Asynchronous Memory Banks" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1048 | default C_AMBEN_ALL |
| 1049 | |
| 1050 | config C_AMBEN |
| 1051 | bool "Disable All Banks" |
| 1052 | |
| 1053 | config C_AMBEN_B0 |
| 1054 | bool "Enable Bank 0" |
| 1055 | |
| 1056 | config C_AMBEN_B0_B1 |
| 1057 | bool "Enable Bank 0 & 1" |
| 1058 | |
| 1059 | config C_AMBEN_B0_B1_B2 |
| 1060 | bool "Enable Bank 0 & 1 & 2" |
| 1061 | |
| 1062 | config C_AMBEN_ALL |
| 1063 | bool "Enable All Banks" |
| 1064 | endchoice |
| 1065 | endmenu |
| 1066 | |
| 1067 | menu "EBIU_AMBCTL Control" |
| 1068 | config BANK_0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1069 | hex "Bank 0 (AMBCTL0.L)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1070 | default 0x7BB0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1071 | help |
| 1072 | These are the low 16 bits of the EBIU_AMBCTL0 MMR which are |
| 1073 | used to control the Asynchronous Memory Bank 0 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1074 | |
| 1075 | config BANK_1 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1076 | hex "Bank 1 (AMBCTL0.H)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1077 | default 0x7BB0 |
Michael Hennerich | 197fba5 | 2008-05-07 17:03:27 +0800 | [diff] [blame] | 1078 | default 0x5558 if BF54x |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1079 | help |
| 1080 | These are the high 16 bits of the EBIU_AMBCTL0 MMR which are |
| 1081 | used to control the Asynchronous Memory Bank 1 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1082 | |
| 1083 | config BANK_2 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1084 | hex "Bank 2 (AMBCTL1.L)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1085 | default 0x7BB0 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1086 | help |
| 1087 | These are the low 16 bits of the EBIU_AMBCTL1 MMR which are |
| 1088 | used to control the Asynchronous Memory Bank 2 settings. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1089 | |
| 1090 | config BANK_3 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1091 | hex "Bank 3 (AMBCTL1.H)" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1092 | default 0x99B3 |
Mike Frysinger | c8342f8 | 2009-03-31 00:18:35 +0000 | [diff] [blame] | 1093 | help |
| 1094 | These are the high 16 bits of the EBIU_AMBCTL1 MMR which are |
| 1095 | used to control the Asynchronous Memory Bank 3 settings. |
| 1096 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1097 | endmenu |
| 1098 | |
Sonic Zhang | e40540b | 2007-11-21 23:49:52 +0800 | [diff] [blame] | 1099 | config EBIU_MBSCTLVAL |
| 1100 | hex "EBIU Bank Select Control Register" |
| 1101 | depends on BF54x |
| 1102 | default 0 |
| 1103 | |
| 1104 | config EBIU_MODEVAL |
| 1105 | hex "Flash Memory Mode Control Register" |
| 1106 | depends on BF54x |
| 1107 | default 1 |
| 1108 | |
| 1109 | config EBIU_FCTLVAL |
| 1110 | hex "Flash Memory Bank Control Register" |
| 1111 | depends on BF54x |
| 1112 | default 6 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1113 | endmenu |
| 1114 | |
| 1115 | ############################################################################# |
| 1116 | menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)" |
| 1117 | |
| 1118 | config PCI |
| 1119 | bool "PCI support" |
Adrian Bunk | a95ca3b | 2008-08-27 10:55:05 +0800 | [diff] [blame] | 1120 | depends on BROKEN |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1121 | help |
| 1122 | Support for PCI bus. |
| 1123 | |
| 1124 | source "drivers/pci/Kconfig" |
| 1125 | |
| 1126 | config HOTPLUG |
| 1127 | bool "Support for hot-pluggable device" |
| 1128 | help |
| 1129 | Say Y here if you want to plug devices into your computer while |
| 1130 | the system is running, and be able to use them quickly. In many |
| 1131 | cases, the devices can likewise be unplugged at any time too. |
| 1132 | |
| 1133 | One well known example of this is PCMCIA- or PC-cards, credit-card |
| 1134 | size devices such as network cards, modems or hard drives which are |
| 1135 | plugged into slots found on all modern laptop computers. Another |
| 1136 | example, used on modern desktops as well as laptops, is USB. |
| 1137 | |
Johannes Berg | a81792f | 2008-07-08 19:00:25 +0200 | [diff] [blame] | 1138 | Enable HOTPLUG and build a modular kernel. Get agent software |
| 1139 | (from <http://linux-hotplug.sourceforge.net/>) and install it. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1140 | Then your kernel will automatically call out to a user mode "policy |
| 1141 | agent" (/sbin/hotplug) to load modules and set up software needed |
| 1142 | to use devices as you hotplug them. |
| 1143 | |
| 1144 | source "drivers/pcmcia/Kconfig" |
| 1145 | |
| 1146 | source "drivers/pci/hotplug/Kconfig" |
| 1147 | |
| 1148 | endmenu |
| 1149 | |
| 1150 | menu "Executable file formats" |
| 1151 | |
| 1152 | source "fs/Kconfig.binfmt" |
| 1153 | |
| 1154 | endmenu |
| 1155 | |
| 1156 | menu "Power management options" |
| 1157 | source "kernel/power/Kconfig" |
| 1158 | |
Johannes Berg | f4cb570 | 2007-12-08 02:14:00 +0100 | [diff] [blame] | 1159 | config ARCH_SUSPEND_POSSIBLE |
| 1160 | def_bool y |
| 1161 | depends on !SMP |
| 1162 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1163 | choice |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1164 | prompt "Standby Power Saving Mode" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1165 | depends on PM |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1166 | default PM_BFIN_SLEEP_DEEPER |
| 1167 | config PM_BFIN_SLEEP_DEEPER |
| 1168 | bool "Sleep Deeper" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1169 | help |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1170 | Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic |
| 1171 | power dissipation by disabling the clock to the processor core (CCLK). |
| 1172 | Furthermore, Standby sets the internal power supply voltage (VDDINT) |
| 1173 | to 0.85 V to provide the greatest power savings, while preserving the |
| 1174 | processor state. |
| 1175 | The PLL and system clock (SCLK) continue to operate at a very low |
| 1176 | frequency of about 3.3 MHz. To preserve data integrity in the SDRAM, |
| 1177 | the SDRAM is put into Self Refresh Mode. Typically an external event |
| 1178 | such as GPIO interrupt or RTC activity wakes up the processor. |
| 1179 | Various Peripherals such as UART, SPORT, PPI may not function as |
| 1180 | normal during Sleep Deeper, due to the reduced SCLK frequency. |
| 1181 | When in the sleep mode, system DMA access to L1 memory is not supported. |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1182 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1183 | If unsure, select "Sleep Deeper". |
| 1184 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1185 | config PM_BFIN_SLEEP |
| 1186 | bool "Sleep" |
| 1187 | help |
| 1188 | Sleep Mode (High Power Savings) - The sleep mode reduces power |
| 1189 | dissipation by disabling the clock to the processor core (CCLK). |
| 1190 | The PLL and system clock (SCLK), however, continue to operate in |
| 1191 | this mode. Typically an external event or RTC activity will wake |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1192 | up the processor. When in the sleep mode, system DMA access to L1 |
| 1193 | memory is not supported. |
| 1194 | |
| 1195 | If unsure, select "Sleep Deeper". |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1196 | endchoice |
| 1197 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1198 | config PM_WAKEUP_BY_GPIO |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1199 | bool "Allow Wakeup from Standby by GPIO" |
Michael Hennerich | ff19fed | 2009-03-04 17:35:51 +0800 | [diff] [blame] | 1200 | depends on PM && !BF54x |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1201 | |
| 1202 | config PM_WAKEUP_GPIO_NUMBER |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1203 | int "GPIO number" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1204 | range 0 47 |
| 1205 | depends on PM_WAKEUP_BY_GPIO |
Mike Frysinger | d1a3336 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1206 | default 2 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1207 | |
| 1208 | choice |
| 1209 | prompt "GPIO Polarity" |
| 1210 | depends on PM_WAKEUP_BY_GPIO |
| 1211 | default PM_WAKEUP_GPIO_POLAR_H |
| 1212 | config PM_WAKEUP_GPIO_POLAR_H |
| 1213 | bool "Active High" |
| 1214 | config PM_WAKEUP_GPIO_POLAR_L |
| 1215 | bool "Active Low" |
| 1216 | config PM_WAKEUP_GPIO_POLAR_EDGE_F |
| 1217 | bool "Falling EDGE" |
| 1218 | config PM_WAKEUP_GPIO_POLAR_EDGE_R |
| 1219 | bool "Rising EDGE" |
| 1220 | config PM_WAKEUP_GPIO_POLAR_EDGE_B |
| 1221 | bool "Both EDGE" |
| 1222 | endchoice |
| 1223 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1224 | comment "Possible Suspend Mem / Hibernate Wake-Up Sources" |
| 1225 | depends on PM |
| 1226 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1227 | config PM_BFIN_WAKE_PH6 |
| 1228 | bool "Allow Wake-Up from on-chip PHY or PH6 GP" |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1229 | depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537) |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1230 | default n |
| 1231 | help |
| 1232 | Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up) |
| 1233 | |
Michael Hennerich | 1efc80b | 2008-07-19 16:57:32 +0800 | [diff] [blame] | 1234 | config PM_BFIN_WAKE_GP |
| 1235 | bool "Allow Wake-Up from GPIOs" |
| 1236 | depends on PM && BF54x |
| 1237 | default n |
| 1238 | help |
| 1239 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) |
Michael Hennerich | 1998628 | 2009-03-05 16:45:55 +0800 | [diff] [blame] | 1240 | (all processors, except ADSP-BF549). This option sets |
| 1241 | the general-purpose wake-up enable (GPWE) control bit to enable |
| 1242 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. |
| 1243 | On ADSP-BF549 this option enables the the same functionality on the |
| 1244 | /MRXON pin also PH7. |
| 1245 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1246 | endmenu |
| 1247 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1248 | menu "CPU Frequency scaling" |
| 1249 | |
| 1250 | source "drivers/cpufreq/Kconfig" |
| 1251 | |
Michael Hennerich | 5ad2ca5 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1252 | config BFIN_CPU_FREQ |
| 1253 | bool |
| 1254 | depends on CPU_FREQ |
| 1255 | select CPU_FREQ_TABLE |
| 1256 | default y |
| 1257 | |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1258 | config CPU_VOLTAGE |
| 1259 | bool "CPU Voltage scaling" |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1260 | depends on EXPERIMENTAL |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1261 | depends on CPU_FREQ |
| 1262 | default n |
| 1263 | help |
| 1264 | Say Y here if you want CPU voltage scaling according to the CPU frequency. |
| 1265 | This option violates the PLL BYPASS recommendation in the Blackfin Processor |
Michael Hennerich | 73feb5c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1266 | manuals. There is a theoretical risk that during VDDINT transitions |
Michael Hennerich | 14b0320 | 2008-05-07 11:41:26 +0800 | [diff] [blame] | 1267 | the PLL may unlock. |
| 1268 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1269 | endmenu |
| 1270 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1271 | source "net/Kconfig" |
| 1272 | |
| 1273 | source "drivers/Kconfig" |
| 1274 | |
| 1275 | source "fs/Kconfig" |
| 1276 | |
Mike Frysinger | 74ce832 | 2007-11-21 23:50:49 +0800 | [diff] [blame] | 1277 | source "arch/blackfin/Kconfig.debug" |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1278 | |
| 1279 | source "security/Kconfig" |
| 1280 | |
| 1281 | source "crypto/Kconfig" |
| 1282 | |
| 1283 | source "lib/Kconfig" |