Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1 | /* |
| 2 | |
| 3 | Broadcom B43 wireless driver |
| 4 | |
| 5 | DMA ringbuffer and descriptor allocation/management |
| 6 | |
| 7 | Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de> |
| 8 | |
| 9 | Some code in this file is derived from the b44.c driver |
| 10 | Copyright (C) 2002 David S. Miller |
| 11 | Copyright (C) Pekka Pietikainen |
| 12 | |
| 13 | This program is free software; you can redistribute it and/or modify |
| 14 | it under the terms of the GNU General Public License as published by |
| 15 | the Free Software Foundation; either version 2 of the License, or |
| 16 | (at your option) any later version. |
| 17 | |
| 18 | This program is distributed in the hope that it will be useful, |
| 19 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | GNU General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; see the file COPYING. If not, write to |
| 25 | the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, |
| 26 | Boston, MA 02110-1301, USA. |
| 27 | |
| 28 | */ |
| 29 | |
| 30 | #include "b43.h" |
| 31 | #include "dma.h" |
| 32 | #include "main.h" |
| 33 | #include "debugfs.h" |
| 34 | #include "xmit.h" |
| 35 | |
| 36 | #include <linux/dma-mapping.h> |
| 37 | #include <linux/pci.h> |
| 38 | #include <linux/delay.h> |
| 39 | #include <linux/skbuff.h> |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 40 | #include <linux/etherdevice.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 41 | #include <linux/slab.h> |
Michael Buesch | 57df40d | 2008-03-07 15:50:02 +0100 | [diff] [blame] | 42 | #include <asm/div64.h> |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 43 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 44 | |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 45 | /* Required number of TX DMA slots per TX frame. |
| 46 | * This currently is 2, because we put the header and the ieee80211 frame |
| 47 | * into separate slots. */ |
| 48 | #define TX_SLOTS_PER_FRAME 2 |
| 49 | |
| 50 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 51 | /* 32bit DMA ops. */ |
| 52 | static |
| 53 | struct b43_dmadesc_generic *op32_idx2desc(struct b43_dmaring *ring, |
| 54 | int slot, |
| 55 | struct b43_dmadesc_meta **meta) |
| 56 | { |
| 57 | struct b43_dmadesc32 *desc; |
| 58 | |
| 59 | *meta = &(ring->meta[slot]); |
| 60 | desc = ring->descbase; |
| 61 | desc = &(desc[slot]); |
| 62 | |
| 63 | return (struct b43_dmadesc_generic *)desc; |
| 64 | } |
| 65 | |
| 66 | static void op32_fill_descriptor(struct b43_dmaring *ring, |
| 67 | struct b43_dmadesc_generic *desc, |
| 68 | dma_addr_t dmaaddr, u16 bufsize, |
| 69 | int start, int end, int irq) |
| 70 | { |
| 71 | struct b43_dmadesc32 *descbase = ring->descbase; |
| 72 | int slot; |
| 73 | u32 ctl; |
| 74 | u32 addr; |
| 75 | u32 addrext; |
| 76 | |
| 77 | slot = (int)(&(desc->dma32) - descbase); |
| 78 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); |
| 79 | |
| 80 | addr = (u32) (dmaaddr & ~SSB_DMA_TRANSLATION_MASK); |
| 81 | addrext = (u32) (dmaaddr & SSB_DMA_TRANSLATION_MASK) |
| 82 | >> SSB_DMA_TRANSLATION_SHIFT; |
| 83 | addr |= ssb_dma_translation(ring->dev->dev); |
Michael Buesch | 8eccb53 | 2009-02-19 23:39:26 +0100 | [diff] [blame] | 84 | ctl = bufsize & B43_DMA32_DCTL_BYTECNT; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 85 | if (slot == ring->nr_slots - 1) |
| 86 | ctl |= B43_DMA32_DCTL_DTABLEEND; |
| 87 | if (start) |
| 88 | ctl |= B43_DMA32_DCTL_FRAMESTART; |
| 89 | if (end) |
| 90 | ctl |= B43_DMA32_DCTL_FRAMEEND; |
| 91 | if (irq) |
| 92 | ctl |= B43_DMA32_DCTL_IRQ; |
| 93 | ctl |= (addrext << B43_DMA32_DCTL_ADDREXT_SHIFT) |
| 94 | & B43_DMA32_DCTL_ADDREXT_MASK; |
| 95 | |
| 96 | desc->dma32.control = cpu_to_le32(ctl); |
| 97 | desc->dma32.address = cpu_to_le32(addr); |
| 98 | } |
| 99 | |
| 100 | static void op32_poke_tx(struct b43_dmaring *ring, int slot) |
| 101 | { |
| 102 | b43_dma_write(ring, B43_DMA32_TXINDEX, |
| 103 | (u32) (slot * sizeof(struct b43_dmadesc32))); |
| 104 | } |
| 105 | |
| 106 | static void op32_tx_suspend(struct b43_dmaring *ring) |
| 107 | { |
| 108 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) |
| 109 | | B43_DMA32_TXSUSPEND); |
| 110 | } |
| 111 | |
| 112 | static void op32_tx_resume(struct b43_dmaring *ring) |
| 113 | { |
| 114 | b43_dma_write(ring, B43_DMA32_TXCTL, b43_dma_read(ring, B43_DMA32_TXCTL) |
| 115 | & ~B43_DMA32_TXSUSPEND); |
| 116 | } |
| 117 | |
| 118 | static int op32_get_current_rxslot(struct b43_dmaring *ring) |
| 119 | { |
| 120 | u32 val; |
| 121 | |
| 122 | val = b43_dma_read(ring, B43_DMA32_RXSTATUS); |
| 123 | val &= B43_DMA32_RXDPTR; |
| 124 | |
| 125 | return (val / sizeof(struct b43_dmadesc32)); |
| 126 | } |
| 127 | |
| 128 | static void op32_set_current_rxslot(struct b43_dmaring *ring, int slot) |
| 129 | { |
| 130 | b43_dma_write(ring, B43_DMA32_RXINDEX, |
| 131 | (u32) (slot * sizeof(struct b43_dmadesc32))); |
| 132 | } |
| 133 | |
| 134 | static const struct b43_dma_ops dma32_ops = { |
| 135 | .idx2desc = op32_idx2desc, |
| 136 | .fill_descriptor = op32_fill_descriptor, |
| 137 | .poke_tx = op32_poke_tx, |
| 138 | .tx_suspend = op32_tx_suspend, |
| 139 | .tx_resume = op32_tx_resume, |
| 140 | .get_current_rxslot = op32_get_current_rxslot, |
| 141 | .set_current_rxslot = op32_set_current_rxslot, |
| 142 | }; |
| 143 | |
| 144 | /* 64bit DMA ops. */ |
| 145 | static |
| 146 | struct b43_dmadesc_generic *op64_idx2desc(struct b43_dmaring *ring, |
| 147 | int slot, |
| 148 | struct b43_dmadesc_meta **meta) |
| 149 | { |
| 150 | struct b43_dmadesc64 *desc; |
| 151 | |
| 152 | *meta = &(ring->meta[slot]); |
| 153 | desc = ring->descbase; |
| 154 | desc = &(desc[slot]); |
| 155 | |
| 156 | return (struct b43_dmadesc_generic *)desc; |
| 157 | } |
| 158 | |
| 159 | static void op64_fill_descriptor(struct b43_dmaring *ring, |
| 160 | struct b43_dmadesc_generic *desc, |
| 161 | dma_addr_t dmaaddr, u16 bufsize, |
| 162 | int start, int end, int irq) |
| 163 | { |
| 164 | struct b43_dmadesc64 *descbase = ring->descbase; |
| 165 | int slot; |
| 166 | u32 ctl0 = 0, ctl1 = 0; |
| 167 | u32 addrlo, addrhi; |
| 168 | u32 addrext; |
| 169 | |
| 170 | slot = (int)(&(desc->dma64) - descbase); |
| 171 | B43_WARN_ON(!(slot >= 0 && slot < ring->nr_slots)); |
| 172 | |
| 173 | addrlo = (u32) (dmaaddr & 0xFFFFFFFF); |
| 174 | addrhi = (((u64) dmaaddr >> 32) & ~SSB_DMA_TRANSLATION_MASK); |
| 175 | addrext = (((u64) dmaaddr >> 32) & SSB_DMA_TRANSLATION_MASK) |
| 176 | >> SSB_DMA_TRANSLATION_SHIFT; |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 177 | addrhi |= (ssb_dma_translation(ring->dev->dev) << 1); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 178 | if (slot == ring->nr_slots - 1) |
| 179 | ctl0 |= B43_DMA64_DCTL0_DTABLEEND; |
| 180 | if (start) |
| 181 | ctl0 |= B43_DMA64_DCTL0_FRAMESTART; |
| 182 | if (end) |
| 183 | ctl0 |= B43_DMA64_DCTL0_FRAMEEND; |
| 184 | if (irq) |
| 185 | ctl0 |= B43_DMA64_DCTL0_IRQ; |
Michael Buesch | 8eccb53 | 2009-02-19 23:39:26 +0100 | [diff] [blame] | 186 | ctl1 |= bufsize & B43_DMA64_DCTL1_BYTECNT; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 187 | ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) |
| 188 | & B43_DMA64_DCTL1_ADDREXT_MASK; |
| 189 | |
| 190 | desc->dma64.control0 = cpu_to_le32(ctl0); |
| 191 | desc->dma64.control1 = cpu_to_le32(ctl1); |
| 192 | desc->dma64.address_low = cpu_to_le32(addrlo); |
| 193 | desc->dma64.address_high = cpu_to_le32(addrhi); |
| 194 | } |
| 195 | |
| 196 | static void op64_poke_tx(struct b43_dmaring *ring, int slot) |
| 197 | { |
| 198 | b43_dma_write(ring, B43_DMA64_TXINDEX, |
| 199 | (u32) (slot * sizeof(struct b43_dmadesc64))); |
| 200 | } |
| 201 | |
| 202 | static void op64_tx_suspend(struct b43_dmaring *ring) |
| 203 | { |
| 204 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) |
| 205 | | B43_DMA64_TXSUSPEND); |
| 206 | } |
| 207 | |
| 208 | static void op64_tx_resume(struct b43_dmaring *ring) |
| 209 | { |
| 210 | b43_dma_write(ring, B43_DMA64_TXCTL, b43_dma_read(ring, B43_DMA64_TXCTL) |
| 211 | & ~B43_DMA64_TXSUSPEND); |
| 212 | } |
| 213 | |
| 214 | static int op64_get_current_rxslot(struct b43_dmaring *ring) |
| 215 | { |
| 216 | u32 val; |
| 217 | |
| 218 | val = b43_dma_read(ring, B43_DMA64_RXSTATUS); |
| 219 | val &= B43_DMA64_RXSTATDPTR; |
| 220 | |
| 221 | return (val / sizeof(struct b43_dmadesc64)); |
| 222 | } |
| 223 | |
| 224 | static void op64_set_current_rxslot(struct b43_dmaring *ring, int slot) |
| 225 | { |
| 226 | b43_dma_write(ring, B43_DMA64_RXINDEX, |
| 227 | (u32) (slot * sizeof(struct b43_dmadesc64))); |
| 228 | } |
| 229 | |
| 230 | static const struct b43_dma_ops dma64_ops = { |
| 231 | .idx2desc = op64_idx2desc, |
| 232 | .fill_descriptor = op64_fill_descriptor, |
| 233 | .poke_tx = op64_poke_tx, |
| 234 | .tx_suspend = op64_tx_suspend, |
| 235 | .tx_resume = op64_tx_resume, |
| 236 | .get_current_rxslot = op64_get_current_rxslot, |
| 237 | .set_current_rxslot = op64_set_current_rxslot, |
| 238 | }; |
| 239 | |
| 240 | static inline int free_slots(struct b43_dmaring *ring) |
| 241 | { |
| 242 | return (ring->nr_slots - ring->used_slots); |
| 243 | } |
| 244 | |
| 245 | static inline int next_slot(struct b43_dmaring *ring, int slot) |
| 246 | { |
| 247 | B43_WARN_ON(!(slot >= -1 && slot <= ring->nr_slots - 1)); |
| 248 | if (slot == ring->nr_slots - 1) |
| 249 | return 0; |
| 250 | return slot + 1; |
| 251 | } |
| 252 | |
| 253 | static inline int prev_slot(struct b43_dmaring *ring, int slot) |
| 254 | { |
| 255 | B43_WARN_ON(!(slot >= 0 && slot <= ring->nr_slots - 1)); |
| 256 | if (slot == 0) |
| 257 | return ring->nr_slots - 1; |
| 258 | return slot - 1; |
| 259 | } |
| 260 | |
| 261 | #ifdef CONFIG_B43_DEBUG |
| 262 | static void update_max_used_slots(struct b43_dmaring *ring, |
| 263 | int current_used_slots) |
| 264 | { |
| 265 | if (current_used_slots <= ring->max_used_slots) |
| 266 | return; |
| 267 | ring->max_used_slots = current_used_slots; |
| 268 | if (b43_debug(ring->dev, B43_DBG_DMAVERBOSE)) { |
| 269 | b43dbg(ring->dev->wl, |
| 270 | "max_used_slots increased to %d on %s ring %d\n", |
| 271 | ring->max_used_slots, |
| 272 | ring->tx ? "TX" : "RX", ring->index); |
| 273 | } |
| 274 | } |
| 275 | #else |
| 276 | static inline |
| 277 | void update_max_used_slots(struct b43_dmaring *ring, int current_used_slots) |
| 278 | { |
| 279 | } |
| 280 | #endif /* DEBUG */ |
| 281 | |
| 282 | /* Request a slot for usage. */ |
| 283 | static inline int request_slot(struct b43_dmaring *ring) |
| 284 | { |
| 285 | int slot; |
| 286 | |
| 287 | B43_WARN_ON(!ring->tx); |
| 288 | B43_WARN_ON(ring->stopped); |
| 289 | B43_WARN_ON(free_slots(ring) == 0); |
| 290 | |
| 291 | slot = next_slot(ring, ring->current_slot); |
| 292 | ring->current_slot = slot; |
| 293 | ring->used_slots++; |
| 294 | |
| 295 | update_max_used_slots(ring, ring->used_slots); |
| 296 | |
| 297 | return slot; |
| 298 | } |
| 299 | |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 300 | static u16 b43_dmacontroller_base(enum b43_dmatype type, int controller_idx) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 301 | { |
| 302 | static const u16 map64[] = { |
| 303 | B43_MMIO_DMA64_BASE0, |
| 304 | B43_MMIO_DMA64_BASE1, |
| 305 | B43_MMIO_DMA64_BASE2, |
| 306 | B43_MMIO_DMA64_BASE3, |
| 307 | B43_MMIO_DMA64_BASE4, |
| 308 | B43_MMIO_DMA64_BASE5, |
| 309 | }; |
| 310 | static const u16 map32[] = { |
| 311 | B43_MMIO_DMA32_BASE0, |
| 312 | B43_MMIO_DMA32_BASE1, |
| 313 | B43_MMIO_DMA32_BASE2, |
| 314 | B43_MMIO_DMA32_BASE3, |
| 315 | B43_MMIO_DMA32_BASE4, |
| 316 | B43_MMIO_DMA32_BASE5, |
| 317 | }; |
| 318 | |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 319 | if (type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 320 | B43_WARN_ON(!(controller_idx >= 0 && |
| 321 | controller_idx < ARRAY_SIZE(map64))); |
| 322 | return map64[controller_idx]; |
| 323 | } |
| 324 | B43_WARN_ON(!(controller_idx >= 0 && |
| 325 | controller_idx < ARRAY_SIZE(map32))); |
| 326 | return map32[controller_idx]; |
| 327 | } |
| 328 | |
| 329 | static inline |
| 330 | dma_addr_t map_descbuffer(struct b43_dmaring *ring, |
| 331 | unsigned char *buf, size_t len, int tx) |
| 332 | { |
| 333 | dma_addr_t dmaaddr; |
| 334 | |
| 335 | if (tx) { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 336 | dmaaddr = dma_map_single(ring->dev->dev->dma_dev, |
| 337 | buf, len, DMA_TO_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 338 | } else { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 339 | dmaaddr = dma_map_single(ring->dev->dev->dma_dev, |
| 340 | buf, len, DMA_FROM_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | return dmaaddr; |
| 344 | } |
| 345 | |
| 346 | static inline |
| 347 | void unmap_descbuffer(struct b43_dmaring *ring, |
| 348 | dma_addr_t addr, size_t len, int tx) |
| 349 | { |
| 350 | if (tx) { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 351 | dma_unmap_single(ring->dev->dev->dma_dev, |
| 352 | addr, len, DMA_TO_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 353 | } else { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 354 | dma_unmap_single(ring->dev->dev->dma_dev, |
| 355 | addr, len, DMA_FROM_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 356 | } |
| 357 | } |
| 358 | |
| 359 | static inline |
| 360 | void sync_descbuffer_for_cpu(struct b43_dmaring *ring, |
| 361 | dma_addr_t addr, size_t len) |
| 362 | { |
| 363 | B43_WARN_ON(ring->tx); |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 364 | dma_sync_single_for_cpu(ring->dev->dev->dma_dev, |
Michael Buesch | f225763 | 2008-06-20 11:50:29 +0200 | [diff] [blame] | 365 | addr, len, DMA_FROM_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 366 | } |
| 367 | |
| 368 | static inline |
| 369 | void sync_descbuffer_for_device(struct b43_dmaring *ring, |
| 370 | dma_addr_t addr, size_t len) |
| 371 | { |
| 372 | B43_WARN_ON(ring->tx); |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 373 | dma_sync_single_for_device(ring->dev->dev->dma_dev, |
| 374 | addr, len, DMA_FROM_DEVICE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | static inline |
| 378 | void free_descriptor_buffer(struct b43_dmaring *ring, |
| 379 | struct b43_dmadesc_meta *meta) |
| 380 | { |
| 381 | if (meta->skb) { |
| 382 | dev_kfree_skb_any(meta->skb); |
| 383 | meta->skb = NULL; |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | static int alloc_ringmemory(struct b43_dmaring *ring) |
| 388 | { |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 389 | gfp_t flags = GFP_KERNEL; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 390 | |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 391 | /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K |
| 392 | * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing |
| 393 | * has shown that 4K is sufficient for the latter as long as the buffer |
| 394 | * does not cross an 8K boundary. |
| 395 | * |
| 396 | * For unknown reasons - possibly a hardware error - the BCM4311 rev |
| 397 | * 02, which uses 64-bit DMA, needs the ring buffer in very low memory, |
| 398 | * which accounts for the GFP_DMA flag below. |
| 399 | * |
| 400 | * The flags here must match the flags in free_ringmemory below! |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 401 | */ |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 402 | if (ring->type == B43_DMA_64BIT) |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 403 | flags |= GFP_DMA; |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 404 | ring->descbase = dma_alloc_coherent(ring->dev->dev->dma_dev, |
| 405 | B43_DMA_RINGMEMSIZE, |
| 406 | &(ring->dmabase), flags); |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 407 | if (!ring->descbase) { |
| 408 | b43err(ring->dev->wl, "DMA ringmemory allocation failed\n"); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 409 | return -ENOMEM; |
| 410 | } |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 411 | memset(ring->descbase, 0, B43_DMA_RINGMEMSIZE); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 412 | |
| 413 | return 0; |
| 414 | } |
| 415 | |
| 416 | static void free_ringmemory(struct b43_dmaring *ring) |
| 417 | { |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 418 | gfp_t flags = GFP_KERNEL; |
| 419 | |
| 420 | if (ring->type == B43_DMA_64BIT) |
| 421 | flags |= GFP_DMA; |
| 422 | |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 423 | dma_free_coherent(ring->dev->dev->dma_dev, B43_DMA_RINGMEMSIZE, |
| 424 | ring->descbase, ring->dmabase); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 425 | } |
| 426 | |
| 427 | /* Reset the RX DMA channel */ |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 428 | static int b43_dmacontroller_rx_reset(struct b43_wldev *dev, u16 mmio_base, |
| 429 | enum b43_dmatype type) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 430 | { |
| 431 | int i; |
| 432 | u32 value; |
| 433 | u16 offset; |
| 434 | |
| 435 | might_sleep(); |
| 436 | |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 437 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXCTL : B43_DMA32_RXCTL; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 438 | b43_write32(dev, mmio_base + offset, 0); |
| 439 | for (i = 0; i < 10; i++) { |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 440 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_RXSTATUS : |
| 441 | B43_DMA32_RXSTATUS; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 442 | value = b43_read32(dev, mmio_base + offset); |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 443 | if (type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 444 | value &= B43_DMA64_RXSTAT; |
| 445 | if (value == B43_DMA64_RXSTAT_DISABLED) { |
| 446 | i = -1; |
| 447 | break; |
| 448 | } |
| 449 | } else { |
| 450 | value &= B43_DMA32_RXSTATE; |
| 451 | if (value == B43_DMA32_RXSTAT_DISABLED) { |
| 452 | i = -1; |
| 453 | break; |
| 454 | } |
| 455 | } |
| 456 | msleep(1); |
| 457 | } |
| 458 | if (i != -1) { |
| 459 | b43err(dev->wl, "DMA RX reset timed out\n"); |
| 460 | return -ENODEV; |
| 461 | } |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 466 | /* Reset the TX DMA channel */ |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 467 | static int b43_dmacontroller_tx_reset(struct b43_wldev *dev, u16 mmio_base, |
| 468 | enum b43_dmatype type) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 469 | { |
| 470 | int i; |
| 471 | u32 value; |
| 472 | u16 offset; |
| 473 | |
| 474 | might_sleep(); |
| 475 | |
| 476 | for (i = 0; i < 10; i++) { |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 477 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
| 478 | B43_DMA32_TXSTATUS; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 479 | value = b43_read32(dev, mmio_base + offset); |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 480 | if (type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 481 | value &= B43_DMA64_TXSTAT; |
| 482 | if (value == B43_DMA64_TXSTAT_DISABLED || |
| 483 | value == B43_DMA64_TXSTAT_IDLEWAIT || |
| 484 | value == B43_DMA64_TXSTAT_STOPPED) |
| 485 | break; |
| 486 | } else { |
| 487 | value &= B43_DMA32_TXSTATE; |
| 488 | if (value == B43_DMA32_TXSTAT_DISABLED || |
| 489 | value == B43_DMA32_TXSTAT_IDLEWAIT || |
| 490 | value == B43_DMA32_TXSTAT_STOPPED) |
| 491 | break; |
| 492 | } |
| 493 | msleep(1); |
| 494 | } |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 495 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXCTL : B43_DMA32_TXCTL; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 496 | b43_write32(dev, mmio_base + offset, 0); |
| 497 | for (i = 0; i < 10; i++) { |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 498 | offset = (type == B43_DMA_64BIT) ? B43_DMA64_TXSTATUS : |
| 499 | B43_DMA32_TXSTATUS; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 500 | value = b43_read32(dev, mmio_base + offset); |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 501 | if (type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 502 | value &= B43_DMA64_TXSTAT; |
| 503 | if (value == B43_DMA64_TXSTAT_DISABLED) { |
| 504 | i = -1; |
| 505 | break; |
| 506 | } |
| 507 | } else { |
| 508 | value &= B43_DMA32_TXSTATE; |
| 509 | if (value == B43_DMA32_TXSTAT_DISABLED) { |
| 510 | i = -1; |
| 511 | break; |
| 512 | } |
| 513 | } |
| 514 | msleep(1); |
| 515 | } |
| 516 | if (i != -1) { |
| 517 | b43err(dev->wl, "DMA TX reset timed out\n"); |
| 518 | return -ENODEV; |
| 519 | } |
| 520 | /* ensure the reset is completed. */ |
| 521 | msleep(1); |
| 522 | |
| 523 | return 0; |
| 524 | } |
| 525 | |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 526 | /* Check if a DMA mapping address is invalid. */ |
| 527 | static bool b43_dma_mapping_error(struct b43_dmaring *ring, |
| 528 | dma_addr_t addr, |
Michael Buesch | ffa9256 | 2008-03-22 22:04:45 +0100 | [diff] [blame] | 529 | size_t buffersize, bool dma_to_device) |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 530 | { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 531 | if (unlikely(dma_mapping_error(ring->dev->dev->dma_dev, addr))) |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 532 | return 1; |
| 533 | |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 534 | switch (ring->type) { |
| 535 | case B43_DMA_30BIT: |
| 536 | if ((u64)addr + buffersize > (1ULL << 30)) |
| 537 | goto address_error; |
| 538 | break; |
| 539 | case B43_DMA_32BIT: |
| 540 | if ((u64)addr + buffersize > (1ULL << 32)) |
| 541 | goto address_error; |
| 542 | break; |
| 543 | case B43_DMA_64BIT: |
| 544 | /* Currently we can't have addresses beyond |
| 545 | * 64bit in the kernel. */ |
| 546 | break; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | /* The address is OK. */ |
| 550 | return 0; |
John W. Linville | 55afc80 | 2009-12-29 14:07:42 -0500 | [diff] [blame] | 551 | |
| 552 | address_error: |
| 553 | /* We can't support this address. Unmap it again. */ |
| 554 | unmap_descbuffer(ring, addr, buffersize, dma_to_device); |
| 555 | |
| 556 | return 1; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 557 | } |
| 558 | |
Michael Buesch | ec9a1d8 | 2009-03-27 22:51:58 +0100 | [diff] [blame] | 559 | static bool b43_rx_buffer_is_poisoned(struct b43_dmaring *ring, struct sk_buff *skb) |
| 560 | { |
| 561 | unsigned char *f = skb->data + ring->frameoffset; |
| 562 | |
| 563 | return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xFF); |
| 564 | } |
| 565 | |
| 566 | static void b43_poison_rx_buffer(struct b43_dmaring *ring, struct sk_buff *skb) |
| 567 | { |
| 568 | struct b43_rxhdr_fw4 *rxhdr; |
| 569 | unsigned char *frame; |
| 570 | |
| 571 | /* This poisons the RX buffer to detect DMA failures. */ |
| 572 | |
| 573 | rxhdr = (struct b43_rxhdr_fw4 *)(skb->data); |
| 574 | rxhdr->frame_len = 0; |
| 575 | |
| 576 | B43_WARN_ON(ring->rx_buffersize < ring->frameoffset + sizeof(struct b43_plcp_hdr6) + 2); |
| 577 | frame = skb->data + ring->frameoffset; |
| 578 | memset(frame, 0xFF, sizeof(struct b43_plcp_hdr6) + 2 /* padding */); |
| 579 | } |
| 580 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 581 | static int setup_rx_descbuffer(struct b43_dmaring *ring, |
| 582 | struct b43_dmadesc_generic *desc, |
| 583 | struct b43_dmadesc_meta *meta, gfp_t gfp_flags) |
| 584 | { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 585 | dma_addr_t dmaaddr; |
| 586 | struct sk_buff *skb; |
| 587 | |
| 588 | B43_WARN_ON(ring->tx); |
| 589 | |
| 590 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); |
| 591 | if (unlikely(!skb)) |
| 592 | return -ENOMEM; |
Michael Buesch | ec9a1d8 | 2009-03-27 22:51:58 +0100 | [diff] [blame] | 593 | b43_poison_rx_buffer(ring, skb); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 594 | dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0); |
Michael Buesch | ffa9256 | 2008-03-22 22:04:45 +0100 | [diff] [blame] | 595 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 596 | /* ugh. try to realloc in zone_dma */ |
| 597 | gfp_flags |= GFP_DMA; |
| 598 | |
| 599 | dev_kfree_skb_any(skb); |
| 600 | |
| 601 | skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags); |
| 602 | if (unlikely(!skb)) |
| 603 | return -ENOMEM; |
Michael Buesch | ec9a1d8 | 2009-03-27 22:51:58 +0100 | [diff] [blame] | 604 | b43_poison_rx_buffer(ring, skb); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 605 | dmaaddr = map_descbuffer(ring, skb->data, |
| 606 | ring->rx_buffersize, 0); |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 607 | if (b43_dma_mapping_error(ring, dmaaddr, ring->rx_buffersize, 0)) { |
| 608 | b43err(ring->dev->wl, "RX DMA buffer allocation failed\n"); |
| 609 | dev_kfree_skb_any(skb); |
| 610 | return -EIO; |
| 611 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | meta->skb = skb; |
| 615 | meta->dmaaddr = dmaaddr; |
| 616 | ring->ops->fill_descriptor(ring, desc, dmaaddr, |
| 617 | ring->rx_buffersize, 0, 0, 0); |
| 618 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | /* Allocate the initial descbuffers. |
| 623 | * This is used for an RX ring only. |
| 624 | */ |
| 625 | static int alloc_initial_descbuffers(struct b43_dmaring *ring) |
| 626 | { |
| 627 | int i, err = -ENOMEM; |
| 628 | struct b43_dmadesc_generic *desc; |
| 629 | struct b43_dmadesc_meta *meta; |
| 630 | |
| 631 | for (i = 0; i < ring->nr_slots; i++) { |
| 632 | desc = ring->ops->idx2desc(ring, i, &meta); |
| 633 | |
| 634 | err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL); |
| 635 | if (err) { |
| 636 | b43err(ring->dev->wl, |
| 637 | "Failed to allocate initial descbuffers\n"); |
| 638 | goto err_unwind; |
| 639 | } |
| 640 | } |
| 641 | mb(); |
| 642 | ring->used_slots = ring->nr_slots; |
| 643 | err = 0; |
| 644 | out: |
| 645 | return err; |
| 646 | |
| 647 | err_unwind: |
| 648 | for (i--; i >= 0; i--) { |
| 649 | desc = ring->ops->idx2desc(ring, i, &meta); |
| 650 | |
| 651 | unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0); |
| 652 | dev_kfree_skb(meta->skb); |
| 653 | } |
| 654 | goto out; |
| 655 | } |
| 656 | |
| 657 | /* Do initial setup of the DMA controller. |
| 658 | * Reset the controller, write the ring busaddress |
| 659 | * and switch the "enable" bit on. |
| 660 | */ |
| 661 | static int dmacontroller_setup(struct b43_dmaring *ring) |
| 662 | { |
| 663 | int err = 0; |
| 664 | u32 value; |
| 665 | u32 addrext; |
| 666 | u32 trans = ssb_dma_translation(ring->dev->dev); |
| 667 | |
| 668 | if (ring->tx) { |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 669 | if (ring->type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 670 | u64 ringbase = (u64) (ring->dmabase); |
| 671 | |
| 672 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) |
| 673 | >> SSB_DMA_TRANSLATION_SHIFT; |
| 674 | value = B43_DMA64_TXENABLE; |
| 675 | value |= (addrext << B43_DMA64_TXADDREXT_SHIFT) |
| 676 | & B43_DMA64_TXADDREXT_MASK; |
| 677 | b43_dma_write(ring, B43_DMA64_TXCTL, value); |
| 678 | b43_dma_write(ring, B43_DMA64_TXRINGLO, |
| 679 | (ringbase & 0xFFFFFFFF)); |
| 680 | b43_dma_write(ring, B43_DMA64_TXRINGHI, |
| 681 | ((ringbase >> 32) & |
| 682 | ~SSB_DMA_TRANSLATION_MASK) |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 683 | | (trans << 1)); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 684 | } else { |
| 685 | u32 ringbase = (u32) (ring->dmabase); |
| 686 | |
| 687 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) |
| 688 | >> SSB_DMA_TRANSLATION_SHIFT; |
| 689 | value = B43_DMA32_TXENABLE; |
| 690 | value |= (addrext << B43_DMA32_TXADDREXT_SHIFT) |
| 691 | & B43_DMA32_TXADDREXT_MASK; |
| 692 | b43_dma_write(ring, B43_DMA32_TXCTL, value); |
| 693 | b43_dma_write(ring, B43_DMA32_TXRING, |
| 694 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) |
| 695 | | trans); |
| 696 | } |
| 697 | } else { |
| 698 | err = alloc_initial_descbuffers(ring); |
| 699 | if (err) |
| 700 | goto out; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 701 | if (ring->type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 702 | u64 ringbase = (u64) (ring->dmabase); |
| 703 | |
| 704 | addrext = ((ringbase >> 32) & SSB_DMA_TRANSLATION_MASK) |
| 705 | >> SSB_DMA_TRANSLATION_SHIFT; |
| 706 | value = (ring->frameoffset << B43_DMA64_RXFROFF_SHIFT); |
| 707 | value |= B43_DMA64_RXENABLE; |
| 708 | value |= (addrext << B43_DMA64_RXADDREXT_SHIFT) |
| 709 | & B43_DMA64_RXADDREXT_MASK; |
| 710 | b43_dma_write(ring, B43_DMA64_RXCTL, value); |
| 711 | b43_dma_write(ring, B43_DMA64_RXRINGLO, |
| 712 | (ringbase & 0xFFFFFFFF)); |
| 713 | b43_dma_write(ring, B43_DMA64_RXRINGHI, |
| 714 | ((ringbase >> 32) & |
| 715 | ~SSB_DMA_TRANSLATION_MASK) |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 716 | | (trans << 1)); |
| 717 | b43_dma_write(ring, B43_DMA64_RXINDEX, ring->nr_slots * |
| 718 | sizeof(struct b43_dmadesc64)); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 719 | } else { |
| 720 | u32 ringbase = (u32) (ring->dmabase); |
| 721 | |
| 722 | addrext = (ringbase & SSB_DMA_TRANSLATION_MASK) |
| 723 | >> SSB_DMA_TRANSLATION_SHIFT; |
| 724 | value = (ring->frameoffset << B43_DMA32_RXFROFF_SHIFT); |
| 725 | value |= B43_DMA32_RXENABLE; |
| 726 | value |= (addrext << B43_DMA32_RXADDREXT_SHIFT) |
| 727 | & B43_DMA32_RXADDREXT_MASK; |
| 728 | b43_dma_write(ring, B43_DMA32_RXCTL, value); |
| 729 | b43_dma_write(ring, B43_DMA32_RXRING, |
| 730 | (ringbase & ~SSB_DMA_TRANSLATION_MASK) |
| 731 | | trans); |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 732 | b43_dma_write(ring, B43_DMA32_RXINDEX, ring->nr_slots * |
| 733 | sizeof(struct b43_dmadesc32)); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 734 | } |
| 735 | } |
| 736 | |
Larry Finger | 013978b | 2007-11-26 10:29:47 -0600 | [diff] [blame] | 737 | out: |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 738 | return err; |
| 739 | } |
| 740 | |
| 741 | /* Shutdown the DMA controller. */ |
| 742 | static void dmacontroller_cleanup(struct b43_dmaring *ring) |
| 743 | { |
| 744 | if (ring->tx) { |
| 745 | b43_dmacontroller_tx_reset(ring->dev, ring->mmio_base, |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 746 | ring->type); |
| 747 | if (ring->type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 748 | b43_dma_write(ring, B43_DMA64_TXRINGLO, 0); |
| 749 | b43_dma_write(ring, B43_DMA64_TXRINGHI, 0); |
| 750 | } else |
| 751 | b43_dma_write(ring, B43_DMA32_TXRING, 0); |
| 752 | } else { |
| 753 | b43_dmacontroller_rx_reset(ring->dev, ring->mmio_base, |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 754 | ring->type); |
| 755 | if (ring->type == B43_DMA_64BIT) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 756 | b43_dma_write(ring, B43_DMA64_RXRINGLO, 0); |
| 757 | b43_dma_write(ring, B43_DMA64_RXRINGHI, 0); |
| 758 | } else |
| 759 | b43_dma_write(ring, B43_DMA32_RXRING, 0); |
| 760 | } |
| 761 | } |
| 762 | |
| 763 | static void free_all_descbuffers(struct b43_dmaring *ring) |
| 764 | { |
| 765 | struct b43_dmadesc_generic *desc; |
| 766 | struct b43_dmadesc_meta *meta; |
| 767 | int i; |
| 768 | |
| 769 | if (!ring->used_slots) |
| 770 | return; |
| 771 | for (i = 0; i < ring->nr_slots; i++) { |
| 772 | desc = ring->ops->idx2desc(ring, i, &meta); |
| 773 | |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 774 | if (!meta->skb || b43_dma_ptr_is_poisoned(meta->skb)) { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 775 | B43_WARN_ON(!ring->tx); |
| 776 | continue; |
| 777 | } |
| 778 | if (ring->tx) { |
| 779 | unmap_descbuffer(ring, meta->dmaaddr, |
| 780 | meta->skb->len, 1); |
| 781 | } else { |
| 782 | unmap_descbuffer(ring, meta->dmaaddr, |
| 783 | ring->rx_buffersize, 0); |
| 784 | } |
| 785 | free_descriptor_buffer(ring, meta); |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | static u64 supported_dma_mask(struct b43_wldev *dev) |
| 790 | { |
| 791 | u32 tmp; |
| 792 | u16 mmio_base; |
| 793 | |
| 794 | tmp = b43_read32(dev, SSB_TMSHIGH); |
| 795 | if (tmp & SSB_TMSHIGH_DMA64) |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 796 | return DMA_BIT_MASK(64); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 797 | mmio_base = b43_dmacontroller_base(0, 0); |
| 798 | b43_write32(dev, mmio_base + B43_DMA32_TXCTL, B43_DMA32_TXADDREXT_MASK); |
| 799 | tmp = b43_read32(dev, mmio_base + B43_DMA32_TXCTL); |
| 800 | if (tmp & B43_DMA32_TXADDREXT_MASK) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 801 | return DMA_BIT_MASK(32); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 802 | |
Yang Hongyang | 28b7679 | 2009-04-06 19:01:17 -0700 | [diff] [blame] | 803 | return DMA_BIT_MASK(30); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 804 | } |
| 805 | |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 806 | static enum b43_dmatype dma_mask_to_engine_type(u64 dmamask) |
| 807 | { |
Yang Hongyang | 28b7679 | 2009-04-06 19:01:17 -0700 | [diff] [blame] | 808 | if (dmamask == DMA_BIT_MASK(30)) |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 809 | return B43_DMA_30BIT; |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 810 | if (dmamask == DMA_BIT_MASK(32)) |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 811 | return B43_DMA_32BIT; |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 812 | if (dmamask == DMA_BIT_MASK(64)) |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 813 | return B43_DMA_64BIT; |
| 814 | B43_WARN_ON(1); |
| 815 | return B43_DMA_30BIT; |
| 816 | } |
| 817 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 818 | /* Main initialization function. */ |
| 819 | static |
| 820 | struct b43_dmaring *b43_setup_dmaring(struct b43_wldev *dev, |
| 821 | int controller_index, |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 822 | int for_tx, |
| 823 | enum b43_dmatype type) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 824 | { |
| 825 | struct b43_dmaring *ring; |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 826 | int i, err; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 827 | dma_addr_t dma_test; |
| 828 | |
| 829 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
| 830 | if (!ring) |
| 831 | goto out; |
| 832 | |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 833 | ring->nr_slots = B43_RXRING_SLOTS; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 834 | if (for_tx) |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 835 | ring->nr_slots = B43_TXRING_SLOTS; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 836 | |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 837 | ring->meta = kcalloc(ring->nr_slots, sizeof(struct b43_dmadesc_meta), |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 838 | GFP_KERNEL); |
| 839 | if (!ring->meta) |
| 840 | goto err_kfree_ring; |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 841 | for (i = 0; i < ring->nr_slots; i++) |
| 842 | ring->meta->skb = B43_DMA_PTR_POISON; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 843 | |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 844 | ring->type = type; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 845 | ring->dev = dev; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 846 | ring->mmio_base = b43_dmacontroller_base(type, controller_index); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 847 | ring->index = controller_index; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 848 | if (type == B43_DMA_64BIT) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 849 | ring->ops = &dma64_ops; |
| 850 | else |
| 851 | ring->ops = &dma32_ops; |
| 852 | if (for_tx) { |
| 853 | ring->tx = 1; |
| 854 | ring->current_slot = -1; |
| 855 | } else { |
| 856 | if (ring->index == 0) { |
| 857 | ring->rx_buffersize = B43_DMA0_RX_BUFFERSIZE; |
| 858 | ring->frameoffset = B43_DMA0_RX_FRAMEOFFSET; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 859 | } else |
| 860 | B43_WARN_ON(1); |
| 861 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 862 | #ifdef CONFIG_B43_DEBUG |
| 863 | ring->last_injected_overflow = jiffies; |
| 864 | #endif |
| 865 | |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 866 | if (for_tx) { |
Michael Buesch | 2d071ca | 2009-02-20 12:24:52 +0100 | [diff] [blame] | 867 | /* Assumption: B43_TXRING_SLOTS can be divided by TX_SLOTS_PER_FRAME */ |
| 868 | BUILD_BUG_ON(B43_TXRING_SLOTS % TX_SLOTS_PER_FRAME != 0); |
| 869 | |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 870 | ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME, |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 871 | b43_txhdr_size(dev), |
| 872 | GFP_KERNEL); |
| 873 | if (!ring->txhdr_cache) |
| 874 | goto err_kfree_meta; |
| 875 | |
| 876 | /* test for ability to dma to txhdr_cache */ |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 877 | dma_test = dma_map_single(dev->dev->dma_dev, |
| 878 | ring->txhdr_cache, |
| 879 | b43_txhdr_size(dev), |
| 880 | DMA_TO_DEVICE); |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 881 | |
| 882 | if (b43_dma_mapping_error(ring, dma_test, |
| 883 | b43_txhdr_size(dev), 1)) { |
| 884 | /* ugh realloc */ |
| 885 | kfree(ring->txhdr_cache); |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 886 | ring->txhdr_cache = kcalloc(ring->nr_slots / TX_SLOTS_PER_FRAME, |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 887 | b43_txhdr_size(dev), |
| 888 | GFP_KERNEL | GFP_DMA); |
| 889 | if (!ring->txhdr_cache) |
| 890 | goto err_kfree_meta; |
| 891 | |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 892 | dma_test = dma_map_single(dev->dev->dma_dev, |
| 893 | ring->txhdr_cache, |
| 894 | b43_txhdr_size(dev), |
| 895 | DMA_TO_DEVICE); |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 896 | |
| 897 | if (b43_dma_mapping_error(ring, dma_test, |
| 898 | b43_txhdr_size(dev), 1)) { |
| 899 | |
| 900 | b43err(dev->wl, |
| 901 | "TXHDR DMA allocation failed\n"); |
| 902 | goto err_kfree_txhdr_cache; |
| 903 | } |
| 904 | } |
| 905 | |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 906 | dma_unmap_single(dev->dev->dma_dev, |
| 907 | dma_test, b43_txhdr_size(dev), |
| 908 | DMA_TO_DEVICE); |
Michael Buesch | 028118a | 2008-06-12 11:58:56 +0200 | [diff] [blame] | 909 | } |
| 910 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 911 | err = alloc_ringmemory(ring); |
| 912 | if (err) |
| 913 | goto err_kfree_txhdr_cache; |
| 914 | err = dmacontroller_setup(ring); |
| 915 | if (err) |
| 916 | goto err_free_ringmemory; |
| 917 | |
| 918 | out: |
| 919 | return ring; |
| 920 | |
| 921 | err_free_ringmemory: |
| 922 | free_ringmemory(ring); |
| 923 | err_kfree_txhdr_cache: |
| 924 | kfree(ring->txhdr_cache); |
| 925 | err_kfree_meta: |
| 926 | kfree(ring->meta); |
| 927 | err_kfree_ring: |
| 928 | kfree(ring); |
| 929 | ring = NULL; |
| 930 | goto out; |
| 931 | } |
| 932 | |
Michael Buesch | 57df40d | 2008-03-07 15:50:02 +0100 | [diff] [blame] | 933 | #define divide(a, b) ({ \ |
| 934 | typeof(a) __a = a; \ |
| 935 | do_div(__a, b); \ |
| 936 | __a; \ |
| 937 | }) |
| 938 | |
| 939 | #define modulo(a, b) ({ \ |
| 940 | typeof(a) __a = a; \ |
| 941 | do_div(__a, b); \ |
| 942 | }) |
| 943 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 944 | /* Main cleanup function. */ |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 945 | static void b43_destroy_dmaring(struct b43_dmaring *ring, |
| 946 | const char *ringname) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 947 | { |
| 948 | if (!ring) |
| 949 | return; |
| 950 | |
Michael Buesch | 57df40d | 2008-03-07 15:50:02 +0100 | [diff] [blame] | 951 | #ifdef CONFIG_B43_DEBUG |
| 952 | { |
| 953 | /* Print some statistics. */ |
| 954 | u64 failed_packets = ring->nr_failed_tx_packets; |
| 955 | u64 succeed_packets = ring->nr_succeed_tx_packets; |
| 956 | u64 nr_packets = failed_packets + succeed_packets; |
| 957 | u64 permille_failed = 0, average_tries = 0; |
| 958 | |
| 959 | if (nr_packets) |
| 960 | permille_failed = divide(failed_packets * 1000, nr_packets); |
| 961 | if (nr_packets) |
| 962 | average_tries = divide(ring->nr_total_packet_tries * 100, nr_packets); |
| 963 | |
| 964 | b43dbg(ring->dev->wl, "DMA-%u %s: " |
| 965 | "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, " |
| 966 | "Average tries %llu.%02llu\n", |
| 967 | (unsigned int)(ring->type), ringname, |
| 968 | ring->max_used_slots, |
| 969 | ring->nr_slots, |
| 970 | (unsigned long long)failed_packets, |
Michael Buesch | 87d9611 | 2008-03-07 19:52:24 +0100 | [diff] [blame] | 971 | (unsigned long long)nr_packets, |
Michael Buesch | 57df40d | 2008-03-07 15:50:02 +0100 | [diff] [blame] | 972 | (unsigned long long)divide(permille_failed, 10), |
| 973 | (unsigned long long)modulo(permille_failed, 10), |
| 974 | (unsigned long long)divide(average_tries, 100), |
| 975 | (unsigned long long)modulo(average_tries, 100)); |
| 976 | } |
| 977 | #endif /* DEBUG */ |
| 978 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 979 | /* Device IRQs are disabled prior entering this function, |
| 980 | * so no need to take care of concurrency with rx handler stuff. |
| 981 | */ |
| 982 | dmacontroller_cleanup(ring); |
| 983 | free_all_descbuffers(ring); |
| 984 | free_ringmemory(ring); |
| 985 | |
| 986 | kfree(ring->txhdr_cache); |
| 987 | kfree(ring->meta); |
| 988 | kfree(ring); |
| 989 | } |
| 990 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 991 | #define destroy_ring(dma, ring) do { \ |
| 992 | b43_destroy_dmaring((dma)->ring, __stringify(ring)); \ |
| 993 | (dma)->ring = NULL; \ |
| 994 | } while (0) |
| 995 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 996 | void b43_dma_free(struct b43_wldev *dev) |
| 997 | { |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 998 | struct b43_dma *dma; |
| 999 | |
| 1000 | if (b43_using_pio_transfers(dev)) |
| 1001 | return; |
| 1002 | dma = &dev->dma; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1003 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1004 | destroy_ring(dma, rx_ring); |
| 1005 | destroy_ring(dma, tx_ring_AC_BK); |
| 1006 | destroy_ring(dma, tx_ring_AC_BE); |
| 1007 | destroy_ring(dma, tx_ring_AC_VI); |
| 1008 | destroy_ring(dma, tx_ring_AC_VO); |
| 1009 | destroy_ring(dma, tx_ring_mcast); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1010 | } |
| 1011 | |
Michael Buesch | 1033b3e | 2008-04-23 19:13:01 +0200 | [diff] [blame] | 1012 | static int b43_dma_set_mask(struct b43_wldev *dev, u64 mask) |
| 1013 | { |
| 1014 | u64 orig_mask = mask; |
| 1015 | bool fallback = 0; |
| 1016 | int err; |
| 1017 | |
| 1018 | /* Try to set the DMA mask. If it fails, try falling back to a |
| 1019 | * lower mask, as we can always also support a lower one. */ |
| 1020 | while (1) { |
FUJITA Tomonori | 718e889 | 2010-06-03 19:37:36 -0700 | [diff] [blame] | 1021 | err = dma_set_mask(dev->dev->dma_dev, mask); |
| 1022 | if (!err) { |
| 1023 | err = dma_set_coherent_mask(dev->dev->dma_dev, mask); |
| 1024 | if (!err) |
| 1025 | break; |
| 1026 | } |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 1027 | if (mask == DMA_BIT_MASK(64)) { |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 1028 | mask = DMA_BIT_MASK(32); |
Michael Buesch | 1033b3e | 2008-04-23 19:13:01 +0200 | [diff] [blame] | 1029 | fallback = 1; |
| 1030 | continue; |
| 1031 | } |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 1032 | if (mask == DMA_BIT_MASK(32)) { |
Yang Hongyang | 28b7679 | 2009-04-06 19:01:17 -0700 | [diff] [blame] | 1033 | mask = DMA_BIT_MASK(30); |
Michael Buesch | 1033b3e | 2008-04-23 19:13:01 +0200 | [diff] [blame] | 1034 | fallback = 1; |
| 1035 | continue; |
| 1036 | } |
| 1037 | b43err(dev->wl, "The machine/kernel does not support " |
| 1038 | "the required %u-bit DMA mask\n", |
| 1039 | (unsigned int)dma_mask_to_engine_type(orig_mask)); |
| 1040 | return -EOPNOTSUPP; |
| 1041 | } |
| 1042 | if (fallback) { |
| 1043 | b43info(dev->wl, "DMA mask fallback from %u-bit to %u-bit\n", |
| 1044 | (unsigned int)dma_mask_to_engine_type(orig_mask), |
| 1045 | (unsigned int)dma_mask_to_engine_type(mask)); |
| 1046 | } |
| 1047 | |
| 1048 | return 0; |
| 1049 | } |
| 1050 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1051 | int b43_dma_init(struct b43_wldev *dev) |
| 1052 | { |
| 1053 | struct b43_dma *dma = &dev->dma; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1054 | int err; |
| 1055 | u64 dmamask; |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 1056 | enum b43_dmatype type; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1057 | |
| 1058 | dmamask = supported_dma_mask(dev); |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 1059 | type = dma_mask_to_engine_type(dmamask); |
Michael Buesch | 1033b3e | 2008-04-23 19:13:01 +0200 | [diff] [blame] | 1060 | err = b43_dma_set_mask(dev, dmamask); |
| 1061 | if (err) |
| 1062 | return err; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1063 | |
| 1064 | err = -ENOMEM; |
| 1065 | /* setup TX DMA channels. */ |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1066 | dma->tx_ring_AC_BK = b43_setup_dmaring(dev, 0, 1, type); |
| 1067 | if (!dma->tx_ring_AC_BK) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1068 | goto out; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1069 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1070 | dma->tx_ring_AC_BE = b43_setup_dmaring(dev, 1, 1, type); |
| 1071 | if (!dma->tx_ring_AC_BE) |
| 1072 | goto err_destroy_bk; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1073 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1074 | dma->tx_ring_AC_VI = b43_setup_dmaring(dev, 2, 1, type); |
| 1075 | if (!dma->tx_ring_AC_VI) |
| 1076 | goto err_destroy_be; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1077 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1078 | dma->tx_ring_AC_VO = b43_setup_dmaring(dev, 3, 1, type); |
| 1079 | if (!dma->tx_ring_AC_VO) |
| 1080 | goto err_destroy_vi; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1081 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1082 | dma->tx_ring_mcast = b43_setup_dmaring(dev, 4, 1, type); |
| 1083 | if (!dma->tx_ring_mcast) |
| 1084 | goto err_destroy_vo; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1085 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1086 | /* setup RX DMA channel. */ |
| 1087 | dma->rx_ring = b43_setup_dmaring(dev, 0, 0, type); |
| 1088 | if (!dma->rx_ring) |
| 1089 | goto err_destroy_mcast; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1090 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1091 | /* No support for the TX status DMA ring. */ |
| 1092 | B43_WARN_ON(dev->dev->id.revision < 5); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1093 | |
Michael Buesch | b79caa6 | 2008-02-05 12:50:41 +0100 | [diff] [blame] | 1094 | b43dbg(dev->wl, "%u-bit DMA initialized\n", |
| 1095 | (unsigned int)type); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1096 | err = 0; |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1097 | out: |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1098 | return err; |
| 1099 | |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1100 | err_destroy_mcast: |
| 1101 | destroy_ring(dma, tx_ring_mcast); |
| 1102 | err_destroy_vo: |
| 1103 | destroy_ring(dma, tx_ring_AC_VO); |
| 1104 | err_destroy_vi: |
| 1105 | destroy_ring(dma, tx_ring_AC_VI); |
| 1106 | err_destroy_be: |
| 1107 | destroy_ring(dma, tx_ring_AC_BE); |
| 1108 | err_destroy_bk: |
| 1109 | destroy_ring(dma, tx_ring_AC_BK); |
| 1110 | return err; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | /* Generate a cookie for the TX header. */ |
| 1114 | static u16 generate_cookie(struct b43_dmaring *ring, int slot) |
| 1115 | { |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1116 | u16 cookie; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1117 | |
| 1118 | /* Use the upper 4 bits of the cookie as |
| 1119 | * DMA controller ID and store the slot number |
| 1120 | * in the lower 12 bits. |
| 1121 | * Note that the cookie must never be 0, as this |
| 1122 | * is a special value used in RX path. |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1123 | * It can also not be 0xFFFF because that is special |
| 1124 | * for multicast frames. |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1125 | */ |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1126 | cookie = (((u16)ring->index + 1) << 12); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1127 | B43_WARN_ON(slot & ~0x0FFF); |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1128 | cookie |= (u16)slot; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1129 | |
| 1130 | return cookie; |
| 1131 | } |
| 1132 | |
| 1133 | /* Inspect a cookie and find out to which controller/slot it belongs. */ |
| 1134 | static |
| 1135 | struct b43_dmaring *parse_cookie(struct b43_wldev *dev, u16 cookie, int *slot) |
| 1136 | { |
| 1137 | struct b43_dma *dma = &dev->dma; |
| 1138 | struct b43_dmaring *ring = NULL; |
| 1139 | |
| 1140 | switch (cookie & 0xF000) { |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1141 | case 0x1000: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1142 | ring = dma->tx_ring_AC_BK; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1143 | break; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1144 | case 0x2000: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1145 | ring = dma->tx_ring_AC_BE; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1146 | break; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1147 | case 0x3000: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1148 | ring = dma->tx_ring_AC_VI; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1149 | break; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1150 | case 0x4000: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1151 | ring = dma->tx_ring_AC_VO; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1152 | break; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1153 | case 0x5000: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1154 | ring = dma->tx_ring_mcast; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1155 | break; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1156 | } |
| 1157 | *slot = (cookie & 0x0FFF); |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1158 | if (unlikely(!ring || *slot < 0 || *slot >= ring->nr_slots)) { |
| 1159 | b43dbg(dev->wl, "TX-status contains " |
| 1160 | "invalid cookie: 0x%04X\n", cookie); |
| 1161 | return NULL; |
| 1162 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1163 | |
| 1164 | return ring; |
| 1165 | } |
| 1166 | |
| 1167 | static int dma_tx_fragment(struct b43_dmaring *ring, |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1168 | struct sk_buff *skb) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1169 | { |
| 1170 | const struct b43_dma_ops *ops = ring->ops; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1171 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1172 | struct b43_private_tx_info *priv_info = b43_get_priv_tx_info(info); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1173 | u8 *header; |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1174 | int slot, old_top_slot, old_used_slots; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1175 | int err; |
| 1176 | struct b43_dmadesc_generic *desc; |
| 1177 | struct b43_dmadesc_meta *meta; |
| 1178 | struct b43_dmadesc_meta *meta_hdr; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1179 | u16 cookie; |
Michael Buesch | eb189d8b | 2008-01-28 14:47:41 -0800 | [diff] [blame] | 1180 | size_t hdrsize = b43_txhdr_size(ring->dev); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1181 | |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 1182 | /* Important note: If the number of used DMA slots per TX frame |
| 1183 | * is changed here, the TX_SLOTS_PER_FRAME definition at the top of |
| 1184 | * the file has to be updated, too! |
| 1185 | */ |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1186 | |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1187 | old_top_slot = ring->current_slot; |
| 1188 | old_used_slots = ring->used_slots; |
| 1189 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1190 | /* Get a slot for the header. */ |
| 1191 | slot = request_slot(ring); |
| 1192 | desc = ops->idx2desc(ring, slot, &meta_hdr); |
| 1193 | memset(meta_hdr, 0, sizeof(*meta_hdr)); |
| 1194 | |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 1195 | header = &(ring->txhdr_cache[(slot / TX_SLOTS_PER_FRAME) * hdrsize]); |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1196 | cookie = generate_cookie(ring, slot); |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1197 | err = b43_generate_txhdr(ring->dev, header, |
gregor kowski | 035d024 | 2009-08-19 22:35:45 +0200 | [diff] [blame] | 1198 | skb, info, cookie); |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1199 | if (unlikely(err)) { |
| 1200 | ring->current_slot = old_top_slot; |
| 1201 | ring->used_slots = old_used_slots; |
| 1202 | return err; |
| 1203 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1204 | |
| 1205 | meta_hdr->dmaaddr = map_descbuffer(ring, (unsigned char *)header, |
Michael Buesch | eb189d8b | 2008-01-28 14:47:41 -0800 | [diff] [blame] | 1206 | hdrsize, 1); |
Michael Buesch | ffa9256 | 2008-03-22 22:04:45 +0100 | [diff] [blame] | 1207 | if (b43_dma_mapping_error(ring, meta_hdr->dmaaddr, hdrsize, 1)) { |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1208 | ring->current_slot = old_top_slot; |
| 1209 | ring->used_slots = old_used_slots; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1210 | return -EIO; |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1211 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1212 | ops->fill_descriptor(ring, desc, meta_hdr->dmaaddr, |
Michael Buesch | eb189d8b | 2008-01-28 14:47:41 -0800 | [diff] [blame] | 1213 | hdrsize, 1, 0, 0); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1214 | |
| 1215 | /* Get a slot for the payload. */ |
| 1216 | slot = request_slot(ring); |
| 1217 | desc = ops->idx2desc(ring, slot, &meta); |
| 1218 | memset(meta, 0, sizeof(*meta)); |
| 1219 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1220 | meta->skb = skb; |
| 1221 | meta->is_last_fragment = 1; |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1222 | priv_info->bouncebuffer = NULL; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1223 | |
| 1224 | meta->dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1); |
| 1225 | /* create a bounce buffer in zone_dma on mapping failure. */ |
Michael Buesch | ffa9256 | 2008-03-22 22:04:45 +0100 | [diff] [blame] | 1226 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
Julia Lawall | a61aac7 | 2010-05-15 23:20:26 +0200 | [diff] [blame] | 1227 | priv_info->bouncebuffer = kmemdup(skb->data, skb->len, |
| 1228 | GFP_ATOMIC | GFP_DMA); |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1229 | if (!priv_info->bouncebuffer) { |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1230 | ring->current_slot = old_top_slot; |
| 1231 | ring->used_slots = old_used_slots; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1232 | err = -ENOMEM; |
| 1233 | goto out_unmap_hdr; |
| 1234 | } |
| 1235 | |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1236 | meta->dmaaddr = map_descbuffer(ring, priv_info->bouncebuffer, skb->len, 1); |
Michael Buesch | ffa9256 | 2008-03-22 22:04:45 +0100 | [diff] [blame] | 1237 | if (b43_dma_mapping_error(ring, meta->dmaaddr, skb->len, 1)) { |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1238 | kfree(priv_info->bouncebuffer); |
| 1239 | priv_info->bouncebuffer = NULL; |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1240 | ring->current_slot = old_top_slot; |
| 1241 | ring->used_slots = old_used_slots; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1242 | err = -EIO; |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1243 | goto out_unmap_hdr; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1244 | } |
| 1245 | } |
| 1246 | |
| 1247 | ops->fill_descriptor(ring, desc, meta->dmaaddr, skb->len, 0, 1, 1); |
| 1248 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1249 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1250 | /* Tell the firmware about the cookie of the last |
| 1251 | * mcast frame, so it can clear the more-data bit in it. */ |
| 1252 | b43_shm_write16(ring->dev, B43_SHM_SHARED, |
| 1253 | B43_SHM_SH_MCASTCOOKIE, cookie); |
| 1254 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1255 | /* Now transfer the whole frame. */ |
| 1256 | wmb(); |
| 1257 | ops->poke_tx(ring, next_slot(ring, slot)); |
| 1258 | return 0; |
| 1259 | |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1260 | out_unmap_hdr: |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1261 | unmap_descbuffer(ring, meta_hdr->dmaaddr, |
Michael Buesch | eb189d8b | 2008-01-28 14:47:41 -0800 | [diff] [blame] | 1262 | hdrsize, 1); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1263 | return err; |
| 1264 | } |
| 1265 | |
| 1266 | static inline int should_inject_overflow(struct b43_dmaring *ring) |
| 1267 | { |
| 1268 | #ifdef CONFIG_B43_DEBUG |
| 1269 | if (unlikely(b43_debug(ring->dev, B43_DBG_DMAOVERFLOW))) { |
| 1270 | /* Check if we should inject another ringbuffer overflow |
| 1271 | * to test handling of this situation in the stack. */ |
| 1272 | unsigned long next_overflow; |
| 1273 | |
| 1274 | next_overflow = ring->last_injected_overflow + HZ; |
| 1275 | if (time_after(jiffies, next_overflow)) { |
| 1276 | ring->last_injected_overflow = jiffies; |
| 1277 | b43dbg(ring->dev->wl, |
| 1278 | "Injecting TX ring overflow on " |
| 1279 | "DMA controller %d\n", ring->index); |
| 1280 | return 1; |
| 1281 | } |
| 1282 | } |
| 1283 | #endif /* CONFIG_B43_DEBUG */ |
| 1284 | return 0; |
| 1285 | } |
| 1286 | |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1287 | /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */ |
John Daiker | 99da185 | 2009-02-24 02:16:42 -0800 | [diff] [blame] | 1288 | static struct b43_dmaring *select_ring_by_priority(struct b43_wldev *dev, |
| 1289 | u8 queue_prio) |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1290 | { |
| 1291 | struct b43_dmaring *ring; |
| 1292 | |
Michael Buesch | 403a3a1 | 2009-06-08 21:04:57 +0200 | [diff] [blame] | 1293 | if (dev->qos_enabled) { |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1294 | /* 0 = highest priority */ |
| 1295 | switch (queue_prio) { |
| 1296 | default: |
| 1297 | B43_WARN_ON(1); |
| 1298 | /* fallthrough */ |
| 1299 | case 0: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1300 | ring = dev->dma.tx_ring_AC_VO; |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1301 | break; |
| 1302 | case 1: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1303 | ring = dev->dma.tx_ring_AC_VI; |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1304 | break; |
| 1305 | case 2: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1306 | ring = dev->dma.tx_ring_AC_BE; |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1307 | break; |
| 1308 | case 3: |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1309 | ring = dev->dma.tx_ring_AC_BK; |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1310 | break; |
| 1311 | } |
| 1312 | } else |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1313 | ring = dev->dma.tx_ring_AC_BE; |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1314 | |
| 1315 | return ring; |
| 1316 | } |
| 1317 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1318 | int b43_dma_tx(struct b43_wldev *dev, struct sk_buff *skb) |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1319 | { |
| 1320 | struct b43_dmaring *ring; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1321 | struct ieee80211_hdr *hdr; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1322 | int err = 0; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1323 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1324 | |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1325 | hdr = (struct ieee80211_hdr *)skb->data; |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1326 | if (info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM) { |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1327 | /* The multicast ring will be sent after the DTIM */ |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1328 | ring = dev->dma.tx_ring_mcast; |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1329 | /* Set the more-data bit. Ucode will clear it on |
| 1330 | * the last frame for us. */ |
| 1331 | hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_MOREDATA); |
| 1332 | } else { |
| 1333 | /* Decide by priority where to put this frame. */ |
Johannes Berg | e253008 | 2008-05-17 00:57:14 +0200 | [diff] [blame] | 1334 | ring = select_ring_by_priority( |
| 1335 | dev, skb_get_queue_mapping(skb)); |
Michael Buesch | 280d0e1 | 2007-12-26 18:26:17 +0100 | [diff] [blame] | 1336 | } |
| 1337 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1338 | B43_WARN_ON(!ring->tx); |
Michael Buesch | ca2d559 | 2009-02-19 20:17:36 +0100 | [diff] [blame] | 1339 | |
Larry Finger | 18c6951 | 2009-07-29 10:54:06 -0500 | [diff] [blame] | 1340 | if (unlikely(ring->stopped)) { |
| 1341 | /* We get here only because of a bug in mac80211. |
| 1342 | * Because of a race, one packet may be queued after |
| 1343 | * the queue is stopped, thus we got called when we shouldn't. |
| 1344 | * For now, just refuse the transmit. */ |
| 1345 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) |
| 1346 | b43err(dev->wl, "Packet after queue stopped\n"); |
| 1347 | err = -ENOSPC; |
Michael Buesch | 637dae3 | 2009-09-04 22:55:00 +0200 | [diff] [blame] | 1348 | goto out; |
Larry Finger | 18c6951 | 2009-07-29 10:54:06 -0500 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | if (unlikely(WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME))) { |
| 1352 | /* If we get here, we have a real error with the queue |
| 1353 | * full, but queues not stopped. */ |
| 1354 | b43err(dev->wl, "DMA queue overflow\n"); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1355 | err = -ENOSPC; |
Michael Buesch | 637dae3 | 2009-09-04 22:55:00 +0200 | [diff] [blame] | 1356 | goto out; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1357 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1358 | |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1359 | /* Assign the queue number to the ring (if not already done before) |
| 1360 | * so TX status handling can use it. The queue to ring mapping is |
| 1361 | * static, so we don't need to store it per frame. */ |
Johannes Berg | e253008 | 2008-05-17 00:57:14 +0200 | [diff] [blame] | 1362 | ring->queue_prio = skb_get_queue_mapping(skb); |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1363 | |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1364 | err = dma_tx_fragment(ring, skb); |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1365 | if (unlikely(err == -ENOKEY)) { |
| 1366 | /* Drop this packet, as we don't have the encryption key |
| 1367 | * anymore and must not transmit it unencrypted. */ |
| 1368 | dev_kfree_skb_any(skb); |
| 1369 | err = 0; |
Michael Buesch | 637dae3 | 2009-09-04 22:55:00 +0200 | [diff] [blame] | 1370 | goto out; |
Michael Buesch | 09552cc | 2008-01-23 21:44:15 +0100 | [diff] [blame] | 1371 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1372 | if (unlikely(err)) { |
| 1373 | b43err(dev->wl, "DMA tx mapping failure\n"); |
Michael Buesch | 637dae3 | 2009-09-04 22:55:00 +0200 | [diff] [blame] | 1374 | goto out; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1375 | } |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 1376 | if ((free_slots(ring) < TX_SLOTS_PER_FRAME) || |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1377 | should_inject_overflow(ring)) { |
| 1378 | /* This TX ring is full. */ |
Johannes Berg | e253008 | 2008-05-17 00:57:14 +0200 | [diff] [blame] | 1379 | ieee80211_stop_queue(dev->wl->hw, skb_get_queue_mapping(skb)); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1380 | ring->stopped = 1; |
| 1381 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { |
| 1382 | b43dbg(dev->wl, "Stopped TX ring %d\n", ring->index); |
| 1383 | } |
| 1384 | } |
Michael Buesch | 637dae3 | 2009-09-04 22:55:00 +0200 | [diff] [blame] | 1385 | out: |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1386 | |
| 1387 | return err; |
| 1388 | } |
| 1389 | |
| 1390 | void b43_dma_handle_txstatus(struct b43_wldev *dev, |
| 1391 | const struct b43_txstatus *status) |
| 1392 | { |
| 1393 | const struct b43_dma_ops *ops; |
| 1394 | struct b43_dmaring *ring; |
| 1395 | struct b43_dmadesc_generic *desc; |
| 1396 | struct b43_dmadesc_meta *meta; |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1397 | int slot, firstused; |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 1398 | bool frame_succeed; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1399 | |
| 1400 | ring = parse_cookie(dev, status->cookie, &slot); |
| 1401 | if (unlikely(!ring)) |
| 1402 | return; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1403 | B43_WARN_ON(!ring->tx); |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1404 | |
| 1405 | /* Sanity check: TX packets are processed in-order on one ring. |
| 1406 | * Check if the slot deduced from the cookie really is the first |
| 1407 | * used slot. */ |
| 1408 | firstused = ring->current_slot - ring->used_slots + 1; |
| 1409 | if (firstused < 0) |
| 1410 | firstused = ring->nr_slots + firstused; |
| 1411 | if (unlikely(slot != firstused)) { |
| 1412 | /* This possibly is a firmware bug and will result in |
| 1413 | * malfunction, memory leaks and/or stall of DMA functionality. */ |
| 1414 | b43dbg(dev->wl, "Out of order TX status report on DMA ring %d. " |
| 1415 | "Expected %d, but got %d\n", |
| 1416 | ring->index, firstused, slot); |
| 1417 | return; |
| 1418 | } |
| 1419 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1420 | ops = ring->ops; |
| 1421 | while (1) { |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1422 | B43_WARN_ON(slot < 0 || slot >= ring->nr_slots); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1423 | desc = ops->idx2desc(ring, slot, &meta); |
| 1424 | |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1425 | if (b43_dma_ptr_is_poisoned(meta->skb)) { |
| 1426 | b43dbg(dev->wl, "Poisoned TX slot %d (first=%d) " |
| 1427 | "on ring %d\n", |
| 1428 | slot, firstused, ring->index); |
| 1429 | break; |
| 1430 | } |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1431 | if (meta->skb) { |
| 1432 | struct b43_private_tx_info *priv_info = |
| 1433 | b43_get_priv_tx_info(IEEE80211_SKB_CB(meta->skb)); |
| 1434 | |
| 1435 | unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1); |
| 1436 | kfree(priv_info->bouncebuffer); |
| 1437 | priv_info->bouncebuffer = NULL; |
| 1438 | } else { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1439 | unmap_descbuffer(ring, meta->dmaaddr, |
Michael Buesch | eb189d8b | 2008-01-28 14:47:41 -0800 | [diff] [blame] | 1440 | b43_txhdr_size(dev), 1); |
Michael Buesch | f54a520 | 2009-11-06 18:32:44 +0100 | [diff] [blame] | 1441 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1442 | |
| 1443 | if (meta->is_last_fragment) { |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1444 | struct ieee80211_tx_info *info; |
| 1445 | |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1446 | if (unlikely(!meta->skb)) { |
| 1447 | /* This is a scatter-gather fragment of a frame, so |
| 1448 | * the skb pointer must not be NULL. */ |
| 1449 | b43dbg(dev->wl, "TX status unexpected NULL skb " |
| 1450 | "at slot %d (first=%d) on ring %d\n", |
| 1451 | slot, firstused, ring->index); |
| 1452 | break; |
| 1453 | } |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1454 | |
| 1455 | info = IEEE80211_SKB_CB(meta->skb); |
| 1456 | |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1457 | /* |
| 1458 | * Call back to inform the ieee80211 subsystem about |
| 1459 | * the status of the transmission. |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1460 | */ |
Johannes Berg | e6a9854 | 2008-10-21 12:40:02 +0200 | [diff] [blame] | 1461 | frame_succeed = b43_fill_txstatus_report(dev, info, status); |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 1462 | #ifdef CONFIG_B43_DEBUG |
| 1463 | if (frame_succeed) |
| 1464 | ring->nr_succeed_tx_packets++; |
| 1465 | else |
| 1466 | ring->nr_failed_tx_packets++; |
| 1467 | ring->nr_total_packet_tries += status->frame_count; |
| 1468 | #endif /* DEBUG */ |
Michael Buesch | ce6c4a1 | 2009-09-10 20:22:02 +0200 | [diff] [blame] | 1469 | ieee80211_tx_status(dev->wl->hw, meta->skb); |
Johannes Berg | e039fa4 | 2008-05-15 12:55:29 +0200 | [diff] [blame] | 1470 | |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1471 | /* skb will be freed by ieee80211_tx_status(). |
| 1472 | * Poison our pointer. */ |
| 1473 | meta->skb = B43_DMA_PTR_POISON; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1474 | } else { |
| 1475 | /* No need to call free_descriptor_buffer here, as |
| 1476 | * this is only the txhdr, which is not allocated. |
| 1477 | */ |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1478 | if (unlikely(meta->skb)) { |
| 1479 | b43dbg(dev->wl, "TX status unexpected non-NULL skb " |
| 1480 | "at slot %d (first=%d) on ring %d\n", |
| 1481 | slot, firstused, ring->index); |
| 1482 | break; |
| 1483 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1484 | } |
| 1485 | |
| 1486 | /* Everything unmapped and free'd. So it's not used anymore. */ |
| 1487 | ring->used_slots--; |
| 1488 | |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1489 | if (meta->is_last_fragment) { |
| 1490 | /* This is the last scatter-gather |
| 1491 | * fragment of the frame. We are done. */ |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1492 | break; |
Michael Buesch | 07681e2 | 2009-11-19 22:24:29 +0100 | [diff] [blame] | 1493 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1494 | slot = next_slot(ring, slot); |
| 1495 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1496 | if (ring->stopped) { |
Michael Buesch | bdceeb2 | 2009-02-19 23:45:43 +0100 | [diff] [blame] | 1497 | B43_WARN_ON(free_slots(ring) < TX_SLOTS_PER_FRAME); |
Michael Buesch | e6f5b93 | 2008-03-05 21:18:49 +0100 | [diff] [blame] | 1498 | ieee80211_wake_queue(dev->wl->hw, ring->queue_prio); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1499 | ring->stopped = 0; |
| 1500 | if (b43_debug(dev, B43_DBG_DMAVERBOSE)) { |
| 1501 | b43dbg(dev->wl, "Woke up TX ring %d\n", ring->index); |
| 1502 | } |
| 1503 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1504 | } |
| 1505 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1506 | static void dma_rx(struct b43_dmaring *ring, int *slot) |
| 1507 | { |
| 1508 | const struct b43_dma_ops *ops = ring->ops; |
| 1509 | struct b43_dmadesc_generic *desc; |
| 1510 | struct b43_dmadesc_meta *meta; |
| 1511 | struct b43_rxhdr_fw4 *rxhdr; |
| 1512 | struct sk_buff *skb; |
| 1513 | u16 len; |
| 1514 | int err; |
| 1515 | dma_addr_t dmaaddr; |
| 1516 | |
| 1517 | desc = ops->idx2desc(ring, *slot, &meta); |
| 1518 | |
| 1519 | sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize); |
| 1520 | skb = meta->skb; |
| 1521 | |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1522 | rxhdr = (struct b43_rxhdr_fw4 *)skb->data; |
| 1523 | len = le16_to_cpu(rxhdr->frame_len); |
| 1524 | if (len == 0) { |
| 1525 | int i = 0; |
| 1526 | |
| 1527 | do { |
| 1528 | udelay(2); |
| 1529 | barrier(); |
| 1530 | len = le16_to_cpu(rxhdr->frame_len); |
| 1531 | } while (len == 0 && i++ < 5); |
| 1532 | if (unlikely(len == 0)) { |
Michael Buesch | cf68636 | 2009-03-28 00:41:25 +0100 | [diff] [blame] | 1533 | dmaaddr = meta->dmaaddr; |
| 1534 | goto drop_recycle_buffer; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1535 | } |
| 1536 | } |
Michael Buesch | ec9a1d8 | 2009-03-27 22:51:58 +0100 | [diff] [blame] | 1537 | if (unlikely(b43_rx_buffer_is_poisoned(ring, skb))) { |
| 1538 | /* Something went wrong with the DMA. |
| 1539 | * The device did not touch the buffer and did not overwrite the poison. */ |
| 1540 | b43dbg(ring->dev->wl, "DMA RX: Dropping poisoned buffer.\n"); |
Michael Buesch | cf68636 | 2009-03-28 00:41:25 +0100 | [diff] [blame] | 1541 | dmaaddr = meta->dmaaddr; |
| 1542 | goto drop_recycle_buffer; |
Michael Buesch | ec9a1d8 | 2009-03-27 22:51:58 +0100 | [diff] [blame] | 1543 | } |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1544 | if (unlikely(len > ring->rx_buffersize)) { |
| 1545 | /* The data did not fit into one descriptor buffer |
| 1546 | * and is split over multiple buffers. |
| 1547 | * This should never happen, as we try to allocate buffers |
| 1548 | * big enough. So simply ignore this packet. |
| 1549 | */ |
| 1550 | int cnt = 0; |
| 1551 | s32 tmp = len; |
| 1552 | |
| 1553 | while (1) { |
| 1554 | desc = ops->idx2desc(ring, *slot, &meta); |
| 1555 | /* recycle the descriptor buffer. */ |
Michael Buesch | cf68636 | 2009-03-28 00:41:25 +0100 | [diff] [blame] | 1556 | b43_poison_rx_buffer(ring, meta->skb); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1557 | sync_descbuffer_for_device(ring, meta->dmaaddr, |
| 1558 | ring->rx_buffersize); |
| 1559 | *slot = next_slot(ring, *slot); |
| 1560 | cnt++; |
| 1561 | tmp -= ring->rx_buffersize; |
| 1562 | if (tmp <= 0) |
| 1563 | break; |
| 1564 | } |
| 1565 | b43err(ring->dev->wl, "DMA RX buffer too small " |
| 1566 | "(len: %u, buffer: %u, nr-dropped: %d)\n", |
| 1567 | len, ring->rx_buffersize, cnt); |
| 1568 | goto drop; |
| 1569 | } |
| 1570 | |
| 1571 | dmaaddr = meta->dmaaddr; |
| 1572 | err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC); |
| 1573 | if (unlikely(err)) { |
| 1574 | b43dbg(ring->dev->wl, "DMA RX: setup_rx_descbuffer() failed\n"); |
Michael Buesch | cf68636 | 2009-03-28 00:41:25 +0100 | [diff] [blame] | 1575 | goto drop_recycle_buffer; |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1576 | } |
| 1577 | |
| 1578 | unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0); |
| 1579 | skb_put(skb, len + ring->frameoffset); |
| 1580 | skb_pull(skb, ring->frameoffset); |
| 1581 | |
| 1582 | b43_rx(ring->dev, skb, rxhdr); |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1583 | drop: |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1584 | return; |
Michael Buesch | cf68636 | 2009-03-28 00:41:25 +0100 | [diff] [blame] | 1585 | |
| 1586 | drop_recycle_buffer: |
| 1587 | /* Poison and recycle the RX buffer. */ |
| 1588 | b43_poison_rx_buffer(ring, skb); |
| 1589 | sync_descbuffer_for_device(ring, dmaaddr, ring->rx_buffersize); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1590 | } |
| 1591 | |
| 1592 | void b43_dma_rx(struct b43_dmaring *ring) |
| 1593 | { |
| 1594 | const struct b43_dma_ops *ops = ring->ops; |
| 1595 | int slot, current_slot; |
| 1596 | int used_slots = 0; |
| 1597 | |
| 1598 | B43_WARN_ON(ring->tx); |
| 1599 | current_slot = ops->get_current_rxslot(ring); |
| 1600 | B43_WARN_ON(!(current_slot >= 0 && current_slot < ring->nr_slots)); |
| 1601 | |
| 1602 | slot = ring->current_slot; |
| 1603 | for (; slot != current_slot; slot = next_slot(ring, slot)) { |
| 1604 | dma_rx(ring, &slot); |
| 1605 | update_max_used_slots(ring, ++used_slots); |
| 1606 | } |
| 1607 | ops->set_current_rxslot(ring, slot); |
| 1608 | ring->current_slot = slot; |
| 1609 | } |
| 1610 | |
| 1611 | static void b43_dma_tx_suspend_ring(struct b43_dmaring *ring) |
| 1612 | { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1613 | B43_WARN_ON(!ring->tx); |
| 1614 | ring->ops->tx_suspend(ring); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1615 | } |
| 1616 | |
| 1617 | static void b43_dma_tx_resume_ring(struct b43_dmaring *ring) |
| 1618 | { |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1619 | B43_WARN_ON(!ring->tx); |
| 1620 | ring->ops->tx_resume(ring); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1621 | } |
| 1622 | |
| 1623 | void b43_dma_tx_suspend(struct b43_wldev *dev) |
| 1624 | { |
| 1625 | b43_power_saving_ctl_bits(dev, B43_PS_AWAKE); |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1626 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BK); |
| 1627 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_BE); |
| 1628 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VI); |
| 1629 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_AC_VO); |
| 1630 | b43_dma_tx_suspend_ring(dev->dma.tx_ring_mcast); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1631 | } |
| 1632 | |
| 1633 | void b43_dma_tx_resume(struct b43_wldev *dev) |
| 1634 | { |
Michael Buesch | b27faf8 | 2008-03-06 16:32:46 +0100 | [diff] [blame] | 1635 | b43_dma_tx_resume_ring(dev->dma.tx_ring_mcast); |
| 1636 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VO); |
| 1637 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_VI); |
| 1638 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BE); |
| 1639 | b43_dma_tx_resume_ring(dev->dma.tx_ring_AC_BK); |
Michael Buesch | e4d6b79 | 2007-09-18 15:39:42 -0400 | [diff] [blame] | 1640 | b43_power_saving_ctl_bits(dev, 0); |
| 1641 | } |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 1642 | |
Michael Buesch | 5100d5a | 2008-03-29 21:01:16 +0100 | [diff] [blame] | 1643 | static void direct_fifo_rx(struct b43_wldev *dev, enum b43_dmatype type, |
| 1644 | u16 mmio_base, bool enable) |
| 1645 | { |
| 1646 | u32 ctl; |
| 1647 | |
| 1648 | if (type == B43_DMA_64BIT) { |
| 1649 | ctl = b43_read32(dev, mmio_base + B43_DMA64_RXCTL); |
| 1650 | ctl &= ~B43_DMA64_RXDIRECTFIFO; |
| 1651 | if (enable) |
| 1652 | ctl |= B43_DMA64_RXDIRECTFIFO; |
| 1653 | b43_write32(dev, mmio_base + B43_DMA64_RXCTL, ctl); |
| 1654 | } else { |
| 1655 | ctl = b43_read32(dev, mmio_base + B43_DMA32_RXCTL); |
| 1656 | ctl &= ~B43_DMA32_RXDIRECTFIFO; |
| 1657 | if (enable) |
| 1658 | ctl |= B43_DMA32_RXDIRECTFIFO; |
| 1659 | b43_write32(dev, mmio_base + B43_DMA32_RXCTL, ctl); |
| 1660 | } |
| 1661 | } |
| 1662 | |
| 1663 | /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine. |
| 1664 | * This is called from PIO code, so DMA structures are not available. */ |
| 1665 | void b43_dma_direct_fifo_rx(struct b43_wldev *dev, |
| 1666 | unsigned int engine_index, bool enable) |
| 1667 | { |
| 1668 | enum b43_dmatype type; |
| 1669 | u16 mmio_base; |
| 1670 | |
| 1671 | type = dma_mask_to_engine_type(supported_dma_mask(dev)); |
| 1672 | |
| 1673 | mmio_base = b43_dmacontroller_base(type, engine_index); |
| 1674 | direct_fifo_rx(dev, type, mmio_base, enable); |
| 1675 | } |